fix(intel): f2sdram bridge quick write thru failed
This patch is to fix the f2sdram bridge quick write thru failing by
removing the clear bit for sidebandmgr flagout register.
Change-Id: Ib03498fbb2d91e9fd85f6315091ff72cbe3f394d
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
diff --git a/plat/intel/soc/common/soc/socfpga_reset_manager.c b/plat/intel/soc/common/soc/socfpga_reset_manager.c
index 5204146..5c80798 100644
--- a/plat/intel/soc/common/soc/socfpga_reset_manager.c
+++ b/plat/intel/soc/common/soc/socfpga_reset_manager.c
@@ -777,14 +777,6 @@
VERBOSE("Deassert F2SDRAM ...\n");
mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
RSTMGR_BRGMODRST_F2SSDRAM0);
-
- /*
- * Clear fpga2sdram_manager_main_SidebandManager_FlagOutClr0
- * f2s_ready_latency_enable
- */
- VERBOSE("Clear F2SDRAM f2s_ready_latency_enable ...\n");
- mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0),
- FLAGOUTCLR0_F2SDRAM0_ENABLE);
}
#else
if (brg_mask != 0U) {