Merge "feat(rk3588): enable crypto function" into integration
diff --git a/plat/rockchip/common/aarch64/plat_helpers.S b/plat/rockchip/common/aarch64/plat_helpers.S
index dde66aa..9b8c971 100644
--- a/plat/rockchip/common/aarch64/plat_helpers.S
+++ b/plat/rockchip/common/aarch64/plat_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -32,6 +32,17 @@
*
*/
func plat_reset_handler
+#ifdef PLAT_RK_CPU_RESET_EARLY
+ mov x18, x30
+ msr spsel, #0
+ bl plat_set_my_stack
+ mov x0, x20
+ mov x1, x21
+ mov x2, x22
+ mov x3, x23
+ bl rockchip_cpu_reset_early
+ mov x30, x18
+#endif
mrs x0, midr_el1
ubfx x0, x0, MIDR_PN_SHIFT, #12
cmp w0, #((CORTEX_A72_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
diff --git a/plat/rockchip/rk3588/drivers/pmu/pmu.c b/plat/rockchip/rk3588/drivers/pmu/pmu.c
index 83d6cad..f693dbd 100644
--- a/plat/rockchip/rk3588/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3588/drivers/pmu/pmu.c
@@ -136,6 +136,22 @@
static __pmusramfunc void ddr_resume(void)
{
+ /* check the crypto function had been enabled or not */
+ if ((mmio_read_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4)) & BIT(4)) != 0) {
+ /* enable the crypto function */
+ mmio_write_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4), BITS_WITH_WMASK(0, 0x1, 4));
+ dsb();
+ isb();
+
+ __asm__ volatile ("mov x0, #3\n"
+ "dsb sy\n"
+ "msr rmr_el3, x0\n"
+ "1:\n"
+ "isb\n"
+ "wfi\n"
+ "b 1b\n");
+ }
+
dsu_restore_early();
}
@@ -1437,3 +1453,60 @@
pm_reg_rgns_init();
}
+
+static uint64_t boot_cpu_save[4];
+/* define in .data section */
+static uint32_t need_en_crypto = 1;
+
+void rockchip_cpu_reset_early(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
+{
+ if (need_en_crypto == 0)
+ return;
+
+ /* check the crypto function had been enabled or not */
+ if ((mmio_read_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4)) & BIT(4)) != 0) {
+ /* save x0~x3 */
+ boot_cpu_save[0] = arg0;
+ boot_cpu_save[1] = arg1;
+ boot_cpu_save[2] = arg2;
+ boot_cpu_save[3] = arg3;
+
+ /* enable the crypto function */
+ mmio_write_32(DSUSGRF_BASE + DSU_SGRF_SOC_CON(4),
+ BITS_WITH_WMASK(0, 0x1, 4));
+
+ /* remap pmusram to 0xffff0000 */
+ mmio_write_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(2), 0x00030001);
+ psram_sleep_cfg->pm_flag = PM_WARM_BOOT_BIT;
+ cpuson_flags[0] = PMU_CPU_HOTPLUG;
+ cpuson_entry_point[0] = (uintptr_t)BL31_BASE;
+ dsb();
+
+ /* Must reset core0 to enable the crypto function.
+ * Core0 will boot from pmu_sram and jump to BL31_BASE.
+ */
+ __asm__ volatile ("mov x0, #3\n"
+ "dsb sy\n"
+ "msr rmr_el3, x0\n"
+ "1:\n"
+ "isb\n"
+ "wfi\n"
+ "b 1b\n");
+ } else {
+ need_en_crypto = 0;
+
+ /* remap bootrom to 0xffff0000 */
+ mmio_write_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(2), 0x00030000);
+
+ /*
+ * the crypto function has been enabled,
+ * restore the x0~x3.
+ */
+ __asm__ volatile ("ldr x20, [%0]\n"
+ "ldr x21, [%0, 0x8]\n"
+ "ldr x22, [%0, 0x10]\n"
+ "ldr x23, [%0, 0x18]\n"
+ : : "r" (&boot_cpu_save[0]));
+ }
+}
diff --git a/plat/rockchip/rk3588/platform.mk b/plat/rockchip/rk3588/platform.mk
index 07eda40..2fadb5a 100644
--- a/plat/rockchip/rk3588/platform.mk
+++ b/plat/rockchip/rk3588/platform.mk
@@ -95,4 +95,4 @@
ENABLE_SPE_FOR_LOWER_ELS := 0
$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
-$(eval $(call add_define,PLAT_SKIP_DFS_TLB_DCACHE_MAINTENANCE))
+$(eval $(call add_define,PLAT_RK_CPU_RESET_EARLY))