rockchip: SIP call use 32 bit return value for rk3399

for compatible 32bit and 64bit, we use 0x82xxxxxx as function ID,
we modify SIP call function return value to 32 bit.

Change-Id: Ib99b03a9ea423853aaa296dcc634ee82c622a552
diff --git a/plat/rockchip/rk3399/drivers/dram/dram.c b/plat/rockchip/rk3399/drivers/dram/dram.c
index ddae84d..94aa076 100644
--- a/plat/rockchip/rk3399/drivers/dram/dram.c
+++ b/plat/rockchip/rk3399/drivers/dram/dram.c
@@ -2147,7 +2147,7 @@
 {
 	int pll_cnt, i;
 
-	pll_cnt = sizeof(dpll_rates_table) / sizeof(struct pll_div);
+	pll_cnt = ARRAY_SIZE(dpll_rates_table);
 
 	/* Assumming rate_table is in descending order */
 	for (i = 0; i < pll_cnt; i++) {
@@ -2155,6 +2155,10 @@
 			break;
 	}
 
+	/* if mhz lower than lowest frequency in table, use lowest frequency */
+	if (i == pll_cnt)
+		i = pll_cnt - 1;
+
 	return i;
 }
 
@@ -2174,7 +2178,7 @@
 	return (24 * fbdiv) / refdiv / postdiv1 / postdiv2;
 }
 
-uint64_t ddr_get_rate(void)
+uint32_t ddr_get_rate(void)
 {
 	uint32_t refdiv, postdiv1, fbdiv, postdiv2;
 
@@ -2464,7 +2468,6 @@
 	 * target freq.
 	 */
 	dram_get_parameter(&rk3399_dram_status.timing_config, &dram_timing);
-
 	gen_rk3399_ctl_params(&rk3399_dram_status.timing_config,
 			      &dram_timing, index);
 	gen_rk3399_pi_params(&rk3399_dram_status.timing_config,
@@ -2494,7 +2497,7 @@
 		tf_printf("%u\n", p[i]);
 }
 
-uint64_t ddr_set_rate(uint64_t hz)
+uint32_t ddr_set_rate(uint32_t hz)
 {
 	uint32_t low_power, index;
 	uint32_t mhz = hz / (1000 * 1000);
@@ -2503,13 +2506,13 @@
 	    rk3399_dram_status.index_freq[rk3399_dram_status.current_index])
 		goto out;
 
+	index = to_get_clk_index(mhz);
+	mhz = dpll_rates_table[index].mhz;
+
 	low_power = exit_low_power();
 	index = prepare_ddr_timing(mhz);
-	if (index > 1) {
-		/* set timing error, quit */
-		mhz = 0;
+	if (index > 1)
 		goto out;
-	}
 
 	dcf_start(mhz, index);
 	wait_dcf_done();
@@ -2526,7 +2529,7 @@
 	return mhz;
 }
 
-uint64_t ddr_round_rate(uint64_t hz)
+uint32_t ddr_round_rate(uint32_t hz)
 {
 	int index;
 	uint32_t mhz = hz / (1000 * 1000);
@@ -2536,7 +2539,7 @@
 	return dpll_rates_table[index].mhz * 1000 * 1000;
 }
 
-uint64_t dts_timing_receive(uint64_t timing, uint64_t index)
+uint32_t dts_timing_receive(uint32_t timing, uint32_t index)
 {
 	uint32_t *p = (uint32_t *) &dts_parameter;
 	static uint32_t receive_nums;