rcar_gen3: plat: Dump EL3 interrupt error registers
Since the interrupts are handled in EL3, dump the EL3 error registers
in case an error happens.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
diff --git a/plat/renesas/rcar/aarch64/plat_helpers.S b/plat/renesas/rcar/aarch64/plat_helpers.S
index df1664d..ae0d675 100644
--- a/plat/renesas/rcar/aarch64/plat_helpers.S
+++ b/plat/renesas/rcar/aarch64/plat_helpers.S
@@ -217,6 +217,8 @@
* ---------------------------------------------
*/
func plat_report_exception
+ /* Switch to SP_EL0 */
+ msr spsel, #0
#if IMAGE_BL2
mov w1, #FIQ_SP_EL0
cmp w0, w1
diff --git a/plat/renesas/rcar/bl2_interrupt_error.c b/plat/renesas/rcar/bl2_interrupt_error.c
index 2346017..d9a4b8e 100644
--- a/plat/renesas/rcar/bl2_interrupt_error.c
+++ b/plat/renesas/rcar/bl2_interrupt_error.c
@@ -24,7 +24,7 @@
ERROR("\n");
if (int_id >= SWDT_ERROR_ID) {
ERROR("Unhandled exception occurred.\n");
- ERROR(" Exception type = FIQ_SP_ELX\n");
+ ERROR(" Exception type = FIQ_SP_EL0\n");
panic();
}
@@ -32,11 +32,11 @@
gicv2_end_of_interrupt((uint32_t) int_id);
rcar_swdt_release();
ERROR("Unhandled exception occurred.\n");
- ERROR(" Exception type = FIQ_SP_ELX\n");
- ERROR(" SPSR_EL1 = 0x%x\n", (uint32_t) read_spsr_el1());
- ERROR(" ELR_EL1 = 0x%x\n", (uint32_t) read_elr_el1());
- ERROR(" ESR_EL1 = 0x%x\n", (uint32_t) read_esr_el1());
- ERROR(" FAR_EL1 = 0x%x\n", (uint32_t) read_far_el1());
+ ERROR(" Exception type = FIQ_SP_EL0\n");
+ ERROR(" SPSR_EL3 = 0x%x\n", (uint32_t) read_spsr_el3());
+ ERROR(" ELR_EL3 = 0x%x\n", (uint32_t) read_elr_el3());
+ ERROR(" ESR_EL3 = 0x%x\n", (uint32_t) read_esr_el3());
+ ERROR(" FAR_EL3 = 0x%x\n", (uint32_t) read_far_el3());
ERROR("\n");
panic();
}
@@ -78,27 +78,27 @@
&interrupt_ex[ex_type][0]);
ERROR("%s", msg);
switch (ex_type) {
- case SYNC_EXCEPTION_SP_ELX:
- ERROR(" SPSR_EL1 = 0x%x\n", (uint32_t) read_spsr_el1());
- ERROR(" ELR_EL1 = 0x%x\n", (uint32_t) read_elr_el1());
- ERROR(" ESR_EL1 = 0x%x\n", (uint32_t) read_esr_el1());
- ERROR(" FAR_EL1 = 0x%x\n", (uint32_t) read_far_el1());
+ case SYNC_EXCEPTION_SP_EL0:
+ ERROR(" SPSR_EL3 = 0x%x\n", (uint32_t) read_spsr_el3());
+ ERROR(" ELR_EL3 = 0x%x\n", (uint32_t) read_elr_el3());
+ ERROR(" ESR_EL3 = 0x%x\n", (uint32_t) read_esr_el3());
+ ERROR(" FAR_EL3 = 0x%x\n", (uint32_t) read_far_el3());
break;
- case IRQ_SP_ELX:
- ERROR(" SPSR_EL1 = 0x%x\n", (uint32_t) read_spsr_el1());
- ERROR(" ELR_EL1 = 0x%x\n", (uint32_t) read_elr_el1());
- ERROR(" IAR_EL1 = 0x%x\n", gicv2_acknowledge_interrupt());
+ case IRQ_SP_EL0:
+ ERROR(" SPSR_EL3 = 0x%x\n", (uint32_t) read_spsr_el3());
+ ERROR(" ELR_EL3 = 0x%x\n", (uint32_t) read_elr_el3());
+ ERROR(" IAR_EL3 = 0x%x\n", gicv2_acknowledge_interrupt());
break;
- case FIQ_SP_ELX:
- ERROR(" SPSR_EL1 = 0x%x\n", (uint32_t) read_spsr_el1());
- ERROR(" ELR_EL1 = 0x%x\n", (uint32_t) read_elr_el1());
- ERROR(" IAR_EL1 = 0x%x\n", gicv2_acknowledge_interrupt());
+ case FIQ_SP_EL0:
+ ERROR(" SPSR_EL3 = 0x%x\n", (uint32_t) read_spsr_el3());
+ ERROR(" ELR_EL3 = 0x%x\n", (uint32_t) read_elr_el3());
+ ERROR(" IAR_EL3 = 0x%x\n", gicv2_acknowledge_interrupt());
break;
- case SERROR_SP_ELX:
- ERROR(" SPSR_EL1 = 0x%x\n", (uint32_t) read_spsr_el1());
- ERROR(" ELR_EL1 = 0x%x\n", (uint32_t) read_elr_el1());
- ERROR(" ESR_EL1 = 0x%x\n", (uint32_t) read_esr_el1());
- ERROR(" FAR_EL1 = 0x%x\n", (uint32_t) read_far_el1());
+ case SERROR_SP_EL0:
+ ERROR(" SPSR_EL3 = 0x%x\n", (uint32_t) read_spsr_el3());
+ ERROR(" ELR_EL3 = 0x%x\n", (uint32_t) read_elr_el3());
+ ERROR(" ESR_EL3 = 0x%x\n", (uint32_t) read_esr_el3());
+ ERROR(" FAR_EL3 = 0x%x\n", (uint32_t) read_far_el3());
break;
default:
break;