intel: QSPI boot enablement
Manages QSPI initialization, configuration and IO handling as boot device
Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
diff --git a/plat/intel/soc/stratix10/aarch64/stratix10_private.h b/plat/intel/soc/stratix10/aarch64/stratix10_private.h
index 89851ef..f437202 100644
--- a/plat/intel/soc/stratix10/aarch64/stratix10_private.h
+++ b/plat/intel/soc/stratix10/aarch64/stratix10_private.h
@@ -29,6 +29,6 @@
} boot_source_type;
void enable_nonsecure_access(void);
-void stratix10_io_setup(void);
+void stratix10_io_setup(int boot_source);
#endif
diff --git a/plat/intel/soc/stratix10/bl2_plat_setup.c b/plat/intel/soc/stratix10/bl2_plat_setup.c
index 71e862f..9a2f9d3 100644
--- a/plat/intel/soc/stratix10/bl2_plat_setup.c
+++ b/plat/intel/soc/stratix10/bl2_plat_setup.c
@@ -30,6 +30,9 @@
#include "s10_handoff.h"
#include "s10_pinmux.h"
#include "aarch64/stratix10_private.h"
+#include "include/s10_mailbox.h"
+#include "drivers/qspi/cadence_qspi.h"
+
const mmap_region_t plat_stratix10_mmap[] = {
MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
@@ -109,8 +112,18 @@
switch (boot_source) {
case BOOT_SOURCE_SDMMC:
dw_mmc_init(¶ms, &info);
- stratix10_io_setup();
+ stratix10_io_setup(boot_source);
+ break;
+
+ case BOOT_SOURCE_QSPI:
+ mailbox_set_qspi_open();
+ mailbox_set_qspi_direct();
+ cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL,
+ QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS,
+ QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0);
+ stratix10_io_setup(boot_source);
break;
+
default:
ERROR("Unsupported boot source\n");
panic();
diff --git a/plat/intel/soc/stratix10/plat_storage.c b/plat/intel/soc/stratix10/plat_storage.c
index cedcf1e..f5fd871 100644
--- a/plat/intel/soc/stratix10/plat_storage.c
+++ b/plat/intel/soc/stratix10/plat_storage.c
@@ -21,17 +21,21 @@
#include <lib/utils.h>
#include <common/tbbr/tbbr_img_def.h>
#include "platform_def.h"
+#include "aarch64/stratix10_private.h"
-#define STRATIX10_FIP_BASE (0)
-#define STRATIX10_FIP_MAX_SIZE (0x1000000)
-#define STRATIX10_MMC_DATA_BASE (0xffe3c000)
-#define STRATIX10_MMC_DATA_SIZE (0x2000)
+#define STRATIX10_FIP_BASE (0)
+#define STRATIX10_FIP_MAX_SIZE (0x1000000)
+#define STRATIX10_MMC_DATA_BASE (0xffe3c000)
+#define STRATIX10_MMC_DATA_SIZE (0x2000)
+#define STRATIX10_QSPI_DATA_BASE (0x3C00000)
+#define STRATIX10_QSPI_DATA_SIZE (0x1000000)
-static const io_dev_connector_t *mmc_dev_con;
+
static const io_dev_connector_t *fip_dev_con;
+static const io_dev_connector_t *boot_dev_con;
static uintptr_t fip_dev_handle;
-static uintptr_t mmc_dev_handle;
+static uintptr_t boot_dev_handle;
static const io_uuid_spec_t bl2_uuid_spec = {
.uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2,
@@ -46,47 +50,35 @@
};
uintptr_t a2_lba_offset;
+const char a2[] = {0xa2, 0x0};
static const io_block_spec_t gpt_block_spec = {
.offset = 0,
.length = MMC_BLOCK_SIZE
};
-static int check_mmc(const uintptr_t spec);
static int check_fip(const uintptr_t spec);
+static int check_dev(const uintptr_t spec);
-static io_block_spec_t mmc_fip_spec = {
+static io_block_dev_spec_t boot_dev_spec;
+static int (*register_io_dev)(const io_dev_connector_t **);
+
+static io_block_spec_t fip_spec = {
.offset = STRATIX10_FIP_BASE,
.length = STRATIX10_FIP_MAX_SIZE,
};
-const char a2[] = {0xa2, 0x0};
-
-static const io_block_dev_spec_t mmc_dev_spec = {
- .buffer = {
- .offset = STRATIX10_MMC_DATA_BASE,
- .length = MMC_BLOCK_SIZE,
- },
-
- .ops = {
- .read = mmc_read_blocks,
- .write = mmc_write_blocks,
- },
-
- .block_size = MMC_BLOCK_SIZE,
-};
-
struct plat_io_policy {
- uintptr_t *dev_handle;
- uintptr_t image_spec;
- int (*check)(const uintptr_t spec);
+ uintptr_t *dev_handle;
+ uintptr_t image_spec;
+ int (*check)(const uintptr_t spec);
};
static const struct plat_io_policy policies[] = {
[FIP_IMAGE_ID] = {
- &mmc_dev_handle,
- (uintptr_t)&mmc_fip_spec,
- check_mmc
+ &boot_dev_handle,
+ (uintptr_t)&fip_spec,
+ check_dev
},
[BL2_IMAGE_ID] = {
&fip_dev_handle,
@@ -104,20 +96,20 @@
check_fip
},
[GPT_IMAGE_ID] = {
- &mmc_dev_handle,
+ &boot_dev_handle,
(uintptr_t) &gpt_block_spec,
- check_mmc
+ check_dev
},
};
-static int check_mmc(const uintptr_t spec)
+static int check_dev(const uintptr_t spec)
{
int result;
uintptr_t local_handle;
- result = io_dev_init(mmc_dev_handle, (uintptr_t)NULL);
+ result = io_dev_init(boot_dev_handle, (uintptr_t)NULL);
if (result == 0) {
- result = io_open(mmc_dev_handle, spec, &local_handle);
+ result = io_open(boot_dev_handle, spec, &local_handle);
if (result == 0)
io_close(local_handle);
}
@@ -138,26 +130,48 @@
return result;
}
-void stratix10_io_setup(void)
+void stratix10_io_setup(int boot_source)
{
int result;
+ switch (boot_source) {
+ case BOOT_SOURCE_SDMMC:
+ register_io_dev = ®ister_io_dev_block;
+ boot_dev_spec.buffer.offset = STRATIX10_MMC_DATA_BASE;
+ boot_dev_spec.buffer.length = MMC_BLOCK_SIZE;
+ boot_dev_spec.ops.read = mmc_read_blocks;
+ boot_dev_spec.ops.write = mmc_write_blocks;
+ boot_dev_spec.block_size = MMC_BLOCK_SIZE;
+ break;
+
+ case BOOT_SOURCE_QSPI:
+ register_io_dev = ®ister_io_dev_memmap;
+ fip_spec.offset = fip_spec.offset + STRATIX10_QSPI_DATA_BASE;
+ break;
+
- result = register_io_dev_block(&mmc_dev_con);
+ default:
+ ERROR("Unsupported boot source\n");
+ panic();
+ break;
+ }
+
+ result = (*register_io_dev)(&boot_dev_con);
assert(result == 0);
result = register_io_dev_fip(&fip_dev_con);
assert(result == 0);
- result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_dev_spec,
- &mmc_dev_handle);
+ result = io_dev_open(boot_dev_con, (uintptr_t)&boot_dev_spec,
+ &boot_dev_handle);
assert(result == 0);
result = io_dev_open(fip_dev_con, (uintptr_t)NULL, &fip_dev_handle);
assert(result == 0);
- partition_init(GPT_IMAGE_ID);
-
- mmc_fip_spec.offset = get_partition_entry(a2)->start;
+ if (boot_source == BOOT_SOURCE_SDMMC) {
+ partition_init(GPT_IMAGE_ID);
+ fip_spec.offset = get_partition_entry(a2)->start;
+ }
(void)result;
}
diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk
index debdea1..1f06fbd 100644
--- a/plat/intel/soc/stratix10/platform.mk
+++ b/plat/intel/soc/stratix10/platform.mk
@@ -31,7 +31,7 @@
drivers/io/io_block.c \
drivers/io/io_fip.c \
drivers/gpio/gpio.c \
- drivers/io/io_memmap.c \
+ drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \
plat/intel/soc/stratix10/bl2_plat_setup.c \
plat/intel/soc/stratix10/plat_storage.c \
plat/intel/soc/stratix10/bl2_plat_mem_params_desc.c \
@@ -44,7 +44,9 @@
lib/cpus/aarch64/cortex_a53.S \
plat/intel/soc/stratix10/stratix10_image_load.c \
plat/intel/soc/stratix10/soc/s10_system_manager.c \
- common/desc_image_load.c
+ common/desc_image_load.c \
+ plat/intel/soc/stratix10/soc/s10_mailbox.c \
+ plat/intel/soc/stratix10/drivers/qspi/cadence_qspi.c
BL31_SOURCES += drivers/arm/cci/cci.c \
lib/cpus/aarch64/cortex_a53.S \