commit 2405621e1e1beb58346d6e4e3f227b508ca7e1ff
author Lucas Stach <l.stach@pengutronix.de> Fri May 20 12:37:39 2022 +0200
committer Lucas Stach <l.stach@pengutronix.de> Mon May 23 12:31:53 2022 +0200
tree cf74572e83f1392d612a3a3d5201349519088176
parent 2103b3ad757661a1c35ea22a9766cc4c5ab0927f

fix(imx8mq): correct architected counter frequency

Different from other i.MX SoCs, which typically use a 24MHz reference clock,
the i.MX8MQ uses a 25MHz reference clock. As the architected timer clock
frequency is directly sourced from the reference clock via a /3 divider this
SoC runs the timers at 8.33MHz.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Change-Id: Ief36af9ffebce7cb75a200124134828d3963e744

plat/imx/imx8m/imx8mq/include/platform_def.h

diff --git a/plat/imx/imx8m/imx8mq/include/platform_def.h b/plat/imx/imx8m/imx8mq/include/platform_def.h
index a76e895..1dd22d9 100644
--- a/plat/imx/imx8m/imx8mq/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mq/include/platform_def.h
@@ -126,7 +126,7 @@
 #define OCRAM_S_SIZE			U(0x8000)
 #define OCRAM_S_LIMIT			(OCRAM_S_BASE + OCRAM_S_SIZE)
 
-#define COUNTER_FREQUENCY		8000000 /* 8MHz */
+#define COUNTER_FREQUENCY		8333333 /* 25MHz / 3 */
 
 #define DEBUG_CONSOLE			0
 #define IMX_WDOG_B_RESET