fix(zynqmp): typecast operands to match data type
This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.
Change-Id: I141fbc554265173df0ca90c2ddc7f28137c6b0f1
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
index b907cfc..1361eda 100644
--- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
+++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
@@ -333,7 +333,7 @@
int32_t plat_get_soc_revision(void)
{
- return mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET);
+ return (int32_t)mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET);
}
static uint32_t zynqmp_get_ps_ver(void)
diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
index 1f09d63..77fbb58 100644
--- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
+++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
@@ -59,7 +59,7 @@
bl32_image_ep_info.pc = BL32_BASE;
bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
- bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
+ bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX,
DISABLE_ALL_EXCEPTIONS);
}
diff --git a/plat/xilinx/zynqmp/plat_zynqmp.c b/plat/xilinx/zynqmp/plat_zynqmp.c
index 65faa2f..e7c0378 100644
--- a/plat/xilinx/zynqmp/plat_zynqmp.c
+++ b/plat/xilinx/zynqmp/plat_zynqmp.c
@@ -18,5 +18,5 @@
return -1;
}
- return zynqmp_calc_core_pos(mpidr);
+ return (int32_t)zynqmp_calc_core_pos(mpidr);
}
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
index e66355f..dbc5f13 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
@@ -110,8 +110,8 @@
.type = TYPE_MUX, \
.offset = PERIPH_MUX_SHIFT, \
.width = PERIPH_MUX_WIDTH, \
- .clkflags = CLK_SET_RATE_NO_REPARENT | \
- CLK_IS_BASIC, \
+ .clkflags = (uint16_t)(CLK_SET_RATE_NO_REPARENT |\
+ CLK_IS_BASIC), \
.typeflags = NA_TYPE_FLAGS, \
.mult = NA_MULT, \
.div = NA_DIV, \
@@ -122,9 +122,9 @@
.type = TYPE_MUX, \
.offset = PERIPH_MUX_SHIFT, \
.width = PERIPH_MUX_WIDTH, \
- .clkflags = CLK_IGNORE_UNUSED | \
+ .clkflags = (uint16_t)(CLK_IGNORE_UNUSED |\
CLK_SET_RATE_NO_REPARENT | \
- CLK_IS_BASIC, \
+ CLK_IS_BASIC), \
.typeflags = NA_TYPE_FLAGS, \
.mult = NA_MULT, \
.div = NA_DIV, \
@@ -135,10 +135,10 @@
.type = TYPE_DIV1, \
.offset = PERIPH_DIV1_SHIFT, \
.width = PERIPH_DIV1_WIDTH, \
- .clkflags = CLK_SET_RATE_NO_REPARENT | \
- CLK_IS_BASIC, \
- .typeflags = CLK_DIVIDER_ONE_BASED | \
- CLK_DIVIDER_ALLOW_ZERO, \
+ .clkflags = (uint16_t)(CLK_SET_RATE_NO_REPARENT |\
+ CLK_IS_BASIC), \
+ .typeflags = (uint16_t)(CLK_DIVIDER_ONE_BASED | \
+ CLK_DIVIDER_ALLOW_ZERO), \
.mult = NA_MULT, \
.div = NA_DIV, \
}
@@ -148,11 +148,11 @@
.type = TYPE_DIV2, \
.offset = PERIPH_DIV2_SHIFT, \
.width = PERIPH_DIV2_WIDTH, \
- .clkflags = CLK_SET_RATE_NO_REPARENT | \
+ .clkflags = (uint16_t)(CLK_SET_RATE_NO_REPARENT |\
CLK_SET_RATE_PARENT | \
- CLK_IS_BASIC, \
- .typeflags = CLK_DIVIDER_ONE_BASED | \
- CLK_DIVIDER_ALLOW_ZERO, \
+ CLK_IS_BASIC), \
+ .typeflags = (uint16_t)(CLK_DIVIDER_ONE_BASED | \
+ CLK_DIVIDER_ALLOW_ZERO), \
.mult = NA_MULT, \
.div = NA_DIV, \
}
@@ -162,11 +162,11 @@
.type = TYPE_DIV##id, \
.offset = PERIPH_DIV##id##_SHIFT, \
.width = PERIPH_DIV##id##_WIDTH, \
- .clkflags = CLK_IGNORE_UNUSED | \
+ .clkflags = (uint16_t)(CLK_IGNORE_UNUSED | \
CLK_SET_RATE_NO_REPARENT | \
- CLK_IS_BASIC, \
- .typeflags = CLK_DIVIDER_ONE_BASED | \
- CLK_DIVIDER_ALLOW_ZERO, \
+ CLK_IS_BASIC), \
+ .typeflags = (uint16_t)(CLK_DIVIDER_ONE_BASED | \
+ CLK_DIVIDER_ALLOW_ZERO), \
.mult = NA_MULT, \
.div = NA_DIV, \
}
@@ -176,9 +176,9 @@
.type = TYPE_GATE, \
.offset = PERIPH_GATE_SHIFT, \
.width = PERIPH_GATE_WIDTH, \
- .clkflags = CLK_SET_RATE_PARENT | \
+ .clkflags = (uint16_t)(CLK_SET_RATE_PARENT | \
CLK_SET_RATE_GATE | \
- CLK_IS_BASIC, \
+ CLK_IS_BASIC), \
.typeflags = NA_TYPE_FLAGS, \
.mult = NA_MULT, \
.div = NA_DIV, \
@@ -189,9 +189,9 @@
.type = TYPE_GATE, \
.offset = PERIPH_GATE_SHIFT, \
.width = PERIPH_GATE_WIDTH, \
- .clkflags = CLK_SET_RATE_PARENT | \
+ .clkflags = (uint16_t)(CLK_SET_RATE_PARENT | \
CLK_IGNORE_UNUSED | \
- CLK_IS_BASIC, \
+ CLK_IS_BASIC), \
.typeflags = NA_TYPE_FLAGS, \
.mult = NA_MULT, \
.div = NA_DIV, \
@@ -253,7 +253,7 @@
.type = TYPE_PLL,
.offset = NA_SHIFT,
.width = NA_WIDTH,
- .clkflags = CLK_SET_RATE_NO_REPARENT,
+ .clkflags = (uint16_t)CLK_SET_RATE_NO_REPARENT,
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
@@ -265,7 +265,7 @@
.type = TYPE_PLL,
.offset = NA_SHIFT,
.width = NA_WIDTH,
- .clkflags = CLK_IGNORE_UNUSED | CLK_SET_RATE_NO_REPARENT,
+ .clkflags = (uint16_t)(CLK_IGNORE_UNUSED | CLK_SET_RATE_NO_REPARENT),
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
@@ -277,7 +277,7 @@
.type = TYPE_MUX,
.offset = PLL_PRESRC_MUX_SHIFT,
.width = PLL_PRESRC_MUX_WIDTH,
- .clkflags = CLK_IS_BASIC,
+ .clkflags = (uint16_t)CLK_IS_BASIC,
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
@@ -289,7 +289,7 @@
.type = TYPE_FIXEDFACTOR,
.offset = NA_SHIFT,
.width = NA_WIDTH,
- .clkflags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
+ .clkflags = (uint16_t)(CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT),
.typeflags = NA_TYPE_FLAGS,
.mult = 1,
.div = 2,
@@ -301,9 +301,9 @@
.type = TYPE_MUX,
.offset = PLL_DIV2_MUX_SHIFT,
.width = PLL_DIV2_MUX_WIDTH,
- .clkflags = CLK_SET_RATE_NO_REPARENT |
+ .clkflags = (uint16_t)(CLK_SET_RATE_NO_REPARENT |
CLK_SET_RATE_PARENT |
- CLK_IS_BASIC,
+ CLK_IS_BASIC),
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
@@ -315,7 +315,7 @@
.type = TYPE_MUX,
.offset = PLL_POSTSRC_MUX_SHIFT,
.width = PLL_POSTSRC_MUX_WIDTH,
- .clkflags = CLK_IS_BASIC,
+ .clkflags = (uint16_t)CLK_IS_BASIC,
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
@@ -327,9 +327,9 @@
.type = TYPE_MUX,
.offset = PLL_BYPASS_MUX_SHIFT,
.width = PLL_BYPASS_MUX_WIDTH,
- .clkflags = CLK_SET_RATE_NO_REPARENT |
+ .clkflags = (uint16_t)(CLK_SET_RATE_NO_REPARENT |
CLK_SET_RATE_PARENT |
- CLK_IS_BASIC,
+ CLK_IS_BASIC),
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
@@ -341,7 +341,7 @@
.type = TYPE_MUX,
.offset = PERIPH_MUX_SHIFT,
.width = PERIPH_MUX_WIDTH,
- .clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC,
+ .clkflags = (uint16_t)(CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC),
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
@@ -350,8 +350,8 @@
.type = TYPE_DIV1,
.offset = PERIPH_DIV1_SHIFT,
.width = PERIPH_DIV1_WIDTH,
- .clkflags = CLK_IS_BASIC,
- .typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+ .clkflags = (uint16_t)CLK_IS_BASIC,
+ .typeflags = (uint16_t)(CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO),
.mult = NA_MULT,
.div = NA_DIV,
},
@@ -386,9 +386,9 @@
.type = TYPE_MUX,
.offset = PERIPH_MUX_SHIFT,
.width = PERIPH_MUX_WIDTH,
- .clkflags = CLK_SET_RATE_NO_REPARENT |
- CLK_SET_RATE_PARENT | CLK_IS_BASIC,
- .typeflags = CLK_FRAC,
+ .clkflags = (uint16_t)(CLK_SET_RATE_NO_REPARENT |
+ CLK_SET_RATE_PARENT | CLK_IS_BASIC),
+ .typeflags = (uint16_t)CLK_FRAC,
.mult = NA_MULT,
.div = NA_DIV,
},
@@ -396,10 +396,10 @@
.type = TYPE_DIV1,
.offset = PERIPH_DIV1_SHIFT,
.width = PERIPH_DIV1_WIDTH,
- .clkflags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
- CLK_IS_BASIC,
- .typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
- CLK_FRAC,
+ .clkflags = (uint16_t)(CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
+ CLK_IS_BASIC),
+ .typeflags = (uint16_t)(CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
+ CLK_FRAC),
.mult = NA_MULT,
.div = NA_DIV,
},
@@ -407,10 +407,10 @@
.type = TYPE_DIV2,
.offset = PERIPH_DIV2_SHIFT,
.width = PERIPH_DIV2_WIDTH,
- .clkflags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
- CLK_IS_BASIC,
- .typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
- CLK_FRAC,
+ .clkflags = (uint16_t)(CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
+ CLK_IS_BASIC),
+ .typeflags = (uint16_t)(CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
+ CLK_FRAC),
.mult = NA_MULT,
.div = NA_DIV,
},
@@ -418,9 +418,9 @@
.type = TYPE_GATE,
.offset = PERIPH_GATE_SHIFT,
.width = PERIPH_GATE_WIDTH,
- .clkflags = CLK_SET_RATE_PARENT |
+ .clkflags = (uint16_t)(CLK_SET_RATE_PARENT |
CLK_SET_RATE_GATE |
- CLK_IS_BASIC,
+ CLK_IS_BASIC),
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
@@ -435,8 +435,8 @@
.type = TYPE_GATE,
.offset = USB_GATE_SHIFT,
.width = PERIPH_GATE_WIDTH,
- .clkflags = CLK_SET_RATE_PARENT | CLK_IS_BASIC |
- CLK_SET_RATE_GATE,
+ .clkflags = (uint16_t)(CLK_SET_RATE_PARENT | CLK_IS_BASIC |
+ CLK_SET_RATE_GATE),
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
@@ -448,8 +448,8 @@
.type = TYPE_DIV1,
.offset = 8,
.width = 6,
- .clkflags = CLK_IS_BASIC,
- .typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+ .clkflags = (uint16_t)CLK_IS_BASIC,
+ .typeflags = (uint16_t)(CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO),
.mult = NA_MULT,
.div = NA_DIV,
},
@@ -460,8 +460,8 @@
.type = TYPE_DIV1,
.offset = 8,
.width = 6,
- .clkflags = CLK_SET_RATE_PARENT | CLK_IS_BASIC,
- .typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+ .clkflags = (uint16_t)(CLK_SET_RATE_PARENT | CLK_IS_BASIC),
+ .typeflags = (uint16_t)(CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO),
.mult = NA_MULT,
.div = NA_DIV,
},
@@ -481,9 +481,9 @@
.type = TYPE_GATE,
.offset = 25,
.width = PERIPH_GATE_WIDTH,
- .clkflags = CLK_IGNORE_UNUSED |
+ .clkflags = (uint16_t)(CLK_IGNORE_UNUSED |
CLK_SET_RATE_PARENT |
- CLK_IS_BASIC,
+ CLK_IS_BASIC),
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
@@ -495,9 +495,9 @@
.type = TYPE_GATE,
.offset = 24,
.width = PERIPH_GATE_WIDTH,
- .clkflags = CLK_IGNORE_UNUSED |
+ .clkflags = (uint16_t)(CLK_IGNORE_UNUSED |
CLK_SET_RATE_PARENT |
- CLK_IS_BASIC,
+ CLK_IS_BASIC),
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
@@ -509,9 +509,9 @@
.type = TYPE_MUX,
.offset = 0,
.width = 1,
- .clkflags = CLK_SET_RATE_PARENT |
+ .clkflags = (uint16_t)(CLK_SET_RATE_PARENT |
CLK_SET_RATE_NO_REPARENT |
- CLK_IS_BASIC,
+ CLK_IS_BASIC),
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
@@ -524,8 +524,8 @@
.type = TYPE_DIV1,
.offset = 8,
.width = 6,
- .clkflags = CLK_IS_BASIC | CLK_IS_CRITICAL,
- .typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+ .clkflags = (uint16_t)(CLK_IS_BASIC | CLK_IS_CRITICAL),
+ .typeflags = (uint16_t)(CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO),
.mult = NA_MULT,
.div = NA_DIV,
},
@@ -537,8 +537,8 @@
.type = TYPE_DIV1,
.offset = PERIPH_DIV1_SHIFT,
.width = PERIPH_DIV1_WIDTH,
- .clkflags = CLK_IS_BASIC,
- .typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+ .clkflags = (uint16_t)(CLK_IS_BASIC),
+ .typeflags = (uint16_t)(CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO),
.mult = NA_MULT,
.div = NA_DIV,
},
@@ -546,8 +546,8 @@
.type = TYPE_DIV2,
.offset = PERIPH_DIV2_SHIFT,
.width = PERIPH_DIV2_WIDTH,
- .clkflags = CLK_IS_BASIC | CLK_SET_RATE_PARENT,
- .typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+ .clkflags = (uint16_t)(CLK_IS_BASIC | CLK_SET_RATE_PARENT),
+ .typeflags = (uint16_t)(CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO),
.mult = NA_MULT,
.div = NA_DIV,
},
@@ -555,7 +555,7 @@
.type = TYPE_GATE,
.offset = PERIPH_GATE_SHIFT,
.width = PERIPH_GATE_WIDTH,
- .clkflags = CLK_SET_RATE_PARENT | CLK_IS_BASIC,
+ .clkflags = (uint16_t)(CLK_SET_RATE_PARENT | CLK_IS_BASIC),
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
@@ -567,7 +567,7 @@
.type = TYPE_GATE,
.offset = 25,
.width = PERIPH_GATE_WIDTH,
- .clkflags = CLK_SET_RATE_PARENT | CLK_IS_BASIC,
+ .clkflags = (uint16_t)(CLK_SET_RATE_PARENT | CLK_IS_BASIC),
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
@@ -579,7 +579,7 @@
.type = TYPE_GATE,
.offset = 26,
.width = PERIPH_GATE_WIDTH,
- .clkflags = CLK_SET_RATE_PARENT | CLK_IS_BASIC,
+ .clkflags = (uint16_t)(CLK_SET_RATE_PARENT | CLK_IS_BASIC),
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
@@ -592,8 +592,8 @@
.type = TYPE_DIV1,
.offset = 8,
.width = 6,
- .clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC,
- .typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+ .clkflags = (uint16_t)(CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC),
+ .typeflags = (uint16_t)(CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO),
.mult = NA_MULT,
.div = NA_DIV,
},
@@ -601,9 +601,9 @@
.type = TYPE_DIV2,
.offset = 16,
.width = 6,
- .clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC |
- CLK_SET_RATE_PARENT,
- .typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+ .clkflags = (uint16_t)(CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC |
+ CLK_SET_RATE_PARENT),
+ .typeflags = (uint16_t)(CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO),
.mult = NA_MULT,
.div = NA_DIV,
},
@@ -614,9 +614,9 @@
.type = TYPE_MUX,
.offset = 1,
.width = 1,
- .clkflags = CLK_SET_RATE_PARENT |
+ .clkflags = (uint16_t)(CLK_SET_RATE_PARENT |
CLK_SET_RATE_NO_REPARENT |
- CLK_IS_BASIC,
+ CLK_IS_BASIC),
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
@@ -628,9 +628,9 @@
.type = TYPE_MUX,
.offset = 6,
.width = 1,
- .clkflags = CLK_SET_RATE_PARENT |
+ .clkflags = (uint16_t)(CLK_SET_RATE_PARENT |
CLK_SET_RATE_NO_REPARENT |
- CLK_IS_BASIC,
+ CLK_IS_BASIC),
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
@@ -642,9 +642,9 @@
.type = TYPE_MUX,
.offset = 11,
.width = 1,
- .clkflags = CLK_SET_RATE_PARENT |
+ .clkflags = (uint16_t)(CLK_SET_RATE_PARENT |
CLK_SET_RATE_NO_REPARENT |
- CLK_IS_BASIC,
+ CLK_IS_BASIC),
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
@@ -656,9 +656,9 @@
.type = TYPE_MUX,
.offset = 16,
.width = 1,
- .clkflags = CLK_SET_RATE_PARENT |
+ .clkflags = (uint16_t)(CLK_SET_RATE_PARENT |
CLK_SET_RATE_NO_REPARENT |
- CLK_IS_BASIC,
+ CLK_IS_BASIC),
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
@@ -670,7 +670,7 @@
.type = TYPE_GATE,
.offset = 25,
.width = PERIPH_GATE_WIDTH,
- .clkflags = CLK_SET_RATE_PARENT | CLK_IS_BASIC,
+ .clkflags = (uint16_t)(CLK_SET_RATE_PARENT | CLK_IS_BASIC),
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
@@ -682,7 +682,7 @@
.type = TYPE_GATE,
.offset = 26,
.width = PERIPH_GATE_WIDTH,
- .clkflags = CLK_IS_BASIC,
+ .clkflags = (uint16_t)(CLK_IS_BASIC),
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
@@ -694,9 +694,9 @@
.type = TYPE_MUX,
.offset = 20,
.width = 2,
- .clkflags = CLK_SET_RATE_PARENT |
+ .clkflags = (uint16_t)(CLK_SET_RATE_PARENT |
CLK_SET_RATE_NO_REPARENT |
- CLK_IS_BASIC,
+ CLK_IS_BASIC),
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
@@ -708,9 +708,9 @@
.type = TYPE_MUX,
.offset = 0,
.width = 7,
- .clkflags = CLK_SET_RATE_PARENT |
+ .clkflags = (uint16_t)(CLK_SET_RATE_PARENT |
CLK_SET_RATE_NO_REPARENT |
- CLK_IS_BASIC,
+ CLK_IS_BASIC),
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
@@ -722,9 +722,9 @@
.type = TYPE_MUX,
.offset = 15,
.width = 1,
- .clkflags = CLK_SET_RATE_PARENT |
+ .clkflags = (uint16_t)(CLK_SET_RATE_PARENT |
CLK_SET_RATE_NO_REPARENT |
- CLK_IS_BASIC,
+ CLK_IS_BASIC),
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
@@ -736,9 +736,9 @@
.type = TYPE_MUX,
.offset = 7,
.width = 1,
- .clkflags = CLK_SET_RATE_PARENT |
+ .clkflags = (uint16_t)(CLK_SET_RATE_PARENT |
CLK_SET_RATE_NO_REPARENT |
- CLK_IS_BASIC,
+ CLK_IS_BASIC),
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
@@ -750,9 +750,9 @@
.type = TYPE_MUX,
.offset = 22,
.width = 1,
- .clkflags = CLK_SET_RATE_PARENT |
+ .clkflags = (uint16_t)(CLK_SET_RATE_PARENT |
CLK_SET_RATE_NO_REPARENT |
- CLK_IS_BASIC,
+ CLK_IS_BASIC),
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
@@ -764,8 +764,8 @@
.type = TYPE_GATE,
.offset = 25,
.width = PERIPH_GATE_WIDTH,
- .clkflags = CLK_IGNORE_UNUSED |
- CLK_IS_BASIC,
+ .clkflags = (uint16_t)(CLK_IGNORE_UNUSED |
+ CLK_IS_BASIC),
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
@@ -777,9 +777,9 @@
.type = TYPE_MUX,
.offset = 0,
.width = 3,
- .clkflags = CLK_SET_RATE_PARENT |
+ .clkflags = (uint16_t)(CLK_SET_RATE_PARENT |
CLK_SET_RATE_NO_REPARENT |
- CLK_IS_BASIC,
+ CLK_IS_BASIC),
.typeflags = NA_TYPE_FLAGS,
.mult = NA_MULT,
.div = NA_DIV,
@@ -792,8 +792,8 @@
.type = TYPE_DIV1,
.offset = 8,
.width = 6,
- .clkflags = CLK_IS_BASIC,
- .typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+ .clkflags = (uint16_t)CLK_IS_BASIC,
+ .typeflags = (uint16_t)(CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO),
.mult = NA_MULT,
.div = NA_DIV,
},
@@ -831,7 +831,7 @@
.status_reg = CRF_APB_PLL_STATUS,
.parents = &((int32_t []) {CLK_APLL_PRE_SRC, CLK_NA_PARENT}),
.nodes = &ignore_unused_pll_nodes,
- .num_nodes = ARRAY_SIZE(ignore_unused_pll_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(ignore_unused_pll_nodes),
},
[CLK_APLL_PRE_SRC] = {
.name = "apll_pre_src",
@@ -849,7 +849,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_pll_pre_src_nodes,
- .num_nodes = ARRAY_SIZE(generic_pll_pre_src_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_pre_src_nodes),
},
[CLK_APLL_HALF] = {
.name = "apll_half",
@@ -857,7 +857,7 @@
.status_reg = CRF_APB_PLL_STATUS,
.parents = &((int32_t []) {CLK_APLL_INT, CLK_NA_PARENT}),
.nodes = &generic_pll_half_nodes,
- .num_nodes = ARRAY_SIZE(generic_pll_half_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_half_nodes),
},
[CLK_APLL_INT_MUX] = {
.name = "apll_int_mux",
@@ -869,7 +869,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_pll_int_nodes,
- .num_nodes = ARRAY_SIZE(generic_pll_int_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_int_nodes),
},
[CLK_APLL_POST_SRC] = {
.name = "apll_post_src",
@@ -887,7 +887,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_pll_post_src_nodes,
- .num_nodes = ARRAY_SIZE(generic_pll_post_src_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_post_src_nodes),
},
[CLK_APLL] = {
.name = "apll",
@@ -899,7 +899,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_pll_system_nodes,
- .num_nodes = ARRAY_SIZE(generic_pll_system_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_system_nodes),
},
[CLK_DPLL_INT] = {
.name = "dpll_int",
@@ -907,7 +907,7 @@
.status_reg = CRF_APB_PLL_STATUS,
.parents = &((int32_t []) {CLK_DPLL_PRE_SRC, CLK_NA_PARENT}),
.nodes = &generic_pll_nodes,
- .num_nodes = ARRAY_SIZE(generic_pll_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_nodes),
},
[CLK_DPLL_PRE_SRC] = {
.name = "dpll_pre_src",
@@ -925,7 +925,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_pll_pre_src_nodes,
- .num_nodes = ARRAY_SIZE(generic_pll_pre_src_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_pre_src_nodes),
},
[CLK_DPLL_HALF] = {
.name = "dpll_half",
@@ -933,7 +933,7 @@
.status_reg = CRF_APB_PLL_STATUS,
.parents = &((int32_t []) {CLK_DPLL_INT, CLK_NA_PARENT}),
.nodes = &generic_pll_half_nodes,
- .num_nodes = ARRAY_SIZE(generic_pll_half_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_half_nodes),
},
[CLK_DPLL_INT_MUX] = {
.name = "dpll_int_mux",
@@ -945,7 +945,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_pll_int_nodes,
- .num_nodes = ARRAY_SIZE(generic_pll_int_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_int_nodes),
},
[CLK_DPLL_POST_SRC] = {
.name = "dpll_post_src",
@@ -963,7 +963,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_pll_post_src_nodes,
- .num_nodes = ARRAY_SIZE(generic_pll_post_src_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_post_src_nodes),
},
[CLK_DPLL] = {
.name = "dpll",
@@ -975,7 +975,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_pll_system_nodes,
- .num_nodes = ARRAY_SIZE(generic_pll_system_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_system_nodes),
},
[CLK_VPLL_INT] = {
.name = "vpll_int",
@@ -983,7 +983,7 @@
.status_reg = CRF_APB_PLL_STATUS,
.parents = &((int32_t []) {CLK_VPLL_PRE_SRC, CLK_NA_PARENT}),
.nodes = &ignore_unused_pll_nodes,
- .num_nodes = ARRAY_SIZE(ignore_unused_pll_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(ignore_unused_pll_nodes),
},
[CLK_VPLL_PRE_SRC] = {
.name = "vpll_pre_src",
@@ -1001,7 +1001,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_pll_pre_src_nodes,
- .num_nodes = ARRAY_SIZE(generic_pll_pre_src_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_pre_src_nodes),
},
[CLK_VPLL_HALF] = {
.name = "vpll_half",
@@ -1009,7 +1009,7 @@
.status_reg = CRF_APB_PLL_STATUS,
.parents = &((int32_t []) {CLK_VPLL_INT, CLK_NA_PARENT}),
.nodes = &generic_pll_half_nodes,
- .num_nodes = ARRAY_SIZE(generic_pll_half_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_half_nodes),
},
[CLK_VPLL_INT_MUX] = {
.name = "vpll_int_mux",
@@ -1021,7 +1021,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_pll_int_nodes,
- .num_nodes = ARRAY_SIZE(generic_pll_int_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_int_nodes),
},
[CLK_VPLL_POST_SRC] = {
.name = "vpll_post_src",
@@ -1051,7 +1051,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_pll_system_nodes,
- .num_nodes = ARRAY_SIZE(generic_pll_system_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_system_nodes),
},
[CLK_IOPLL_INT] = {
.name = "iopll_int",
@@ -1059,7 +1059,7 @@
.status_reg = CRF_APB_PLL_STATUS,
.parents = &((int32_t []) {CLK_IOPLL_PRE_SRC, CLK_NA_PARENT}),
.nodes = &generic_pll_nodes,
- .num_nodes = ARRAY_SIZE(generic_pll_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_nodes),
},
[CLK_IOPLL_PRE_SRC] = {
.name = "iopll_pre_src",
@@ -1077,7 +1077,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_pll_pre_src_nodes,
- .num_nodes = ARRAY_SIZE(generic_pll_pre_src_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_pre_src_nodes),
},
[CLK_IOPLL_HALF] = {
.name = "iopll_half",
@@ -1085,7 +1085,7 @@
.status_reg = CRF_APB_PLL_STATUS,
.parents = &((int32_t []) {CLK_IOPLL_INT, CLK_NA_PARENT}),
.nodes = &generic_pll_half_nodes,
- .num_nodes = ARRAY_SIZE(generic_pll_half_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_half_nodes),
},
[CLK_IOPLL_INT_MUX] = {
.name = "iopll_int_mux",
@@ -1097,7 +1097,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_pll_int_nodes,
- .num_nodes = ARRAY_SIZE(generic_pll_int_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_int_nodes),
},
[CLK_IOPLL_POST_SRC] = {
.name = "iopll_post_src",
@@ -1115,7 +1115,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_pll_post_src_nodes,
- .num_nodes = ARRAY_SIZE(generic_pll_post_src_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_post_src_nodes),
},
[CLK_IOPLL] = {
.name = "iopll",
@@ -1127,7 +1127,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_pll_system_nodes,
- .num_nodes = ARRAY_SIZE(generic_pll_system_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_system_nodes),
},
[CLK_RPLL_INT] = {
.name = "rpll_int",
@@ -1135,7 +1135,7 @@
.status_reg = CRF_APB_PLL_STATUS,
.parents = &((int32_t []) {CLK_RPLL_PRE_SRC, CLK_NA_PARENT}),
.nodes = &generic_pll_nodes,
- .num_nodes = ARRAY_SIZE(generic_pll_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_nodes),
},
[CLK_RPLL_PRE_SRC] = {
.name = "rpll_pre_src",
@@ -1154,7 +1154,7 @@
}),
.nodes = &generic_pll_pre_src_nodes,
- .num_nodes = ARRAY_SIZE(generic_pll_pre_src_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_pre_src_nodes),
},
[CLK_RPLL_HALF] = {
.name = "rpll_half",
@@ -1162,7 +1162,7 @@
.status_reg = CRF_APB_PLL_STATUS,
.parents = &((int32_t []) {CLK_RPLL_INT, CLK_NA_PARENT}),
.nodes = &generic_pll_half_nodes,
- .num_nodes = ARRAY_SIZE(generic_pll_half_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_half_nodes),
},
[CLK_RPLL_INT_MUX] = {
.name = "rpll_int_mux",
@@ -1174,7 +1174,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_pll_int_nodes,
- .num_nodes = ARRAY_SIZE(generic_pll_int_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_int_nodes),
},
[CLK_RPLL_POST_SRC] = {
.name = "rpll_post_src",
@@ -1192,7 +1192,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_pll_post_src_nodes,
- .num_nodes = ARRAY_SIZE(generic_pll_post_src_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_post_src_nodes),
},
[CLK_RPLL] = {
.name = "rpll",
@@ -1204,7 +1204,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_pll_system_nodes,
- .num_nodes = ARRAY_SIZE(generic_pll_system_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_pll_system_nodes),
},
/* Peripheral Clocks */
[CLK_ACPU] = {
@@ -1219,7 +1219,7 @@
CLK_NA_PARENT
}),
.nodes = &acpu_nodes,
- .num_nodes = ARRAY_SIZE(acpu_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(acpu_nodes),
},
[CLK_ACPU_FULL] = {
.name = "acpu_full",
@@ -1244,7 +1244,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_gate_nodes),
},
[CLK_DBG_FPD] = {
.name = "dbg_fpd",
@@ -1258,7 +1258,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_gate_nodes),
},
[CLK_DBG_TSTMP] = {
.name = "dbg_tstmp",
@@ -1272,7 +1272,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_nodes),
},
[CLK_DP_VIDEO_REF] = {
.name = "dp_video_ref",
@@ -1286,7 +1286,7 @@
CLK_NA_PARENT
}),
.nodes = &dp_audio_video_ref_nodes,
- .num_nodes = ARRAY_SIZE(dp_audio_video_ref_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(dp_audio_video_ref_nodes),
},
[CLK_DP_AUDIO_REF] = {
.name = "dp_audio_ref",
@@ -1300,7 +1300,7 @@
CLK_NA_PARENT
}),
.nodes = &dp_audio_video_ref_nodes,
- .num_nodes = ARRAY_SIZE(dp_audio_video_ref_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(dp_audio_video_ref_nodes),
},
[CLK_DP_STC_REF] = {
.name = "dp_stc_ref",
@@ -1314,7 +1314,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_div_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_div_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_div_gate_nodes),
},
[CLK_DPDMA_REF] = {
.name = "dpdma_ref",
@@ -1328,7 +1328,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_gate_nodes),
},
[CLK_DDR_REF] = {
.name = "ddr_ref",
@@ -1340,7 +1340,7 @@
CLK_NA_PARENT
}),
.nodes = &ddr_nodes,
- .num_nodes = ARRAY_SIZE(ddr_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(ddr_nodes),
},
[CLK_GPU_REF] = {
.name = "gpu_ref",
@@ -1354,7 +1354,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_gate_nodes),
},
[CLK_SATA_REF] = {
.name = "sata_ref",
@@ -1368,7 +1368,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_gate_nodes),
},
[CLK_PCIE_REF] = {
.name = "pcie_ref",
@@ -1382,7 +1382,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_gate_nodes),
},
[CLK_GDMA_REF] = {
.name = "gdma_ref",
@@ -1396,7 +1396,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_gate_nodes),
},
[CLK_GTGREF0_REF] = {
.name = "gtgref0_ref",
@@ -1410,7 +1410,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_gate_nodes),
},
[CLK_TOPSW_MAIN] = {
.name = "topsw_main",
@@ -1424,7 +1424,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_unused_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_unused_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_unused_gate_nodes),
},
[CLK_TOPSW_LSBUS] = {
.name = "topsw_lsbus",
@@ -1438,7 +1438,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_unused_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_unused_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_unused_gate_nodes),
},
[CLK_IOU_SWITCH] = {
.name = "iou_switch",
@@ -1452,7 +1452,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_unused_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_unused_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_unused_gate_nodes),
},
[CLK_GEM0_REF_UNGATED] = {
.name = "gem0_ref_ung",
@@ -1574,7 +1574,7 @@
CLK_NA_PARENT
}),
.nodes = &usb_nodes,
- .num_nodes = ARRAY_SIZE(usb_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(usb_nodes),
},
[CLK_USB1_BUS_REF] = {
.name = "usb1_bus_ref",
@@ -1588,7 +1588,7 @@
CLK_NA_PARENT
}),
.nodes = &usb_nodes,
- .num_nodes = ARRAY_SIZE(usb_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(usb_nodes),
},
[CLK_USB3_DUAL_REF] = {
.name = "usb3_dual_ref",
@@ -1602,7 +1602,7 @@
CLK_NA_PARENT
}),
.nodes = &usb_nodes,
- .num_nodes = ARRAY_SIZE(usb_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(usb_nodes),
},
[CLK_QSPI_REF] = {
.name = "qspi_ref",
@@ -1616,7 +1616,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_div_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_div_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_div_gate_nodes),
},
[CLK_SDIO0_REF] = {
.name = "sdio0_ref",
@@ -1630,7 +1630,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_div_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_div_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_div_gate_nodes),
},
[CLK_SDIO1_REF] = {
.name = "sdio1_ref",
@@ -1644,7 +1644,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_div_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_div_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_div_gate_nodes),
},
[CLK_UART0_REF] = {
.name = "uart0_ref",
@@ -1658,7 +1658,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_div_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_div_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_div_gate_nodes),
},
[CLK_UART1_REF] = {
.name = "uart1_ref",
@@ -1672,7 +1672,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_div_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_div_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_div_gate_nodes),
},
[CLK_SPI0_REF] = {
.name = "spi0_ref",
@@ -1686,7 +1686,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_div_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_div_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_div_gate_nodes),
},
[CLK_SPI1_REF] = {
.name = "spi1_ref",
@@ -1700,7 +1700,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_div_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_div_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_div_gate_nodes),
},
[CLK_CAN0_REF] = {
.name = "can0_ref",
@@ -1714,7 +1714,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_div_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_div_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_div_gate_nodes),
},
[CLK_CAN1_REF] = {
.name = "can1_ref",
@@ -1728,7 +1728,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_div_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_div_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_div_gate_nodes),
},
[CLK_NAND_REF] = {
.name = "nand_ref",
@@ -1742,7 +1742,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_div_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_div_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_div_gate_nodes),
},
[CLK_GEM_TSU_REF] = {
.name = "gem_tsu_ref",
@@ -1756,7 +1756,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_div_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_div_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_div_gate_nodes),
},
[CLK_DLL_REF] = {
.name = "dll_ref",
@@ -1768,7 +1768,7 @@
CLK_NA_PARENT
}),
.nodes = &dll_ref_nodes,
- .num_nodes = ARRAY_SIZE(dll_ref_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(dll_ref_nodes),
},
[CLK_ADMA_REF] = {
.name = "adma_ref",
@@ -1782,7 +1782,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_gate_nodes),
},
[CLK_DBG_LPD] = {
.name = "dbg_lpd",
@@ -1796,7 +1796,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_gate_nodes),
},
[CLK_CPU_R5] = {
.name = "cpu_r5",
@@ -1810,7 +1810,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_unused_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_unused_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_unused_gate_nodes),
},
[CLK_CSU_PLL] = {
.name = "csu_pll",
@@ -1824,7 +1824,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_gate_nodes),
},
[CLK_PCAP] = {
.name = "pcap",
@@ -1838,7 +1838,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_gate_nodes),
},
[CLK_LPD_LSBUS] = {
.name = "lpd_lsbus",
@@ -1852,7 +1852,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_unused_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_unused_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_unused_gate_nodes),
},
[CLK_LPD_SWITCH] = {
.name = "lpd_switch",
@@ -1866,7 +1866,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_unused_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_unused_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_unused_gate_nodes),
},
[CLK_I2C0_REF] = {
.name = "i2c0_ref",
@@ -1880,7 +1880,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_div_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_div_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_div_gate_nodes),
},
[CLK_I2C1_REF] = {
.name = "i2c1_ref",
@@ -1894,7 +1894,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_div_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_div_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_div_gate_nodes),
},
[CLK_TIMESTAMP_REF] = {
.name = "timestamp_ref",
@@ -1912,7 +1912,7 @@
CLK_NA_PARENT
}),
.nodes = ×tamp_ref_nodes,
- .num_nodes = ARRAY_SIZE(timestamp_ref_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(timestamp_ref_nodes),
},
[CLK_PL0_REF] = {
.name = "pl0_ref",
@@ -1926,7 +1926,7 @@
CLK_NA_PARENT
}),
.nodes = &pl_nodes,
- .num_nodes = ARRAY_SIZE(pl_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(pl_nodes),
},
[CLK_PL1_REF] = {
.name = "pl1_ref",
@@ -1940,7 +1940,7 @@
CLK_NA_PARENT
}),
.nodes = &pl_nodes,
- .num_nodes = ARRAY_SIZE(pl_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(pl_nodes),
},
[CLK_PL2_REF] = {
.name = "pl2_ref",
@@ -1954,7 +1954,7 @@
CLK_NA_PARENT
}),
.nodes = &pl_nodes,
- .num_nodes = ARRAY_SIZE(pl_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(pl_nodes),
},
[CLK_PL3_REF] = {
.name = "pl3_ref",
@@ -1968,7 +1968,7 @@
CLK_NA_PARENT
}),
.nodes = &pl_nodes,
- .num_nodes = ARRAY_SIZE(pl_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(pl_nodes),
},
[CLK_AMS_REF] = {
.name = "ams_ref",
@@ -1982,7 +1982,7 @@
CLK_NA_PARENT
}),
.nodes = &generic_mux_div_div_gate_nodes,
- .num_nodes = ARRAY_SIZE(generic_mux_div_div_gate_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_mux_div_div_gate_nodes),
},
[CLK_IOPLL_TO_FPD] = {
.name = "iopll_to_fpd",
@@ -1990,7 +1990,7 @@
.status_reg = 0,
.parents = &((int32_t []) {CLK_IOPLL, CLK_NA_PARENT}),
.nodes = &generic_domain_crossing_nodes,
- .num_nodes = ARRAY_SIZE(generic_domain_crossing_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_domain_crossing_nodes),
},
[CLK_RPLL_TO_FPD] = {
.name = "rpll_to_fpd",
@@ -1998,7 +1998,7 @@
.status_reg = 0,
.parents = &((int32_t []) {CLK_RPLL, CLK_NA_PARENT}),
.nodes = &rpll_to_fpd_nodes,
- .num_nodes = ARRAY_SIZE(rpll_to_fpd_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(rpll_to_fpd_nodes),
},
[CLK_APLL_TO_LPD] = {
.name = "apll_to_lpd",
@@ -2006,7 +2006,7 @@
.status_reg = 0,
.parents = &((int32_t []) {CLK_APLL, CLK_NA_PARENT}),
.nodes = &generic_domain_crossing_nodes,
- .num_nodes = ARRAY_SIZE(generic_domain_crossing_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_domain_crossing_nodes),
},
[CLK_DPLL_TO_LPD] = {
.name = "dpll_to_lpd",
@@ -2014,7 +2014,7 @@
.status_reg = 0,
.parents = &((int32_t []) {CLK_DPLL, CLK_NA_PARENT}),
.nodes = &generic_domain_crossing_nodes,
- .num_nodes = ARRAY_SIZE(generic_domain_crossing_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_domain_crossing_nodes),
},
[CLK_VPLL_TO_LPD] = {
.name = "vpll_to_lpd",
@@ -2022,7 +2022,7 @@
.status_reg = 0,
.parents = &((int32_t []) {CLK_VPLL, CLK_NA_PARENT}),
.nodes = &generic_domain_crossing_nodes,
- .num_nodes = ARRAY_SIZE(generic_domain_crossing_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(generic_domain_crossing_nodes),
},
[CLK_GEM0_TX] = {
.name = "gem0_tx",
@@ -2033,7 +2033,7 @@
CLK_NA_PARENT
}),
.nodes = &gem_tx_nodes,
- .num_nodes = ARRAY_SIZE(gem_tx_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(gem_tx_nodes),
},
[CLK_GEM1_TX] = {
.name = "gem1_tx",
@@ -2044,7 +2044,7 @@
CLK_NA_PARENT
}),
.nodes = &gem_tx_nodes,
- .num_nodes = ARRAY_SIZE(gem_tx_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(gem_tx_nodes),
},
[CLK_GEM2_TX] = {
.name = "gem2_tx",
@@ -2055,7 +2055,7 @@
CLK_NA_PARENT
}),
.nodes = &gem_tx_nodes,
- .num_nodes = ARRAY_SIZE(gem_tx_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(gem_tx_nodes),
},
[CLK_GEM3_TX] = {
.name = "gem3_tx",
@@ -2066,7 +2066,7 @@
CLK_NA_PARENT
}),
.nodes = &gem_tx_nodes,
- .num_nodes = ARRAY_SIZE(gem_tx_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(gem_tx_nodes),
},
[CLK_GEM0_RX] = {
.name = "gem0_rx",
@@ -2077,7 +2077,7 @@
CLK_NA_PARENT
}),
.nodes = &gem_rx_nodes,
- .num_nodes = ARRAY_SIZE(gem_rx_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(gem_rx_nodes),
},
[CLK_GEM1_RX] = {
.name = "gem1_rx",
@@ -2088,7 +2088,7 @@
CLK_NA_PARENT
}),
.nodes = &gem_rx_nodes,
- .num_nodes = ARRAY_SIZE(gem_rx_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(gem_rx_nodes),
},
[CLK_GEM2_RX] = {
.name = "gem2_rx",
@@ -2099,7 +2099,7 @@
CLK_NA_PARENT
}),
.nodes = &gem_rx_nodes,
- .num_nodes = ARRAY_SIZE(gem_rx_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(gem_rx_nodes),
},
[CLK_GEM3_RX] = {
.name = "gem3_rx",
@@ -2110,7 +2110,7 @@
CLK_NA_PARENT
}),
.nodes = &gem_rx_nodes,
- .num_nodes = ARRAY_SIZE(gem_rx_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(gem_rx_nodes),
},
[CLK_ACPU_HALF] = {
.name = "acpu_half",
@@ -2121,7 +2121,7 @@
CLK_NA_PARENT
}),
.nodes = &acpu_half_nodes,
- .num_nodes = ARRAY_SIZE(acpu_half_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(acpu_half_nodes),
},
[CLK_FPD_WDT] = {
.name = "fpd_wdt",
@@ -2133,7 +2133,7 @@
CLK_NA_PARENT
}),
.nodes = &wdt_nodes,
- .num_nodes = ARRAY_SIZE(wdt_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(wdt_nodes),
},
[CLK_GPU_PP0_REF] = {
.name = "gpu_pp0_ref",
@@ -2144,7 +2144,7 @@
CLK_NA_PARENT
}),
.nodes = &gpu_pp0_nodes,
- .num_nodes = ARRAY_SIZE(gpu_pp0_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(gpu_pp0_nodes),
},
[CLK_GPU_PP1_REF] = {
.name = "gpu_pp1_ref",
@@ -2155,7 +2155,7 @@
CLK_NA_PARENT
}),
.nodes = &gpu_pp1_nodes,
- .num_nodes = ARRAY_SIZE(gpu_pp1_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(gpu_pp1_nodes),
},
[CLK_GEM_TSU] = {
.name = "gem_tsu",
@@ -2169,7 +2169,7 @@
CLK_NA_PARENT
}),
.nodes = &gem_tsu_nodes,
- .num_nodes = ARRAY_SIZE(gem_tsu_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(gem_tsu_nodes),
},
[CLK_CPU_R5_CORE] = {
.name = "cpu_r5_core",
@@ -2181,7 +2181,7 @@
CLK_NA_PARENT
}),
.nodes = &cpu_r5_core_nodes,
- .num_nodes = ARRAY_SIZE(cpu_r5_core_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(cpu_r5_core_nodes),
},
[CLK_CAN0_MIO] = {
.name = "can0_mio",
@@ -2209,7 +2209,7 @@
CLK_NA_PARENT
}),
.nodes = &can0_nodes,
- .num_nodes = ARRAY_SIZE(can0_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(can0_nodes),
},
[CLK_CAN1] = {
.name = "can1",
@@ -2221,7 +2221,7 @@
CLK_NA_PARENT
}),
.nodes = &can1_nodes,
- .num_nodes = ARRAY_SIZE(can1_nodes),
+ .num_nodes = (uint8_t)ARRAY_SIZE(can1_nodes),
},
[CLK_LPD_WDT] = {
.name = "lpd_wdt",
@@ -2625,7 +2625,7 @@
}
for (i = 0; i < 3U; i++) {
- parents[i] = clk_parents[index + i];
+ parents[i] = (uint32_t)clk_parents[index + i];
if (clk_parents[index + i] == CLK_NA_PARENT) {
break;
}
@@ -2691,7 +2691,7 @@
*max_div = (((uint32_t)1U <<
((uint32_t)BIT(nodes[i].width) - (uint32_t)1U)));
} else {
- *max_div = BIT(nodes[i].width) - 1U;
+ *max_div = (uint32_t)BIT(nodes[i].width) - (uint32_t)1U;
}
return PM_RET_SUCCESS;
}
@@ -2996,7 +2996,7 @@
if ((pll == NULL) || ((mode != PLL_FRAC_MODE) && (mode != PLL_INT_MODE))) {
return PM_RET_ERROR_ARGS;
}
- pll->mode = mode;
+ pll->mode = (uint8_t)mode;
return PM_RET_SUCCESS;
}
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
index 5411ec9..a8404ba 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
@@ -703,7 +703,7 @@
IOCTL_AFI,
};
uint8_t i, ioctl_id;
- int32_t ret;
+ enum pm_ret_status ret;
for (i = 0U; i < ARRAY_SIZE(supported_ids); i++) {
ioctl_id = supported_ids[i];
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
index d9d1161..763d9fa 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
@@ -2058,7 +2058,7 @@
if ((grps + index + i) >= end_of_grp_offset) {
break;
}
- groups[i] = (grps + index + i);
+ groups[i] = (uint16_t)(grps + index + i);
}
return PM_RET_SUCCESS;
diff --git a/plat/xilinx/zynqmp/pm_service/pm_client.c b/plat/xilinx/zynqmp/pm_service/pm_client.c
index fdbf590..9882e30 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_client.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_client.c
@@ -46,22 +46,22 @@
/* Order in pm_procs_all array must match cpu ids */
static const struct pm_proc pm_procs_all[] = {
{
- .node_id = NODE_APU_0,
+ .node_id = (uint32_t)NODE_APU_0,
.pwrdn_mask = APU_0_PWRCTL_CPUPWRDWNREQ_MASK,
.ipi = &apu_ipi,
},
{
- .node_id = NODE_APU_1,
+ .node_id = (uint32_t)NODE_APU_1,
.pwrdn_mask = APU_1_PWRCTL_CPUPWRDWNREQ_MASK,
.ipi = &apu_ipi,
},
{
- .node_id = NODE_APU_2,
+ .node_id = (uint32_t)NODE_APU_2,
.pwrdn_mask = APU_2_PWRCTL_CPUPWRDWNREQ_MASK,
.ipi = &apu_ipi,
},
{
- .node_id = NODE_APU_3,
+ .node_id = (uint32_t)NODE_APU_3,
.pwrdn_mask = APU_3_PWRCTL_CPUPWRDWNREQ_MASK,
.ipi = &apu_ipi,
},
@@ -206,9 +206,10 @@
while (reg != 0U) {
enum pm_node_id node;
- uint32_t idx, ret, irq, lowest_set = reg & (-reg);
+ uint32_t idx, irq, lowest_set = reg & (-reg);
+ enum pm_ret_status ret;
- idx = __builtin_ctz(lowest_set);
+ idx = (uint32_t)__builtin_ctz(lowest_set);
irq = base_irq + idx;
if (irq > IRQ_MAX) {
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
index 80871e5..215bf30 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
@@ -51,164 +51,164 @@
/* Dependent APIs for TF-A to check their version from firmware */
static const eemi_api_dependency api_dep_table[] = {
{
- .id = PM_SELF_SUSPEND,
- .api_id = PM_SELF_SUSPEND,
+ .id = (uint8_t)PM_SELF_SUSPEND,
+ .api_id = (uint8_t)PM_SELF_SUSPEND,
},
{
- .id = PM_REQ_WAKEUP,
- .api_id = PM_REQ_WAKEUP,
+ .id = (uint8_t)PM_REQ_WAKEUP,
+ .api_id = (uint8_t)PM_REQ_WAKEUP,
},
{
- .id = PM_ABORT_SUSPEND,
- .api_id = PM_ABORT_SUSPEND,
+ .id = (uint8_t)PM_ABORT_SUSPEND,
+ .api_id = (uint8_t)PM_ABORT_SUSPEND,
},
{
- .id = PM_SET_WAKEUP_SOURCE,
- .api_id = PM_SET_WAKEUP_SOURCE,
+ .id = (uint8_t)PM_SET_WAKEUP_SOURCE,
+ .api_id = (uint8_t)PM_SET_WAKEUP_SOURCE,
},
{
- .id = PM_SYSTEM_SHUTDOWN,
- .api_id = PM_SYSTEM_SHUTDOWN,
+ .id = (uint8_t)PM_SYSTEM_SHUTDOWN,
+ .api_id = (uint8_t)PM_SYSTEM_SHUTDOWN,
},
{
- .id = PM_GET_API_VERSION,
- .api_id = PM_GET_API_VERSION,
+ .id = (uint8_t)PM_GET_API_VERSION,
+ .api_id = (uint8_t)PM_GET_API_VERSION,
},
{
- .id = PM_CLOCK_ENABLE,
- .api_id = PM_PLL_SET_MODE,
+ .id = (uint8_t)PM_CLOCK_ENABLE,
+ .api_id = (uint8_t)PM_PLL_SET_MODE,
},
{
- .id = PM_CLOCK_ENABLE,
- .api_id = PM_CLOCK_ENABLE,
+ .id = (uint8_t)PM_CLOCK_ENABLE,
+ .api_id = (uint8_t)PM_CLOCK_ENABLE,
},
{
- .id = PM_CLOCK_DISABLE,
- .api_id = PM_PLL_SET_MODE,
+ .id = (uint8_t)PM_CLOCK_DISABLE,
+ .api_id = (uint8_t)PM_PLL_SET_MODE,
},
{
- .id = PM_CLOCK_DISABLE,
- .api_id = PM_CLOCK_DISABLE,
+ .id = (uint8_t)PM_CLOCK_DISABLE,
+ .api_id = (uint8_t)PM_CLOCK_DISABLE,
},
{
- .id = PM_CLOCK_GETSTATE,
- .api_id = PM_PLL_GET_MODE,
+ .id = (uint8_t)PM_CLOCK_GETSTATE,
+ .api_id = (uint8_t)PM_PLL_GET_MODE,
},
{
- .id = PM_CLOCK_GETSTATE,
- .api_id = PM_CLOCK_GETSTATE,
+ .id = (uint8_t)PM_CLOCK_GETSTATE,
+ .api_id = (uint8_t)PM_CLOCK_GETSTATE,
},
{
- .id = PM_CLOCK_SETDIVIDER,
- .api_id = PM_PLL_SET_PARAMETER,
+ .id = (uint8_t)PM_CLOCK_SETDIVIDER,
+ .api_id = (uint8_t)PM_PLL_SET_PARAMETER,
},
{
- .id = PM_CLOCK_SETDIVIDER,
- .api_id = PM_CLOCK_SETDIVIDER,
+ .id = (uint8_t)PM_CLOCK_SETDIVIDER,
+ .api_id = (uint8_t)PM_CLOCK_SETDIVIDER,
},
{
- .id = PM_CLOCK_GETDIVIDER,
- .api_id = PM_PLL_GET_PARAMETER,
+ .id = (uint8_t)PM_CLOCK_GETDIVIDER,
+ .api_id = (uint8_t)PM_PLL_GET_PARAMETER,
},
{
- .id = PM_CLOCK_GETDIVIDER,
- .api_id = PM_CLOCK_GETDIVIDER,
+ .id = (uint8_t)PM_CLOCK_GETDIVIDER,
+ .api_id = (uint8_t)PM_CLOCK_GETDIVIDER,
},
{
- .id = PM_CLOCK_SETPARENT,
- .api_id = PM_PLL_SET_PARAMETER,
+ .id = (uint8_t)PM_CLOCK_SETPARENT,
+ .api_id = (uint8_t)PM_PLL_SET_PARAMETER,
},
{
- .id = PM_CLOCK_SETPARENT,
- .api_id = PM_CLOCK_SETPARENT,
+ .id = (uint8_t)PM_CLOCK_SETPARENT,
+ .api_id = (uint8_t)PM_CLOCK_SETPARENT,
},
{
- .id = PM_CLOCK_GETPARENT,
- .api_id = PM_PLL_GET_PARAMETER,
+ .id = (uint8_t)PM_CLOCK_GETPARENT,
+ .api_id = (uint8_t)PM_PLL_GET_PARAMETER,
},
{
- .id = PM_CLOCK_GETPARENT,
- .api_id = PM_CLOCK_GETPARENT,
+ .id = (uint8_t)PM_CLOCK_GETPARENT,
+ .api_id = (uint8_t)PM_CLOCK_GETPARENT,
},
{
- .id = PM_PLL_SET_PARAMETER,
- .api_id = PM_PLL_SET_PARAMETER,
+ .id = (uint8_t)PM_PLL_SET_PARAMETER,
+ .api_id = (uint8_t)PM_PLL_SET_PARAMETER,
},
{
- .id = PM_PLL_GET_PARAMETER,
- .api_id = PM_PLL_GET_PARAMETER,
+ .id = (uint8_t)PM_PLL_GET_PARAMETER,
+ .api_id = (uint8_t)PM_PLL_GET_PARAMETER,
},
{
- .id = PM_PLL_SET_MODE,
- .api_id = PM_PLL_SET_MODE,
+ .id = (uint8_t)PM_PLL_SET_MODE,
+ .api_id = (uint8_t)PM_PLL_SET_MODE,
},
{
- .id = PM_PLL_GET_MODE,
- .api_id = PM_PLL_GET_MODE,
+ .id = (uint8_t)PM_PLL_GET_MODE,
+ .api_id = (uint8_t)PM_PLL_GET_MODE,
},
{
- .id = PM_REGISTER_ACCESS,
- .api_id = PM_MMIO_WRITE,
+ .id = (uint8_t)PM_REGISTER_ACCESS,
+ .api_id = (uint8_t)PM_MMIO_WRITE,
},
{
- .id = PM_REGISTER_ACCESS,
- .api_id = PM_MMIO_READ,
+ .id = (uint8_t)PM_REGISTER_ACCESS,
+ .api_id = (uint8_t)PM_MMIO_READ,
},
{
- .id = PM_FEATURE_CHECK,
- .api_id = PM_FEATURE_CHECK,
+ .id = (uint8_t)PM_FEATURE_CHECK,
+ .api_id = (uint8_t)PM_FEATURE_CHECK,
},
{
- .id = IOCTL_SET_TAPDELAY_BYPASS,
- .api_id = PM_MMIO_WRITE,
+ .id = (uint8_t)IOCTL_SET_TAPDELAY_BYPASS,
+ .api_id = (uint8_t)PM_MMIO_WRITE,
},
{
- .id = IOCTL_SD_DLL_RESET,
- .api_id = PM_MMIO_WRITE,
+ .id = (uint8_t)IOCTL_SD_DLL_RESET,
+ .api_id = (uint8_t)PM_MMIO_WRITE,
},
{
- .id = IOCTL_SET_SD_TAPDELAY,
- .api_id = PM_MMIO_WRITE,
+ .id = (uint8_t)IOCTL_SET_SD_TAPDELAY,
+ .api_id = (uint8_t)PM_MMIO_WRITE,
},
{
- .id = IOCTL_SET_SD_TAPDELAY,
- .api_id = PM_MMIO_READ,
+ .id = (uint8_t)IOCTL_SET_SD_TAPDELAY,
+ .api_id = (uint8_t)PM_MMIO_READ,
},
{
- .id = IOCTL_SET_PLL_FRAC_DATA,
- .api_id = PM_PLL_SET_PARAMETER,
+ .id = (uint8_t)IOCTL_SET_PLL_FRAC_DATA,
+ .api_id = (uint8_t)PM_PLL_SET_PARAMETER,
},
{
- .id = IOCTL_GET_PLL_FRAC_DATA,
- .api_id = PM_PLL_GET_PARAMETER,
+ .id = (uint8_t)IOCTL_GET_PLL_FRAC_DATA,
+ .api_id = (uint8_t)PM_PLL_GET_PARAMETER,
},
{
- .id = IOCTL_WRITE_GGS,
- .api_id = PM_MMIO_WRITE,
+ .id = (uint8_t)IOCTL_WRITE_GGS,
+ .api_id = (uint8_t)PM_MMIO_WRITE,
},
{
- .id = IOCTL_READ_GGS,
- .api_id = PM_MMIO_READ,
+ .id = (uint8_t)IOCTL_READ_GGS,
+ .api_id = (uint8_t)PM_MMIO_READ,
},
{
- .id = IOCTL_WRITE_PGGS,
- .api_id = PM_MMIO_WRITE,
+ .id = (uint8_t)IOCTL_WRITE_PGGS,
+ .api_id = (uint8_t)PM_MMIO_WRITE,
},
{
- .id = IOCTL_READ_PGGS,
- .api_id = PM_MMIO_READ,
+ .id = (uint8_t)IOCTL_READ_PGGS,
+ .api_id = (uint8_t)PM_MMIO_READ,
},
{
- .id = IOCTL_ULPI_RESET,
- .api_id = PM_MMIO_WRITE,
+ .id = (uint8_t)IOCTL_ULPI_RESET,
+ .api_id = (uint8_t)PM_MMIO_WRITE,
},
{
- .id = IOCTL_SET_BOOT_HEALTH_STATUS,
- .api_id = PM_MMIO_WRITE,
+ .id = (uint8_t)IOCTL_SET_BOOT_HEALTH_STATUS,
+ .api_id = (uint8_t)PM_MMIO_WRITE,
},
{
- .id = IOCTL_AFI,
- .api_id = PM_MMIO_WRITE,
+ .id = (uint8_t)IOCTL_AFI,
+ .api_id = (uint8_t)PM_MMIO_WRITE,
},
};
@@ -770,7 +770,7 @@
{
uint8_t i;
uint32_t version_type;
- int ret;
+ enum pm_ret_status ret;
for (i = 0U; i < ARRAY_SIZE(api_dep_table); i++) {
if (api_dep_table[i].id == id) {
@@ -1521,47 +1521,47 @@
pm_clock_get_name(arg1, (char *)data);
break;
case PM_QID_CLOCK_GET_TOPOLOGY:
- data[0] = pm_clock_get_topology(arg1, arg2, &data[1]);
+ data[0] = (uint32_t)pm_clock_get_topology(arg1, arg2, &data[1]);
break;
case PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS:
- data[0] = pm_clock_get_fixedfactor_params(arg1, &data[1],
+ data[0] = (uint32_t)pm_clock_get_fixedfactor_params(arg1, &data[1],
&data[2]);
break;
case PM_QID_CLOCK_GET_PARENTS:
- data[0] = pm_clock_get_parents(arg1, arg2, &data[1]);
+ data[0] = (uint32_t)pm_clock_get_parents(arg1, arg2, &data[1]);
break;
case PM_QID_CLOCK_GET_ATTRIBUTES:
- data[0] = pm_clock_get_attributes(arg1, &data[1]);
+ data[0] = (uint32_t)pm_clock_get_attributes(arg1, &data[1]);
break;
case PM_QID_PINCTRL_GET_NUM_PINS:
- data[0] = pm_pinctrl_get_num_pins(&data[1]);
+ data[0] = (uint32_t)pm_pinctrl_get_num_pins(&data[1]);
break;
case PM_QID_PINCTRL_GET_NUM_FUNCTIONS:
- data[0] = pm_pinctrl_get_num_functions(&data[1]);
+ data[0] = (uint32_t)pm_pinctrl_get_num_functions(&data[1]);
break;
case PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS:
- data[0] = pm_pinctrl_get_num_function_groups(arg1, &data[1]);
+ data[0] = (uint32_t)pm_pinctrl_get_num_function_groups(arg1, &data[1]);
break;
case PM_QID_PINCTRL_GET_FUNCTION_NAME:
pm_pinctrl_get_function_name(arg1, (char *)data);
break;
case PM_QID_PINCTRL_GET_FUNCTION_GROUPS:
- data[0] = pm_pinctrl_get_function_groups(arg1, arg2,
+ data[0] = (uint32_t)pm_pinctrl_get_function_groups(arg1, arg2,
(uint16_t *)&data[1]);
break;
case PM_QID_PINCTRL_GET_PIN_GROUPS:
- data[0] = pm_pinctrl_get_pin_groups(arg1, arg2,
+ data[0] = (uint32_t)pm_pinctrl_get_pin_groups(arg1, arg2,
(uint16_t *)&data[1]);
break;
case PM_QID_CLOCK_GET_NUM_CLOCKS:
- data[0] = pm_clock_get_num_clocks(&data[1]);
+ data[0] = (uint32_t)pm_clock_get_num_clocks(&data[1]);
break;
case PM_QID_CLOCK_GET_MAX_DIVISOR:
- data[0] = pm_clock_get_max_divisor(arg1, arg2, &data[1]);
+ data[0] = (uint32_t)pm_clock_get_max_divisor(arg1, (uint8_t)arg2, &data[1]);
break;
default:
- data[0] = PM_RET_ERROR_ARGS;
+ data[0] = (uint32_t)PM_RET_ERROR_ARGS;
WARN("Unimplemented query service call: 0x%x\n", qid);
break;
}
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_defs.h b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_defs.h
index af75c5c..c7d2b2c 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_defs.h
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_defs.h
@@ -187,9 +187,9 @@
*
*/
enum pm_shutdown_subtype {
- PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM,
- PMF_SHUTDOWN_SUBTYPE_PS_ONLY,
- PMF_SHUTDOWN_SUBTYPE_SYSTEM,
+ PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM = (0U),
+ PMF_SHUTDOWN_SUBTYPE_PS_ONLY = (1U),
+ PMF_SHUTDOWN_SUBTYPE_SYSTEM = (2U),
};
/**
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
index 5694fea..21435c6 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
@@ -560,7 +560,7 @@
uint32_t bit_mask[2] = {0};
ret = pm_feature_check(pm_arg[0], &version_type, bit_mask,
- ARRAY_SIZE(bit_mask));
+ (uint8_t)ARRAY_SIZE(bit_mask));
SMC_RET2(handle, ((uint64_t)ret | ((uint64_t)version_type << 32U)),
((uint64_t)bit_mask[0] | ((uint64_t)bit_mask[1] << 32U)));
}