plat/marvell/armada: allow builds without MSS support
Setting MSS_SUPPORT to 0 also removes requirement for SCP_BL2
definition.
Images build with MSS_SUPPORT=0 will not include service CPUs
FW and will not support PM, FC and other features implemented
in these FW images.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: Idf301ebd218ce65a60f277f3876d0aeb6c72f105
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/37769
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
diff --git a/plat/marvell/armada/a8k/common/a8k_common.mk b/plat/marvell/armada/a8k/common/a8k_common.mk
index 3acc3b4..90883f2 100644
--- a/plat/marvell/armada/a8k/common/a8k_common.mk
+++ b/plat/marvell/armada/a8k/common/a8k_common.mk
@@ -10,13 +10,14 @@
MARVELL_DRV_BASE := drivers/marvell
MARVELL_COMMON_BASE := plat/marvell/armada/common
-MARVELL_SVC_TEST := 0
+MARVELL_SVC_TEST := 0
$(eval $(call add_define,MARVELL_SVC_TEST))
ERRATA_A72_859971 := 1
# Enable MSS support for a8k family
MSS_SUPPORT := 1
+$(eval $(call add_define,MSS_SUPPORT))
# Disable EL3 cache for power management
BL31_CACHE_DISABLE := 0
@@ -114,12 +115,15 @@
$(MARVELL_DRV_BASE)/cache_llc.c \
$(MARVELL_DRV_BASE)/comphy/phy-comphy-cp110.c \
$(MARVELL_DRV_BASE)/mc_trustzone/mc_trustzone.c \
- $(MARVELL_DRV_BASE)/mg_conf_cm3/mg_conf_cm3.c \
$(MARVELL_DRV_BASE)/secure_dfx_access/armada_thermal.c \
$(MARVELL_DRV_BASE)/secure_dfx_access/misc_dfx.c \
$(MARVELL_DRV_BASE)/ddr_phy_access.c \
drivers/rambus/trng_ip_76.c
+ifeq (${MSS_SUPPORT}, 1)
+MARVELL_DRV += $(MARVELL_DRV_BASE)/mg_conf_cm3/mg_conf_cm3.c
+endif
+
BL31_PORTING_SOURCES := $(BOARD_DIR)/board/marvell_plat_config.c
ifeq ($(SYSTEM_POWER_SUPPORT),1)
@@ -142,6 +146,8 @@
# Add trace functionality for PM
BL31_SOURCES += $(PLAT_COMMON_BASE)/plat_pm_trace.c
+
+ifeq (${MSS_SUPPORT}, 1)
# Force builds with BL2 image on a80x0 platforms
ifndef SCP_BL2
$(error "Error: SCP_BL2 image is mandatory for a8k family")
@@ -149,6 +155,7 @@
# MSS (SCP) build
include $(PLAT_COMMON_BASE)/mss/mss_a8k.mk
+endif
# BLE (ROM context execution code, AKA binary extension)
BLE_PATH ?= $(PLAT_COMMON_BASE)/ble
diff --git a/plat/marvell/armada/a8k/common/plat_bl31_setup.c b/plat/marvell/armada/a8k/common/plat_bl31_setup.c
index 552c9b2..50dcd28 100644
--- a/plat/marvell/armada/a8k/common/plat_bl31_setup.c
+++ b/plat/marvell/armada/a8k/common/plat_bl31_setup.c
@@ -16,8 +16,10 @@
#include <marvell_pm.h>
#include <mc_trustzone/mc_trustzone.h>
#include <plat_marvell.h>
+#if MSS_SUPPORT
#include <mss_ipc_drv.h>
#include <mss_mem.h>
+#endif
/* In Armada-8k family AP806/AP807, CP0 connected to PIDI
* and CP1 connected to IHB via MCI #0
@@ -51,6 +53,7 @@
mmio_write_32(MVEBU_CP_MPP_REGS(0, 4), reg | 0x2200000);
}
+#if MSS_SUPPORT
void marvell_bl31_mss_init(void)
{
struct mss_pm_ctrl_block *mss_pm_crtl =
@@ -70,6 +73,7 @@
if (mss_pm_crtl->ipc_state == IPC_INITIALIZED)
mv_pm_ipc_init(mss_pm_crtl->ipc_base_address | MVEBU_REGS_BASE);
}
+#endif
_Bool is_pm_fw_running(void)
{
@@ -125,11 +129,12 @@
for (cp = 1; cp < CP_COUNT; cp++)
mci_link_tune(cp - 1);
+#if MSS_SUPPORT
/* initialize IPC between MSS and ATF */
if (mailbox[MBOX_IDX_MAGIC] != MVEBU_MAILBOX_MAGIC_NUM ||
mailbox[MBOX_IDX_SUSPEND_MAGIC] != MVEBU_MAILBOX_SUSPEND_STATE)
marvell_bl31_mss_init();
-
+#endif
/* Configure GPIO */
marvell_gpio_config();
diff --git a/plat/marvell/armada/a8k/common/plat_pm.c b/plat/marvell/armada/a8k/common/plat_pm.c
index 96e95c2..9ea9276 100644
--- a/plat/marvell/armada/a8k/common/plat_pm.c
+++ b/plat/marvell/armada/a8k/common/plat_pm.c
@@ -18,7 +18,9 @@
#include <armada_common.h>
#include <marvell_pm.h>
+#if MSS_SUPPORT
#include <mss_pm_ipc.h>
+#endif
#include <plat_marvell.h>
#include <plat_pm_trace.h>
@@ -396,6 +398,7 @@
/* Power up CPU (CPUs 1-3 are powered off at start of BLE) */
plat_marvell_cpu_powerup(mpidr);
+#if MSS_SUPPORT
if (is_pm_fw_running()) {
unsigned int target =
((mpidr & 0xFF) + (((mpidr >> 8) & 0xFF) * 2));
@@ -417,11 +420,12 @@
/* trace message */
PM_TRACE(TRACE_PWR_DOMAIN_ON | target);
- } else {
+ } else
+#endif
+ {
/* proprietary CPU ON exection flow */
plat_marvell_cpu_on(mpidr);
}
-
return 0;
}
@@ -441,6 +445,7 @@
*/
static void a8k_pwr_domain_off(const psci_power_state_t *target_state)
{
+#if MSS_SUPPORT
if (is_pm_fw_running()) {
unsigned int idx = plat_my_core_pos();
@@ -466,6 +471,7 @@
} else {
INFO("%s: is not supported without SCP\n", __func__);
}
+#endif
}
/* Get PM config to power off the SoC */
@@ -586,6 +592,7 @@
*/
static void a8k_pwr_domain_suspend(const psci_power_state_t *target_state)
{
+#if MSS_SUPPORT
if (is_pm_fw_running()) {
unsigned int idx;
@@ -610,7 +617,9 @@
/* trace message */
PM_TRACE(TRACE_PWR_DOMAIN_SUSPEND);
- } else {
+ } else
+#endif
+ {
uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE;
INFO("Suspending to RAM\n");
diff --git a/plat/marvell/armada/a8k/common/plat_pm_trace.c b/plat/marvell/armada/a8k/common/plat_pm_trace.c
index f589ff3..e02a893 100644
--- a/plat/marvell/armada/a8k/common/plat_pm_trace.c
+++ b/plat/marvell/armada/a8k/common/plat_pm_trace.c
@@ -8,10 +8,11 @@
#include <lib/mmio.h>
#include <plat/common/platform.h>
+#if MSS_SUPPORT
#include <mss_mem.h>
-#include <plat_pm_trace.h>
#ifdef PM_TRACE_ENABLE
+#include <plat_pm_trace.h>
/* core trace APIs */
core_trace_func funcTbl[PLATFORM_CORE_COUNT] = {
@@ -90,3 +91,4 @@
AP_MSS_ATF_TRACE_SIZE_MASK));
}
#endif /* PM_TRACE_ENABLE */
+#endif /* MSS_SUPPORT */