tree 51bb6490d8e7e3a23bafe9d8391d6958bc8f50a3
parent 9fd242b7b5c0321dd4b71b69cf5083e75eb980b4
author Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> 1722934091 +0300
committer Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> 1724160536 +0300

feat(nxp-clk): add PERIPH PLL enablement

Peripheral PLL is one of the platform's PLLs, providing a clock for
peripherals such as UART, QSPI, uSDHC, SPI and CAN. Its source can be
either the FIRC or FXOSC oscillators. It has eight outputs (PHIs) and
their frequencies can be controlled programmatically using output
dividers. An additional output clocks the PERIPH DFS using the VCO
frequency of the PERIPH PLL.

Change-Id: I637294b2da94f35e95dc1750dad36c129a276bb9
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>