feat(nxp-clk): add PERIPH PLL enablement
Peripheral PLL is one of the platform's PLLs, providing a clock for
peripherals such as UART, QSPI, uSDHC, SPI and CAN. Its source can be
either the FIRC or FXOSC oscillators. It has eight outputs (PHIs) and
their frequencies can be controlled programmatically using output
dividers. An additional output clocks the PERIPH DFS using the VCO
frequency of the PERIPH PLL.
Change-Id: I637294b2da94f35e95dc1750dad36c129a276bb9
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
diff --git a/drivers/nxp/clk/s32cc/s32cc_early_clks.c b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
index 2c256a5..496724f 100644
--- a/drivers/nxp/clk/s32cc/s32cc_early_clks.c
+++ b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
@@ -8,11 +8,13 @@
#include <s32cc-clk-ids.h>
#include <s32cc-clk-utils.h>
-#define S32CC_FXOSC_FREQ (40U * MHZ)
-#define S32CC_ARM_PLL_VCO_FREQ (2U * GHZ)
-#define S32CC_ARM_PLL_PHI0_FREQ (1U * GHZ)
-#define S32CC_A53_FREQ (1U * GHZ)
-#define S32CC_XBAR_2X_FREQ (800U * MHZ)
+#define S32CC_FXOSC_FREQ (40U * MHZ)
+#define S32CC_ARM_PLL_VCO_FREQ (2U * GHZ)
+#define S32CC_ARM_PLL_PHI0_FREQ (1U * GHZ)
+#define S32CC_A53_FREQ (1U * GHZ)
+#define S32CC_XBAR_2X_FREQ (800U * MHZ)
+#define S32CC_PERIPH_PLL_VCO_FREQ (2U * GHZ)
+#define S32CC_PERIPH_PLL_PHI3_FREQ (125U * MHZ)
static int enable_fxosc_clk(void)
{
@@ -63,6 +65,38 @@
return ret;
}
+static int enable_periph_pll(void)
+{
+ int ret;
+
+ ret = clk_set_parent(S32CC_CLK_PERIPH_PLL_MUX, S32CC_CLK_FXOSC);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = clk_set_rate(S32CC_CLK_PERIPH_PLL_VCO, S32CC_PERIPH_PLL_VCO_FREQ, NULL);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = clk_set_rate(S32CC_CLK_PERIPH_PLL_PHI3, S32CC_PERIPH_PLL_PHI3_FREQ, NULL);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = clk_enable(S32CC_CLK_PERIPH_PLL_VCO);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = clk_enable(S32CC_CLK_PERIPH_PLL_PHI3);
+ if (ret != 0) {
+ return ret;
+ }
+
+ return ret;
+}
+
static int enable_a53_clk(void)
{
int ret;
@@ -128,6 +162,11 @@
return ret;
}
+ ret = enable_periph_pll();
+ if (ret != 0) {
+ return ret;
+ }
+
ret = enable_a53_clk();
if (ret != 0) {
return ret;