commit 22d227776d10c6a6a62d749bc65f33db5e083195
author Rohit Mathew <Rohit.Mathew@arm.com> Fri Dec 15 12:50:58 2023 +0000
committer Rohit Mathew <Rohit.Mathew@arm.com> Thu Jan 04 19:06:38 2024 +0000
tree f5b43d070da9c3fc92fce92929d40059859ef782
parent 960a77e1a828acf3089c0152e240323684749704

feat(cpu): add support for Poseidon V CPU

Enable support for Poseidon V CPUs. Poseidon V CPUs are distinguished by
a 3MB L2 cache, differing from Poseidon VN(AE) CPUs with a 2MB L2 cache.
This enhancement ensures compatibility with RD-Fremont and similar
platforms utilizing Poseidon V CPUs.

CC: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Icdcc5f57c62855b2ec54c58a401d3bf09f292189

include/lib/cpus/aarch64/neoverse_poseidon.h

diff --git a/include/lib/cpus/aarch64/neoverse_poseidon.h b/include/lib/cpus/aarch64/neoverse_poseidon.h
index 670d90a..117826d 100644
--- a/include/lib/cpus/aarch64/neoverse_poseidon.h
+++ b/include/lib/cpus/aarch64/neoverse_poseidon.h
@@ -9,6 +9,7 @@
 
 
 #define NEOVERSE_POSEIDON_VNAE_MIDR				U(0x410FD830)
+#define NEOVERSE_POSEIDON_V_MIDR				U(0x410FD840)
 
 /* Neoverse Poseidon loop count for CVE-2022-23960 mitigation */
 #define NEOVERSE_POSEIDON_BHB_LOOP_COUNT			U(132)