diff --git a/plat/renesas/common/bl2_secure_setting.c b/plat/renesas/common/bl2_secure_setting.c
index 2f8b001..297b1a9 100644
--- a/plat/renesas/common/bl2_secure_setting.c
+++ b/plat/renesas/common/bl2_secure_setting.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2023, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -107,8 +107,10 @@
 	/*
 	 * Security group 0 attribute setting for master ports 3
 	 * Security group 1 attribute setting for master ports 3
-	 *	{SEC_GRP0CR3,           0x00000000U},
-	 *	{SEC_GRP1CR3,           0x00000000U},
+	 */
+	{ SEC_GRP0CR3, 0x00003780U },
+	{ SEC_GRP1CR3, 0x00003780U },
+	/*
 	 * Security group 0 attribute setting for slave ports 0
 	 * Security group 1 attribute setting for slave ports 0
 	 *	{SEC_GRP0COND0,         0x00000000U},
@@ -259,10 +261,51 @@
 };
 
 /* AXI settings */
-static const struct {
+struct axi_t {
 	uint32_t reg;
 	uint32_t val;
-} axi[] = {
+};
+
+static const struct axi_t axi[] = {
+	/*
+	 * SRAM ptotection
+	 * AXI sram protected area division
+	 */
+	{AXI_SPTDIVCR0,  0x0E0E6304U},
+	{AXI_SPTDIVCR1,  0x0E0E6360U},
+	{AXI_SPTDIVCR2,  0x0E0E6360U},
+	{AXI_SPTDIVCR3,  0x0E0E6360U},
+	{AXI_SPTDIVCR4,  0x0E0E6360U},
+	{AXI_SPTDIVCR5,  0x0E0E6360U},
+	{AXI_SPTDIVCR6,  0x0E0E6360U},
+	{AXI_SPTDIVCR7,  0x0E0E6360U},
+	{AXI_SPTDIVCR8,  0x0E0E6360U},
+	{AXI_SPTDIVCR9,  0x0E0E6360U},
+	{AXI_SPTDIVCR10, 0x0E0E6360U},
+	{AXI_SPTDIVCR11, 0x0E0E6360U},
+	{AXI_SPTDIVCR12, 0x0E0E6360U},
+	{AXI_SPTDIVCR13, 0x0E0E6360U},
+	{AXI_SPTDIVCR14, 0x0E0E6360U},
+	/* AXI sram protected area setting */
+	{AXI_SPTCR0,  0x0E000E0EU},
+	{AXI_SPTCR1,  0x0E000000U},
+	{AXI_SPTCR2,  0x0E000000U},
+	{AXI_SPTCR3,  0x0E000000U},
+	{AXI_SPTCR4,  0x0E000000U},
+	{AXI_SPTCR5,  0x0E000000U},
+	{AXI_SPTCR6,  0x0E000000U},
+	{AXI_SPTCR7,  0x0E000000U},
+	{AXI_SPTCR8,  0x0E000000U},
+	{AXI_SPTCR9,  0x0E000000U},
+	{AXI_SPTCR10, 0x0E000000U},
+	{AXI_SPTCR11, 0x0E000000U},
+	{AXI_SPTCR12, 0x0E000000U},
+	{AXI_SPTCR13, 0x0E000000U},
+	{AXI_SPTCR14, 0x0E000000U},
+	{AXI_SPTCR15, 0x0E000000U}
+};
+
+static const struct axi_t axi_dram[] = {
 	/*
 	 * DRAM protection
 	 * AXI dram protected area division
@@ -299,41 +342,7 @@
 	{AXI_DPTCR13, 0x0E000000U},
 	{AXI_DPTCR14, 0x0E000000U},
 	{AXI_DPTCR15, 0x0E000000U},
-	/*
-	 * SRAM ptotection
-	 * AXI sram protected area division
-	 */
-	{AXI_SPTDIVCR0,  0x0E0E6304U},
-	{AXI_SPTDIVCR1,  0x0E0E6360U},
-	{AXI_SPTDIVCR2,  0x0E0E6360U},
-	{AXI_SPTDIVCR3,  0x0E0E6360U},
-	{AXI_SPTDIVCR4,  0x0E0E6360U},
-	{AXI_SPTDIVCR5,  0x0E0E6360U},
-	{AXI_SPTDIVCR6,  0x0E0E6360U},
-	{AXI_SPTDIVCR7,  0x0E0E6360U},
-	{AXI_SPTDIVCR8,  0x0E0E6360U},
-	{AXI_SPTDIVCR9,  0x0E0E6360U},
-	{AXI_SPTDIVCR10, 0x0E0E6360U},
-	{AXI_SPTDIVCR11, 0x0E0E6360U},
-	{AXI_SPTDIVCR12, 0x0E0E6360U},
-	{AXI_SPTDIVCR13, 0x0E0E6360U},
-	{AXI_SPTDIVCR14, 0x0E0E6360U},
 	/* AXI sram protected area setting */
-	{AXI_SPTCR0,  0x0E000E0EU},
-	{AXI_SPTCR1,  0x0E000000U},
-	{AXI_SPTCR2,  0x0E000000U},
-	{AXI_SPTCR3,  0x0E000000U},
-	{AXI_SPTCR4,  0x0E000000U},
-	{AXI_SPTCR5,  0x0E000000U},
-	{AXI_SPTCR6,  0x0E000000U},
-	{AXI_SPTCR7,  0x0E000000U},
-	{AXI_SPTCR8,  0x0E000000U},
-	{AXI_SPTCR9,  0x0E000000U},
-	{AXI_SPTCR10, 0x0E000000U},
-	{AXI_SPTCR11, 0x0E000000U},
-	{AXI_SPTCR12, 0x0E000000U},
-	{AXI_SPTCR13, 0x0E000000U},
-	{AXI_SPTCR14, 0x0E000000U},
 	{AXI_SPTCR15, 0x0E000000U}
 };
 
@@ -345,7 +354,7 @@
 		mmio_write_32(lifec[i].reg, lifec[i].val);
 }
 
-/* SRAM/DRAM protection setting */
+/* SRAM protection setting */
 static void axi_security_setting(void)
 {
 	uint32_t i;
@@ -354,6 +363,15 @@
 		mmio_write_32(axi[i].reg, axi[i].val);
 }
 
+/* DRAM protection setting */
+void bl2_ram_security_setting_finish(void)
+{
+	uint32_t i;
+
+	for (i = 0; i < ARRAY_SIZE(axi_dram); i++)
+		mmio_write_32(axi_dram[i].reg, axi_dram[i].val);
+}
+
 void bl2_secure_setting(void)
 {
 	lifec_security_setting();
diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c
index 6b1d4fc..cf77da2 100644
--- a/plat/renesas/rcar/bl2_plat_setup.c
+++ b/plat/renesas/rcar/bl2_plat_setup.c
@@ -68,6 +68,7 @@
 extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info);
 extern void bl2_system_cpg_init(void);
 extern void bl2_secure_setting(void);
+extern void bl2_ram_security_setting_finish(void);
 extern void bl2_cpg_init(void);
 extern void rcar_io_emmc_setup(void);
 extern void rcar_io_setup(void);
@@ -1285,6 +1286,11 @@
 #endif
 }
 
+void bl2_el3_plat_prepare_exit(void)
+{
+	bl2_ram_security_setting_finish();
+}
+
 void bl2_platform_setup(void)
 {