tree b5a955547342b2608456438fdfd716bab3ee185b
parent 6e86c5ad5fec171d6bfcb685b0be82bde1250502
author Oliver Swede <oli.swede@arm.com> 1575293620 +0000
committer Oliver Swede <oli.swede@arm.com> 1585255250 +0000

plat/arm/board/arm_fpga: Initialize the System Counter

This sets the frequency of the system counter so that the Delay Timer
driver programs the correct value to CNTCRL. This value depends on
the FPGA image being used, and is 10MHz for the initial test image.
Once configured, the BL31 platform setup sequence then enables the
system counter.

Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: Ieb036a36fd990f350b5953357424a255b8ac5d5a