Merge changes Idde51a13,Ife8f1e84 into integration
* changes:
feat(mediatek): add smcc call for MSDC
refactor(mediatek): refactor plat_sip_calls.h for mt8192/mt8195/mt8186
diff --git a/fdts/stm32mp157a-avenger96.dts b/fdts/stm32mp157a-avenger96.dts
index 6ae97c7..f0da350 100644
--- a/fdts/stm32mp157a-avenger96.dts
+++ b/fdts/stm32mp157a-avenger96.dts
@@ -163,7 +163,6 @@
&iwdg2 {
timeout-sec = <32>;
status = "okay";
- secure-status = "okay";
};
&pwr_regulators {
@@ -172,7 +171,6 @@
};
&rcc {
- secure-status = "disabled";
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P
diff --git a/fdts/stm32mp157c-ed1.dts b/fdts/stm32mp157c-ed1.dts
index 659e8bf..d928563 100644
--- a/fdts/stm32mp157c-ed1.dts
+++ b/fdts/stm32mp157c-ed1.dts
@@ -201,7 +201,6 @@
};
&rcc {
- secure-status = "disabled";
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P
diff --git a/fdts/stm32mp157c-odyssey-som.dtsi b/fdts/stm32mp157c-odyssey-som.dtsi
index c4e1398..091e327 100644
--- a/fdts/stm32mp157c-odyssey-som.dtsi
+++ b/fdts/stm32mp157c-odyssey-som.dtsi
@@ -203,7 +203,6 @@
};
&rcc {
- secure-status = "disabled";
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P
diff --git a/fdts/stm32mp15xx-dhcom-som.dtsi b/fdts/stm32mp15xx-dhcom-som.dtsi
index 3021ef8..c9f21b0 100644
--- a/fdts/stm32mp15xx-dhcom-som.dtsi
+++ b/fdts/stm32mp15xx-dhcom-som.dtsi
@@ -160,7 +160,6 @@
&iwdg2 {
timeout-sec = <32>;
status = "okay";
- secure-status = "okay";
};
&pwr_regulators {
@@ -187,7 +186,6 @@
};
&rcc {
- secure-status = "disabled";
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P
diff --git a/fdts/stm32mp15xx-dhcor-som.dtsi b/fdts/stm32mp15xx-dhcor-som.dtsi
index 0774c1d..c241efc 100644
--- a/fdts/stm32mp15xx-dhcor-som.dtsi
+++ b/fdts/stm32mp15xx-dhcor-som.dtsi
@@ -155,7 +155,6 @@
&iwdg2 {
timeout-sec = <32>;
status = "okay";
- secure-status = "okay";
};
&pwr_regulators {
@@ -182,7 +181,6 @@
};
&rcc {
- secure-status = "disabled";
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P
diff --git a/fdts/stm32mp15xx-dkx.dtsi b/fdts/stm32mp15xx-dkx.dtsi
index 74e529d..52d4170 100644
--- a/fdts/stm32mp15xx-dkx.dtsi
+++ b/fdts/stm32mp15xx-dkx.dtsi
@@ -180,7 +180,6 @@
&iwdg2 {
timeout-sec = <32>;
status = "okay";
- secure-status = "okay";
};
&pwr_regulators {
@@ -189,7 +188,6 @@
};
&rcc {
- secure-status = "disabled";
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P
@@ -304,10 +302,6 @@
status = "okay";
};
-&timers15 {
- secure-status = "okay";
-};
-
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins_a>;
diff --git a/fdts/stm32mp15xx-osd32.dtsi b/fdts/stm32mp15xx-osd32.dtsi
index c7ddc92..52a5d38 100644
--- a/fdts/stm32mp15xx-osd32.dtsi
+++ b/fdts/stm32mp15xx-osd32.dtsi
@@ -181,7 +181,6 @@
/* CLOCK init */
&rcc {
- secure-status = "disabled";
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P
diff --git a/plat/renesas/common/common.mk b/plat/renesas/common/common.mk
index aef0ad1..26a5798 100644
--- a/plat/renesas/common/common.mk
+++ b/plat/renesas/common/common.mk
@@ -140,5 +140,4 @@
drivers/arm/cci/cci.c
include lib/xlat_tables_v2/xlat_tables.mk
-include drivers/auth/mbedtls/mbedtls_crypto.mk
PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
diff --git a/plat/ti/k3/board/j784s4/board.mk b/plat/ti/k3/board/j784s4/board.mk
new file mode 100644
index 0000000..92433ab
--- /dev/null
+++ b/plat/ti/k3/board/j784s4/board.mk
@@ -0,0 +1,24 @@
+#
+# Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+BL32_BASE ?= 0x9e800000
+$(eval $(call add_define,BL32_BASE))
+
+PRELOADED_BL33_BASE ?= 0x80080000
+$(eval $(call add_define,PRELOADED_BL33_BASE))
+
+K3_HW_CONFIG_BASE ?= 0x82000000
+$(eval $(call add_define,K3_HW_CONFIG_BASE))
+
+# Define sec_proxy usage as the full prioritized communication scheme
+K3_SEC_PROXY_LITE := 0
+$(eval $(call add_define,K3_SEC_PROXY_LITE))
+
+# System coherency is managed in hardware
+USE_COHERENT_MEM := 1
+
+PLAT_INCLUDES += \
+ -Iplat/ti/k3/board/j784s4/include \
diff --git a/plat/ti/k3/board/j784s4/include/board_def.h b/plat/ti/k3/board/j784s4/include/board_def.h
new file mode 100644
index 0000000..c2debc7
--- /dev/null
+++ b/plat/ti/k3/board/j784s4/include/board_def.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef BOARD_DEF_H
+#define BOARD_DEF_H
+
+#include <lib/utils_def.h>
+
+/* The ports must be in order and contiguous */
+#define K3_CLUSTER0_CORE_COUNT U(4)
+#define K3_CLUSTER1_CORE_COUNT U(4)
+#define K3_CLUSTER2_CORE_COUNT U(0)
+#define K3_CLUSTER3_CORE_COUNT U(0)
+/*
+ * This RAM will be used for the bootloader including code, bss, and stacks.
+ * It may need to be increased if BL31 grows in size.
+ *
+ * The link addresses are determined by SEC_SRAM_BASE + offset.
+ * When ENABLE_PIE is set, the TF images can be loaded anywhere, so
+ * SEC_SRAM_BASE is really arbitrary.
+ *
+ * When ENABLE_PIE is unset, SEC_SRAM_BASE should be chosen so that
+ * it matches to the physical address where BL31 is loaded, that is,
+ * SEC_SRAM_BASE should be the base address of the RAM region.
+ *
+ * Lets make things explicit by mapping SRAM_BASE to 0x0 since ENABLE_PIE is
+ * defined as default for our platform.
+ */
+#define SEC_SRAM_BASE UL(0x00000000) /* PIE remapped on fly */
+#define SEC_SRAM_SIZE UL(0x00020000) /* 128k */
+
+#define PLAT_MAX_OFF_STATE U(2)
+#define PLAT_MAX_RET_STATE U(1)
+
+#define PLAT_PROC_START_ID U(32)
+
+#define PLAT_PROC_DEVICE_START_ID U(202)
+#define PLAT_CLUSTER_DEVICE_START_ID U(198)
+
+#endif /* BOARD_DEF_H */