tree cbe6853dc666dbf4a1e64fc7e8e03db1eaf2acff
parent 5a5c2bb0f9c27825ede6341dc79df55128d0f9c4
author Lin Huang <hl@rock-chips.com> 1495008877 +0800
committer Caesar Wang <wxt@rock-chips.com> 1503978809 +0800

rockchip/rk3399: set ddr clock source back to dpll when ddr resume

when logic power rail shutdown, CRU register will back to reset
value, ddr use abpll as clock source when do suspend, we need to save
and dpll value in pmusram, then set back these ddr clock back to dpll
when dddr resume.

Change-Id: I95dc0173649e8515859cfa46b40a606e0cc2fe3f
Signed-off-by: Lin Huang <hl@rock-chips.com>