diff --git a/plat/arm/board/rdn2/include/platform_def.h b/plat/arm/board/rdn2/include/platform_def.h
index 8e63de5..ff1a437 100644
--- a/plat/arm/board/rdn2/include/platform_def.h
+++ b/plat/arm/board/rdn2/include/platform_def.h
@@ -8,7 +8,7 @@
 #define PLATFORM_DEF_H
 
 #include <lib/utils_def.h>
-
+#include <sgi_sdei.h>
 #include <sgi_soc_platform_def_v2.h>
 
 #if (CSS_SGI_PLATFORM_VARIANT == 1)
diff --git a/plat/arm/board/rdn2/include/rdn2_ras.h b/plat/arm/board/rdn2/include/rdn2_ras.h
new file mode 100644
index 0000000..1d9af60
--- /dev/null
+++ b/plat/arm/board/rdn2/include/rdn2_ras.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RDN2_RAS_H
+#define RDN2_RAS_H
+
+#include <sgi_ras.h>
+
+extern struct plat_sgi_ras_config ras_config;
+
+#endif /* RDN2_RAS_H */
diff --git a/plat/arm/board/rdn2/platform.mk b/plat/arm/board/rdn2/platform.mk
index ca55036..9ebca23 100644
--- a/plat/arm/board/rdn2/platform.mk
+++ b/plat/arm/board/rdn2/platform.mk
@@ -69,6 +69,12 @@
 BL31_CFLAGS		+=	-DPLAT_XLAT_TABLES_DYNAMIC
 endif
 
+ifeq (${RAS_FFH_SUPPORT},1)
+BL31_SOURCES		+=	${RDN2_BASE}/rdn2_ras.c			\
+				${CSS_ENT_BASE}/ras/sgi_ras_common.c	\
+				${CSS_ENT_BASE}/ras/sgi_ras_sram.c
+endif
+
 # Add the FDT_SOURCES and options for Dynamic Config
 FDT_SOURCES		+=	${RDN2_BASE}/fdts/${PLAT}_fw_config.dts	\
 				${RDN2_BASE}/fdts/${PLAT}_tb_fw_config.dts
diff --git a/plat/arm/board/rdn2/rdn2_plat.c b/plat/arm/board/rdn2/rdn2_plat.c
index a5564ce..e8a967e 100644
--- a/plat/arm/board/rdn2/rdn2_plat.c
+++ b/plat/arm/board/rdn2/rdn2_plat.c
@@ -8,6 +8,7 @@
 #include <drivers/arm/gic600_multichip.h>
 #include <plat/arm/common/plat_arm.h>
 #include <plat/common/platform.h>
+#include <rdn2_ras.h>
 #include <sgi_soc_platform_def_v2.h>
 #include <sgi_plat.h>
 
@@ -134,5 +135,9 @@
 #endif
 
 	sgi_bl31_common_platform_setup();
+
+#if RAS_FFH_SUPPORT
+	sgi_ras_platform_setup(&ras_config);
+#endif
 }
 #endif /* IMAGE_BL31 */
diff --git a/plat/arm/board/rdn2/rdn2_ras.c b/plat/arm/board/rdn2/rdn2_ras.c
new file mode 100644
index 0000000..c1e5ab6
--- /dev/null
+++ b/plat/arm/board/rdn2/rdn2_ras.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <platform_def.h>
+#include <sgi_ras.h>
+#include <sgi_sdei.h>
+
+struct sgi_ras_ev_map plat_ras_map[] = {
+	/* Non Secure base RAM ECC CE interrupt */
+	{SGI_SDEI_DS_EVENT_0, NS_RAM_ECC_CE_INT, SGI_RAS_INTR_TYPE_SPI},
+
+	/* Non Secure base RAM ECC UE interrupt */
+	{SGI_SDEI_DS_EVENT_0, NS_RAM_ECC_UE_INT, SGI_RAS_INTR_TYPE_SPI},
+};
+
+/* RAS error record list definition, used by the common RAS framework. */
+struct err_record_info plat_err_records[] = {
+	/* Base element RAM Non-secure error record. */
+	ERR_RECORD_MEMMAP_V1(SOC_NS_RAM_ERR_REC_BASE, 4, NULL,
+				&sgi_ras_sram_intr_handler, 0),
+};
+
+/* RAS error interrupt list definition, used by the common RAS framework. */
+struct ras_interrupt plat_ras_interrupts[] = {
+	{
+		.intr_number = NS_RAM_ECC_CE_INT,
+		.err_record = &plat_err_records[0],
+	}, {
+		.intr_number = NS_RAM_ECC_UE_INT,
+		.err_record = &plat_err_records[0],
+	},
+};
+
+/* Registers the RAS error record list with common RAS framework. */
+REGISTER_ERR_RECORD_INFO(plat_err_records);
+/* Registers the RAS error interrupt info list with common RAS framework. */
+REGISTER_RAS_INTERRUPTS(plat_ras_interrupts);
+
+/* Platform RAS handling config data definition */
+struct plat_sgi_ras_config ras_config = {
+	plat_ras_map,
+	ARRAY_SIZE(plat_ras_map)
+};
diff --git a/plat/arm/board/rdn2/rdn2_security.c b/plat/arm/board/rdn2/rdn2_security.c
index dff6a19..b836a7f 100644
--- a/plat/arm/board/rdn2/rdn2_security.c
+++ b/plat/arm/board/rdn2/rdn2_security.c
@@ -8,8 +8,16 @@
 #include <plat/arm/common/plat_arm.h>
 #include <platform_def.h>
 
+#define RDN2_TZC_CPER_REGION					\
+	{CSS_SGI_SP_CPER_BUF_BASE, (CSS_SGI_SP_CPER_BUF_BASE +	\
+	CSS_SGI_SP_CPER_BUF_SIZE) - 1, TZC_REGION_S_NONE,	\
+	PLAT_ARM_TZC_NS_DEV_ACCESS}
+
 static const arm_tzc_regions_info_t tzc_regions[] = {
 	ARM_TZC_REGIONS_DEF,
+#if RAS_FFH_SUPPORT
+	RDN2_TZC_CPER_REGION,
+#endif
 	{}
 };