Merge "fix(intel): implement soc and lwsoc bridge control for burst speed" into integration
diff --git a/plat/intel/soc/agilex5/include/socfpga_plat_def.h b/plat/intel/soc/agilex5/include/socfpga_plat_def.h
index 412e5e2..5789261 100644
--- a/plat/intel/soc/agilex5/include/socfpga_plat_def.h
+++ b/plat/intel/soc/agilex5/include/socfpga_plat_def.h
@@ -11,6 +11,7 @@
#include "agilex5_memory_controller.h"
#include "agilex5_system_manager.h"
+
#include <platform_def.h>
/* Platform Setting */
diff --git a/plat/intel/soc/common/include/socfpga_handoff.h b/plat/intel/soc/common/include/socfpga_handoff.h
index d001887..7e1d0c0 100644
--- a/plat/intel/soc/common/include/socfpga_handoff.h
+++ b/plat/intel/soc/common/include/socfpga_handoff.h
@@ -11,12 +11,12 @@
#define HANDOFF_MAGIC_HEADER 0x424f4f54 /* BOOT */
#define HANDOFF_MAGIC_PINMUX_SEL 0x504d5558 /* PMUX */
#define HANDOFF_MAGIC_IOCTLR 0x494f4354 /* IOCT */
-#define HANDOFF_MAGIC_FPGA 0x46504741 /* FPGA */
+#define HANDOFF_MAGIC_FPGA 0x46504741 /* FPGA */
#define HANDOFF_MAGIC_IODELAY 0x444c4159 /* DLAY */
-#define HANDOFF_MAGIC_CLOCK 0x434c4b53 /* CLKS */
-#define HANDOFF_MAGIC_MISC 0x4d495343 /* MISC */
+#define HANDOFF_MAGIC_CLOCK 0x434c4b53 /* CLKS */
+#define HANDOFF_MAGIC_MISC 0x4d495343 /* MISC */
#define HANDOFF_MAGIC_PERIPHERAL 0x50455249 /* PERIPHERAL */
-#define HANDOFF_MAGIC_DDR 0x5344524d /* DDR */
+#define HANDOFF_MAGIC_DDR 0x5344524d /* DDR */
#include <socfpga_plat_def.h>
@@ -127,6 +127,8 @@
uint32_t clock_magic;
uint32_t clock_length;
uint32_t _pad_0x588_0x590[2];
+
+ /* main group PLL */
uint32_t main_pll_nocclk;
uint32_t main_pll_nocdiv;
uint32_t main_pll_pllglob;
@@ -136,6 +138,8 @@
uint32_t main_pll_pllc2;
uint32_t main_pll_pllc3;
uint32_t main_pll_pllm;
+
+ /* peripheral group PLL */
uint32_t per_pll_emacctl;
uint32_t per_pll_gpiodiv;
uint32_t per_pll_pllglob;
@@ -145,29 +149,25 @@
uint32_t per_pll_pllc2;
uint32_t per_pll_pllc3;
uint32_t per_pll_pllm;
+
+ /* control group */
uint32_t alt_emacactr;
uint32_t alt_emacbctr;
uint32_t alt_emacptpctr;
uint32_t alt_gpiodbctr;
- uint32_t alt_sdmmcctr;
uint32_t alt_s2fuser0ctr;
uint32_t alt_s2fuser1ctr;
uint32_t alt_psirefctr;
- /* TODO: Temp added for clk manager. */
- uint32_t qspi_clk_khz;
+ uint32_t alt_usb31ctr;
+ uint32_t alt_dsuctr;
+ uint32_t alt_core01ctr;
+ uint32_t alt_core23ctr;
+ uint32_t alt_core2ctr;
+ uint32_t alt_core3ctr;
uint32_t hps_osc_clk_hz;
uint32_t fpga_clk_hz;
- /* TODO: Temp added for clk manager. */
- uint32_t ddr_reset_type;
- /* TODO: Temp added for clk manager. */
- uint32_t hps_status_coldreset;
- /* TODO: Temp remove due to add in extra handoff data */
- //uint32_t _pad_0x604_0x610[3];
+ uint32_t _pad_0x604_0x610[3];
#endif
- /* misc configuration */
- uint32_t misc_magic;
- uint32_t misc_length;
- uint32_t _pad_0x618_0x620[2];
#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
/* peripheral configuration - select */