Merge changes from topic "fw-caps" into integration
* changes:
feat(ti): query firmware for suspend capability
feat(ti): add TI-SCI query firmware capabilities command support
feat(ti): remove extra core counts in cluster 2 and 3
diff --git a/Makefile b/Makefile
index 5edd625..7f781a0 100644
--- a/Makefile
+++ b/Makefile
@@ -448,6 +448,96 @@
include common/backtrace/backtrace.mk
################################################################################
+# Generic definitions
+################################################################################
+include ${MAKE_HELPERS_DIRECTORY}plat_helpers.mk
+
+ifeq (${BUILD_BASE},)
+ BUILD_BASE := ./build
+endif
+BUILD_PLAT := $(abspath ${BUILD_BASE})/${PLAT}/${BUILD_TYPE}
+
+SPDS := $(sort $(filter-out none, $(patsubst services/spd/%,%,$(wildcard services/spd/*))))
+
+# Platforms providing their own TBB makefile may override this value
+INCLUDE_TBBR_MK := 1
+
+################################################################################
+# Include SPD Makefile if one has been specified
+################################################################################
+
+ifneq (${SPD},none)
+ ifeq (${ARCH},aarch32)
+ $(error "Error: SPD is incompatible with AArch32.")
+ endif
+
+ ifdef EL3_PAYLOAD_BASE
+ $(warning "SPD and EL3_PAYLOAD_BASE are incompatible build options.")
+ $(warning "The SPD and its BL32 companion will be present but \
+ ignored.")
+ endif
+
+ ifeq (${SPD},spmd)
+ # SPMD is located in std_svc directory
+ SPD_DIR := std_svc
+
+ ifeq ($(SPMD_SPM_AT_SEL2),1)
+ CTX_INCLUDE_EL2_REGS := 1
+ ifeq ($(SPMC_AT_EL3),1)
+ $(error SPM cannot be enabled in both S-EL2 and EL3.)
+ endif
+ endif
+
+ ifeq ($(findstring optee_sp,$(ARM_SPMC_MANIFEST_DTS)),optee_sp)
+ DTC_CPPFLAGS += -DOPTEE_SP_FW_CONFIG
+ endif
+
+ ifeq ($(TS_SP_FW_CONFIG),1)
+ DTC_CPPFLAGS += -DTS_SP_FW_CONFIG
+ endif
+
+ ifneq ($(ARM_BL2_SP_LIST_DTS),)
+ DTC_CPPFLAGS += -DARM_BL2_SP_LIST_DTS=$(ARM_BL2_SP_LIST_DTS)
+ endif
+
+ ifneq ($(SP_LAYOUT_FILE),)
+ BL2_ENABLE_SP_LOAD := 1
+ endif
+ else
+ # All other SPDs in spd directory
+ SPD_DIR := spd
+ endif #(SPD)
+
+ # We expect to locate an spd.mk under the specified SPD directory
+ SPD_MAKE := $(wildcard services/${SPD_DIR}/${SPD}/${SPD}.mk)
+
+ ifeq (${SPD_MAKE},)
+ $(error Error: No services/${SPD_DIR}/${SPD}/${SPD}.mk located)
+ endif
+ $(info Including ${SPD_MAKE})
+ include ${SPD_MAKE}
+
+ # If there's BL32 companion for the chosen SPD, we expect that the SPD's
+ # Makefile would set NEED_BL32 to "yes". In this case, the build system
+ # supports two mutually exclusive options:
+ # * BL32 is built from source: then BL32_SOURCES must contain the list
+ # of source files to build BL32
+ # * BL32 is a prebuilt binary: then BL32 must point to the image file
+ # that will be included in the FIP
+ # If both BL32_SOURCES and BL32 are defined, the binary takes precedence
+ # over the sources.
+endif #(SPD=none)
+
+ifeq (${ENABLE_SPMD_LP}, 1)
+ifneq (${SPD},spmd)
+ $(error Error: ENABLE_SPMD_LP requires SPD=spmd.)
+endif
+ifeq ($(SPMC_AT_EL3),1)
+ $(error SPMC at EL3 not supported when enabling SPMD Logical partitions.)
+endif
+endif
+
+################################################################################
# Process BRANCH_PROTECTION value and set
# Pointer Authentication and Branch Target Identification flags
################################################################################
@@ -491,6 +581,18 @@
BL_COMMON_SOURCES += lib/extensions/pauth/pauth_helpers.S
endif
+################################################################################
+# Include the platform specific Makefile after the SPD Makefile (the platform
+# makefile may use all previous definitions in this file)
+################################################################################
+include ${PLAT_MAKEFILE_FULL}
+
+################################################################################
+# Setup arch_features based on ARM_ARCH_MAJOR, ARM_ARCH_MINOR provided from
+# platform.
+################################################################################
+include ${MAKE_HELPERS_DIRECTORY}arch_features.mk
+
####################################################
# Enable required options for Memory Stack Tagging.
####################################################
@@ -521,6 +623,9 @@
################################################################################
# FEAT_RME
ifeq (${ENABLE_RME},1)
+ # RME doesn't support BRBE
+ ENABLE_BRBE_FOR_NS := 0
+
# RME doesn't support PIE
ifneq (${ENABLE_PIE},0)
$(error ENABLE_RME does not support PIE)
@@ -670,12 +775,14 @@
$(warning "RME is an experimental feature")
endif
-################################################################################
-# Include the platform specific Makefile after the SPD Makefile (the platform
-# makefile may use all previous definitions in this file)
-################################################################################
-
-include ${PLAT_MAKEFILE_FULL}
+ifeq (${CTX_INCLUDE_EL2_REGS}, 1)
+ ifeq (${SPD},none)
+ ifeq (${ENABLE_RME},0)
+ $(error CTX_INCLUDE_EL2_REGS is available only when SPD \
+ or RME is enabled)
+ endif
+ endif
+endif
################################################################################
# Platform specific Makefile might provide us ARCH_MAJOR/MINOR use that to come
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S
index 7336b91..8298696 100644
--- a/bl31/aarch64/runtime_exceptions.S
+++ b/bl31/aarch64/runtime_exceptions.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -401,7 +401,7 @@
#if ENABLE_RME
/* Copy SCR_EL3.NSE bit to the flag to indicate caller's security */
- ubfx x7, x18, #SCR_NSE_SHIFT, 1
+ ubfx x7, x18, #SCR_NSE_SHIFT, #1
/*
* Shift copied SCR_EL3.NSE bit by 5 to create space for
diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c
index cae55f3..925c6a6 100644
--- a/bl31/bl31_main.c
+++ b/bl31/bl31_main.c
@@ -121,6 +121,9 @@
/* Init registers that never change for the lifetime of TF-A */
cm_manage_extensions_el3();
+ /* Init per-world context registers for non-secure world */
+ manage_extensions_nonsecure_per_world();
+
NOTICE("BL31: %s\n", version_string);
NOTICE("BL31: %s\n", build_message);
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 654ddc5..347cf20 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -1195,7 +1195,8 @@
The platform will use PSA compliant Crypto APIs during authentication and
image measurement process by enabling this option. It uses APIs defined as
per the `PSA Crypto API specification`_. This feature is only supported if
- using MbedTLS 3.x version. By default it is disabled (``0``).
+ using MbedTLS 3.x version. By default it is disabled (``0``), and this is an
+ experimental feature.
- ``ENABLE_CONSOLE_GETC``: Boolean option to enable `getc()` feature in console
driver(s). By default it is disabled (``0``) because it constitutes an attack
diff --git a/drivers/auth/mbedtls/mbedtls_psa_crypto.c b/drivers/auth/mbedtls/mbedtls_psa_crypto.c
index 2fa8e63..5891acf 100644
--- a/drivers/auth/mbedtls/mbedtls_psa_crypto.c
+++ b/drivers/auth/mbedtls/mbedtls_psa_crypto.c
@@ -28,6 +28,13 @@
#define LIB_NAME "mbed TLS PSA"
+/* Maximum length of R_S pair in the ECDSA signature in bytes */
+#define MAX_ECDSA_R_S_PAIR_LEN 64U
+
+/* Size of ASN.1 length and tag in bytes*/
+#define SIZE_OF_ASN1_LEN 1U
+#define SIZE_OF_ASN1_TAG 1U
+
#if CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY || \
CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC
/*
@@ -108,6 +115,7 @@
static void construct_psa_key_alg_and_type(mbedtls_pk_type_t pk_alg,
mbedtls_md_type_t md_alg,
+ psa_ecc_family_t psa_ecc_family,
psa_algorithm_t *psa_alg,
psa_key_type_t *psa_key_type)
{
@@ -118,14 +126,173 @@
*psa_alg = PSA_ALG_RSA_PSS(psa_md_alg);
*psa_key_type = PSA_KEY_TYPE_RSA_PUBLIC_KEY;
break;
+ case MBEDTLS_PK_ECDSA:
+ *psa_alg = PSA_ALG_ECDSA(psa_md_alg);
+ *psa_key_type = PSA_KEY_TYPE_ECC_PUBLIC_KEY(psa_ecc_family);
+ break;
default:
*psa_alg = PSA_ALG_NONE;
*psa_key_type = PSA_KEY_TYPE_NONE;
break;
}
+}
+
+
+#if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA || \
+TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA
+
+/*
+ * This is a helper function to detect padding byte (if the MSB bit of the
+ * first data byte is set to 1, for example 0x80) and on detection, ignore the
+ * padded byte(0x00) and increase the buffer pointer beyond padded byte and
+ * decrease the length of the buffer by 1.
+ *
+ * On Success returns 0, error otherwise.
+ **/
+static inline int ignore_asn1_int_padding_byte(unsigned char **buf_start,
+ size_t *buf_len)
+{
+ unsigned char *local_buf = *buf_start;
+
+ /* Check for negative number */
+ if ((local_buf[0] & 0x80U) != 0U) {
+ return -1;
+ }
+
+ if ((local_buf[0] == 0U) && (local_buf[1] > 0x7FU) &&
+ (*buf_len > 1U)) {
+ *buf_start = &local_buf[1];
+ (*buf_len)--;
+ }
+
+ return 0;
+}
+
+/*
+ * This is a helper function that gets a pointer to the encoded ECDSA publicKey
+ * and its length (as per RFC5280) and returns corresponding decoded publicKey
+ * and its length. As well, it retrieves the family of ECC key in the PSA
+ * format.
+ *
+ * This function returns error(CRYPTO_ERR_SIGNATURE) on ASN.1 parsing failure,
+ * otherwise success(0).
+ **/
+static int get_ecdsa_pkinfo_from_asn1(unsigned char **pk_start,
+ unsigned int *pk_len,
+ psa_ecc_family_t *psa_ecc_family)
+{
+ mbedtls_asn1_buf alg_oid, alg_params;
+ mbedtls_ecp_group_id grp_id;
+ int rc;
+ unsigned char *pk_end;
+ size_t len;
+ size_t curve_bits;
+ unsigned char *pk_ptr = *pk_start;
+
+ pk_end = pk_ptr + *pk_len;
+ rc = mbedtls_asn1_get_tag(&pk_ptr, pk_end, &len,
+ MBEDTLS_ASN1_CONSTRUCTED |
+ MBEDTLS_ASN1_SEQUENCE);
+ if (rc != 0) {
+ return CRYPTO_ERR_SIGNATURE;
+ }
+
+ pk_end = pk_ptr + len;
+ rc = mbedtls_asn1_get_alg(&pk_ptr, pk_end, &alg_oid, &alg_params);
+ if (rc != 0) {
+ return CRYPTO_ERR_SIGNATURE;
+ }
+
+ if (alg_params.tag == MBEDTLS_ASN1_OID) {
+ if (mbedtls_oid_get_ec_grp(&alg_params, &grp_id) != 0) {
+ return CRYPTO_ERR_SIGNATURE;
+ }
+ *psa_ecc_family = mbedtls_ecc_group_to_psa(grp_id,
+ &curve_bits);
+ } else {
+ return CRYPTO_ERR_SIGNATURE;
+ }
+
+ pk_end = pk_ptr + len - (alg_oid.len + alg_params.len +
+ 2 * (SIZE_OF_ASN1_LEN + SIZE_OF_ASN1_TAG));
+ rc = mbedtls_asn1_get_bitstring_null(&pk_ptr, pk_end, &len);
+ if (rc != 0) {
+ return CRYPTO_ERR_SIGNATURE;
+ }
+
+ *pk_start = pk_ptr;
+ *pk_len = len;
+
+ return rc;
}
/*
+ * Ecdsa-Sig-Value ::= SEQUENCE {
+ * r INTEGER,
+ * s INTEGER
+ * }
+ *
+ * This helper function that gets a pointer to the encoded ECDSA signature and
+ * its length (as per RFC5280) and returns corresponding decoded signature
+ * (R_S pair) and its size.
+ *
+ * This function returns error(CRYPTO_ERR_SIGNATURE) on ASN.1 parsing failure,
+ * otherwise success(0).
+ **/
+static int get_ecdsa_signature_from_asn1(unsigned char *sig_ptr,
+ size_t *sig_len,
+ unsigned char *r_s_pair)
+{
+ int rc;
+ unsigned char *sig_end;
+ size_t len, r_len, s_len;
+
+ sig_end = sig_ptr + *sig_len;
+ rc = mbedtls_asn1_get_tag(&sig_ptr, sig_end, &len,
+ MBEDTLS_ASN1_CONSTRUCTED |
+ MBEDTLS_ASN1_SEQUENCE);
+ if (rc != 0) {
+ return CRYPTO_ERR_SIGNATURE;
+ }
+
+ sig_end = sig_ptr + len;
+ rc = mbedtls_asn1_get_tag(&sig_ptr, sig_end, &r_len,
+ MBEDTLS_ASN1_INTEGER);
+ if (rc != 0) {
+ return CRYPTO_ERR_SIGNATURE;
+ }
+
+ if (ignore_asn1_int_padding_byte(&sig_ptr, &r_len) != 0) {
+ return CRYPTO_ERR_SIGNATURE;
+ }
+
+ (void)memcpy((void *)&r_s_pair[0], (const void *)sig_ptr, r_len);
+
+ sig_ptr = sig_ptr + r_len;
+ sig_end = sig_ptr + len - (r_len + (SIZE_OF_ASN1_LEN +
+ SIZE_OF_ASN1_TAG));
+ rc = mbedtls_asn1_get_tag(&sig_ptr, sig_end, &s_len,
+ MBEDTLS_ASN1_INTEGER);
+ if (rc != 0) {
+ return CRYPTO_ERR_SIGNATURE;
+ }
+
+ if (ignore_asn1_int_padding_byte(&sig_ptr, &s_len) != 0) {
+ return CRYPTO_ERR_SIGNATURE;
+ }
+
+ (void)memcpy((void *)&r_s_pair[r_len], (const void *)sig_ptr, s_len);
+
+ *sig_len = s_len + r_len;
+
+ return 0;
+}
+#endif /*
+ * TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA || \
+ * TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA
+ **/
+
+/*
* Verify a signature.
*
* Parameters are passed using the DER encoding format following the ASN.1
@@ -143,6 +310,10 @@
int rc;
void *sig_opts = NULL;
unsigned char *p, *end;
+ unsigned char *local_sig_ptr;
+ size_t local_sig_len;
+ psa_ecc_family_t psa_ecc_family = 0U;
+ __unused unsigned char reformatted_sig[MAX_ECDSA_R_S_PAIR_LEN] = {0};
/* construct PSA key algo and type */
psa_status_t status = PSA_SUCCESS;
@@ -174,10 +345,36 @@
rc = CRYPTO_ERR_SIGNATURE;
goto end2;
}
- signature.p = p;
+
+ local_sig_ptr = p;
+ local_sig_len = signature.len;
+
+#if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA || \
+TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA
+ if (pk_alg == MBEDTLS_PK_ECDSA) {
+ rc = get_ecdsa_signature_from_asn1(local_sig_ptr,
+ &local_sig_len,
+ reformatted_sig);
+ if (rc != 0) {
+ goto end2;
+ }
+
+ local_sig_ptr = reformatted_sig;
+
+ rc = get_ecdsa_pkinfo_from_asn1((unsigned char **)&pk_ptr,
+ &pk_len,
+ &psa_ecc_family);
+ if (rc != 0) {
+ goto end2;
+ }
+ }
+#endif /*
+ * TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA || \
+ * TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA
+ **/
/* Convert this pk_alg and md_alg to PSA key type and key algorithm */
- construct_psa_key_alg_and_type(pk_alg, md_alg,
+ construct_psa_key_alg_and_type(pk_alg, md_alg, psa_ecc_family,
&psa_alg, &psa_key_type);
@@ -208,7 +405,7 @@
*/
status = psa_verify_message(psa_key_id, psa_alg,
data_ptr, data_len,
- signature.p, signature.len);
+ local_sig_ptr, local_sig_len);
if (status != PSA_SUCCESS) {
rc = CRYPTO_ERR_SIGNATURE;
diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h
index da4ee7f..a711753 100644
--- a/include/arch/aarch32/arch.h
+++ b/include/arch/aarch32/arch.h
@@ -796,5 +796,6 @@
#define DSU_CLUSTER_PWR_OFF 0
#define DSU_CLUSTER_PWR_ON 1
#define DSU_CLUSTER_PWR_MASK U(1)
+#define DSU_CLUSTER_MEM_RET BIT(1)
#endif /* ARCH_H */
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 001fad5..13927bd 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -1416,6 +1416,7 @@
#define DSU_CLUSTER_PWR_OFF 0
#define DSU_CLUSTER_PWR_ON 1
#define DSU_CLUSTER_PWR_MASK U(1)
+#define DSU_CLUSTER_MEM_RET BIT(1)
/*******************************************************************************
* Definitions for CPU Power/Performance Management registers
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index 536d807..9c9c00f 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S
@@ -441,4 +441,20 @@
#endif
.endm
+/* -----------------------------------------------------------------
+ * The below macro reads SCR_EL3 from the context structure to
+ * determine the security state of the context upon ERET.
+ * ------------------------------------------------------------------
+ */
+ .macro get_security_state _ret:req, _scr_reg:req
+ ubfx \_ret, \_scr_reg, #SCR_NSE_SHIFT, #1
+ cmp \_ret, #1
+ beq realm_state
+ bfi \_ret, \_scr_reg, #0, #1
+ b end
+ realm_state:
+ mov \_ret, #2
+ end:
+ .endm
+
#endif /* EL3_COMMON_MACROS_S */
diff --git a/include/common/tbbr/cot_def.h b/include/common/tbbr/cot_def.h
index 1d28772..bf23917 100644
--- a/include/common/tbbr/cot_def.h
+++ b/include/common/tbbr/cot_def.h
@@ -32,7 +32,12 @@
* buffers must be big enough to hold either. As RSA keys are bigger than ECDSA
* ones for all key sizes we support, they impose the minimum size of these
* buffers.
+ *
+ * If the platform employs its own mbedTLS configuration, it is the platform's
+ * responsibility to define TF_MBEDTLS_USE_RSA or TF_MBEDTLS_USE_ECDSA to
+ * establish the appropriate PK_DER_LEN size.
*/
+#ifdef MBEDTLS_CONFIG_FILE
#if TF_MBEDTLS_USE_RSA
#if TF_MBEDTLS_KEY_SIZE == 1024
#define PK_DER_LEN 162
@@ -45,7 +50,7 @@
#else
#error "Invalid value for TF_MBEDTLS_KEY_SIZE"
#endif
-#else /* Only using ECDSA keys. */
+#elif TF_MBEDTLS_USE_ECDSA
#if TF_MBEDTLS_KEY_SIZE == 384
#define PK_DER_LEN 120
#elif TF_MBEDTLS_KEY_SIZE == 256
@@ -53,7 +58,9 @@
#else
#error "Invalid value for TF_MBEDTLS_KEY_SIZE"
#endif
-#endif
+#else
+#error "Invalid value of algorithm"
+#endif /* TF_MBEDTLS_USE_RSA */
#if TF_MBEDTLS_HASH_ALG_ID == TF_MBEDTLS_SHA256
#define HASH_DER_LEN 51
@@ -64,5 +71,6 @@
#else
#error "Invalid value for TF_MBEDTLS_HASH_ALG_ID"
#endif
+#endif /* MBEDTLS_CONFIG_FILE */
#endif /* COT_DEF_H */
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index e7e9f58..470d113 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,6 +7,7 @@
#ifndef CONTEXT_H
#define CONTEXT_H
+#include <lib/el3_runtime/cpu_data.h>
#include <lib/utils_def.h>
/*******************************************************************************
@@ -61,10 +62,8 @@
#define CTX_ELR_EL3 U(0x20)
#define CTX_PMCR_EL0 U(0x28)
#define CTX_IS_IN_EL3 U(0x30)
-#define CTX_CPTR_EL3 U(0x38)
-#define CTX_ZCR_EL3 U(0x40)
-#define CTX_MPAM3_EL3 U(0x48)
-#define CTX_EL3STATE_END U(0x50) /* Align to the next 16 byte boundary */
+#define CTX_MPAM3_EL3 U(0x38)
+#define CTX_EL3STATE_END U(0x40) /* Align to the next 16 byte boundary */
/*******************************************************************************
* Constants that allow assembler code to access members of and the
@@ -324,6 +323,13 @@
#define CTX_PAUTH_REGS_END U(0)
#endif /* CTX_INCLUDE_PAUTH_REGS */
+/*******************************************************************************
+ * Registers initialised in a per-world context.
+ ******************************************************************************/
+#define CTX_CPTR_EL3 U(0x0)
+#define CTX_ZCR_EL3 U(0x8)
+#define CTX_GLOBAL_EL3STATE_END U(0x10)
+
#ifndef __ASSEMBLER__
#include <stdint.h>
@@ -434,6 +440,17 @@
#endif
} cpu_context_t;
+/*
+ * Per-World Context.
+ * It stores registers whose values can be shared across CPUs.
+ */
+typedef struct per_world_context {
+ uint64_t ctx_cptr_el3;
+ uint64_t ctx_zcr_el3;
+} per_world_context_t;
+
+extern per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM];
+
/* Macros to access members of the 'cpu_context_t' structure */
#define get_el3state_ctx(h) (&((cpu_context_t *) h)->el3state_ctx)
#if CTX_INCLUDE_FPREGS
diff --git a/include/lib/el3_runtime/context_mgmt.h b/include/lib/el3_runtime/context_mgmt.h
index aa76f3b..b2bdaf5 100644
--- a/include/lib/el3_runtime/context_mgmt.h
+++ b/include/lib/el3_runtime/context_mgmt.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -39,6 +39,7 @@
#ifdef __aarch64__
#if IMAGE_BL31
void cm_manage_extensions_el3(void);
+void manage_extensions_nonsecure_per_world(void);
#endif
#if CTX_INCLUDE_EL2_REGS
void cm_el2_sysregs_context_save(uint32_t security_state);
@@ -88,6 +89,7 @@
void *cm_get_next_context(void);
void cm_set_next_context(void *context);
static inline void cm_manage_extensions_el3(void) {}
+static inline void manage_extensions_nonsecure_per_world(void) {}
#endif /* __aarch64__ */
#endif /* CONTEXT_MGMT_H */
diff --git a/include/lib/extensions/amu.h b/include/lib/extensions/amu.h
index 09d8dee..a396b99 100644
--- a/include/lib/extensions/amu.h
+++ b/include/lib/extensions/amu.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,9 +19,11 @@
void amu_enable(cpu_context_t *ctx);
void amu_init_el3(void);
void amu_init_el2_unused(void);
+void amu_enable_per_world(per_world_context_t *per_world_ctx);
#else
void amu_enable(bool el2_unused);
-#endif
+#endif /* __aarch64__ */
+
#else
#if __aarch64__
void amu_enable(cpu_context_t *ctx)
@@ -33,12 +35,15 @@
void amu_init_el2_unused(void)
{
}
+void amu_enable_per_world(per_world_context_t *per_world_ctx)
+{
+}
#else
static inline void amu_enable(bool el2_unused)
{
}
-#endif
-#endif
+#endif /*__aarch64__ */
+#endif /* ENABLE_FEAT_AMU */
#if ENABLE_AMU_AUXILIARY_COUNTERS
/*
diff --git a/include/lib/extensions/sme.h b/include/lib/extensions/sme.h
index dbefdfc..bd7948e 100644
--- a/include/lib/extensions/sme.h
+++ b/include/lib/extensions/sme.h
@@ -21,23 +21,31 @@
#define SME_SMCR_LEN_MAX U(0x1FF)
#if ENABLE_SME_FOR_NS
-void sme_enable(cpu_context_t *context);
void sme_init_el3(void);
void sme_init_el2_unused(void);
+void sme_enable(cpu_context_t *context);
void sme_disable(cpu_context_t *context);
+void sme_enable_per_world(per_world_context_t *per_world_ctx);
+void sme_disable_per_world(per_world_context_t *per_world_ctx);
#else
-static inline void sme_enable(cpu_context_t *context)
-{
-}
static inline void sme_init_el3(void)
{
}
static inline void sme_init_el2_unused(void)
{
}
+static inline void sme_enable(cpu_context_t *context)
+{
+}
static inline void sme_disable(cpu_context_t *context)
{
}
+static inline void sme_enable_per_world(per_world_context_t *per_world_ctx)
+{
+}
+static inline void sme_disable_per_world(per_world_context_t *per_world_ctx)
+{
+}
#endif /* ENABLE_SME_FOR_NS */
#endif /* SME_H */
diff --git a/include/lib/extensions/sve.h b/include/lib/extensions/sve.h
index fc76a16..947c905 100644
--- a/include/lib/extensions/sve.h
+++ b/include/lib/extensions/sve.h
@@ -10,17 +10,17 @@
#include <context.h>
#if (ENABLE_SME_FOR_NS || ENABLE_SVE_FOR_NS)
-void sve_enable(cpu_context_t *context);
void sve_init_el2_unused(void);
-void sve_disable(cpu_context_t *context);
+void sve_enable_per_world(per_world_context_t *per_world_ctx);
+void sve_disable_per_world(per_world_context_t *per_world_ctx);
#else
-static inline void sve_enable(cpu_context_t *context)
+static inline void sve_init_el2_unused(void)
{
}
-static inline void sve_init_el2_unused(void)
+static inline void sve_enable_per_world(per_world_context_t *per_world_ctx)
{
}
-static inline void sve_disable(cpu_context_t *context)
+static inline void sve_disable_per_world(per_world_context_t *per_world_ctx)
{
}
#endif /* ( ENABLE_SME_FOR_NS | ENABLE_SVE_FOR_NS ) */
diff --git a/include/lib/extensions/sys_reg_trace.h b/include/lib/extensions/sys_reg_trace.h
index beda88a..7004267 100644
--- a/include/lib/extensions/sys_reg_trace.h
+++ b/include/lib/extensions/sys_reg_trace.h
@@ -12,8 +12,8 @@
#if ENABLE_SYS_REG_TRACE_FOR_NS
#if __aarch64__
-void sys_reg_trace_enable(cpu_context_t *context);
-void sys_reg_trace_disable(cpu_context_t *context);
+void sys_reg_trace_enable_per_world(per_world_context_t *per_world_ctx);
+void sys_reg_trace_disable_per_world(per_world_context_t *per_world_ctx);
void sys_reg_trace_init_el2_unused(void);
#else
void sys_reg_trace_init_el3(void);
@@ -22,10 +22,10 @@
#else /* !ENABLE_SYS_REG_TRACE_FOR_NS */
#if __aarch64__
-static inline void sys_reg_trace_enable(cpu_context_t *context)
+static inline void sys_reg_trace_enable_per_world(per_world_context_t *per_world_ctx)
{
}
-static inline void sys_reg_trace_disable(cpu_context_t *context)
+static inline void sys_reg_trace_disable_per_world(per_world_context_t *per_world_ctx)
{
}
static inline void sys_reg_trace_init_el2_unused(void)
diff --git a/include/services/rmmd_svc.h b/include/services/rmmd_svc.h
index 55d778e..a567d28 100644
--- a/include/services/rmmd_svc.h
+++ b/include/services/rmmd_svc.h
@@ -91,6 +91,10 @@
#define E_RMM_NOMEM -4
#define E_RMM_INVAL -5
+/* Return error codes from RMI SMCs */
+#define RMI_SUCCESS 0
+#define RMI_ERROR_INPUT 1
+
/* Acceptable SHA sizes for Challenge object */
#define SHA256_DIGEST_SIZE 32U
#define SHA384_DIGEST_SIZE 48U
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index 758355a..41b25d6 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -570,6 +570,25 @@
ret
endfunc save_and_update_ptw_el1_sys_regs
+/* -----------------------------------------------------------------
+* The below macro returns the address of the per_world context for
+* the security state, retrieved through "get_security_state" macro.
+* The per_world context address is returned in the register argument.
+* Clobbers: x9, x10
+* ------------------------------------------------------------------
+*/
+
+.macro get_per_world_context _reg:req
+ ldr x10, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
+ get_security_state x9, x10
+ mov_imm x10, (CTX_GLOBAL_EL3STATE_END - CTX_CPTR_EL3)
+ mul x9, x9, x10
+ adrp x10, per_world_context
+ add x10, x10, :lo12:per_world_context
+ add x9, x9, x10
+ mov \_reg, x9
+.endm
+
/* ------------------------------------------------------------------
* This routine assumes that the SP_EL3 is pointing to a valid
* context structure from where the gp regs and other special
@@ -600,7 +619,11 @@
* Synchronization is required before zcr_el3 is addressed.
* ----------------------------------------------------------
*/
- ldp x19, x20, [sp, #CTX_EL3STATE_OFFSET + CTX_CPTR_EL3]
+
+ /* The address of the per_world context is stored in x9 */
+ get_per_world_context x9
+
+ ldp x19, x20, [x9, #CTX_CPTR_EL3]
msr cptr_el3, x19
#if IMAGE_BL31
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 98cee16..6231898 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -20,6 +20,7 @@
#include <context.h>
#include <drivers/arm/gicv3.h>
#include <lib/el3_runtime/context_mgmt.h>
+#include <lib/el3_runtime/cpu_data.h>
#include <lib/el3_runtime/pubsub_events.h>
#include <lib/extensions/amu.h>
#include <lib/extensions/brbe.h>
@@ -38,8 +39,12 @@
CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check);
#endif /* ENABLE_FEAT_TWED */
+per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM];
+static bool has_secure_perworld_init;
+
static void manage_extensions_nonsecure(cpu_context_t *ctx);
static void manage_extensions_secure(cpu_context_t *ctx);
+static void manage_extensions_secure_per_world(void);
static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep)
{
@@ -146,6 +151,18 @@
#endif
manage_extensions_secure(ctx);
+
+ /**
+ * manage_extensions_secure_per_world api has to be executed once,
+ * as the registers getting initialised, maintain constant value across
+ * all the cpus for the secure world.
+ * Henceforth, this check ensures that the registers are initialised once
+ * and avoids re-initialization from multiple cores.
+ */
+ if (!has_secure_perworld_init) {
+ manage_extensions_secure_per_world();
+ }
+
}
#if ENABLE_RME
@@ -301,7 +318,6 @@
******************************************************************************/
static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep)
{
- u_register_t cptr_el3;
u_register_t scr_el3;
el3_state_t *state;
gp_regs_t *gp_regs;
@@ -425,21 +441,6 @@
}
/*
- * Initialise CPTR_EL3, setting all fields rather than relying on hw.
- * All fields are architecturally UNKNOWN on reset.
- *
- * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers
- * by Advanced SIMD, floating-point or SVE instructions (if
- * implemented) do not trap to EL3.
- *
- * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1,
- * CPTR_EL2,CPACR, or HCPTR do not trap to EL3.
- */
- cptr_el3 = CPTR_EL3_RESET_VAL & ~(TFP_BIT | TCPAC_BIT);
-
- write_ctx_reg(state, CTX_CPTR_EL3, cptr_el3);
-
- /*
* SCR_EL3.HCE: Enable HVC instructions if next execution state is
* AArch64 and next EL is EL2, or if next execution state is AArch32 and
* next mode is Hyp.
@@ -600,28 +601,95 @@
#endif /* IMAGE_BL31 */
/*******************************************************************************
- * Enable architecture extensions on first entry to Non-secure world.
+ * Initialise per_world_context for Non-Secure world.
+ * This function enables the architecture extensions, which have same value
+ * across the cores for the non-secure world.
******************************************************************************/
-static void manage_extensions_nonsecure(cpu_context_t *ctx)
-{
#if IMAGE_BL31
- if (is_feat_amu_supported()) {
- amu_enable(ctx);
+void manage_extensions_nonsecure_per_world(void)
+{
+ if (is_feat_sme_supported()) {
+ sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
}
- /* Enable SVE and FPU/SIMD */
if (is_feat_sve_supported()) {
- sve_enable(ctx);
+ sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
+ }
+
+ if (is_feat_amu_supported()) {
+ amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
+ }
+
+ if (is_feat_sys_reg_trace_supported()) {
+ sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
}
+}
+#endif /* IMAGE_BL31 */
+/*******************************************************************************
+ * Initialise per_world_context for Secure world.
+ * This function enables the architecture extensions, which have same value
+ * across the cores for the secure world.
+ ******************************************************************************/
+
+static void manage_extensions_secure_per_world(void)
+{
+#if IMAGE_BL31
if (is_feat_sme_supported()) {
- sme_enable(ctx);
+
+ if (ENABLE_SME_FOR_SWD) {
+ /*
+ * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure
+ * SME, SVE, and FPU/SIMD context properly managed.
+ */
+ sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
+ } else {
+ /*
+ * Disable SME, SVE, FPU/SIMD in secure context so non-secure
+ * world can safely use the associated registers.
+ */
+ sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
+ }
+ }
+ if (is_feat_sve_supported()) {
+ if (ENABLE_SVE_FOR_SWD) {
+ /*
+ * Enable SVE and FPU in secure context, SPM must ensure
+ * that the SVE and FPU register contexts are properly managed.
+ */
+ sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
+ } else {
+ /*
+ * Disable SVE and FPU in secure context so non-secure world
+ * can safely use them.
+ */
+ sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
+ }
}
+ /* NS can access this but Secure shouldn't */
if (is_feat_sys_reg_trace_supported()) {
- sys_reg_trace_enable(ctx);
+ sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
}
+ has_secure_perworld_init = true;
+#endif /* IMAGE_BL31 */
+}
+
+/*******************************************************************************
+ * Enable architecture extensions on first entry to Non-secure world.
+ ******************************************************************************/
+static void manage_extensions_nonsecure(cpu_context_t *ctx)
+{
+#if IMAGE_BL31
+ if (is_feat_amu_supported()) {
+ amu_enable(ctx);
+ }
+
+ if (is_feat_sme_supported()) {
+ sme_enable(ctx);
+ }
+
if (is_feat_mpam_supported()) {
mpam_enable(ctx);
}
@@ -696,23 +764,6 @@
static void manage_extensions_secure(cpu_context_t *ctx)
{
#if IMAGE_BL31
- if (is_feat_sve_supported()) {
- if (ENABLE_SVE_FOR_SWD) {
- /*
- * Enable SVE and FPU in secure context, secure manager must
- * ensure that the SVE and FPU register contexts are properly
- * managed.
- */
- sve_enable(ctx);
- } else {
- /*
- * Disable SVE and FPU in secure context so non-secure world
- * can safely use them.
- */
- sve_disable(ctx);
- }
- }
-
if (is_feat_sme_supported()) {
if (ENABLE_SME_FOR_SWD) {
/*
@@ -729,11 +780,6 @@
sme_disable(ctx);
}
}
-
- /* NS can access this but Secure shouldn't */
- if (is_feat_sys_reg_trace_supported()) {
- sys_reg_trace_disable(ctx);
- }
#endif /* IMAGE_BL31 */
}
diff --git a/lib/extensions/amu/aarch64/amu.c b/lib/extensions/amu/aarch64/amu.c
index 53bdb55..cb9a0f2 100644
--- a/lib/extensions/amu/aarch64/amu.c
+++ b/lib/extensions/amu/aarch64/amu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -180,15 +180,6 @@
*/
void amu_enable(cpu_context_t *ctx)
{
- /*
- * Set CPTR_EL3.TAM to zero so that any accesses to the Activity Monitor
- * registers do not trap to EL3.
- */
- u_register_t cptr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3);
-
- cptr_el3 &= ~TAM_BIT;
- write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, cptr_el3);
-
/* Initialize FEAT_AMUv1p1 features if present. */
if (is_feat_amuv1p1_supported()) {
/*
@@ -199,6 +190,18 @@
}
}
+void amu_enable_per_world(per_world_context_t *per_world_ctx)
+{
+ /*
+ * Set CPTR_EL3.TAM to zero so that any accesses to the Activity Monitor
+ * registers do not trap to EL3.
+ */
+ uint64_t cptr_el3 = per_world_ctx->ctx_cptr_el3;
+
+ cptr_el3 &= ~TAM_BIT;
+ per_world_ctx->ctx_cptr_el3 = cptr_el3;
+}
+
void amu_init_el3(void)
{
uint64_t group0_impl_ctr = read_amcgcr_el0_cg0nc();
diff --git a/lib/extensions/sme/sme.c b/lib/extensions/sme/sme.c
index d705b64..b1409b9 100644
--- a/lib/extensions/sme/sme.c
+++ b/lib/extensions/sme/sme.c
@@ -22,17 +22,22 @@
/* Get the context state. */
state = get_el3state_ctx(context);
- /* Enable SME in CPTR_EL3. */
- reg = read_ctx_reg(state, CTX_CPTR_EL3);
- reg |= ESM_BIT;
- write_ctx_reg(state, CTX_CPTR_EL3, reg);
-
/* Set the ENTP2 bit in SCR_EL3 to enable access to TPIDR2_EL0. */
reg = read_ctx_reg(state, CTX_SCR_EL3);
reg |= SCR_ENTP2_BIT;
write_ctx_reg(state, CTX_SCR_EL3, reg);
}
+void sme_enable_per_world(per_world_context_t *per_world_ctx)
+{
+ u_register_t reg;
+
+ /* Enable SME in CPTR_EL3. */
+ reg = per_world_ctx->ctx_cptr_el3;
+ reg |= ESM_BIT;
+ per_world_ctx->ctx_cptr_el3 = reg;
+}
+
void sme_init_el3(void)
{
u_register_t cptr_el3 = read_cptr_el3();
@@ -43,7 +48,7 @@
isb();
/*
- * Set the max LEN value and FA64 bit. This register is set up globally
+ * Set the max LEN value and FA64 bit. This register is set up per_world
* to be the least restrictive, then lower ELs can restrict as needed
* using SMCR_EL2 and SMCR_EL1.
*/
@@ -87,15 +92,20 @@
/* Get the context state. */
state = get_el3state_ctx(context);
- /* Disable SME, SVE, and FPU since they all share registers. */
- reg = read_ctx_reg(state, CTX_CPTR_EL3);
- reg &= ~ESM_BIT; /* Trap SME */
- reg &= ~CPTR_EZ_BIT; /* Trap SVE */
- reg |= TFP_BIT; /* Trap FPU/SIMD */
- write_ctx_reg(state, CTX_CPTR_EL3, reg);
-
/* Disable access to TPIDR2_EL0. */
reg = read_ctx_reg(state, CTX_SCR_EL3);
reg &= ~SCR_ENTP2_BIT;
write_ctx_reg(state, CTX_SCR_EL3, reg);
}
+
+void sme_disable_per_world(per_world_context_t *per_world_ctx)
+{
+ u_register_t reg;
+
+ /* Disable SME, SVE, and FPU since they all share registers. */
+ reg = per_world_ctx->ctx_cptr_el3;
+ reg &= ~ESM_BIT; /* Trap SME */
+ reg &= ~CPTR_EZ_BIT; /* Trap SVE */
+ reg |= TFP_BIT; /* Trap FPU/SIMD */
+ per_world_ctx->ctx_cptr_el3 = reg;
+}
diff --git a/lib/extensions/sve/sve.c b/lib/extensions/sve/sve.c
index eb4ac8d..143717e 100644
--- a/lib/extensions/sve/sve.c
+++ b/lib/extensions/sve/sve.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,19 +22,17 @@
*/
#define CONVERT_SVE_LENGTH(x) (((x / 128) - 1))
-void sve_enable(cpu_context_t *context)
+void sve_enable_per_world(per_world_context_t *per_world_ctx)
{
u_register_t cptr_el3;
- cptr_el3 = read_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3);
-
/* Enable access to SVE functionality for all ELs. */
+ cptr_el3 = per_world_ctx->ctx_cptr_el3;
cptr_el3 = (cptr_el3 | CPTR_EZ_BIT) & ~(TFP_BIT);
- write_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3, cptr_el3);
+ per_world_ctx->ctx_cptr_el3 = cptr_el3;
/* Restrict maximum SVE vector length (SVE_VECTOR_LEN+1) * 128. */
- write_ctx_reg(get_el3state_ctx(context), CTX_ZCR_EL3,
- (ZCR_EL3_LEN_MASK & CONVERT_SVE_LENGTH(SVE_VECTOR_LEN)));
+ per_world_ctx->ctx_zcr_el3 = (ZCR_EL3_LEN_MASK & CONVERT_SVE_LENGTH(SVE_VECTOR_LEN));
}
void sve_init_el2_unused(void)
@@ -47,17 +45,13 @@
write_cptr_el2(read_cptr_el2() & ~CPTR_EL2_TFP_BIT);
}
-void sve_disable(cpu_context_t *context)
+void sve_disable_per_world(per_world_context_t *per_world_ctx)
{
u_register_t reg;
- el3_state_t *state;
-
- /* Get the context state. */
- state = get_el3state_ctx(context);
/* Disable SVE and FPU since they share registers. */
- reg = read_ctx_reg(state, CTX_CPTR_EL3);
+ reg = per_world_ctx->ctx_cptr_el3;
reg &= ~CPTR_EZ_BIT; /* Trap SVE */
reg |= TFP_BIT; /* Trap FPU/SIMD */
- write_ctx_reg(state, CTX_CPTR_EL3, reg);
+ per_world_ctx->ctx_cptr_el3 = reg;
}
diff --git a/lib/extensions/sys_reg_trace/aarch64/sys_reg_trace.c b/lib/extensions/sys_reg_trace/aarch64/sys_reg_trace.c
index 1349566..2170763 100644
--- a/lib/extensions/sys_reg_trace/aarch64/sys_reg_trace.c
+++ b/lib/extensions/sys_reg_trace/aarch64/sys_reg_trace.c
@@ -10,29 +10,27 @@
#include <arch_helpers.h>
#include <lib/extensions/sys_reg_trace.h>
-void sys_reg_trace_enable(cpu_context_t *ctx)
+void sys_reg_trace_enable_per_world(per_world_context_t *per_world_ctx)
{
/*
* CPTR_EL3.TTA: Set to zero so that System register accesses to the
* trace registers do not trap to EL3.
*/
- uint64_t val = read_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3);
-
+ uint64_t val = per_world_ctx->ctx_cptr_el3;
val &= ~(TTA_BIT);
- write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, val);
+ per_world_ctx->ctx_cptr_el3 = val;
}
-void sys_reg_trace_disable(cpu_context_t *ctx)
+void sys_reg_trace_disable_per_world(per_world_context_t *per_world_ctx)
{
/*
* CPTR_EL3.TTA: Set to one so that System register accesses to the
* trace registers trap to EL3, unless it is trapped by CPACR.TRCDIS,
* CPACR_EL1.TTA, or CPTR_EL2.TTA
*/
- uint64_t val = read_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3);
-
+ uint64_t val = per_world_ctx->ctx_cptr_el3;
val |= TTA_BIT;
- write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, val);
+ per_world_ctx->ctx_cptr_el3 = val;
}
void sys_reg_trace_init_el2_unused(void)
diff --git a/lib/psa/delegated_attestation.c b/lib/psa/delegated_attestation.c
index a813e84..81e2621 100644
--- a/lib/psa/delegated_attestation.c
+++ b/lib/psa/delegated_attestation.c
@@ -5,13 +5,10 @@
*
*/
-#include <string.h>
-
#include <delegated_attestation.h>
#include <psa/client.h>
#include <psa_manifest/sid.h>
-#if !PLAT_RSS_NOT_SUPPORTED
psa_status_t
rss_delegated_attest_get_delegated_key(uint8_t ecc_curve,
uint32_t key_bits,
@@ -74,143 +71,3 @@
return status;
}
-
-
-#else /* !PLAT_RSS_NOT_SUPPORTED */
-
-static const uint8_t delegated_key[] = {
- 0x20, 0x11, 0xC7, 0xF0, 0x3C, 0xEE, 0x43, 0x25, 0x17, 0x6E,
- 0x52, 0x4F, 0x03, 0x3C, 0x0C, 0xE1, 0xE2, 0x1A, 0x76, 0xE6,
- 0xC1, 0xA4, 0xF0, 0xB8, 0x39, 0xAA, 0x1D, 0xF6, 0x1E, 0x0E,
- 0x8A, 0x5C, 0x8A, 0x05, 0x74, 0x0F, 0x9B, 0x69, 0xEF, 0xA7,
- 0xEB, 0x1A, 0x41, 0x85, 0xBD, 0x11, 0x7F, 0x68
-};
-
-static const uint8_t platform_token[] = {
- 0xD2, 0x84, 0x44, 0xA1, 0x01, 0x38, 0x22, 0xA0,
- 0x59, 0x02, 0x33, 0xA9, 0x19, 0x01, 0x09, 0x78,
- 0x1C, 0x68, 0x74, 0x74, 0x70, 0x3A, 0x2F, 0x2F,
- 0x61, 0x72, 0x6D, 0x2E, 0x63, 0x6F, 0x6D, 0x2F,
- 0x43, 0x43, 0x41, 0x2D, 0x53, 0x53, 0x44, 0x2F,
- 0x31, 0x2E, 0x30, 0x2E, 0x30, 0x0A, 0x58, 0x20,
- 0xB5, 0x97, 0x3C, 0xB6, 0x8B, 0xAA, 0x9F, 0xC5,
- 0x55, 0x58, 0x78, 0x6B, 0x7E, 0xC6, 0x7F, 0x69,
- 0xE4, 0x0D, 0xF5, 0xBA, 0x5A, 0xA9, 0x21, 0xCD,
- 0x0C, 0x27, 0xF4, 0x05, 0x87, 0xA0, 0x11, 0xEA,
- 0x19, 0x09, 0x5C, 0x58, 0x20, 0x7F, 0x45, 0x4C,
- 0x46, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x3E,
- 0x00, 0x01, 0x00, 0x00, 0x00, 0x50, 0x58, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x01, 0x00,
- 0x58, 0x21, 0x01, 0x07, 0x06, 0x05, 0x04, 0x03,
- 0x02, 0x01, 0x00, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B,
- 0x0A, 0x09, 0x08, 0x17, 0x16, 0x15, 0x14, 0x13,
- 0x12, 0x11, 0x10, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B,
- 0x1A, 0x19, 0x18, 0x19, 0x09, 0x61, 0x58, 0x21,
- 0x01, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01,
- 0x00, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09,
- 0x08, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11,
- 0x10, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19,
- 0x18, 0x19, 0x09, 0x5B, 0x19, 0x30, 0x03, 0x19,
- 0x09, 0x62, 0x67, 0x73, 0x68, 0x61, 0x2D, 0x32,
- 0x35, 0x36, 0x19, 0x09, 0x5F, 0x84, 0xA5, 0x01,
- 0x62, 0x42, 0x4C, 0x05, 0x58, 0x20, 0x07, 0x06,
- 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E,
- 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16,
- 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E,
- 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, 0x65,
- 0x33, 0x2E, 0x34, 0x2E, 0x32, 0x02, 0x58, 0x20,
- 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00,
- 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08,
- 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10,
- 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18,
- 0x06, 0x74, 0x54, 0x46, 0x2D, 0x4D, 0x5F, 0x53,
- 0x48, 0x41, 0x32, 0x35, 0x36, 0x4D, 0x65, 0x6D,
- 0x50, 0x72, 0x65, 0x58, 0x49, 0x50, 0xA4, 0x01,
- 0x62, 0x4D, 0x31, 0x05, 0x58, 0x20, 0x07, 0x06,
- 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E,
- 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16,
- 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E,
- 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, 0x63,
- 0x31, 0x2E, 0x32, 0x02, 0x58, 0x20, 0x07, 0x06,
- 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E,
- 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16,
- 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E,
- 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0xA4, 0x01,
- 0x62, 0x4D, 0x32, 0x05, 0x58, 0x20, 0x07, 0x06,
- 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E,
- 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16,
- 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E,
- 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, 0x65,
- 0x31, 0x2E, 0x32, 0x2E, 0x33, 0x02, 0x58, 0x20,
- 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00,
- 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08,
- 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10,
- 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18,
- 0xA4, 0x01, 0x62, 0x4D, 0x33, 0x05, 0x58, 0x20,
- 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00,
- 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08,
- 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10,
- 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18,
- 0x04, 0x61, 0x31, 0x02, 0x58, 0x20, 0x07, 0x06,
- 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E,
- 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16,
- 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E,
- 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x19, 0x09,
- 0x60, 0x6C, 0x77, 0x68, 0x61, 0x74, 0x65, 0x76,
- 0x65, 0x72, 0x2E, 0x63, 0x6F, 0x6D, 0x58, 0x60,
- 0xE6, 0xB6, 0x38, 0x4F, 0xAE, 0x3F, 0x6E, 0x67,
- 0xF5, 0xD4, 0x97, 0x4B, 0x3F, 0xFD, 0x0A, 0xFA,
- 0x1D, 0xF0, 0x2F, 0x73, 0xB8, 0xFF, 0x5F, 0x02,
- 0xC0, 0x0F, 0x40, 0xAC, 0xF3, 0xA2, 0x9D, 0xB5,
- 0x31, 0x50, 0x16, 0x4F, 0xFA, 0x34, 0x3D, 0x0E,
- 0xAF, 0xE0, 0xD0, 0xD1, 0x6C, 0xF0, 0x9D, 0xC1,
- 0x01, 0x42, 0xA2, 0x3C, 0xCE, 0xD4, 0x4A, 0x59,
- 0xDC, 0x29, 0x0A, 0x30, 0x93, 0x5F, 0xB4, 0x98,
- 0x61, 0xBA, 0xE3, 0x91, 0x22, 0x95, 0x24, 0xF4,
- 0xAE, 0x47, 0x93, 0xD3, 0x84, 0xA3, 0x76, 0xD0,
- 0xC1, 0x26, 0x96, 0x53, 0xA3, 0x60, 0x3F, 0x6C,
- 0x75, 0x96, 0x90, 0x6A, 0xF9, 0x4E, 0xDA, 0x30
-};
-
-psa_status_t
-rss_delegated_attest_get_delegated_key(uint8_t ecc_curve,
- uint32_t key_bits,
- uint8_t *key_buf,
- size_t key_buf_size,
- size_t *key_size,
- uint32_t hash_algo)
-{
- (void)ecc_curve;
- (void)key_bits;
- (void)hash_algo;
-
- if (key_buf_size < sizeof(delegated_key)) {
- return PSA_ERROR_BUFFER_TOO_SMALL;
- }
-
- (void)memcpy(key_buf, delegated_key, sizeof(delegated_key));
- *key_size = sizeof(delegated_key);
-
- return PSA_SUCCESS;
-}
-psa_status_t
-rss_delegated_attest_get_token(const uint8_t *dak_pub_hash,
- size_t dak_pub_hash_size,
- uint8_t *token_buf,
- size_t token_buf_size,
- size_t *token_size)
-{
- (void)dak_pub_hash;
- (void)dak_pub_hash_size;
-
- if (token_buf_size < sizeof(platform_token)) {
- return PSA_ERROR_BUFFER_TOO_SMALL;
- }
-
- (void)memcpy(token_buf, platform_token, sizeof(platform_token));
- *token_size = sizeof(platform_token);
-
- return PSA_SUCCESS;
-}
-#endif /* !PLAT_RSS_NOT_SUPPORTED */
diff --git a/make_helpers/arch_features.mk b/make_helpers/arch_features.mk
index c92b4a5..a337e76 100644
--- a/make_helpers/arch_features.mk
+++ b/make_helpers/arch_features.mk
@@ -8,12 +8,64 @@
# and enables them based on the configured architecture version.
# This file follows the following format:
-# - By default disable any mandatory features.
-# - Then Enable mandatory feature if applicable to an Arch Version.
+# - Enable mandatory feature if applicable to an Arch Version.
+# - By default disable any mandatory features if they have not been defined yet.
# - Disable or enable any optional feature this would be enabled/disabled if needed by platform.
#
################################################################################
+# Enable Mandatory features based on Arch versions.
+################################################################################
+#
+
+# Enable the features which are mandatory from ARCH version 8.1 and upwards.
+ifeq "8.1" "$(word 1, $(sort 8.1 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
+ENABLE_FEAT_PAN := 1
+ENABLE_FEAT_VHE := 1
+endif
+
+# Enable the features which are mandatory from ARCH version 8.2 and upwards.
+ifeq "8.2" "$(word 1, $(sort 8.2 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
+ENABLE_FEAT_RAS := 1
+endif
+
+# Enable the features which are mandatory from ARCH version 8.4 and upwards.
+ifeq "8.4" "$(word 1, $(sort 8.4 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
+ENABLE_FEAT_SEL2 := 1
+ENABLE_TRF_FOR_NS := 1
+ENABLE_FEAT_DIT := 1
+endif
+
+# Enable the features which are mandatory from ARCH version 8.5 and upwards.
+ifeq "8.5" "$(word 1, $(sort 8.5 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
+ENABLE_FEAT_RNG := 1
+ENABLE_FEAT_SB := 1
+
+# Enable Memory tagging, Branch Target Identification for aarch64 only.
+ifeq ($(ARCH), aarch64)
+ mem_tag_arch_support := yes
+endif #(ARCH=aarch64)
+
+endif
+
+# Enable the features which are mandatory from ARCH version 8.6 and upwards.
+ifeq "8.6" "$(word 1, $(sort 8.6 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
+ENABLE_FEAT_ECV := 1
+ENABLE_FEAT_FGT := 1
+endif
+
+# Enable the features which are mandatory from ARCH version 8.7 and upwards.
+ifeq "8.7" "$(word 1, $(sort 8.7 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
+ENABLE_FEAT_HCX := 1
+endif
+
+# Enable the features which are mandatory from ARCH version 8.9 and upwards.
+ifeq "8.9" "$(word 1, $(sort 8.9 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
+ENABLE_FEAT_TCR2 := 1
+endif
+
+#
+################################################################################
# Set mandatory features by default to zero.
################################################################################
#
@@ -23,17 +75,17 @@
#----
# Flag to enable access to Privileged Access Never bit of PSTATE.
-ENABLE_FEAT_PAN := 0
+ENABLE_FEAT_PAN ?= 0
# Flag to enable Virtualization Host Extensions.
-ENABLE_FEAT_VHE := 0
+ENABLE_FEAT_VHE ?= 0
#----
# 8.2
#----
# Enable RAS Support.
-ENABLE_FEAT_RAS := 0
+ENABLE_FEAT_RAS ?= 0
#----
# 8.3
@@ -41,121 +93,70 @@
# Flag to enable Pointer Authentication. Internal flag not meant for
# direct setting. Use BRANCH_PROTECTION to enable PAUTH.
-ENABLE_PAUTH := 0
+ENABLE_PAUTH ?= 0
# Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This
# must be set to 1 if the platform wants to use this feature in the Secure
# world. It is not necessary for use in the Non-secure world.
-CTX_INCLUDE_PAUTH_REGS := 0
+CTX_INCLUDE_PAUTH_REGS ?= 0
+
#----
# 8.4
#----
# Flag to enable Secure EL-2 feature.
-ENABLE_FEAT_SEL2 := 0
+ENABLE_FEAT_SEL2 ?= 0
# By default, disable trace filter control register access to lower non-secure
# exception levels, i.e. NS-EL2, or NS-EL1 if NS-EL2 is implemented, but
# trace filter control register access is unused if FEAT_TRF is implemented.
-ENABLE_TRF_FOR_NS := 0
+ENABLE_TRF_FOR_NS ?= 0
# Flag to enable Data Independent Timing instructions.
-ENABLE_FEAT_DIT := 0
+ENABLE_FEAT_DIT ?= 0
#----
# 8.5
#----
-# Flag to enable access to the Random Number Generator registers.
-ENABLE_FEAT_RNG := 0
-
-# Flag to enable Speculation Barrier Instruction.
-ENABLE_FEAT_SB := 0
-
# Flag to enable Branch Target Identification.
# Internal flag not meant for direct setting.
# Use BRANCH_PROTECTION to enable BTI.
-ENABLE_BTI := 0
+ENABLE_BTI ?= 0
+
+# Flag to enable access to the Random Number Generator registers.
+ENABLE_FEAT_RNG ?= 0
+
+# Flag to enable Speculation Barrier Instruction.
+ENABLE_FEAT_SB ?= 0
#----
# 8.6
#----
# Flag to enable access to the CNTPOFF_EL2 register.
-ENABLE_FEAT_ECV := 0
+ENABLE_FEAT_ECV ?= 0
# Flag to enable access to the HDFGRTR_EL2 register.
-ENABLE_FEAT_FGT := 0
+ENABLE_FEAT_FGT ?= 0
#----
# 8.7
#----
# Flag to enable access to the HCRX_EL2 register by setting SCR_EL3.HXEn.
-ENABLE_FEAT_HCX := 0
+ENABLE_FEAT_HCX ?= 0
#----
# 8.9
#----
# Flag to enable access to TCR2 (FEAT_TCR2).
-ENABLE_FEAT_TCR2 := 0
+ENABLE_FEAT_TCR2 ?= 0
#
################################################################################
-# Enable Mandatory features based on Arch versions.
-################################################################################
-#
-
-# Enable the features which are mandatory from ARCH version 8.1 and upwards.
-ifeq "8.1" "$(word 1, $(sort 8.1 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
-ENABLE_FEAT_PAN := 1
-ENABLE_FEAT_VHE := 1
-endif
-
-# Enable the features which are mandatory from ARCH version 8.2 and upwards.
-ifeq "8.2" "$(word 1, $(sort 8.2 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
-ENABLE_FEAT_RAS := 1
-endif
-
-# Enable the features which are mandatory from ARCH version 8.4 and upwards.
-ifeq "8.4" "$(word 1, $(sort 8.4 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
-ENABLE_FEAT_SEL2 := 1
-ENABLE_TRF_FOR_NS := 1
-ENABLE_FEAT_DIT := 1
-endif
-
-# Enable the features which are mandatory from ARCH version 8.5 and upwards.
-ifeq "8.5" "$(word 1, $(sort 8.5 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
-ENABLE_FEAT_RNG := 1
-ENABLE_FEAT_SB := 1
-
-# Enable Memory tagging, Branch Target Identification for aarch64 only.
-ifeq ($(ARCH), aarch64)
- mem_tag_arch_support := yes
-endif #(ARCH=aarch64)
-
-endif
-
-# Enable the features which are mandatory from ARCH version 8.6 and upwards.
-ifeq "8.6" "$(word 1, $(sort 8.6 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
-ENABLE_FEAT_ECV := 1
-ENABLE_FEAT_FGT := 1
-endif
-
-# Enable the features which are mandatory from ARCH version 8.7 and upwards.
-ifeq "8.7" "$(word 1, $(sort 8.7 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
-ENABLE_FEAT_HCX := 1
-endif
-
-# Enable the features which are mandatory from ARCH version 8.9 and upwards.
-ifeq "8.9" "$(word 1, $(sort 8.9 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
-ENABLE_FEAT_TCR2 := 1
-endif
-
-#
-################################################################################
# Optional Features defaulted to 0 or 2, if they are not enabled from
# build option. Can also be disabled or enabled by platform if needed.
################################################################################
@@ -184,7 +185,7 @@
ifeq (${ARCH},aarch64)
ENABLE_SPE_FOR_NS ?= 2
else ifeq (${ARCH},aarch32)
- ifdef ENABLE_SPE_FOR_NS
+ ifneq ($(or $(ENABLE_SPE_FOR_NS),0),0)
$(error ENABLE_SPE_FOR_NS is not supported for AArch32)
else
ENABLE_SPE_FOR_NS := 0
@@ -196,7 +197,7 @@
ENABLE_SVE_FOR_NS ?= 2
# SVE is only supported on AArch64 so disable it on AArch32.
else ifeq (${ARCH},aarch32)
- ifdef ENABLE_SVE_FOR_NS
+ ifneq ($(or $(ENABLE_SVE_FOR_NS),0),0)
$(error ENABLE_SVE_FOR_NS is not supported for AArch32)
else
ENABLE_SVE_FOR_NS := 0
@@ -216,13 +217,13 @@
# Build option to enable MPAM for lower ELs.
# Enabling it by default
ifeq (${ARCH},aarch64)
- ENABLE_FEAT_MPAM ?= 2
+ ENABLE_FEAT_MPAM ?= 2
else ifeq (${ARCH},aarch32)
- ifdef ENABLE_FEAT_MPAM
- $(error ENABLE_FEAT_MPAM is not supported for AArch32)
- else
- ENABLE_FEAT_MPAM := 0
- endif
+ ifneq ($(or $(ENABLE_FEAT_MPAM),0),0)
+ $(error ENABLE_FEAT_MPAM is not supported for AArch32)
+ else
+ ENABLE_FEAT_MPAM := 0
+ endif
endif
# Include nested virtualization control (Armv8.4-NV) registers in cpu context.
@@ -302,10 +303,10 @@
ifeq (${ARCH},aarch64)
ENABLE_TRBE_FOR_NS ?= 0
else ifeq (${ARCH},aarch32)
- ifdef ENABLE_TRBE_FOR_NS
- $(error ENABLE_TRBE_FOR_NS is not supported for AArch32)
+ ifneq ($(or $(ENABLE_TRBE_FOR_NS),0),0)
+ $(error ENABLE_TRBE_FOR_NS is not supported for AArch32)
else
- ENABLE_TRBE_FOR_NS := 0
+ ENABLE_TRBE_FOR_NS := 0
endif
endif
diff --git a/plat/arm/board/a5ds/a5ds_bl2_setup.c b/plat/arm/board/a5ds/a5ds_bl2_setup.c
index 1979c50..a0aa639 100644
--- a/plat/arm/board/a5ds/a5ds_bl2_setup.c
+++ b/plat/arm/board/a5ds/a5ds_bl2_setup.c
@@ -16,3 +16,8 @@
{
arm_bl2_platform_setup();
}
+
+int bl2_plat_handle_post_image_load(unsigned int image_id)
+{
+ return arm_bl2_plat_handle_post_image_load(image_id);
+}
diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk
index c71c99a..f44b37d 100644
--- a/plat/arm/board/arm_fpga/platform.mk
+++ b/plat/arm/board/arm_fpga/platform.mk
@@ -41,7 +41,6 @@
ENABLE_FEAT_ECV := 2
ENABLE_FEAT_FGT := 2
ENABLE_FEAT_HCX := 2
-ENABLE_FEAT_MPAM := 2
ENABLE_SYS_REG_TRACE_FOR_NS := 2
ENABLE_TRF_FOR_NS := 2
diff --git a/plat/arm/board/corstone1000/common/corstone1000_plat.c b/plat/arm/board/corstone1000/common/corstone1000_plat.c
index 0235f8b..ed3801c 100644
--- a/plat/arm/board/corstone1000/common/corstone1000_plat.c
+++ b/plat/arm/board/corstone1000/common/corstone1000_plat.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -33,36 +33,16 @@
static void set_fip_image_source(void)
{
const struct plat_io_policy *policy;
- /*
- * metadata for firmware update is written at 0x0000 offset of the flash.
- * PLAT_ARM_BOOT_BANK_FLAG contains the boot bank that TF-M is booted.
- * As per firmware update spec, at a given point of time, only one bank
- * is active. This means, TF-A should boot from the same bank as TF-M.
- */
- volatile uint32_t *boot_bank_flag = (uint32_t *)(PLAT_ARM_BOOT_BANK_FLAG);
-
- if (*boot_bank_flag > 1) {
- VERBOSE("Boot_bank is set higher than possible values");
- }
-
- VERBOSE("Boot bank flag = %u.\n\r", *boot_bank_flag);
-
policy = FCONF_GET_PROPERTY(arm, io_policies, FIP_IMAGE_ID);
assert(policy != NULL);
assert(policy->image_spec != 0UL);
+ /* FIP Partition contains Signature area at the beginning which TF-A doesn't expect */
io_block_spec_t *spec = (io_block_spec_t *)policy->image_spec;
+ spec->offset += FIP_SIGNATURE_AREA_SIZE;
+ spec->length -= FIP_SIGNATURE_AREA_SIZE;
- if ((*boot_bank_flag) == 0) {
- VERBOSE("Booting from bank 0: fip offset = 0x%lx\n\r",
- PLAT_ARM_FIP_BASE_BANK0);
- spec->offset = PLAT_ARM_FIP_BASE_BANK0;
- } else {
- VERBOSE("Booting from bank 1: fip offset = 0x%lx\n\r",
- PLAT_ARM_FIP_BASE_BANK1);
- spec->offset = PLAT_ARM_FIP_BASE_BANK1;
- }
}
void bl2_platform_setup(void)
diff --git a/plat/arm/board/corstone1000/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h
index 584d485..442d187 100644
--- a/plat/arm/board/corstone1000/common/include/platform_def.h
+++ b/plat/arm/board/corstone1000/common/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -173,16 +173,15 @@
/* NOR Flash */
-#define PLAT_ARM_BOOT_BANK_FLAG UL(0x08002000)
-#define PLAT_ARM_FIP_BASE_BANK0 UL(0x081EF000)
-#define PLAT_ARM_FIP_BASE_BANK1 UL(0x0916F000)
-#define PLAT_ARM_FIP_MAX_SIZE UL(0x1ff000) /* 1.996 MB */
-
#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
#define PLAT_ARM_NVM_SIZE (SZ_32M) /* 32 MB */
-
-#define PLAT_ARM_FLASH_IMAGE_BASE PLAT_ARM_FIP_BASE_BANK0
+#define PLAT_ARM_FIP_MAX_SIZE UL(0x1ff000) /* 1.996 MB */
+#define PLAT_ARM_FLASH_IMAGE_BASE UL(0x08000000)
#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE PLAT_ARM_FIP_MAX_SIZE
+#define PLAT_ARM_FIP_OFFSET_IN_GPT (0x86000)
+
+/* FIP Information */
+#define FIP_SIGNATURE_AREA_SIZE (0x1000) /* 4 KB */
/*
* Some data must be aligned on the biggest cache line size in the platform.
diff --git a/plat/arm/board/fvp/fvp_bl2_setup.c b/plat/arm/board/fvp/fvp_bl2_setup.c
index d3dc5a3..ebd5266 100644
--- a/plat/arm/board/fvp/fvp_bl2_setup.c
+++ b/plat/arm/board/fvp/fvp_bl2_setup.c
@@ -19,6 +19,8 @@
#include "fvp_private.h"
+static struct transfer_list_header *ns_tl __unused;
+
void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3)
{
arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
@@ -31,6 +33,10 @@
{
arm_bl2_platform_setup();
+#if TRANSFER_LIST
+ ns_tl = transfer_list_init((void *)FW_NS_HANDOFF_BASE, FW_HANDOFF_SIZE);
+ assert(ns_tl != NULL);
+#endif
/* Initialize System level generic or SP804 timer */
fvp_timer_init();
}
@@ -42,16 +48,14 @@
{
struct bl_params *arm_bl_params;
const struct dyn_cfg_dtb_info_t *hw_config_info __unused;
- bl_mem_params_node_t *param_node __unused;
- static struct transfer_list_header *ns_tl __unused;
struct transfer_list_entry *te __unused;
+ bl_mem_params_node_t *param_node __unused;
arm_bl_params = arm_get_next_bl_params();
#if !RESET_TO_BL2 && !EL3_PAYLOAD_BASE
const struct dyn_cfg_dtb_info_t *fw_config_info;
uintptr_t fw_config_base = 0UL;
- entry_point_info_t *ep_info;
#if __aarch64__
/* Get BL31 image node */
@@ -62,61 +66,75 @@
#endif /* __aarch64__ */
assert(param_node != NULL);
- /* get fw_config load address */
+ /* Update the next image's ep info with the FW config address */
fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID);
assert(fw_config_info != NULL);
fw_config_base = fw_config_info->config_addr;
assert(fw_config_base != 0UL);
- /*
- * Get the entry point info of next executable image and override
- * arg1 of entry point info with fw_config base address
- */
- ep_info = ¶m_node->ep_info;
- ep_info->args.arg1 = (uint32_t)fw_config_base;
+ param_node->ep_info.args.arg1 = (uint32_t)fw_config_base;
- /* grab NS HW config address */
- hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID);
- assert(hw_config_info != NULL);
-
- /* To retrieve actual size of the HW_CONFIG */
- param_node = get_bl_mem_params_node(HW_CONFIG_ID);
+ /* Update BL33's ep info with the NS HW config address */
+ param_node = get_bl_mem_params_node(BL33_IMAGE_ID);
assert(param_node != NULL);
- bl_mem_params_node_t *bl33_param_node = get_bl_mem_params_node(BL33_IMAGE_ID);
- assert(bl33_param_node != NULL);
-
#if TRANSFER_LIST
- ns_tl = transfer_list_init((void *)FW_NS_HANDOFF_BASE, FW_HANDOFF_SIZE);
- assert(ns_tl != NULL);
-
/* Update BL33's ep info with NS HW config address */
- te = transfer_list_add(ns_tl, TL_TAG_FDT, param_node->image_info.image_size,
- (void *)hw_config_info->config_addr);
+ te = transfer_list_find(ns_tl, TL_TAG_FDT);
assert(te != NULL);
- bl33_param_node->ep_info.args.arg1 = TRANSFER_LIST_SIGNATURE | REGISTER_CONVENTION_VERSION_MASK;
- bl33_param_node->ep_info.args.arg2 = 0;
- bl33_param_node->ep_info.args.arg3 = (uintptr_t)ns_tl;
- bl33_param_node->ep_info.args.arg0 = te ? (uintptr_t)transfer_list_entry_data(te) : 0;
+ param_node->ep_info.args.arg1 = TRANSFER_LIST_SIGNATURE |
+ REGISTER_CONVENTION_VERSION_MASK;
+ param_node->ep_info.args.arg2 = 0;
+ param_node->ep_info.args.arg3 = (uintptr_t)ns_tl;
+ param_node->ep_info.args.arg0 =
+ te ? (uintptr_t)transfer_list_entry_data(te) : 0;
#else
- /* Copy HW config from Secure address to NS address */
- memcpy((void *)hw_config_info->secondary_config_addr,
- (void *)hw_config_info->config_addr,
- (size_t)param_node->image_info.image_size);
-
- /*
- * Ensure HW-config device tree committed to memory, as there is
- * a possibility to use HW-config without cache and MMU enabled
- * at BL33
- */
- flush_dcache_range(hw_config_info->secondary_config_addr,
- param_node->image_info.image_size);
+ hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID);
+ assert(hw_config_info != NULL);
- bl33_param_node->ep_info.args.arg1 = hw_config_info->secondary_config_addr;
+ param_node->ep_info.args.arg1 = hw_config_info->secondary_config_addr;
#endif /* TRANSFER_LIST */
#endif /* !RESET_TO_BL2 && !EL3_PAYLOAD_BASE */
return arm_bl_params;
}
+
+int bl2_plat_handle_post_image_load(unsigned int image_id)
+{
+#if !RESET_TO_BL2 && !EL3_PAYLOAD_BASE
+ if (image_id == HW_CONFIG_ID) {
+ const struct dyn_cfg_dtb_info_t *hw_config_info;
+ struct transfer_list_entry *te __unused;
+
+ const bl_mem_params_node_t *param_node =
+ get_bl_mem_params_node(image_id);
+ assert(param_node != NULL);
+
+ hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID);
+ assert(hw_config_info != NULL);
+
+#if TRANSFER_LIST
+ /* Update BL33's ep info with NS HW config address */
+ te = transfer_list_add(ns_tl, TL_TAG_FDT,
+ param_node->image_info.image_size,
+ (void *)hw_config_info->config_addr);
+ assert(te != NULL);
+#else
+ memcpy((void *)hw_config_info->secondary_config_addr,
+ (void *)hw_config_info->config_addr,
+ (size_t)param_node->image_info.image_size);
+
+ /*
+ * Ensure HW-config device tree is committed to memory, as the HW-Config
+ * might be used without cache and MMU enabled at BL33.
+ */
+ flush_dcache_range(hw_config_info->secondary_config_addr,
+ param_node->image_info.image_size);
+#endif /* TRANSFER_LIST */
+ }
+#endif /* !RESET_TO_BL2 && !EL3_PAYLOAD_BASE */
+
+ return arm_bl2_plat_handle_post_image_load(image_id);
+}
diff --git a/plat/arm/board/fvp/fvp_plat_attest_token.c b/plat/arm/board/fvp/fvp_plat_attest_token.c
index 5af2405..5fb3141 100644
--- a/plat/arm/board/fvp/fvp_plat_attest_token.c
+++ b/plat/arm/board/fvp/fvp_plat_attest_token.c
@@ -4,23 +4,115 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include <delegated_attestation.h>
-#include <psa/error.h>
+#include <errno.h>
+#include <string.h>
+
+#include <plat/common/platform.h>
+
+static const uint8_t sample_platform_token[] = {
+ 0xD2, 0x84, 0x44, 0xA1, 0x01, 0x38, 0x22, 0xA0,
+ 0x59, 0x02, 0x33, 0xA9, 0x19, 0x01, 0x09, 0x78,
+ 0x1C, 0x68, 0x74, 0x74, 0x70, 0x3A, 0x2F, 0x2F,
+ 0x61, 0x72, 0x6D, 0x2E, 0x63, 0x6F, 0x6D, 0x2F,
+ 0x43, 0x43, 0x41, 0x2D, 0x53, 0x53, 0x44, 0x2F,
+ 0x31, 0x2E, 0x30, 0x2E, 0x30, 0x0A, 0x58, 0x20,
+ 0xB5, 0x97, 0x3C, 0xB6, 0x8B, 0xAA, 0x9F, 0xC5,
+ 0x55, 0x58, 0x78, 0x6B, 0x7E, 0xC6, 0x7F, 0x69,
+ 0xE4, 0x0D, 0xF5, 0xBA, 0x5A, 0xA9, 0x21, 0xCD,
+ 0x0C, 0x27, 0xF4, 0x05, 0x87, 0xA0, 0x11, 0xEA,
+ 0x19, 0x09, 0x5C, 0x58, 0x20, 0x7F, 0x45, 0x4C,
+ 0x46, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x3E,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x50, 0x58, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x01, 0x00,
+ 0x58, 0x21, 0x01, 0x07, 0x06, 0x05, 0x04, 0x03,
+ 0x02, 0x01, 0x00, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B,
+ 0x0A, 0x09, 0x08, 0x17, 0x16, 0x15, 0x14, 0x13,
+ 0x12, 0x11, 0x10, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B,
+ 0x1A, 0x19, 0x18, 0x19, 0x09, 0x61, 0x58, 0x21,
+ 0x01, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01,
+ 0x00, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09,
+ 0x08, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11,
+ 0x10, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19,
+ 0x18, 0x19, 0x09, 0x5B, 0x19, 0x30, 0x03, 0x19,
+ 0x09, 0x62, 0x67, 0x73, 0x68, 0x61, 0x2D, 0x32,
+ 0x35, 0x36, 0x19, 0x09, 0x5F, 0x84, 0xA5, 0x01,
+ 0x62, 0x42, 0x4C, 0x05, 0x58, 0x20, 0x07, 0x06,
+ 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E,
+ 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16,
+ 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E,
+ 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, 0x65,
+ 0x33, 0x2E, 0x34, 0x2E, 0x32, 0x02, 0x58, 0x20,
+ 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00,
+ 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08,
+ 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10,
+ 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18,
+ 0x06, 0x74, 0x54, 0x46, 0x2D, 0x4D, 0x5F, 0x53,
+ 0x48, 0x41, 0x32, 0x35, 0x36, 0x4D, 0x65, 0x6D,
+ 0x50, 0x72, 0x65, 0x58, 0x49, 0x50, 0xA4, 0x01,
+ 0x62, 0x4D, 0x31, 0x05, 0x58, 0x20, 0x07, 0x06,
+ 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E,
+ 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16,
+ 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E,
+ 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, 0x63,
+ 0x31, 0x2E, 0x32, 0x02, 0x58, 0x20, 0x07, 0x06,
+ 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E,
+ 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16,
+ 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E,
+ 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0xA4, 0x01,
+ 0x62, 0x4D, 0x32, 0x05, 0x58, 0x20, 0x07, 0x06,
+ 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E,
+ 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16,
+ 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E,
+ 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, 0x65,
+ 0x31, 0x2E, 0x32, 0x2E, 0x33, 0x02, 0x58, 0x20,
+ 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00,
+ 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08,
+ 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10,
+ 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18,
+ 0xA4, 0x01, 0x62, 0x4D, 0x33, 0x05, 0x58, 0x20,
+ 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00,
+ 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08,
+ 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10,
+ 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18,
+ 0x04, 0x61, 0x31, 0x02, 0x58, 0x20, 0x07, 0x06,
+ 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E,
+ 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16,
+ 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E,
+ 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x19, 0x09,
+ 0x60, 0x6C, 0x77, 0x68, 0x61, 0x74, 0x65, 0x76,
+ 0x65, 0x72, 0x2E, 0x63, 0x6F, 0x6D, 0x58, 0x60,
+ 0xE6, 0xB6, 0x38, 0x4F, 0xAE, 0x3F, 0x6E, 0x67,
+ 0xF5, 0xD4, 0x97, 0x4B, 0x3F, 0xFD, 0x0A, 0xFA,
+ 0x1D, 0xF0, 0x2F, 0x73, 0xB8, 0xFF, 0x5F, 0x02,
+ 0xC0, 0x0F, 0x40, 0xAC, 0xF3, 0xA2, 0x9D, 0xB5,
+ 0x31, 0x50, 0x16, 0x4F, 0xFA, 0x34, 0x3D, 0x0E,
+ 0xAF, 0xE0, 0xD0, 0xD1, 0x6C, 0xF0, 0x9D, 0xC1,
+ 0x01, 0x42, 0xA2, 0x3C, 0xCE, 0xD4, 0x4A, 0x59,
+ 0xDC, 0x29, 0x0A, 0x30, 0x93, 0x5F, 0xB4, 0x98,
+ 0x61, 0xBA, 0xE3, 0x91, 0x22, 0x95, 0x24, 0xF4,
+ 0xAE, 0x47, 0x93, 0xD3, 0x84, 0xA3, 0x76, 0xD0,
+ 0xC1, 0x26, 0x96, 0x53, 0xA3, 0x60, 0x3F, 0x6C,
+ 0x75, 0x96, 0x90, 0x6A, 0xF9, 0x4E, 0xDA, 0x30
+};
/*
- * Get the platform attestation token through the PSA delegated attestation
- * layer.
- *
- * FVP cannot support RSS hardware at the moment, but it can still mock the
- * RSS implementation of the PSA interface (see PLAT_RSS_NOT_SUPPORTED).
+ * Get the hardcoded platform attestation token as FVP does not support
+ * RSS.
*/
int plat_rmmd_get_cca_attest_token(uintptr_t buf, size_t *len,
uintptr_t hash, size_t hash_size)
{
- psa_status_t ret;
+ (void)hash;
+ (void)hash_size;
- ret = rss_delegated_attest_get_token((const uint8_t *)hash, hash_size,
- (uint8_t *)buf, *len, len);
+ if (*len < sizeof(sample_platform_token)) {
+ return -EINVAL;
+ }
+
+ (void)memcpy((void *)buf, (const void *)sample_platform_token,
+ sizeof(sample_platform_token));
+ *len = sizeof(sample_platform_token);
- return ret;
+ return 0;
}
diff --git a/plat/arm/board/fvp/fvp_realm_attest_key.c b/plat/arm/board/fvp/fvp_realm_attest_key.c
index 26354f4..fe0cde7 100644
--- a/plat/arm/board/fvp/fvp_realm_attest_key.c
+++ b/plat/arm/board/fvp/fvp_realm_attest_key.c
@@ -4,27 +4,33 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include <assert.h>
-#include <delegated_attestation.h>
-#include <psa/error.h>
-#include <services/rmmd_svc.h>
+#include <errno.h>
+#include <string.h>
+
+#include <plat/common/platform.h>
+
+static const uint8_t sample_delegated_key[] = {
+ 0x20, 0x11, 0xC7, 0xF0, 0x3C, 0xEE, 0x43, 0x25, 0x17, 0x6E,
+ 0x52, 0x4F, 0x03, 0x3C, 0x0C, 0xE1, 0xE2, 0x1A, 0x76, 0xE6,
+ 0xC1, 0xA4, 0xF0, 0xB8, 0x39, 0xAA, 0x1D, 0xF6, 0x1E, 0x0E,
+ 0x8A, 0x5C, 0x8A, 0x05, 0x74, 0x0F, 0x9B, 0x69, 0xEF, 0xA7,
+ 0xEB, 0x1A, 0x41, 0x85, 0xBD, 0x11, 0x7F, 0x68
+};
/*
- * Get the delegated realm attestation key through the PSA delegated
- * attestation layer.
- *
- * FVP cannot support RSS hardware at the moment, but it can still mock
- * the RSS implementation of the PSA interface (see PLAT_RSS_NOT_SUPPORTED).
+ * Get the hardcoded delegated realm attestation key as FVP
+ * does not support RSS.
*/
int plat_rmmd_get_cca_realm_attest_key(uintptr_t buf, size_t *len,
unsigned int type)
{
- psa_status_t ret;
+ if (*len < sizeof(sample_delegated_key)) {
+ return -EINVAL;
+ }
- assert(type == ATTEST_KEY_CURVE_ECC_SECP384R1);
-
- ret = rss_delegated_attest_get_delegated_key(0U, 0U, (uint8_t *)buf,
- *len, len, 0U);
+ (void)memcpy((void *)buf, (const void *)sample_delegated_key,
+ sizeof(sample_delegated_key));
+ *len = sizeof(sample_delegated_key);
- return ret;
+ return 0;
}
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index 836080a..aad0417 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -193,8 +193,10 @@
/*
* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
* plus a little space for growth.
+ * In case of PSA Crypto API, few algorithms like ECDSA needs bigger BL1 RW
+ * area.
*/
-#if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA
+#if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA || PSA_CRYPTO
#define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xC000)
#else
#define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000)
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index d70eb49..f7c174f 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -53,7 +53,6 @@
ENABLE_FEAT_AMU := 2
ENABLE_FEAT_AMUv1p1 := 2
ENABLE_FEAT_HCX := 2
- ENABLE_FEAT_MPAM := 2
ENABLE_FEAT_RNG := 2
ENABLE_FEAT_TWED := 2
ENABLE_FEAT_GCS := 2
@@ -72,9 +71,7 @@
# enable unconditionally for all builds
ifeq (${ARCH}, aarch64)
-ifeq (${ENABLE_RME},0)
- ENABLE_BRBE_FOR_NS := 2
-endif
+ ENABLE_BRBE_FOR_NS := 2
ENABLE_TRBE_FOR_NS := 2
endif
ENABLE_SYS_REG_TRACE_FOR_NS := 2
@@ -271,11 +268,6 @@
BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \
plat/arm/board/fvp/fvp_realm_attest_key.c
-
-# FVP platform does not support RSS, but it can leverage RSS APIs to
-# provide hardcoded token/key on request.
-BL31_SOURCES += lib/psa/delegated_attestation.c
-
endif
ifeq (${ENABLE_FEAT_RNG_TRAP},1)
diff --git a/plat/arm/board/fvp_ve/fvp_ve_bl2_setup.c b/plat/arm/board/fvp_ve/fvp_ve_bl2_setup.c
index 4ccae27..cc29f36 100644
--- a/plat/arm/board/fvp_ve/fvp_ve_bl2_setup.c
+++ b/plat/arm/board/fvp_ve/fvp_ve_bl2_setup.c
@@ -39,3 +39,8 @@
generic_delay_timer_init();
#endif /* USE_SP804_TIMER */
}
+
+int bl2_plat_handle_post_image_load(unsigned int image_id)
+{
+ return arm_bl2_plat_handle_post_image_load(image_id);
+}
diff --git a/plat/arm/board/n1sdp/platform.mk b/plat/arm/board/n1sdp/platform.mk
index bd62614..f937ee7 100644
--- a/plat/arm/board/n1sdp/platform.mk
+++ b/plat/arm/board/n1sdp/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2022, Arm Limited. All rights reserved.
+# Copyright (c) 2018-2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -14,6 +14,10 @@
N1SDP_CPU_SOURCES := lib/cpus/aarch64/neoverse_n1.S
+# Neoverse N1 cores support Armv8.2 extensions
+ARM_ARCH_MAJOR := 8
+ARM_ARCH_MINOR := 2
+
# GIC-600 configuration
GICV3_SUPPORT_GIC600 := 1
GICV3_IMPL_GIC600_MULTICHIP := 1
diff --git a/plat/arm/common/arm_bl2_el3_setup.c b/plat/arm/common/arm_bl2_el3_setup.c
index b598c59..01e0db0 100644
--- a/plat/arm/common/arm_bl2_el3_setup.c
+++ b/plat/arm/common/arm_bl2_el3_setup.c
@@ -7,6 +7,7 @@
#include <assert.h>
#include <drivers/generic_delay_timer.h>
+#include <drivers/partition/partition.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
#include <platform_def.h>
@@ -94,7 +95,15 @@
void bl2_el3_plat_arch_setup(void)
{
+ int __maybe_unused ret;
arm_bl2_el3_plat_arch_setup();
+#if ARM_GPT_SUPPORT
+ ret = gpt_partition_init();
+ if (ret != 0) {
+ ERROR("GPT partition initialisation failed!\n");
+ panic();
+ }
+#endif /* ARM_GPT_SUPPORT */
}
void bl2_el3_plat_prepare_exit(void)
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index 6f3d0e9..e15bf0f 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -318,8 +318,3 @@
#endif
return arm_bl2_handle_post_image_load(image_id);
}
-
-int bl2_plat_handle_post_image_load(unsigned int image_id)
-{
- return arm_bl2_plat_handle_post_image_load(image_id);
-}
diff --git a/plat/arm/css/common/css_bl2_setup.c b/plat/arm/css/common/css_bl2_setup.c
index 002c6eb..1e055c5 100644
--- a/plat/arm/css/common/css_bl2_setup.c
+++ b/plat/arm/css/common/css_bl2_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -84,3 +84,8 @@
# endif /* EL3_PAYLOAD_BASE */
#endif /* CSS_USE_SCMI_SDS_DRIVER */
+
+int bl2_plat_handle_post_image_load(unsigned int image_id)
+{
+ return arm_bl2_plat_handle_post_image_load(image_id);
+}
diff --git a/plat/aspeed/ast2700/plat_bl31_setup.c b/plat/aspeed/ast2700/plat_bl31_setup.c
index fde5dbb..92a48ff 100644
--- a/plat/aspeed/ast2700/plat_bl31_setup.c
+++ b/plat/aspeed/ast2700/plat_bl31_setup.c
@@ -76,6 +76,12 @@
BL_END - BL_CODE_END,
MT_RW_DATA | MT_SECURE);
+#if USE_COHERENT_MEM
+ mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
+ MT_DEVICE | MT_RW | MT_SECURE);
+#endif
+
mmap_add_region(BL32_BASE, BL32_BASE, BL32_SIZE,
MT_MEMORY | MT_RW);
diff --git a/plat/nvidia/tegra/soc/t186/plat_setup.c b/plat/nvidia/tegra/soc/t186/plat_setup.c
index d6d090a..b21faa3 100644
--- a/plat/nvidia/tegra/soc/t186/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t186/plat_setup.c
@@ -302,14 +302,14 @@
*/
if ((cluster_id >= (u_register_t)PLATFORM_CLUSTER_COUNT) ||
(cpu_id >= (u_register_t)PLATFORM_MAX_CPUS_PER_CLUSTER)) {
- ret = PSCI_E_NOT_PRESENT;
+ ret = -1;
} else {
/* calculate the core position */
pos = cpu_id + (cluster_id << 2U);
/* check for non-existent CPUs */
if ((pos == TEGRA186_CLUSTER0_CORE2) || (pos == TEGRA186_CLUSTER0_CORE3)) {
- ret = PSCI_E_NOT_PRESENT;
+ ret = -1;
} else {
ret = (int32_t)pos;
}
diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk
index a183d0e..289e921 100644
--- a/plat/nvidia/tegra/soc/t194/platform_t194.mk
+++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk
@@ -1,11 +1,14 @@
#
-# Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
+# Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
include common/fdt_wrappers.mk
+ARM_ARCH_MAJOR := 8
+ARM_ARCH_MINOR := 2
+
# platform configs
ENABLE_CONSOLE_SPE := 1
$(eval $(call add_define,ENABLE_CONSOLE_SPE))
@@ -34,7 +37,6 @@
# enable RAS handling
HANDLE_EA_EL3_FIRST_NS := 1
-ENABLE_FEAT_RAS := 1
RAS_FFH_SUPPORT := 1
# platform files
diff --git a/plat/xilinx/versal/include/platform_def.h b/plat/xilinx/versal/include/platform_def.h
index 4c02402..286a706 100644
--- a/plat/xilinx/versal/include/platform_def.h
+++ b/plat/xilinx/versal/include/platform_def.h
@@ -35,10 +35,10 @@
# define BL31_BASE U(0xfffe0000)
# define BL31_LIMIT U(0x100000000)
#else
-# define BL31_BASE (VERSAL_ATF_MEM_BASE)
-# define BL31_LIMIT (VERSAL_ATF_MEM_BASE + VERSAL_ATF_MEM_SIZE)
+# define BL31_BASE U(VERSAL_ATF_MEM_BASE)
+# define BL31_LIMIT U(VERSAL_ATF_MEM_BASE + VERSAL_ATF_MEM_SIZE)
# ifdef VERSAL_ATF_MEM_PROGBITS_SIZE
-# define BL31_PROGBITS_LIMIT (VERSAL_ATF_MEM_BASE + VERSAL_ATF_MEM_PROGBITS_SIZE)
+# define BL31_PROGBITS_LIMIT U(VERSAL_ATF_MEM_BASE + VERSAL_ATF_MEM_PROGBITS_SIZE)
# endif
#endif
@@ -49,8 +49,8 @@
# define BL32_BASE U(0x60000000)
# define BL32_LIMIT U(0x80000000)
#else
-# define BL32_BASE (VERSAL_BL32_MEM_BASE)
-# define BL32_LIMIT (VERSAL_BL32_MEM_BASE + VERSAL_BL32_MEM_SIZE)
+# define BL32_BASE U(VERSAL_BL32_MEM_BASE)
+# define BL32_LIMIT U(VERSAL_BL32_MEM_BASE + VERSAL_BL32_MEM_SIZE)
#endif
/*******************************************************************************
@@ -59,7 +59,7 @@
#ifndef PRELOADED_BL33_BASE
# define PLAT_ARM_NS_IMAGE_BASE U(0x8000000)
#else
-# define PLAT_ARM_NS_IMAGE_BASE PRELOADED_BL33_BASE
+# define PLAT_ARM_NS_IMAGE_BASE U(PRELOADED_BL33_BASE)
#endif
/*******************************************************************************
diff --git a/services/std_svc/rmmd/rmmd_main.c b/services/std_svc/rmmd/rmmd_main.c
index fa24a91..d6d25d8 100644
--- a/services/std_svc/rmmd/rmmd_main.c
+++ b/services/std_svc/rmmd/rmmd_main.c
@@ -17,6 +17,7 @@
#include <common/runtime_svc.h>
#include <context.h>
#include <lib/el3_runtime/context_mgmt.h>
+#include <lib/el3_runtime/cpu_data.h>
#include <lib/el3_runtime/pubsub.h>
#include <lib/extensions/pmuv3.h>
#include <lib/extensions/sys_reg_trace.h>
@@ -118,34 +119,41 @@
/*******************************************************************************
* Enable architecture extensions on first entry to Realm world.
******************************************************************************/
+
static void manage_extensions_realm(cpu_context_t *ctx)
{
+ pmuv3_enable(ctx);
+
+ /*
+ * If SME/SME2 is supported and enabled for NS world, then enables SME
+ * for Realm world. RMM will save/restore required registers that are
+ * shared with SVE/FPU so that Realm can use FPU or SVE.
+ */
+ if (is_feat_sme_supported()) {
+ /* sme_enable() also enables SME2 if supported by hardware */
+ sme_enable(ctx);
+ }
+}
+
+#if IMAGE_BL31
+static void manage_extensions_realm_per_world(void)
+{
if (is_feat_sve_supported()) {
/*
* Enable SVE and FPU in realm context when it is enabled for NS.
* Realm manager must ensure that the SVE and FPU register
* contexts are properly managed.
*/
- sve_enable(ctx);
+ sve_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]);
}
/* NS can access this but Realm shouldn't */
if (is_feat_sys_reg_trace_supported()) {
- sys_reg_trace_disable(ctx);
+ sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_REALM]);
}
- pmuv3_enable(ctx);
-
- /*
- * If SME/SME2 is supported and enabled for NS world, then enables SME
- * for Realm world. RMM will save/restore required registers that are
- * shared with SVE/FPU so that Realm can use FPU or SVE.
- */
- if (is_feat_sme_supported()) {
- /* sme_enable() also enables SME2 if supported by hardware */
- sme_enable(ctx);
- }
}
+#endif /* IMAGE_BL31 */
/*******************************************************************************
* Jump to the RMM for the first time.
@@ -160,6 +168,8 @@
/* Enable architecture extensions */
manage_extensions_realm(&ctx->cpu_ctx);
+ manage_extensions_realm_per_world();
+
/* Initialize RMM EL2 context. */
rmm_el2_context_init(&ctx->cpu_ctx.el2_sysregs_ctx);
diff --git a/services/std_svc/rmmd/trp/trp_main.c b/services/std_svc/rmmd/trp/trp_main.c
index 4eb3e12..33f2fb0 100644
--- a/services/std_svc/rmmd/trp/trp_main.c
+++ b/services/std_svc/rmmd/trp/trp_main.c
@@ -106,11 +106,18 @@
/*******************************************************************************
* Returning RMI version back to Normal World
******************************************************************************/
-static void trp_ret_rmi_version(struct trp_smc_result *smc_ret)
+static void trp_ret_rmi_version(unsigned long long rmi_version,
+ struct trp_smc_result *smc_ret)
{
+ if (rmi_version != RMI_ABI_VERSION) {
+ smc_ret->x[0] = RMI_ERROR_INPUT;
+ } else {
+ smc_ret->x[0] = RMI_SUCCESS;
+ }
VERBOSE("RMM version is %u.%u\n", RMI_ABI_VERSION_MAJOR,
RMI_ABI_VERSION_MINOR);
- smc_ret->x[0] = RMI_ABI_VERSION;
+ smc_ret->x[1] = RMI_ABI_VERSION;
+ smc_ret->x[2] = RMI_ABI_VERSION;
}
/*******************************************************************************
@@ -163,7 +170,7 @@
switch (fid) {
case RMI_RMM_REQ_VERSION:
- trp_ret_rmi_version(smc_ret);
+ trp_ret_rmi_version(x1, smc_ret);
break;
case RMI_RMM_GRANULE_DELEGATE:
trp_asc_mark_realm(x1, smc_ret);