fix(s32g274a): reduce the uSDHC clock to 200MHz
Reduce the uSDHC clock to 200 MHz to ensure compatibility with the uSDHC
driver and alignment with the S32G274A data sheet.
Change-Id: Ic67c75056189075b1ba260e32426421e1e79a2e7
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
diff --git a/drivers/nxp/clk/s32cc/s32cc_early_clks.c b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
index 92182a0..ac9d99a 100644
--- a/drivers/nxp/clk/s32cc/s32cc_early_clks.c
+++ b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
@@ -19,7 +19,7 @@
#define S32CC_DDR_PLL_VCO_FREQ (1600U * MHZ)
#define S32CC_DDR_PLL_PHI0_FREQ (800U * MHZ)
#define S32CC_PERIPH_DFS_PHI3_FREQ (800U * MHZ)
-#define S32CC_USDHC_FREQ (400U * MHZ)
+#define S32CC_USDHC_FREQ (200U * MHZ)
static int setup_fxosc(void)
{