diff --git a/plat/fvp/aarch64/fvp_common.c b/plat/fvp/aarch64/fvp_common.c
index 174085f..b7d8926 100644
--- a/plat/fvp/aarch64/fvp_common.c
+++ b/plat/fvp/aarch64/fvp_common.c
@@ -36,17 +36,18 @@
 #include <debug.h>
 #include <mmio.h>
 #include <platform.h>
+#include <plat_config.h>
 #include <xlat_tables.h>
 #include "../fvp_def.h"
 
 /*******************************************************************************
- * This array holds the characteristics of the differences between the three
+ * plat_config holds the characteristics of the differences between the three
  * FVP platforms (Base, A53_A57 & Foundation). It will be populated during cold
  * boot at each boot stage by the primary before enabling the MMU (to allow cci
  * configuration) & used thereafter. Each BL will have its own copy to allow
  * independent operation.
  ******************************************************************************/
-static unsigned long fvp_config[CONFIG_LIMIT];
+plat_config_t plat_config;
 
 /*
  * Table of regions to map using the MMU.
@@ -107,13 +108,6 @@
 DEFINE_CONFIGURE_MMU_EL(1)
 DEFINE_CONFIGURE_MMU_EL(3)
 
-/* Simple routine which returns a configuration variable value */
-unsigned long fvp_get_cfgvar(unsigned int var_id)
-{
-	assert(var_id < CONFIG_LIMIT);
-	return fvp_config[var_id];
-}
-
 /*******************************************************************************
  * A single boot loader stack is expected to work on both the Foundation FVP
  * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The
@@ -142,16 +136,16 @@
 	 */
 	switch (bld) {
 	case BLD_GIC_VE_MMAP:
-		fvp_config[CONFIG_GICD_ADDR] = VE_GICD_BASE;
-		fvp_config[CONFIG_GICC_ADDR] = VE_GICC_BASE;
-		fvp_config[CONFIG_GICH_ADDR] = VE_GICH_BASE;
-		fvp_config[CONFIG_GICV_ADDR] = VE_GICV_BASE;
+		plat_config.gicd_base = VE_GICD_BASE;
+		plat_config.gicc_base = VE_GICC_BASE;
+		plat_config.gich_base = VE_GICH_BASE;
+		plat_config.gicv_base = VE_GICV_BASE;
 		break;
 	case BLD_GIC_A53A57_MMAP:
-		fvp_config[CONFIG_GICD_ADDR] = BASE_GICD_BASE;
-		fvp_config[CONFIG_GICC_ADDR] = BASE_GICC_BASE;
-		fvp_config[CONFIG_GICH_ADDR] = BASE_GICH_BASE;
-		fvp_config[CONFIG_GICV_ADDR] = BASE_GICV_BASE;
+		plat_config.gicd_base = BASE_GICD_BASE;
+		plat_config.gicc_base = BASE_GICC_BASE;
+		plat_config.gich_base = BASE_GICH_BASE;
+		plat_config.gicv_base = BASE_GICV_BASE;
 		break;
 	default:
 		ERROR("Unsupported board build %x\n", bld);
@@ -164,12 +158,9 @@
 	 */
 	switch (hbi) {
 	case HBI_FOUNDATION:
-		fvp_config[CONFIG_MAX_AFF0] = 4;
-		fvp_config[CONFIG_MAX_AFF1] = 1;
-		fvp_config[CONFIG_CPU_SETUP] = 0;
-		fvp_config[CONFIG_BASE_MMAP] = 0;
-		fvp_config[CONFIG_HAS_CCI] = 0;
-		fvp_config[CONFIG_HAS_TZC] = 0;
+		plat_config.max_aff0 = 4;
+		plat_config.max_aff1 = 1;
+		plat_config.flags = 0;
 
 		/*
 		 * Check for supported revisions of Foundation FVP
@@ -186,16 +177,14 @@
 		break;
 	case HBI_FVP_BASE:
 		midr_pn = (read_midr() >> MIDR_PN_SHIFT) & MIDR_PN_MASK;
-		if ((midr_pn == MIDR_PN_A57) || (midr_pn == MIDR_PN_A53))
-			fvp_config[CONFIG_CPU_SETUP] = 1;
-		else
-			fvp_config[CONFIG_CPU_SETUP] = 0;
+		plat_config.flags =
+			((midr_pn == MIDR_PN_A57) || (midr_pn == MIDR_PN_A53))
+			? CONFIG_CPUECTLR_SMP_BIT : 0;
 
-		fvp_config[CONFIG_MAX_AFF0] = 4;
-		fvp_config[CONFIG_MAX_AFF1] = 2;
-		fvp_config[CONFIG_BASE_MMAP] = 1;
-		fvp_config[CONFIG_HAS_CCI] = 1;
-		fvp_config[CONFIG_HAS_TZC] = 1;
+		plat_config.max_aff0 = 4;
+		plat_config.max_aff1 = 2;
+		plat_config.flags |= CONFIG_BASE_MMAP | CONFIG_HAS_CCI |
+			CONFIG_HAS_TZC;
 
 		/*
 		 * Check for supported revisions
@@ -237,15 +226,12 @@
 
 void fvp_cci_setup(void)
 {
-	unsigned long cci_setup;
-
 	/*
 	 * Enable CCI-400 for this cluster. No need
 	 * for locks as no other cpu is active at the
 	 * moment
 	 */
-	cci_setup = fvp_get_cfgvar(CONFIG_HAS_CCI);
-	if (cci_setup)
+	if (plat_config.flags & CONFIG_HAS_CCI)
 		cci_enable_coherency(read_mpidr());
 }