commit 1c2b5c7d28012e00c9fd04fbacc6d009f6b91a20
author Pritesh Raithatha <praithatha@nvidia.com> Tue Jan 24 14:16:07 2017 +0530
committer Varun Wadekar <vwadekar@nvidia.com> Thu Oct 24 15:43:26 2019 -0700
tree 754d392ac809da98dd5d4edcbae3265c624f26b3
parent 537bce44d3aecf78b272f54459f15b43d689ff06

Tegra194: add support for multiple SMMU devices

This patch adds support for all three SMMU devices present on the SoC.

The following changes have been done:
    Add SMMU devices to the memory map
    Update register read and write functions

Change-Id: I0007b496d2ae7264f4fa9f605d4b0a15fa747a0f
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

plat/nvidia/tegra/soc/t194/drivers/include/smmu_plat_config.h

diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/smmu_plat_config.h b/plat/nvidia/tegra/soc/t194/drivers/include/smmu_plat_config.h
index f955e53..7254711 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/include/smmu_plat_config.h
+++ b/plat/nvidia/tegra/soc/t194/drivers/include/smmu_plat_config.h
@@ -414,4 +414,29 @@
 	_END_OF_TABLE_,
 };
 
+static inline uint32_t tegra_smmu_read_32(uint32_t smmu_id, uint32_t off)
+{
+	if (smmu_id == 0)
+		return mmio_read_32(TEGRA_SMMU0_BASE + off);
+	else if (smmu_id == 1)
+		return mmio_read_32(TEGRA_SMMU1_BASE + off);
+	else if (smmu_id == 2)
+		return mmio_read_32(TEGRA_SMMU2_BASE + off);
+	else
+		panic();
+}
+
+static inline void tegra_smmu_write_32(uint32_t smmu_id,
+			uint32_t off, uint32_t val)
+{
+	if (smmu_id == 0)
+		mmio_write_32(TEGRA_SMMU0_BASE + off, val);
+	else if (smmu_id == 1)
+		mmio_write_32(TEGRA_SMMU1_BASE + off, val);
+	else if (smmu_id == 2)
+		mmio_write_32(TEGRA_SMMU2_BASE + off, val);
+	else
+		panic();
+}
+
 #endif //__SMMU_PLAT_CONFIG_H

plat/nvidia/tegra/soc/t194/plat_setup.c

diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c
index aab884e..3424d19 100644
--- a/plat/nvidia/tegra/soc/t194/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t194/plat_setup.c
@@ -81,7 +81,11 @@
 			MT_DEVICE | MT_RW | MT_SECURE),
 	MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */
 			MT_DEVICE | MT_RW | MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_SMMU_BASE, 0x1000000, /* 64KB */
+	MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000, /* 64KB */
+			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x1000000, /* 64KB */
+			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x1000000, /* 64KB */
 			MT_DEVICE | MT_RW | MT_SECURE),
 	{0}
 };

plat/nvidia/tegra/soc/t194/platform_t194.mk

diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk
index 54bc941..cb31bdd 100644
--- a/plat/nvidia/tegra/soc/t194/platform_t194.mk
+++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk
@@ -23,6 +23,9 @@
 ENABLE_SMMU_DEVICE			:= 0
 $(eval $(call add_define,ENABLE_SMMU_DEVICE))
 
+NUM_SMMU_DEVICES			:= 3
+$(eval $(call add_define,NUM_SMMU_DEVICES))
+
 RESET_TO_BL31				:= 1
 
 PROGRAMMABLE_RESET_ADDRESS		:= 1