Merge "fix(imx8ulp): fix variable may be used uninitialized error" into integration

commit: 1b98861a780a43352f1ea8aaaa2ec06e89855e28 [log] [tgz]
author: Manish V Badarkhe <manish.badarkhe@arm.com> Fri Jun 20 07:23:29 2025 +0000
committer: TrustedFirmware Code Review <review@review.trustedfirmware.org> Fri Jun 20 07:23:29 2025 +0000
tree: 9c3e61cc13356ff04bc70795d5863d708846b61a
parent: 68461b13c891e2f2ac4d639970b8b4384cb5cde2 [diff]
parent: 5b940ec3ee0319d8c06b4522d038d665eb06f892 [diff]
diff --git a/.commitlintrc.js b/.commitlintrc.js
index 53e3a63..51493ea 100644
--- a/.commitlintrc.js
+++ b/.commitlintrc.js

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -67,6 +67,6 @@
         "type-enum": [2, "always", types], /* Error */
 
         "scope-case": [2, "always", "lower-case"], /* Error */
-        "scope-enum": [1, "always", scopes] /* Warning */
+        "scope-enum": [2, "always", scopes] /* Error */
     },
 };

diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 0000000..858e0c1
--- /dev/null
+++ b/.gitmodules

@@ -0,0 +1,4 @@
+[submodule "libtl"]
+	path = contrib/libtl
+	url = https://review.trustedfirmware.org/shared/transfer-list-library
+	shallow = true

diff --git a/Makefile b/Makefile
index 150aa30..2d85b72 100644
--- a/Makefile
+++ b/Makefile

@@ -8,7 +8,7 @@
 # Trusted Firmware Version
 #
 VERSION_MAJOR			:= 2
-VERSION_MINOR			:= 12
+VERSION_MINOR			:= 13
 # VERSION_PATCH is only used for LTS releases
 VERSION_PATCH			:= 0
 VERSION				:= ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH}
@@ -546,31 +546,6 @@
 	BL_COMMON_SOURCES	+=	lib/extensions/pauth/pauth.c
 endif
 
-####################################################
-# Enable required options for Memory Stack Tagging.
-####################################################
-
-# Currently, these options are enabled only for clang and armclang compiler.
-ifeq (${SUPPORT_STACK_MEMTAG},yes)
-    ifdef mem_tag_arch_support
-        # Check for armclang and clang compilers
-        ifneq ($(filter %-clang,$($(ARCH)-cc-id)),)
-        # Add "memtag" architecture feature modifier if not specified
-            ifeq ( ,$(findstring memtag,$(arch-features)))
-                arch-features	:=	$(arch-features)+memtag
-            endif	# memtag
-            ifeq ($($(ARCH)-cc-id),arm-clang)
-                TF_CFLAGS	+=	-mmemtag-stack
-            else ifeq ($($(ARCH)-cc-id),llvm-clang)
-                TF_CFLAGS	+=	-fsanitize=memtag
-            endif	# armclang
-        endif
-    else
-        $(error "Error: stack memory tagging is not supported for  \
-        architecture ${ARCH},armv${ARM_ARCH_MAJOR}.${ARM_ARCH_MINOR}-a")
-	endif #(mem_tag_arch_support)
-endif #(SUPPORT_STACK_MEMTAG)
-
 ################################################################################
 # RME dependent flags configuration, Enable optional features for RME.
 ################################################################################
@@ -1027,6 +1002,9 @@
 	ifneq (${ENABLE_FEAT_MOPS},0)
 		$(error "ENABLE_FEAT_MOPS cannot be used with ARCH=aarch32")
 	endif
+	ifneq (${ENABLE_FEAT_GCIE},0)
+                $(error "ENABLE_FEAT_GCIE cannot be used with ARCH=aarch32")
+	endif
 endif #(ARCH=aarch32)
 
 ifneq (${ENABLE_FEAT_FPMR},0)
@@ -1263,6 +1241,7 @@
 	ENABLE_RUNTIME_INSTRUMENTATION \
 	ENABLE_SME_FOR_SWD \
 	ENABLE_SVE_FOR_SWD \
+	ENABLE_FEAT_GCIE \
 	ENABLE_FEAT_RAS	\
 	FFH_SUPPORT	\
 	ERROR_DEPRECATED \
@@ -1550,6 +1529,7 @@
 	ENABLE_FEAT_D128 \
 	ENABLE_FEAT_GCS \
 	ENABLE_FEAT_MOPS \
+	ENABLE_FEAT_GCIE \
 	ENABLE_FEAT_MTE2 \
 	FEATURE_DETECTION \
 	TWED_DELAY \
@@ -1852,7 +1832,7 @@
 
 memmap: all
 	$(if $(host-poetry),$(q)poetry -q install --no-root)
-	$(q)$(if $(host-poetry),poetry run )memory -sr ${BUILD_PLAT}
+	$(q)$(if $(host-poetry),poetry run )memory symbols --root ${BUILD_PLAT}
 
 tl: ${BUILD_PLAT}/tl.bin
 ${BUILD_PLAT}/tl.bin: ${HW_CONFIG}
@@ -1861,7 +1841,8 @@
 
 doc:
 	$(s)echo "  BUILD DOCUMENTATION"
-	$(q)${MAKE} --no-print-directory -C ${DOCS_PATH} html
+	$(if $(host-poetry),$(q)poetry -q install --with docs --no-root)
+	$(q)$(if $(host-poetry),poetry run )${MAKE} --no-print-directory -C ${DOCS_PATH} html
 
 enctool: ${ENCTOOL}
 

diff --git a/changelog.yaml b/changelog.yaml
index 029b927..5a8ca1e 100644
--- a/changelog.yaml
+++ b/changelog.yaml

@@ -98,13 +98,16 @@
           - d128
           - debugv8p9
           - fgt2
+          - fpmr
           - gcs
           - hcx
+          - mops
           - mpam
           - mte
           - mte2
           - pauth
           - pmu
+          - pmuv3
           - rng-trap
           - sctlr2
           - feat_sctlr2
@@ -135,6 +138,13 @@
         deprecated:
           - plat/allwinner
 
+      - title: AMLogic
+        scope: amlogic
+
+        subsections:
+          - title: GXL
+            scope: gxl
+
       - title: Arm
         scope: arm
 
@@ -198,6 +208,7 @@
 
             deprecated:
               - neoverse
+              - neoverse_rd
 
           - title: TC
             scope: tc
@@ -301,6 +312,9 @@
           - title: MT8188
             scope: mt8188
 
+          - title: MT8189
+            scope: mt8189
+
           - title: MT8192
             scope: mt8192
 
@@ -315,6 +329,9 @@
               - plat/mediatek/mt8195
               - plat/mdeiatek/mt8195
 
+          - title: MT8196
+            scope: mt8196
+
       - title: NVIDIA
         scope: nvidia
 
@@ -548,6 +565,12 @@
         scope: rockchip
 
         subsections:
+          - title: PX30
+            scope: px30
+
+          - title: RK3288
+            scope: rk3288
+
           - title: RK3399
             scope: rk3399
 
@@ -558,6 +581,9 @@
           - title: RK3328
             scope: rk3328
 
+          - title: RK3576
+            scope: rk3576
+
           - title: RK3588
             scope: rk3588
 
@@ -595,6 +621,12 @@
             scope: stm32mp2
 
             subsections:
+              - title: STM32MP21
+                scope: stm32mp21
+
+              - title: STM32MP23
+                scope: stm32mp23
+
               - title: STM32MP25
                 scope: stm32mp25
 
@@ -716,6 +748,7 @@
             scope: el3-spmc
 
             deprecated:
+              - el3_spmc
               - spmc
 
           - title: SPMD
@@ -724,6 +757,9 @@
           - title: SPM MM
             scope: spm-mm
 
+            deprecated:
+              - spm_mm
+
       - title: DRTM
         scope: drtm
 
@@ -792,6 +828,9 @@
       - title: FCONF
         scope: fconf
 
+      - title: HOB
+        scope: hob
+
       - title: MPMM
         scope: mpmm
 
@@ -801,7 +840,7 @@
       - title: ROMlib
         scope: romlib
 
-      - title: GPT
+      - title: Granule Protection Tables
         scope: gpt
 
         deprecated:
@@ -813,6 +852,9 @@
       - title: Translation Tables
         scope: xlat
 
+        deprecated:
+          - xlat_tables_v2
+
       - title: C Standard Library
         scope: libc
 
@@ -954,6 +996,9 @@
             scope: gic
 
             subsections:
+              - title: GICv5
+                scope: gicv5
+
               - title: GICv3
                 scope: gicv3
 
@@ -1139,6 +1184,9 @@
           - title: Clock
             scope: nxp-clk
 
+          - title: uSDHC
+            scope: nxp-mmc
+
       - title: Renesas
         scope: renesas-drivers
 
@@ -1316,6 +1364,12 @@
                 scope: stm32mp2-fdts
 
                 subsections:
+                  - title: STM32MP21
+                    scope: stm32mp21-fdts
+
+                  - title: STM32MP23
+                    scope: stm32mp23-fdts
+
                   - title: STM32MP25
                     scope: stm32mp25-fdts
 

diff --git a/common/feat_detect.c b/common/feat_detect.c
index 2d80b42..fa817d9 100644
--- a/common/feat_detect.c
+++ b/common/feat_detect.c

@@ -279,6 +279,11 @@
 	return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_D128_SHIFT,
 			     ID_AA64MMFR3_EL1_D128_MASK);
 }
+static unsigned int read_feat_gcie_id_field(void)
+{
+	return ISOLATE_FIELD(read_id_aa64pfr2_el1(), ID_AA64PFR2_EL1_GCIE_SHIFT,
+			     ID_AA64PFR2_EL1_GCIE_MASK);
+}
 
 static unsigned int read_feat_fpmr_id_field(void)
 {
@@ -425,6 +430,8 @@
 	/* v9.3 features */
 	check_feature(ENABLE_FEAT_D128, read_feat_d128_id_field(),
 		      "D128", 1, 1);
+	check_feature(ENABLE_FEAT_GCIE, read_feat_gcie_id_field(),
+		      "GCIE", 1, 1);
 
 	/* v9.4 features */
 	check_feature(ENABLE_FEAT_GCS, read_feat_gcs_id_field(), "GCS", 1, 1);

diff --git a/contrib/libtl b/contrib/libtl
new file mode 160000
index 0000000..9630cb0
--- /dev/null
+++ b/contrib/libtl

@@ -0,0 +1 @@
+Subproject commit 9630cb01984503a9fe6974d31b0d581fb693540c

diff --git a/docs/about/features.rst b/docs/about/features.rst
index f15144a..78f5ff3 100644
--- a/docs/about/features.rst
+++ b/docs/about/features.rst

@@ -128,6 +128,7 @@
 in a platform:
 
 -  RSE comms driver ``drivers/arm/rse``
+-  GICv5 driver ``drivers/arm/gicv5`` via ``USE_GIC_DRIVER=5``
 
 Still to come
 -------------

diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 2627555..10b5c16 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst

@@ -73,8 +73,6 @@
 :|G|: `vwadekar`_
 :|M|: Yann Gautier <yann.gautier@st.com>
 :|G|: `Yann-lms`_
-:|M|: Chris Palmer <palmer@google.com>
-:|G|: `noncombatant`_
 :|M|: Govindraj Raja <govindraj.raja@arm.com>
 :|G|: `govindraj-arm`_
 
@@ -1118,7 +1116,6 @@
 .. _MrVan: https://github.com/MrVan
 .. _Neal-liu: https://github.com/neal-liu
 .. _niej: https://github.com/niej
-.. _noncombatant: https://github.com/noncombatant
 .. _nmenon: https://github.com/nmenon
 .. _npoushin: https://github.com/npoushin
 .. _odeprez: https://github.com/odeprez

diff --git a/docs/change-log.md b/docs/change-log.md
index 721e0f3..c865c34 100644
--- a/docs/change-log.md
+++ b/docs/change-log.md

@@ -3,6 +3,1203 @@
 This document contains a summary of the new features, changes, fixes and known
 issues in each release of Trusted Firmware-A.
 
+## [2.13.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.12.0..refs/tags/v2.13.0) (2025-05-14)
+
+The threat model for context management support is not available in the release.
+
+### ⚠ BREAKING CHANGES
+
+- **Platforms**
+
+  - **Arm**
+
+    - rename PLAT_MHU_VERSION flag
+
+      **See:** rename PLAT_MHU_VERSION flag ([a773955](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a7739550946acc0f9fd9f3360738eb046057ce28))
+
+- **Bootloader Images**
+
+  - **BL32**
+
+    - **TSP**
+
+      - The prototype for `tsp_early_platform_setup` has been
+        redefined. Platforms must update their implementations to match the new
+        function signature.
+
+        **See:** cascade boot arguments to platforms ([32d9e8e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/32d9e8ec6c1f2889ffeb549007a7569754add5f1))
+
+- **Drivers**
+
+  - **Arm**
+
+    - **RSE**
+
+      - remove rse_comms_init
+
+        **See:** remove rse_comms_init ([91c7a95](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/91c7a952bedb34f1b4c691988f9da9af02209441))
+
+### New Features
+
+- **Architecture**
+
+  - **CPU feature like FEAT_XXXX / ID register handling in general**
+
+    - add support for FEAT_PAUTH_LR ([025b1b8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/025b1b816b607c7ac43a77172040c44b7750a622))
+    - add support for PMUv3p9 ([ba9e6a3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ba9e6a342de0a8922d75559bc3c539a5174e2004))
+    - enable FEAT_BTI to FEAT_STATE_CHECKED ([10ecd58](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/10ecd58093a34e95e2dfad65b1180610f29397cc))
+    - enable FEAT_PAuth to FEAT_STATE_CHECKED ([8d9f5f2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8d9f5f2586d32ca19c11f65f3c6954615f3efdf6))
+    - disable FPMR trap ([a57e18e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a57e18e4337b74ce3d133a18f07fa891f0fd5fa9))
+    - enable FEAT_MOPS in EL3 when INIT_UNUSED_NS_EL2=1 ([6b8df7b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6b8df7b9e5cc70ef0433a99bf73db6db6002482c))
+    - setup per world MDCR_EL3 ([c95aa2e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c95aa2eb0dc7471df5f2c7a3d1cf939046bc170e))
+    - add support for FEAT_SPE_FDS ([4fd9814](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4fd9814f4865efdffca17b7bbfc8d4bd244866f3))
+
+- **Platforms**
+
+  - **AMLogic**
+
+    - **GXL**
+
+      - add support for booting from U-Boot SPL/with standard params ([8dca65d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8dca65d96f787b6802b75bc72f830149293cbb6d))
+
+  - **Arm**
+
+    - add a macro for SPMC manifest base address ([eab1ed5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/eab1ed54bfb6038a0c1ada79de409a5506e4dae0))
+    - add initrd props to dtb at build time ([1c08ff3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1c08ff3277d47979c7897842ba683c23aa8197f7))
+    - add support for Transfer List creation ([4c5ccbf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4c5ccbf43c1e34e3f2f71878f732efbe2449e9f6))
+    - convert arm platforms to expect a wakeup ([da305ec](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/da305ec75dedca5e8e939790ab02fe7c0ba999d5))
+    - enable Linux boot from fip as BL33 ([eb8cb95](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/eb8cb9534b58537e4ead8d1f8112ece45993c86d))
+    - migrate heap info to fw handoff ([ada4e59](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ada4e59d166ab9fe7b039ed0f0b272398f71bdb9))
+    - port event log to firmware handoff ([b30d904](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b30d9043be420f6a288687cf9f282d4e578f69aa))
+    - support AArch32 booting with handoff ([abdb953](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/abdb953b00fff4aace32d9be10005b89751858d0))
+    - support boot info handoff and event log ([a852fa1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a852fa1d594f63bdc502a0c73eb77c5ce88aa02e))
+    - use provided algs for (swd/p)rotpk ([da57b6e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/da57b6e3cfdb36ad96d136d17ec3d300f699fee3))
+    - use the provided hash alg to hash rotpk ([d51981e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d51981e15dd8383d727bd15e718f657f2cd2aaf5))
+
+    - **FVP**
+
+      - add StandaloneMm manifest in fvp ([8416e79](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8416e7917f9c82336e900659d35038942418582f))
+      - add stub function to retrieve DLME image auth features ([1733deb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1733deb46c02444febfd25e411d09b1888ba8a7b))
+      - add stub platform function to get ACPI table region size ([5d37755](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5d377555e862dd07e11022ba0a70f0150e34454b))
+      - allocate L0 GPT at the top of SRAM ([7a4a070](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7a4a07078b3d15648c1cbbd9f309b0c11da56165))
+      - build hob library ([8740771](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/874077132cf9a0504cccde6651c5714fa97beb07))
+      - change size of PCIe memory region 2 ([2e55a3d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2e55a3d74d588780e04f1632c1b9d7ad33fb5f4f))
+      - define single Root region ([665a8fd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/665a8fdf3aa372862d62c34d23ffd678798a265c))
+      - give bootargs on all configs ([a507f4f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a507f4f5f07253986b585e03583d40a818ebc3fb))
+      - increase BL1 RW for PSA Crypto ([51bdb70](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/51bdb70fdb3719ad1eabb4e0d1037f4d89a552d6))
+      - increase bl2 mmap len for handoff ([24f7830](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/24f78301288195f511528fc58b00e48f61933fa8))
+      - increase cactus-tertiary size ([dcd8d7f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dcd8d7f13d5318ea3b38e6558c13e7401d57530c))
+      - increase GPT PPS to 1TB ([aeec55c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/aeec55c8760f384bee46e1999287b0a757227c69))
+      - port event log to firmware handoff ([5bf0b80](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5bf0b80784e29e9e77edb26b605d2c1791ecded2))
+      - set defaults for build commandline ([bf9a25f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bf9a25f075c4c94a3d47bc54c1a8a7b964444ff1))
+      - support AArch32 booting with handoff ([2ab298b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2ab298b58bf3096f033ec922acc163c106118f62))
+
+    - **Neoverse-RD**
+
+      - deprecate and remove RD-N1-Edge platform variants ([71ad967](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/71ad967333a684f66eccd0de559ad2159ca9c1bd))
+      - deprecate and remove RD-V1 platform variants ([afb3075](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/afb3075592bc8cc2f130f2ed6c5871a391bf0e56))
+      - deprecate and remove SGI-575 platform ([a023201](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a0232015d089c0fca1e78b1d5fb9c8be61acca67))
+      - use larger stack size when S-EL2 spmc is enabled ([82f4659](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/82f46593de26d758457391d8b5036abcc533c7e3))
+
+      - **RD-V3**
+
+        - add carveout for BL32 image ([6823f5f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6823f5f520e7dfcd0812bdf8d93deb8c770de5e8))
+        - add dts files to enable hafnium as BL32 ([4d9b828](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4d9b8281f35256f7367a6b76b1259d9edbefe713))
+        - define SPMC manifest base address ([12973bc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/12973bcc89eff3a4bb4953061d48e8805b3c6079))
+        - enable the support to fetch dynamic config ([37cc7fa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/37cc7fa539d9cfbbe1fefadb2346bc7415422fec))
+        - introduce platform handler for Group0 interrupt ([4593b93](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4593b932396dca2ed945ab2c95c6cc6712c3eeeb))
+
+    - **TC**
+
+      - add 'kaslr-seed' node in device tree for TC3 ([2d967e9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2d967e92e00fe05f0c1ecaddf414d50078050f9d))
+      - add devicetree node for AP/RSE MHU ([06fa4c4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/06fa4c4df28165dbf1d08158d86ef9997f099ad6))
+      - add dsu pmu node for TC4 ([50ad0cf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/50ad0cfda371f520c3b0452af8955aac30634431))
+      - add MCN PMU nodes in dts for TC4 ([624deb0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/624deb0825cf6b7e27165edf182bd075e58ee2ff))
+      - add SLC MSC nodes to TC4 DT ([99f6790](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/99f6790cb9681d0a2960f8d30d82c20db19f6ab7))
+      - allow Android load and Boot From RAM ([932e64a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/932e64a1d79ef5ea7ed1525c45c9f11725ce5079))
+      - configure UART for TC4 FPGA ([84ca47a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/84ca47a8ac03821cfd4dbe902c0ae71621e2f12f))
+      - define MCN related macros for TC4 ([8f61c20](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8f61c20457c8e683b9c6b2a3f3c4ebcf4b1a5371))
+      - enable Arm SPE for TC4 ([cea55c8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cea55c836f205a988634c04416082e35ac350ff9))
+      - enable DSU PMU el1 access for TC4 ([00397b3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/00397b30b8da9489dd8ed5f51aa976bb34165a27))
+      - enable MCN non-secure access to pmu counters on TC4 ([d1062c4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d1062c472a2976a03c74479eb18327e46f604f6c))
+      - enable stack protector ([d1de6b2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d1de6b2b57d9e52c3b08c63ae4ce2d1e6703ce70))
+      - enable trng ([2ae197a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2ae197acd6a91a96619090e503521d44bee494b2))
+      - fpga: Enable support for loading FIP image to DRAM ([969b759](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/969b7591dcd94b0380116d301c2ba463dd9bfd7c))
+      - get entropy with PSA Crypto API ([8f0235f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8f0235fb8f2d46ee6ca6309f8c365ad57e3a1565))
+      - increase SCP BL2 size to support optimization 0 ([3755e82](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3755e82c0f2c557d38dc4111f4ccd31a9394ee25))
+      - initialize MHU channels with RSE ([0328f34](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0328f3422275a3d292c9025a1a1faaf9d54aa8d9))
+      - initialize the RSE communication in earlier phase ([a3f9617](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a3f9617964ee30070855f9ba5e42ccb28dcc6a05))
+      - port BL1-BL2 interface to firmware handoff framework ([93c50ae](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/93c50ae67fbdefd0fa2457a1b44fc538265b8fe0))
+      - port BL2-BL31 interface to firmware handoff framework ([2a36dee](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2a36dee8f158290cc30425df0753b6d887f12256))
+      - port BL31-BL33 interface to firmware handoff framework ([25a6bcd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/25a6bcd57104507c2f23760c2cc2ace43b5c00dd))
+      - print ni-tower discovery tree ([d87a856](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d87a8562306a46049560ba4387789918ecbca4b6))
+      - update CPU PMU nodes for tc4 ([1ce2c74](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1ce2c745a8b471dcc9e9f64e2163add566f5ce69))
+
+    - **Automotive RD**
+
+      - **RD-1 AE**
+
+        - add Generic Timer in device tree ([6e1bf7e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6e1bf7e97f7389f59c2ea0d28cfeef5399db7881))
+        - add support for OP-TEE SPMC ([8b27eb7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8b27eb7d91d97d707af94fff11ea02963ee2c3c0))
+
+  - **Intel**
+
+    - add FDT support for Altera products ([29d1e29](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/29d1e29d7cb137311529603056ce36ff268f861c))
+    - add support for query SDM config error and status ([fcf906c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fcf906c90088227b51a526533e71f4c8cd879778))
+    - implementation of SiPSVC-V3 protocol framework ([204d5e6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/204d5e67b90b9dfaf7d7e064c048b4587a73f965))
+    - provide atf build version via smc call ([d1c58d8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d1c58d86496164d701d3286786db73182925d0e9))
+    - support FCS commands with SiPSVC V3 framework ([597fff5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/597fff5f8739b29fb779075be216d16acc28ab58))
+
+  - **Marvell**
+
+    - add trng driver ([6d5fad8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6d5fad8d9ea4011fa49556592c7a4560e7206940))
+
+  - **MediaTek**
+
+    - add gic driver ([d905b3d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d905b3df300c1a822e666c5d8bd903ce16f5d507))
+    - add UFS stub implementation ([57c7351](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/57c7351545befba76ae4725ef602eca0491cc5ac))
+    - add vcp driver support ([a1763ae](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a1763ae97eab53476eef556a068de4bdf36b737a))
+    - update mtk_sip_def.h ([ead2602](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ead26026ff9f877b65011de55e3b3874e14aa137))
+
+    - **MT8189**
+
+      - add GIC driver on MT8189 ([1d193f9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1d193f91ea89ad525acc9ec5d78084da445d3813))
+      - add GPIO support ([cecbb93](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cecbb93c1e623f163621a97a2368c72ac9068bfb))
+      - add reset and poweroff function for PSCI call ([4e40a1f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4e40a1fdcf50dcfacd4331163f5a547d325714b3))
+      - disable L3C shared SRAM if the bootloader is coreboot ([7794e7c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7794e7c0b19f1fe470e62f59421d5770de1fcc95))
+      - enable cirq for Mediatek MT8189 ([83a5a0d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/83a5a0d1cc2d7cbb90ed9a11bb2b929a5f3b26e0))
+      - initialize platform for MT8189 ([6c60901](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6c60901a4569ac2d7c5807158186d6701d3a2cf3))
+
+    - **MT8196**
+
+      - add APU kernel control operations ([5e5c57d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5e5c57d52b1cfaec5182b2d01f804fae9ed54af4))
+      - add APU power on/off functions ([3ee4b2d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3ee4b2def6d1ee92dafb1730ff7852d8af532009))
+      - add APU power-on init flow ([0781f78](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0781f7804a6922b3bb40f2b50880a9563e8ccd84))
+      - add APU RCX DevAPC setting ([f31932b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f31932b43087af86c56f919307a3ba4f7e994138))
+      - add APU SMMU hardware semaphore operations ([2d134d2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2d134d28f585f4bbcbf2e698443ab79b64128af2))
+      - add APUMMU setting ([e534d4f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e534d4f633c30742ef7ced69abe077399b8eb5e6))
+      - add APUSYS AO DevAPC setting ([31a0b87](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/31a0b877566b0ebac6d11f2f8711cc11c0665e44))
+      - add CPC module for power management ([75530ee](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/75530ee280048a416844265f947d7a11b920d1f1))
+      - add DCM driver ([e578702](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e578702f71f99f728ca2406a89c1345132f44b78))
+      - add GPIO support ([4cb9f2a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4cb9f2a5bf3a89d99f31505f830431e67a552709))
+      - add LPM v2 support ([da8cc41](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/da8cc41bc802555e15e280a7c7bf97bece8f69b3))
+      - add mcdi driver ([5cb0bc0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5cb0bc07e3700ae9354e48adad8a990b02d7c80d))
+      - add mcusys moudles for power management ([95e974f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/95e974fa15da2e5f5ff2e151d0d97390e483be98))
+      - add Mediatek EMI stub implementation for mt8196 ([39f5e27](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/39f5e2782061835650a80832a4a058921bd79568))
+      - add Mediatek MMinfra stub implementation ([4794746](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4794746eec6191563a97fec55c06027e42abe9bb))
+      - add mtcmos driver ([1f913a6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1f913a6e3a3eb6349db9a2263e15594c4dcd5766))
+      - add PMIC driver ([d4e6f98](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d4e6f98d7f8b33ebd7706e8a440c568262500e21))
+      - add pwr_ctrl module for CPU power management ([4ba679d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4ba679da8b90ee15dd1234bc773854debb9b2466))
+      - add reset and poweroff function for PSCI call ([22d74da](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/22d74da7cd0132b3b40c2289a3cbd152e548632c))
+      - add SMMU driver for PM ([86dd08d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/86dd08d838a6a49e7915df0f20c90c3a3e003056))
+      - add smpu protection for APU secure memory ([7ed4d67](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7ed4d67c6351e61dd5500a0887e4d5e85b8ab764))
+      - add SPM basic features support ([fb57af7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fb57af70ae8c93ebe806eb6281036a15113dc4f5))
+      - add SPM common driver support ([a24b53e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a24b53e0e581cde7b5c43607ab76ded8336dc353))
+      - add SPM common version support ([5532feb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5532feb70c699c54a21b02fada8fed59a3992786))
+      - add SPM features support ([01ce1d5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/01ce1d5d2fedb4e7db2127286080f6495a5403cf))
+      - add SPMI driver ([adf73ae](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/adf73ae20a7aa6f8230cb7a19551edb239db8afe))
+      - add topology module for power management ([da54c72](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/da54c7243618cbb21c5269cc153f4ac2508ee76f))
+      - add vcore dvfs drivers ([f0dce79](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f0dce79600f239d9c2f382ba4573aba5e5126001))
+      - disable debug flag in APU driver ([31137e1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/31137e1b1559b6e838e9a4e4b9f74a5473ba8837))
+      - enable appropriate errata ([0d11e62](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0d11e62e67deb9a898b2ac5e7fbda58408df371b))
+      - enable APU on mt8196 ([f5a6aa0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f5a6aa02a9332c42712c709c6017927b99ca04c2))
+      - enable APU spmi operation ([823a57e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/823a57e11cd98ee6043e9637ff3a4cf58feb60ff))
+      - enable apusys mailbox mpu protection ([83f836c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/83f836c96238c0d0765d94cc1f8ed1c179d1878c))
+      - enable apusys security control ([9059a37](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9059a375eeb20c08cdcd5e604b9fd68b47a31e7e))
+      - enable cirq for MediaTek MT8196 ([49d8c11](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/49d8c11285b28bddf9cdc7830ce039d4fc734f35))
+      - enable DP and eDP for mt8196 ([3e43d1d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3e43d1d317fa0f4ba6fdfc95583b8e313333769d))
+      - enable IRQ configuration ([16f94b9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/16f94b91f10a5f8d52b6eb16a685881c97f7df89))
+      - enable PMIC low power setting ([e8e8768](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e8e87683f2b4d8213a84475e5f981961dcc8a16b))
+      - enable vcore dvfsrc feature ([a3c218a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a3c218afd6596a46791b7f5d84a8d45d3c6977a0))
+      - fix MT8196 gpio driver ([6f891e6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6f891e68964888bb9d97f83600d85e606882a8d2))
+      - initialize platform for MediaTek MT8196 ([a65fadf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a65fadfbbd5919939bfe367fe3f2d3c22ca4cbf0))
+      - link prebuilt library ([e033943](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e0339436614a2b86cae04dabc74efdb31e2b0fb4))
+      - refactor LPM header include paths to use lpm_v2 ([6fac00a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6fac00a49099beda9caeb66d8bc35b00f0f52f10))
+      - show ERROR log if need ([1ba50c3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1ba50c33fcdf10d2132d6d96a5238c378b57de2f))
+      - turn on APU smpu protection ([5de1ace](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5de1ace54a7088828dfaccd275ec2f1938ce7ee4))
+
+  - **NXP**
+
+    - **S32G274A**
+
+      - add console mapping ([a1e07b3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a1e07b399b5724e0d8f68a2e6ba6ce3102c2c424))
+      - dynamically map GIC regions ([5680f81](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5680f81cecbbbb8a584dcf62bcb766a1cb25345f))
+      - dynamically map SIUL2 and fip img ([507ce7e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/507ce7ed6f5c2c34a94f18c6d66db27b163e0f2a))
+      - enable MMU for BL2 stage ([eb4d418](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/eb4d4185fa67edb6d137a5f7a0eb5e209b4e6299))
+      - enable MMU for BL31 stage ([e2ae6ce](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e2ae6ceccc6fc96debbfbacfb4b288cbf78da0f2))
+      - enable SDHC clock ([47b3a82](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/47b3a8251f1b7948360714254f8ec22b0e23875e))
+      - increase the number of MMU regions ([0089258](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/008925861f3d6b30722895bc9701b85ec3d81215))
+      - map each image before its loading ([34fb2b3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/34fb2b35b9996d2afe40ad52f3a004bb90bf95f2))
+      - split early clock initialization ([61b5ef2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/61b5ef21af8bcb38d3492e15d1d3d1fbecf3cf49))
+
+  - **QEMU**
+
+    - add hob support for qemu platforms ([648d2d8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/648d2d8e2dab8cf939350a1788c5204751dcc9be))
+    - add plat_rmmd_mecid_key_update() ([9c9a31e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9c9a31eb9ae36cab9db58ddc5d49f82ca3cf976d))
+    - hand off TPM event log via TL ([cc58f08](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cc58f08fe6a53ab375322dbdec6edbe5707110b8))
+    - update for renamed struct memory_bank ([991f536](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/991f5360b68d6cdfbda2950100dbf78ac1c482cc))
+
+    - **SBSA**
+
+      - add support for RME on SBSA machine ([acb0937](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/acb09373baa1f951b68168e044ddf94d299ef44f))
+      - adjust DT memory start address when supporting RME ([99bc6cf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/99bc6cf518c1d6c0995d53d00670c0ac972ea64d))
+      - configure GPT based on system RAM ([d079d65](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d079d65d420d0f9edd4aa64b27305fc6537095da))
+      - configure RMM manifest based on system RAM ([fb4edc3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fb4edc35bc19e411ae566d1089198760042324eb))
+      - dissociate QEMU NS start address and NS_DRAM0_BASE ([26da60e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/26da60e2a0e47768997b1b2079848beb9b5479c6))
+      - increase maximum FIP size ([122dbc2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/122dbc2c17494e96e7fd45ce6e03b68f8722585b))
+      - relocate DT after the RMM when RME is enabled ([17af959](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/17af9597e2b5d7cda2aaadad74b352e9805522d2))
+
+  - **QTI**
+
+    - platform support for qcs615 ([f60617d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f60617d3b1f9446d7f1528b3ac16fe6c4db9779d))
+
+  - **Raspberry Pi**
+
+    - **Raspberry Pi 3**
+
+      - add dTPM backed measured boot ([4f9894d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4f9894db3572b6e375c7369bc2619cc690169604))
+      - implement eventlog handoff to BL33 ([6dfcf4e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6dfcf4e1df3b4690fdf2629815d2a91294f34493))
+      - implement mboot for rpi3 ([c4c9e2b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c4c9e2bc436198ee8f4544e8091c0067c4b4d9be))
+
+  - **Rockchip**
+
+    - increase FDT Buffer for Rockchip Devices ([ab99dce](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ab99dce4b7c8473d5bcb8c833bd410ab87b1e801))
+    - update uart baudrate for rk3399 ([6d7f1d4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6d7f1d4945ad3b85e33fb85eb7374d0fef2e9b64))
+
+    - **RK3576**
+
+      - support rk3576 ([036935a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/036935a8144b9c4b9f95f249ff4384945b846d40))
+
+  - **Socionext**
+
+    - **Synquacer**
+
+      - add support Hob creation ([357f28d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/357f28db6bcca7856a8cdbedfe6ce4668b06b48c))
+
+  - **ST**
+
+    - use dedicated version of DT for SP_MIN ([71ba164](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/71ba1647e09ca7ccecfeca417b22d1f7d023e338))
+
+    - **STM32MP1**
+
+      - rework SVC services ([39b08bc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/39b08bc366ff1bb08a2ab1dfd9c1eab3157fe16d))
+
+    - **STM32MP2**
+
+      - add a runtime service for STGEN configuration ([7f41506](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7f41506fa7c10ba8cc393a9e67ae81bed379d07b))
+      - add common SMC runtime services ([f55b136](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f55b136abcdd2d6ba3bd5613eee8fff943de0fd1))
+      - add FWU support ([c28c0ca](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c28c0ca213147fff56555b038de8261fc5b92211))
+      - disable PIE by default on STM32MP2 platform ([ac9abe7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ac9abe7e597b1c5712a449b4a2366c859621e435))
+      - use USART1 for debug console on ultra-fly boards ([d59dd96](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d59dd96ddb2d58df989de07dc3d3fd86a1130652))
+
+  - **Texas Instruments**
+
+    - add support for TI mailbox driver ([9347ff4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9347ff4561e445d48839eac215cb452571cb8e54))
+    - introduce basic support for the AM62L ([21b14fd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/21b14fd2aef32cdb8e6304b0e1383157e651a86c))
+    - introduce PSCI Driver for AM62L ([1abdc20](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1abdc20b35f7b39862f91dbf1dfb462872380f71))
+
+  - **Xilinx**
+
+    - **Versal NET**
+
+      - add SDEI support ([10510c9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/10510c98c7501a76af16f7345225cc4225ee2cda))
+
+    - **ZynqMP**
+
+      - add pin group for lower qspi interface ([fe81d9c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fe81d9c959968599db8b8a5b1f150224f3315a38))
+
+  - **AMD**
+
+    - **Versal Gen 2**
+
+      - add bufferless IPI Support ([af22b19](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/af22b19d6b9cc3985ca61c68eb1a364dff7c4874))
+      - add dependency macro for PM ([aec66c3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/aec66c38c72a71cd1d37926c29ce08a25823bf89))
+      - add support for platform management ([414cf08](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/414cf08b76bcf7e8fdb841c3663716d151b133a8))
+      - extended SMCCC payload for EEMI ([0cc5e21](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0cc5e2105564bbcf9fae8d39869d51fb6c58ba23))
+      - is OCM configured as coherent ([c3ab09d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c3ab09d1c543bda64d543557556e8e03d2b26c32))
+      - retrieve DT address from transfer list ([ea45387](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ea453871ef70c116d40c950926c3c1a2c4036896))
+      - update platform version to versal2 ([4003ac0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4003ac02eb4e5b0551614710f3e99a2e23cfe799))
+
+- **Bootloader Images**
+
+  - adding psa crypto - crypto_mod_finish() ([055c97a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/055c97afb2427092766687253d6ff851ee77455e))
+
+  - **BL32**
+
+    - enable r3 usage for boot args ([3fabca7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3fabca724a724266f41a210d377d79072b36e140))
+
+    - **TSP**
+
+      - cascade boot arguments to platforms ([32d9e8e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/32d9e8ec6c1f2889ffeb549007a7569754add5f1))
+
+- **Services**
+
+  - **FF-A**
+
+    - add FFA_MEM_PERM_GET/SET_SMC64 ([ddf72e6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ddf72e6a36bd6ef0958af5cfd638926861fe5c21))
+    - support FFA_MSG_SEND_DIRECT_REQ2/RESP2 ([09a580b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/09a580b7961827501f94dd3dafbc27c7c5b69237))
+       ```
+       The FFA_MSG_SEND_DIRECT_REQ2/RESP2 early implementation in the EL3 SPMC is limited
+       to the use of 8 input/output registers per the SMCCC which isn't compliant to the
+       FF-A v1.2 specification mandating the use of 18 registers. This non compliance will
+       be fixed in the next release with the necessary versioning checks.
+       ```
+
+  - **RME**
+
+    - add SMMU and PCIe information to Boot manifest ([90552c6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/90552c612e31ba88c6a7ad47c4081bc89d09c9c5))
+
+    - **TRP**
+
+      - test el3-rmm ide km interface ([8b3a89f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8b3a89faddca3a955324adc4b48c864781e4c802))
+
+    - **RMMD**
+
+      - add FEAT_MEC support ([7e84f3c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7e84f3cf908c8eab1565b8e2d9a543e50de2e78e))
+      - add RMM_MECID_KEY_UPDATE call ([f801fdc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f801fdc22ef4fce3cc24fd1cbccde5772c15b633))
+      - el3-rmm ide key management interface ([2132c70](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2132c707d73753338ce05f262843a91738177f5e))
+      - verify FEAT_MEC present before calling plat hoook ([609ada9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/609ada9691ca3793ad7203536fb4c95088bd3026))
+
+    - **RMM**
+
+      - add PCIe IO info to Boot manifest ([bef44f6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bef44f60edaa763031bce6144c0267aefbb1f2bf))
+
+  - **SPM**
+
+    - use xfer list with Hob list in SPM_MM ([9ae5f67](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9ae5f67306b380c626a74782eff9e98b7f7996ee))
+
+    - **EL3 SPMC**
+
+      - ffa error handling in direct msg ([e1168bc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e1168bc37563d1f18d6d2a6dc4ed468eadf673f2))
+      - support Hob list to boot S-EL0 SP ([4053a64](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4053a647f6eca71e5a34bc52303a049e3324ca90))
+      - use spmd_smc_switch_state after secure interrupt ([a0a7f15](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a0a7f158d2932117d57ec0d74113890a565e0cbc))
+
+    - **SPM MM**
+
+      - move mm_communication header define to general header ([b51436c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b51436c2ca4f1ceb2145dc752584df6ab1b77670))
+
+  - **DRTM**
+
+    - add platform API to retrieve ACPI tables region size ([7792bdb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7792bdbdf91a5854e580adea0f993886c3eec5df))
+    - ensure event types aligns with DRTM specification v1.1 ([8d24a30](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8d24a30d6073239a40eb835cb6014172080f2f06))
+    - introduce plat API for DLME authentication features ([0f7ebef](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0f7ebef73eb72f4627cf657fcb92f60c01001b41))
+    - log No-Action Event in Event Log for DRTM measurements ([2ec4488](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2ec44880d0a47a60b851fea09b7bec0cd694e858))
+    - retrieve DLME image authentication features ([94127ae](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/94127ae299aedf7642e598785c90961ab6e18266))
+    - update DLME data header with actual Event Log size ([9753238](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9753238fee94e97aff307a2c98d8e76bcbcfa211))
+    - validate launch features in DRTM parameters ([8666bcf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8666bcfa75c2d7b80ccd0a92b252d5308e08216c))
+
+- **Libraries**
+
+  - **CPU Support**
+
+    - add ENABLE_ERRATA_ALL flag ([593ae35](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/593ae35435f855ff3e48facc6a049261c0c37ea7))
+    - add support for Alto CPU ([940ecd0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/940ecd072c695f51fc09eed1c13e50bbfa1690da))
+    - add sysreg_bit_toggle ([bb80185](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bb801857eaf21365402a4748296c05cb3c6e861f))
+
+  - **EL3 Runtime**
+
+    - **RAS**
+
+      - add asynchronous error type corrected ([daeae49](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/daeae495117e8e1496a44392217230ced17b39be))
+      - add eabort get helper function ([ec6f49c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ec6f49c26be266e9d2b26818f35765ba9edd4e10))
+
+  - **HOB**
+
+    - copy StandaloneMm Hob creation library in edk2 ([2105831](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2105831848c4aef432f49e229c530cbda3489b10))
+    - introduce Hob creation library ([8953568](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8953568a2db48032f2a2d4065e68fd1b20980caf))
+    - modify Hob creation code imported from edk2 ([6b68b4a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6b68b4a42f9858102f2c804026ed1ce136e15813))
+
+  - **PSCI**
+
+    - allow cores to wake up from powerdown ([2b5e00d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2b5e00d4eacbac4b315c1c2925882d0b77bc9205))
+    - remove cpu context init by index ([ef738d1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ef738d19d3565e44ed44a6b06c6d9ab036322ac5))
+
+  - **ROMlib**
+
+    - add PSA Crypto ROMLIB support ([cf1b7fe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cf1b7fe657a3215423ab397363cc4fa1a0e6399f))
+
+  - **GPT**
+
+    - statically allocate bitlocks array ([b0f1c84](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b0f1c84035fb25e331b21f08f3f3e8e643c3394d))
+
+  - **SMCCC**
+
+    - add FEAT_TWED to ARCH_FEATURE_AVAILABILITY ([d33ff5e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d33ff5e0eec0f90cf74a442fd83faec4a03ecde5))
+    - implement SMCCC_ARCH_FEATURE_AVAILABILITY ([8db1705](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8db170524de1eb83c21ee6344d628961f9b84456))
+
+  - **C Standard Library**
+
+    - import qsort implementation ([277713e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/277713e0ae3b9a20d661cbd9e214112f67bed35b))
+
+  - **PSA**
+
+    - add interface with RSE for retrieving entropy ([1147a47](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1147a470c257403466cdbd55a13823ca1652063e))
+
+  - **Firmware Handoff**
+
+    - add 32-bit variant of ep info ([7ffc1d6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7ffc1d6cf3c3981d74a3ac830f8a57f953b4ff03))
+    - add 32-bit variant of SRAM layout ([8001247](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8001247ce267a583ae6a24a37a77f17427bd5204))
+    - add func to check and init a tl ([f1d9459](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f1d94593354a948dfc81ca569d4832afb20aaf41))
+    - add lib to sp-min sources ([79e7aae](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/79e7aae82dd173d1ccc63e5d553222f1d58f12f5))
+    - add Mbed-TLS heap info entry tag ([0e932b8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0e932b8563b6e25ae5f233a789cd420e46ae9297))
+    - add transfer entry printer ([937c513](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/937c513d5e8996d106e2661ea88786bde513ae74))
+    - common API for TPM event log handoff ([4d8b4ca](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4d8b4ca0f5ab98e2d5d764a1530ae5fe55ba79bc))
+    - transfer entry ID for TPM event log ([9821775](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9821775657a415aac4b1d1f9c66da6390a016934))
+
+- **Drivers**
+
+  - **Authentication**
+
+    - add crypto_mod_finish() function ([0331bd2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0331bd22c6082776a3d82b3cd3a1e5771643562b))
+    - add update of current_pk_oid in auth ([9c18c35](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9c18c35cbb21632d817ed2650ce80e5d544cac3b))
+    - add util file for current pk_oid ([1716805](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/17168053b38878f700d5c4ac11421cb96a50bc1b))
+    - extend REGISTER_CRYPTO_LIB calls ([95d49c6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/95d49c624f7a7784db1af6bb4de2007d2f044d61))
+    - increase mbedtls heap for PSA RSA ([2ffc28c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2ffc28c833337d72b32580178ace9b466c7ebc24))
+    - introducing auth.mk ([142ee34](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/142ee34ea375479282d842e1905a61436e792cd8))
+    - mbedtls psa key id mgmt ([8a7505b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8a7505b008c71e61fa4e4d2b973932ec5720d526))
+
+    - **mbedTLS**
+
+      - introduce crypto lib heap info struct ([24da55e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/24da55eef7f032a8b4957fd9eb53dc3b87d01997))
+      - mbedtls config update for v3.6.2 ([c307efc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c307efce85cab2336ce0786b8ac46130508b8bfa))
+      - optimize SHA256 for reduced memory footprint ([b57468b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b57468b3d029cb123b7881cefc68290cdeb31d9d))
+      - update mbedtls to version 3.6.3 ([08f8c0a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/08f8c0a503b5c61d32f07edc8dae1a8179a174cd))
+
+  - **I/O**
+
+    - add generic gpio spi bit-bang driver ([3c54570](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3c54570afca013e050db3d01a4c948ae938d908a))
+
+  - **Measured Boot**
+
+    - add fw handoff event log utils ([ca39163](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ca391636ada5a382e35bdc41b930b46852a822a1))
+    - make event log lib standalone ([cb03020](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cb03020e20859e61e94a2cf6a3eda86f87e796e2))
+
+  - **TPM**
+
+    - add Infineon SLB9670 GPIO SPI config ([6fa56e9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6fa56e93679631b0d23c88e962b9e40c97971942))
+    - add tpm drivers and framework ([36e3d87](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/36e3d877cd6caf51155a74936f15b461cc9b814c))
+
+  - **Arm**
+
+    - **GIC**
+
+      - add support for local chip addressing ([c89438b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c89438bcea49bf9d265e6e17f1ef13e6cfc9f62b))
+
+  - **NXP**
+
+    - **Clock**
+
+      - add a basic get_rate implementation ([bd69113](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bd691136639963b61c028e55d5889997430e7fa7))
+      - add base address for PERIPH_DFS ([29f8a95](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/29f8a952cbbc7ee91188464cdf01b243735d41f8))
+      - add clock modules for uSDHC ([cf6d73d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cf6d73d4c3b0fc4b299e6249f063b5adb5e3bedc))
+      - add clock objects for CGM dividers ([63d536f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/63d536fe183bdf1c6ad99a5fd81cda7e2f32750f))
+      - add get_rate for clock muxes ([d1567da](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d1567da68d954be8f454ed641cbf7a08ca86f0bd))
+      - add get_rate for partition objects ([a74cf75](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a74cf75f084e62888f57f7718f614bcd6e5eb50f))
+      - add get_rate for s32cc_clk ([46de0b9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/46de0b9c992fd4da90075b39ccff0a849a976301))
+      - add get_rate for s32cc_dfs ([2fb2550](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2fb25509b800726342955194a0c6ac24299fb08e))
+      - add get_rate for s32cc_dfs_div ([8f23e76](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8f23e76fa5886ef9adbd867a546f291200fc2142))
+      - add get_rate for s32cc_fixed_div ([7c298eb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7c298ebcbf1003b98f815b86b2014112e89644d3))
+      - add get_rate for s32cc_pll ([fbebafa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fbebafa518d5cbc69d0c64023f002ff6706019f2))
+      - add get_rate for s32cc_pll_out_div ([a762c50](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a762c50579cb3bcae9c266e652c7c959e66fa943))
+      - dynamic map of the clock modules ([514c738](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/514c738045b5c2de0f8e99b68830322af88dad4d))
+      - enable MC_CGM dividers ([2710bda](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2710bdadc4cefd45bb7056c7e4c1e20dd1dfddc4))
+      - get MC_CGM divider's parent ([1586904](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/15869048b26f2ca2ebb78913ba1824532745744a))
+      - get MC_CGM divider's rate ([ad412c0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ad412c0d823ec1acad76f75419f40bdb09b2ad51))
+      - get parent for the fixed dividers ([35988a9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/35988a9db0aad69d068715ffe4d2f456aed5b508))
+      - get pll rate using get_module_rate ([43b4b29](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/43b4b29fb996ee05d2ca98c7f824d6a003342215))
+      - restore pll output dividers rate ([c23dde6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c23dde6c193d26fae9b2a8e18140b90faeba3661))
+      - set MC_CGM divider's rate ([f99078a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f99078a6a09c09c93ac8f0aa679e1e85ab9658f3))
+      - set the rate for partition objects ([8501b1f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8501b1fc60e3f6d01a38a3055dc0f274ecb039c6))
+
+  - **ST**
+
+    - **ST PMIC**
+
+      - add defines for NVM shadow registers ([c1222e7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c1222e7b8e635061690fe430e9213e86aae87920))
+
+- **Miscellaneous**
+  - add a generic EXTRACT macro ([f963578](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f963578b24906121b75375517f46c8d4d2a538fd))
+  - add EXTRACT_FIELD macro for field extraction ([af1dd6e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/af1dd6e1a58957dc04747b9c87f482166022265c))
+  - implement strnlen secure and strcpy secure function ([eb08889](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/eb088894dc9fb08eb3da82b86ebdabe82ae45940))
+
+  - **AArch64**
+
+    - add DBGPRCR_EL1 register accessors ([bdcef87](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bdcef87cf5e16896688ee69aef216f7929a065c5))
+
+  - **FDTs**
+
+    - **ST**
+
+      - **STM32MP1**
+
+        - **STM32MP15**
+
+          - add Linux Automation GmbH Fairy Tux 2 ([093c738](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/093c738ab642005ca273aa6f21d306c81163012c))
+          - add Linux Automation GmbH TAC ([e67497f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e67497f9cc435e37c53b6a6361af3824247597df))
+          - add SP_MIN versions of DT files ([20544d6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/20544d66ccd53f8524d9d616fdab98dab88df37a))
+
+      - **STM32MP2**
+
+        - add LPDDR4 files ([64f82e5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/64f82e5a06cf4aeef9da40a8d503dc3f77cdb840))
+        - add STM32MP257F-DK board support ([6a9e5ff](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6a9e5ffda76a7625786cfe6d4246dfdcb4a9f8f1))
+        - add dual-ranked LPDDR4 config for STM32MP2 ([99adf4d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/99adf4d43e09915e190b645227f41fa3ea10dd51))
+
+        - **STM32MP25**
+
+          - enable WDQS for LPDDR4 ([29917d3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/29917d3a12c98ebe9776c3191cb699e1687771be))
+          - update 2GB DDR configs ([388cb47](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/388cb47cf0275cfc435df305a75781f2cf5a5ca7))
+          - add support for STM32MP257D-based ultra-fly-sbc board ([a4e31cf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a4e31cf0d96438bca564e219490f55fa2e6abeb4))
+
+- **Documentation**
+
+  - update mboot threat model with dTPM ([b00f6ec](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b00f6ece560696a89bf2a91289ea9ef51a768c5d))
+
+- **Build System**
+
+  - rk3399: m0: add support for new binutils versions ([6fbec46](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6fbec46a59de301edd9ad63af3a8a007977173cf))
+
+- **Tools**
+
+  - **Secure Partition Tool**
+
+    - add StMM memory region descriptor ([3553087](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/35530877967fd943186cd0afc895f71f0976bf23))
+    - add the HOB list creation script ([cc594af](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cc594af66e05b5f863b00dfab939f53e558d9c23))
+    - include HOB file in the TL pkg ([32ecc0e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/32ecc0ef781d44f462aaeb441458d72b7dd5023d))
+    - invoke the HOB list creation code ([2d317e8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2d317e80c201573e9a05472ac1c96b0e6fe6e3bf))
+    - populate secure partition number in makefile ([9327361](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/93273613b48048a4a884770e292e765fa85e3ad7))
+    - specify endianness for HOB bin ([49c6566](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/49c656633178d21679afd467e41f43a761d4238c))
+    - transfer list to replace SP Pkg ([0fe374e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0fe374ef046f70b6e990024922034d14d418b109))
+
+  - **Transfer List Compiler**
+
+    - add --align argument ([c4c8e26](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c4c8e26a69411902516d394d8ca593db435c612b))
+    - formalise random generation of TEs ([157c619](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/157c61978679ca7115e06df92d481b57fa2ae1ef))
+
+### Resolved Issues
+
+- **Architecture**
+
+  - **CPU feature like FEAT_XXXX / ID register handling in general**
+
+    - add support for 128-bit sysregs to EL3 crash handler ([58fadd6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/58fadd62beba8e9fefddae884bfd34f71a183997))
+    - add feat_hcx check before enabling FEAT_MOPS ([484befb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/484befbfcbe5289fa237a96c36a2da75ff3ff2ba))
+    - avoid using mrrs/msrr for tspd ([f3e2b49](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f3e2b499707c5cde85033c8ed16efe4f16de5231))
+    - improve xpaci wrapper ([787977c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/787977c3afe9d951a088a1f12959b00d8343a18d))
+    - include FEAT_MOPS declaration in aarch32 header ([8656bda](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8656bdab57b22b5a65bb0480429553c084c1b0a6))
+    - replace "bti" mnemonic with hint instructions ([bdac600](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bdac600bc8c61e2facdd0b872cacfb7a24045fe4))
+    - add a psb before updating context and remove context saving ([f808873](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f808873372381a401dcd86d7d45a5ee6fd164d50))
+    - add a tsb before context switching ([73d98e3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/73d98e37593f4a4044dd28f52127cdc890911c0c))
+
+- **Platforms**
+
+  - **Arm**
+
+    - create build directory before key generation ([db69d11](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/db69d118294f08aae86378c98aa082ac73e15b73))
+    - don't race on the build directory ([9855568](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9855568cc5ab8af9a8bee54fcc35112240e16b28))
+    - reinit secure and non-secure tls ([2948d1f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2948d1f81904f02034a0d12faf9b8c7f34b05795))
+    - resolve build issue with ARM_ROTPK_LOCATION=regs option ([4569a49](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4569a496fd5b41b371c676b9313b796fe8bd27c2))
+    - resolve dangling comments around macros ([523c787](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/523c78704fabfd5f35f0e6abe6df2192d33a3c95))
+    - resolve misra rule R11.6 violation ([307a533](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/307a533301881869c0f54a5145a81a6a705156b9))
+    - update tsp_early_platform_setup prototype ([9018b7b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9018b7b8401ab106228842140b53502ee64f1432))
+    - use EL3_PAS in MAP_BL2_TOTAL definition ([875423d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/875423de49646402cd6a7c1850f52982a3b56299))
+
+    - **Common**
+
+      - add missing curly braces ([7e288d1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7e288d11a5f155de4d6ad2ab9827fd71c0c9f74e))
+      - modify function to have single return ([50029b9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/50029b9ac3c60371f8606fb874df9038fb6839d0))
+      - remove platform_core_pos_helper() ([96e46f5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/96e46f58d54a1a711bd7474a4ea949785119798e))
+      - remove fvp_r ([2cadf21](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2cadf21bc8cc58e9ed8c7ae2af6089ffdb3d0a02))
+      - remove unused vfp code ([18b129f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/18b129f4c1539444f9b91655d325a013264f7312))
+      - add missing curly braces ([0eeda63](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0eeda638a8a6e8d9ff0448ba7405a8a5b86d17e0))
+      - ignore the unused function return value ([fc7a720](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fc7a7208e0ccc0722bb29fcbb0cb7a3d74ff0953))
+
+    - **CSS**
+
+      - turn the redistributor off on PSCI CPU_OFF ([50009f6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/50009f61177421118f42d6a000611ba0e613d54b))
+
+    - **FVP**
+
+      - allow PSCI 0.2 in the device tree ([94b500d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/94b500dcbb94b11c5b89657eda10e6f0b5fc87a1))
+      - exclude extend memory map TZC regions ([06cec93](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/06cec933def225ef64d81983829c349f47b89319))
+      - increase EventLog size for OP-TEE with multiple SPs ([d1a824e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d1a824ea0e8887151d1237f3836e7e0df4d9e5bd))
+
+    - **Juno**
+
+      - resolve BL2 RAM overflow with RSA+ECDSA in GCC(14.2.1) ([dd566a9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dd566a9e565842eb97b6e14da63ba01d13d061ec))
+
+    - **Morello**
+
+      - remove stray white-space in 'morello/platform.mk' ([05533d9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/05533d99922f76af82b765159bb56e6592c09cf0))
+
+    - **Neoverse-RD**
+
+      - initialize CNTFRQ_EL0 for RESET_TO_BL31 ([94a4383](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/94a4383a2b7de555ac68fc4f571d08105cdb3296))
+      - initialize timer before use in smmuv3_poll ([64ff172](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/64ff172abe1edf333d41fb99aac1b4c50d85f248))
+      - set correct SVE vector lengths ([842ba2f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/842ba2f22196beab45a581517ad43a6cdbf61d9a))
+
+      - **RD-N2**
+
+        - add LCA multichip data for RD-N2-Cfg2 ([289578e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/289578e610b6e4dfb62068a07bc56216e431fb17))
+        - correct RD-N2 StMM uuid format ([6fb8d8c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6fb8d8cf8427ebf2c63986ea3451ca835eac3aa2))
+
+      - **RD-V3**
+
+        - add console name to checksum calculation on RD-V3 ([222c87e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/222c87e75c747e4fb100a08910c5f870c473449d))
+        - add LCA multichip data for RD-V3-Cfg2 ([d0b93a0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d0b93a0dd04c755264355633cc77c8c1ea78ada4))
+        - correctly define plat_mboot_measure_key() ([fa0eb3c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fa0eb3cf5bab4cf86671a0ec3c7b0ceab33b7666))
+        - correctly handle FP regs context saving ([ac05182](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ac05182df0b7c46c70faf92058063f8498a8624a))
+        - fix comment for DRAM1 carveout size ([4e2369c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4e2369c707ba6ebd26810052532afa7d30cc4cc8))
+        - handle invalid build combination ([fe488c3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fe488c3796e01187fb6cffdd27a1bee1a33e0931))
+
+    - **TC**
+
+      - define status to fix SPM tests ([8d4d190](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8d4d190915af07750cfc0c05b79c4ebd4bc1df4f))
+      - eliminate unneeded MbedTLS dependency ([22220e6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/22220e69f996b68c50dcc34cd05152a0fcb0e904))
+      - enable certificate on the last secure partition ([2e36131](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2e361319ac1907009b42da657f7c55a50a9ccca0))
+      - enable Last-level cache (LLC) for tc4 ([7b41aca](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7b41acaf72dc208601c315189756fdb9f24f4abf))
+      - fix compilation error ([26a520b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/26a520b2befb310b9ee23da108854c9d9c294c11))
+      - fix SMMU streamId for tc4 gpu ([bf223c7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bf223c79377ed5d94f58acd2f354e8524ed6b1c6))
+      - map mem_protect flash region ([4bfe49e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4bfe49ec4eff17ded7f7b13fe4ceaa7307a78f92))
+      - modify DPU configuration in dts for TC4 FPGA ([bb9b893](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bb9b89366f580d6166d0abcd4ae8b3c45943ca1c))
+      - modify ethernet configuration for TC4 FPGA ([8dec630](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8dec63032e8d173215fc5a4b6540ecbc189cbf87))
+      - modify gpio controller base addr for TC4 FPGA ([5de9d79](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5de9d79bc4b2febe3b55db47039ab2004d8cd4af))
+      - modify mmc configuration for TC4 FPGA ([ba1faaf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ba1faaf117158dc1f1272192f3d8131421e96458))
+      - replace vencoder with simple panel for kernel > 6.6 ([1d2d96d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1d2d96dd5cefdd8ae1872022d4b3b0d564188a29))
+      - set console baurate to 38400 for fvp as well ([5428938](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/54289385f128e5ddad8d2f1be0d63a9edf685922))
+      - set system-coherency to 0(ACE-LITE) for tc4-gpu ([cada6ca](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cada6ca36c0a59a0050abf481ffa82a1838b1fe0))
+
+    - **Automotive RD**
+
+      - **RD-1 AE**
+
+        - fix rd1-ae device tree ([f72eeb2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f72eeb2d227702817d38b44bec8ee988f30f1fb3))
+        - rename legacy MPAM build option ([7a5e580](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7a5e580957a426ba4d4db2a07449a43d04628814))
+
+  - **Intel**
+
+    - add FPGA isolation trigger when reconfiguration ([6ce576c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6ce576c63d6333261f48ecee301a11e77cc5f0d0))
+    - handle cold reset via physical reset switch ([bf3877e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bf3877e072af2b718454e9ee1ee16d769980378e))
+    - redesign F2SOC bridge enable and disable flow for Agilex5 ([42e9062](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/42e906205ecbb3e157a802a86ae98ef392a4b6eb))
+    - this patch is used to solve DDR and VAB ([458b40d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/458b40df58d60974f2f57017c8f17663e8e0973e))
+    - update debug messages to appropriate class ([a550aeb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a550aeb39460d34e5b75421639f54b215b46e616))
+    - update ssbl naming conventions ([bf2c213](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bf2c213670feb2ecc6acc316be0c0342c5a5159f))
+    - update warm reset routine and bootscratch register usage ([646a9a1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/646a9a16150066eaa3146d4e2819d589333b6454))
+    - add in support for agilex5 b0 jtag id ([8a0a006](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8a0a006af3362a114ed899f2cfe6c2ef0ec84061))
+
+  - **Marvell**
+
+    - **Armada**
+
+      - don't race on the UART_IMAGE ([3395bd1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3395bd12bcd7595b66902c0fc70ffee0a4681eea))
+
+  - **MediaTek**
+
+    - covert MTK_BL to uppercase for the build ([c710579](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c7105798eda68240093d4c2bb34fcbc09f0ea587))
+
+    - **MT8189**
+
+      - fix mt8189 platform build failure ([49d8678](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/49d8678efbae57a2445af4c535f2ebd73dfb6b48))
+
+    - **MT8196**
+
+      - add whole-archive option to prebuilt library ([8f7d9bf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8f7d9bfa0a15d3063f9475da9c5e579ea935ac68))
+      - fix wrong register offset of dptx on MT8196 ([b38f8f7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b38f8f7a3e2f4cdd323f195d2a17a6091aa75722))
+      - remove CPU_IDLE_SRAM_BASE entry from plat_mmap ([83f37d9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/83f37d998123f269e7ce901b190e016d52f9ebe3))
+      - remove EC_SUSPEND_PIN initial setting ([1185526](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/11855267b55fb70522ed2ac015a6a0002641412e))
+      - remove SPM support for ES chip ([ee2e99c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ee2e99c3e3fc8443bf48b05fe3776e3f2aaa6b23))
+
+  - **NXP**
+
+    - imx_trdc.h header guard ([2e9198d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2e9198d0e0cbe9546348dd0a71ff6c3d2061d4eb))
+
+    - **i.MX**
+
+      - **i.MX 8M**
+
+        - fix imx8mq build break ([1b65be5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1b65be5943fc4f6a0382d03a4ed7393b383e56a4))
+
+        - **i.MX 8M Plus**
+
+          - apply ERRATA_A53_1530924 erratum ([e6d39da](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e6d39da0473b84488dd012091c8deede0adc7d87))
+
+        - **i.MX 8Q**
+
+          - fix imx8mq build break due to hab ([3a36f70](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3a36f70ba02e88ed20083c1278a739c6c870aae0))
+
+      - **i.MX 9**
+
+        - **i.MX93**
+
+          - trdc: restrict BLK_CTRL_S_AONMIX to secure world ([c6bf928](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c6bf92894c6c7096e380fe60c0e57b3db87ea0c7))
+
+    - **S32G274A**
+
+      - reduce the uSDHC clock to 200MHz ([9c640e0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9c640e09a86bdcc4cf77233c71b2ac0d36b7f9d1))
+
+  - **QEMU**
+
+    - fix register convention in BL31 for qemu ([7ad6775](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7ad6775bde8fb719ab94ab7d47736fd2dd66cddc))
+    - fix RMM manifest checksum calculation ([d08dca4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d08dca4263e5286b7f9b36612dae5767aac74a63))
+    - ignore TPM error ([ddb5e2f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ddb5e2fd12a759270dd3566d086bbb91076ae0ae))
+    - statically allocate bitlocks array ([a32a77f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a32a77f9c7567141556a823c0b9d4d5488c95722))
+
+    - **SBSA**
+
+      - fix compilation error when accessing DT functions ([33ac6f9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/33ac6f99abcbb2d3b8303af5194390cafb4e6853))
+
+  - **QTI**
+
+    - **MSM8916**
+
+      - update tsp_early_platform_setup prototype ([2f02426](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2f024262e986f241fed5dbadbb7f0ab68165bb74))
+
+  - **Raspberry Pi**
+
+    - **Raspberry Pi 3**
+
+      - expose BL1_RW to BL2 map for mboot ([9acaade](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9acaaded3ca9b6966efb72e3a989f8ee753b3a44))
+      - use correct name for include guards ([5c0cbb2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5c0cbb2faaa0ddfbe7c36d037918fbda13a661f6))
+
+  - **Renesas**
+
+    - **R-Car**
+
+      - use platform_def ([99fe5c2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/99fe5c2fd531298457214a61dafcfae15053e900))
+
+  - **Rockchip**
+
+    - pmu: Do not mark already defined functions as weak ([7f25d3c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7f25d3cc782337ce2fd445d39cbe295090beb5c9))
+
+    - **PX30**
+
+      - remove unused function ([ce66647](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ce666476812099bc5e27dcc1d336e712e0cd78fb))
+
+    - **RK3288**
+
+      - remove unused function ([6e38cc9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6e38cc97df86ac1c45aacc9ce301f6df1fc72056))
+
+    - **RK3399**
+
+      - dram: Fix build with gcc 11 ([f86c230](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f86c230ab02ce94d54866c072e8c118095a8783e))
+      - fix unquoted .incbin for clang ([ddd70f1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ddd70f199bd0b09a229aa624497b86dbff5b8db5))
+      - m0: Makefile: fix outside array bounds warning ([5049f91](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5049f910aec254b9656dafe6c4cf7dd3d8b91d5c))
+      - mark INCBIN-generated sections as SHF_ALLOC ([279cad8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/279cad8ed38c186aebce3502f9f1ebc52e22b281))
+
+    - **RK3588**
+
+      - pmu: fix assembly symbol redefinition ([f879388](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f879388831795c948c7d5954d5ea6b1c224e6e08))
+
+  - **Socionext**
+
+    - update tsp_early_platform_setup prototype ([c45dbe7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c45dbe7e5d28da67f831159830cdc835095b142b))
+
+  - **ST**
+
+    - **STM32MP2**
+
+      - correct early/crash console init ([23647bd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/23647bd52c805594050c5cd0e387389760778492))
+
+  - **Texas Instruments**
+
+    - fix UNUSED_VALUE in AM62L PSCI Driver ([32302b4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/32302b44abc3a725b4197cec8f1411d8320542d9))
+
+  - **Xilinx**
+
+    - avoid unexpected variable update ([b3d25dc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b3d25dca86ad438423e2554b0c72ea8e429c30fb))
+    - dcc console tests failing ([e14ae4b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e14ae4b30175d6c9877fd33497d43a8895f5b3d9))
+    - modify function to have single return ([906d589](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/906d58927760c70112fd8e70a7e67f2a4989e9ed))
+    - remove unused write_icc_asgi1r_el1() ([1c12cd1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1c12cd10fc4662141777f5b0fc0fbac2d00f50c3))
+    - resolve misra rule 10.3 violations ([72eb16b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/72eb16b7f8d679e9da960185904e6e608d5c5a5c))
+    - resolve misra rule 10.4 violations ([bdba3c8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bdba3c84baa5c595e504ef2902832d04102a223a))
+    - resolve misra rule 11.3 violations ([c35fe29](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c35fe2946b6e2b1e4e3fcf845289bcea791eb60a))
+    - resolve misra rule 14.4 violation ([a5d5cb3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a5d5cb3cfc83928bee0a00dd987f2731e1b8ec56))
+    - resolve misra rule 15.7 violations ([fd44cc7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fd44cc7e9b660a8baae2e8a0d3a2b3efde2e2c7e))
+    - resolve misra rule 2.2 violations ([e5adcfc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e5adcfcdd143660bb9c3d56a44a42621066fca59))
+    - resolve misra rule 2.3 violations ([09abae0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/09abae060d5c65ec8cb7a42a5ac75fa30eb1aabc))
+    - resolve misra rule 2.7 violations ([d87b0ce](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d87b0ce30189cf692a6a6e21393bde0ac5029780))
+    - resolve misra rule 8.3 violations ([3df32f8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3df32f852400be6d4c1f3199c89d9f36169ede71))
+    - resolve misra rule 8.4 violations ([4b4080d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4b4080d78637fd0f071e0d6860114eb9ea16dea5))
+    - resolve misra rule 8.6 violations ([eec03e9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/eec03e947b3855c0a19bb64d39b4627e253a22b5))
+    - runtime console to handle dt failure ([0791be8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0791be881388c32c13b5ed9e79dc640aeefaaab4))
+    - typecast expression to match data type ([50ab135](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/50ab13577fd533ab99c874772e6630929506229c))
+    - typecast expressions to match data type ([83bcef3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/83bcef3f509d77582e4534f75ca2b4fd3ea4ffee))
+    - typecast operands to match data type ([3a1a2da](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3a1a2dae10ef3058e3973715fc4406544ff4aad7))
+    - typecast operands to match data type ([7d15b94](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7d15b94ba3d7160c79c5c3229015f7e9373490ff))
+    - update tsp_early_platform_setup prototype ([470dd8b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/470dd8b49dab7211ca425f16fd94e8c18bbd37bf))
+
+    - **Versal**
+
+      - add unsigned suffix to match data type ([4b23240](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4b2324042a292d6e1bd877daaf91c05dc888a926))
+      - handle invalid entry point in cpu hotplug scenario ([435bc14](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/435bc14a94008ab811ebac2735875a99ea6e464c))
+      - modify function to have single return ([890781d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/890781d10ce362150359c00b06c8b7e9e1ee34d2))
+      - typecast expressions to match data type ([b802b27](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b802b2784c8bcaae56d450ab55ee305880293c85))
+      - typecast operands to match data type ([8e4d5c6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8e4d5c6db0e462ea33db2eaee4229583ace6cd6f))
+      - typecast operands to match data type ([9b89de5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9b89de5fc4aa22e0cdc8e9f216135041549bbdff))
+
+    - **Versal NET**
+
+      - add missing curly braces ([9334fdf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9334fdf9718fed0f98a990f2f7f43cc40426b6dc))
+      - add unsigned suffix to match data type ([baeeadd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/baeeaddff4840028d627f21af64e6397da88a058))
+      - enable PSCI reset2 interface ([5f22f57](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5f22f573adbbcb30b7e1793fdcc1ba7c88eceff0))
+      - handle invalid entry point in cpu hotplug scenario ([e5e417d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e5e417ddecfaedd875adf47de4ad1396dd514ab9))
+      - modify function to have single return ([5003a33](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5003a332b8e40ff93333b70a4365c1e13e8b1d10))
+      - remove_redundant_lock_defs ([19799fd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/19799fd8fb318682a8169d5e4fc32e41ae50c0b1))
+      - typecast expressions to match data type ([3cbe0ae](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3cbe0ae5b8b2f79fe87c73d160ef7e33603ae604))
+      - typecast operands to match data type ([d51c8e4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d51c8e4c654a27e7487b7d15a64cec6f5eeab4e5))
+      - typecast operands to match data type ([3dc93e5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3dc93e5139b262ff099c450d82433180b802a484))
+
+    - **ZynqMP**
+
+      - add missing curly braces ([e4a0c44](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e4a0c44f690d0658310914bcb5ae2355808a17b7))
+      - align essential type categories ([1877bf2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1877bf2ce18092259cace97cec41ea32a97a8ed7))
+      - fix length of clock name ([f535068](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f535068c84c00da3d4af40d6b571d9df39e07264))
+      - fix syscnt frequency for QEMU ([55ae162](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/55ae162fd521cbe2ba500570692785159777a0ff))
+      - handle invalid entry point in cpu hotplug scenario ([df44616](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/df44616a12096c16dd497646fc06684bdc818760))
+      - modify function to have single return ([3f6d479](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3f6d47945a4bd94eae2d6ad17f50b59cda551c10))
+      - typecast expression to match data type ([e2cc129](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e2cc129bcc58234dcb4607fe9264c1bdf4b282ea))
+      - typecast expressions to match data type ([895e802](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/895e8029aa1f88da164966504be8fc8120c9f7a5))
+      - typecast operands to match data type ([6ae9562](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6ae9562473812cce8d97f3a3f2a8ae7aafa75201))
+      - typecast operands to match data type ([2863b0c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2863b0c46633d28a920ef14c68ee4a6e4842ab0b))
+
+  - **AMD**
+
+    - update transfer list args for OP-TEE ([573ec22](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/573ec2287eb616d1629b2c32fb28e894d852a78b))
+
+    - **Versal Gen 2**
+
+      - add missing curly braces ([9f51da5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9f51da5e2e6fcd81b22fb1c7f5cd5712bdc6cb3b))
+      - align QEMU APU GT frequency with silicon ([f7a380e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f7a380e23ce8c7e4835367ee71af0bdeb505baa7))
+      - enable system reset ([058edb8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/058edb8fcd7d32346bda0e43389cd0903074034a))
+      - modify function to have single return ([fb2fdcd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fb2fdcd9536874aaff0c14f9c466214e717b0e91))
+      - pass tl address to bl32 ([1fb3446](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1fb3446ed230c1011c982eb0bf62214f8abd38b2))
+      - rename console build arg to generic ([2333ab4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2333ab4cd214150ac099ba0894bb6d1c3963d945))
+      - typecast expressions to match data type ([fbc415d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fbc415d2046ca6e940323a88252fd40a68bebec4))
+      - typecast operands to match data type ([07be78d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/07be78d500aaabf2401bb4b31eb3b40b677fa110))
+      - update DDR address map ([66569a7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/66569a76880ceb6c02fbcfe993584c67336df353))
+      - update transfer list as optional ([5cb9125](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5cb9125e9654e374dff4f322c3bbaef59511fcda))
+
+- **Bootloader Images**
+
+  - **BL1**
+
+    - prevent null pointer dereference ([2d3b44e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2d3b44e3073e8d6ec49dde45ec353d6f41290917))
+
+  - **BL31**
+
+    - add const qualifier ([e358089](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e358089d8382e4239a4b606b0e97cf5475da4976))
+    - add missing curly braces ([88edd9c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/88edd9c6a09cc867ea377c7ad968e6a17595acf5))
+
+  - **BL32**
+
+    - **TSP**
+
+      - use %u to display unsigned values ([3b06438](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3b06438dd1e038a7453d3b812ca6ef2da54f6ba8))
+
+- **Services**
+
+  - avoid altering function parameters ([1a0f565](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1a0f565b6240392ccb6982a15098ec288df7ea94))
+
+  - **RME**
+
+    - do not trap access to MPAM system registers in Realm mode ([d048af0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d048af0da1022a844e153093395087c724f12e40))
+    - map DEVICE0_BASE as EL3_PAS ([b577248](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b57724806143e36ae17be7e33e5792863c5c026c))
+    - remove ENABLE_PIE restriction ([e126ed1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e126ed1ae7d498110b349be5f0bbd40e3bdc32ba))
+
+    - **RMM**
+
+      - add support for BRBCR_EL2 register for feat_brbe ([41ae047](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/41ae04735284f7c97a3993dc6d2d45de3954c2b7))
+
+  - **SPM**
+
+    - **EL3 SPMC**
+
+      - fix FF-A v1.2 version check ([6feaad6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6feaad6c6e36f3bd92dd7181f08b2abc87f54240))
+      - move ERROR line inside conditional ([bbf28dc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bbf28dc37d50ea8a5bf40ab3fcc2f529cbb1e024))
+
+    - **SPMD**
+
+      - check pwr mgmt status for SPMC framework response ([8723eaf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8723eaf2fea9d09526fd7e6bc544b9c3103240ac))
+      - fix build failure due to redefinition ([a869e2d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a869e2dc4549e86465d485d9ec5d1c18d21c10be))
+      - prevent SIMD context loss ([8f60d99](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8f60d99f44f3f75108f7cf707e8d1c8f6ef33be0))
+
+    - **SPM MM**
+
+      - prevent excessive racing ([48426cf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/48426cff7250486b9a00a2e0e69d53cb5ae6e413))
+
+  - **DRTM**
+
+    - add missing DLME data regions for min size requirement ([a65fa57](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a65fa57b129713ddaa3cdff048921368f9dacc2e))
+    - adjust Event Log size in DLME ([63d2020](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/63d2020f577aadb9f600a7f1a525d427117fd11d))
+    - fix DLME data size check ([28e8f9d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/28e8f9d93329b45e8dc9bf6ee1f3d14bde9adda2))
+    - sort the address-map in ascending order ([7cf3784](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7cf37848140d3ba29b5967b46acbc5464b0b04b0))
+
+  - **TRNG**
+
+    - allow FEAT_RNG_TRAP in dynamic fashion ([bc30945](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bc30945bb660c5be04d82bfa95f5b9caaffba3ef))
+
+  - **ERRATA ABI**
+
+    - add support for handling split workarounds ([bbff267](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bbff267b6f2777483a37781850dd1be01c16b937))
+
+- **Libraries**
+
+  - **CPU Support**
+
+    - add missing add_erratum_entry ([a74b009](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a74b0094163b0efc5525131c5b807aaea2591e9e))
+    - avoid SME related loss of context on powerdown ([45c7328](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/45c7328c0b94d043745b4a44c2e14e1a77f5c347))
+    - clear CPUPWRCTLR_EL1.CORE_PWRDN_EN_BIT on reset ([c9f352c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c9f352c362a8d114a055bb9206c5b6391ec3b96a))
+    - declare reset errata correctly ([5cba510](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5cba510ee31c520c6bd3254a4fd791d411d02152))
+    - drop esb from the Neoverse N1 ([e75eea7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e75eea749a59ba67c3eb3dfba41bd8d6770cc708))
+    - fix a typo in errata doc ([845213e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/845213ed0ddb08be79f621990db1314f4988d2e5))
+    - fix clang compilation issue ([bdaf0d9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bdaf0d9ba71c1fd17f5d35f8fd2a6205136116a3))
+    - remove errata setting PF_MODE to conservative ([ac9f4b4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ac9f4b4da6f6ef695a25aa2ed525281a89d40bf9))
+    - workaround for accessing ICH_VMCR_EL2 ([7455cd1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7455cd1721ec3b8671d6a2fae879f86ecfe497fb))
+    - workaround for Cortex-A710 erratum 3701772 ([463b5b4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/463b5b4a46552887c4fb70536d20f315f889add1))
+    - workaround for Cortex-A715 erratum 2804830 ([fcf2ab7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fcf2ab71ac00122bd382973f6e9f08e30b7eca80))
+    - workaround for Cortex-A715 erratum 3699560 ([26437af](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/26437afde1e7c16a5a05b8c7e0bb062efe63c3cf))
+    - workaround for Cortex-A720 erratum 3699561 ([050c4a3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/050c4a38a335c721c2f6ce38c33f1aa6aa328800))
+    - workaround for Cortex-A720-AE erratum 3699562 ([af5ae9a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/af5ae9a73f67dc8c9ed493846d031b052b0f22a0))
+    - workaround for Cortex-A725 erratum 3699564 ([d732300](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d732300b86238ac7166bc9bebd667a24dc3ed062))
+    - workaround for Cortex-X2 erratum 3701772 ([ae6c7c9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ae6c7c97d4e0f491854b34628e0fa1038668f8e4))
+    - workaround for Cortex-X3 erratum 3701769 ([77feb74](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/77feb745e42296c553c33bcaea5be3304168eff3))
+    - workaround for Cortex-X4 erratum 2923985 ([cc46166](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cc46166144b9a3746807f1d137ff784da3013e26))
+    - workaround for Cortex-X4 erratum 2957258 ([09c1edb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/09c1edb84b9d2e91ce425b4300042751b3899434))
+    - workaround for Cortex-X4 erratum 3701758 ([38401c5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/38401c5388b5c3127745b758b3dc939d27041d7d))
+    - workaround for Cortex-X925 erratum 2963999 ([29bda25](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/29bda258d5655d2ac24dda0f73e6b0ec93c3037e))
+    - workaround for Cortex-X925 erratum 3701747 ([511148e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/511148ef5077dfb8f6bc7b9655e4ac19e16c4af0))
+    - workaround for CVE-2024-5660 for Cortex-A710 ([0d7b503](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0d7b503f8a11237fa129ae7baa2d979d64b9ab68))
+    - workaround for CVE-2024-5660 for Cortex-A77 ([aed3e8b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/aed3e8b59a034ddcd073f2295cf0ae70a313ccf5))
+    - workaround for CVE-2024-5660 for Cortex-A78 ([c818bf1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c818bf1d60c01e1a8953bf0051987dea4db7c4bf))
+    - workaround for CVE-2024-5660 for Cortex-A78_AE ([902dc0e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/902dc0e01ffc5f215eabde8e0428ce462db18a73))
+    - workaround for CVE-2024-5660 for Cortex-A78C ([46a4cad](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/46a4cadb9d63f4265756d82c9e252d7760c43ae8))
+    - workaround for CVE-2024-5660 for Cortex-X1 ([26293a7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/26293a746319e7073dd3699be0afcd2277ad1999))
+    - workaround for CVE-2024-5660 for Cortex-X2 ([5b58142](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5b58142c460b9d28740c610d51023a444583a10e))
+    - workaround for CVE-2024-5660 for Cortex-X3 ([b0d441b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b0d441bdadae3b38e3a670e03341603785b39f3c))
+    - workaround for CVE-2024-5660 for Cortex-X4 ([af65cbb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/af65cbb9549765917cf79ab0a819fe58773882ab))
+    - workaround for CVE-2024-5660 for Cortex-X925 ([ebc090f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ebc090fbf47a25a1ef84657d03198fc3a29d28e3))
+    - workaround for CVE-2024-5660 for Neoverse-N2 ([26e0ff9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/26e0ff9d5e99b2ea0eedfd202401655ee404e52f))
+    - workaround for CVE-2024-5660 for Neoverse-V1 ([85709f6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/85709f66194cef32377a32f8e153316648ebb4a9))
+    - workaround for CVE-2024-5660 for Neoverse-V2 ([878464f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/878464f02a043207f29282f05109012152df569b))
+    - workaround for CVE-2024-5660 for Neoverse-V3 ([ad3da01](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ad3da019904302d9ecfc2cf50dfdd6d672427b5d))
+    - workaround for Neoverse-N2 erratum 3701773 ([adea6e5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/adea6e52a782eeabd9027e3ca9a9847a13453cfa))
+    - workaround for Neoverse-N3 erratum 3699563 ([fded839](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fded839285bdbdb72d492a573274abe22edc9311))
+    - workaround for Neoverse-V3 erratum 2970647 ([5f32fd2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5f32fd2145020b0007b3f12ae6a95b734ff8e6a2))
+    - workaround for Neoverse-V3 erratum 3701767 ([e25fc9d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e25fc9df25092be31e7f7a9cc740e8df661a35c1))
+    - workaround for Cortex-A510 erratum 2971420 ([f2bd352](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f2bd35282066f512c26d859aa086cff13955d76b))
+
+  - **EL3 Runtime**
+
+    - add const qualifier ([54c9c68](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/54c9c68a49bc7b3aaa29207f798b1973e3cdb542))
+    - add missing curly braces ([858dc35](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/858dc35cfde12ddf6250ed393298fa85d01b77d5))
+    - for nested serrors, restore x30 to lower EL address ([0bc3115](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0bc3115f6e7b857344c6ac034d74b0fe81d216ed))
+    - replace CTX_ESR_EL3 with CTX_DOUBLE_FAULT_ESR ([c722003](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c72200357aed49fd51dc21e45d4396f5402df811))
+    - make sure LTO doesn't garbage collect the handlers ([f8d2a0e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f8d2a0e5caa1b57edf9f7a8e09f9c438a7f3b4be))
+
+    - **Context Management**
+
+      - change back owning security state when a feature is disabled ([13f4a25](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/13f4a25251cc6ce0230e999f39a4668cff25dcd0))
+      - don't access a field that doesn't exist ([600717f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/600717fe5909e02a9ec9ee08bcb921a66e653d58))
+      - fix context management SYSREG128 write macros ([6595f4c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6595f4cb393090992733eb5e73928424b1e9395a))
+
+    - **RAS**
+
+      - fix status synchronous error type fields ([9c17687](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9c17687aabc9e64a26575d5662ef273185d9d275))
+      - fix typo in uncorrectable error type UEO ([e5cd3e8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e5cd3e81d11cb7f9439e5077cf9063e30fc8c2ae))
+
+    - **SIMD**
+
+      - fix base register in fpregs_context_* ([09ada2f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/09ada2f8d63fabd1bb01494c2466f647441107b1))
+
+  - **PSCI**
+
+    - add const qualifier ([7b97084](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7b970841ad1c9925e72c170734ca30016813743d))
+    - add missing curly braces ([c7b0a28](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c7b0a28d32ba78a1bec8fe1f9edbcdc215bf7b1a))
+    - avoid altering function parameters ([e64cdee](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e64cdee4dad610e8f4efb873e133a5fffdea397c))
+    - check if a core is the last one in a requested power level ([71d4e03](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/71d4e03444f689210803323b437ee15d537fc6ea))
+    - initialise variables ([382ba74](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/382ba743a81c9b61d2ab794a22e37af0ac6128fe))
+    - modify variable conflicting with external function ([0839cfc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0839cfc980998d24740e41b44164de39b70079a1))
+
+  - **ROMlib**
+
+    - romlib build without MbedTLS ([e4a070e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e4a070e3d6dd0af0e74184333b9238e70c9a7075))
+
+  - **SMCCC**
+
+    - properly set RAS feature bit ([04b80c1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/04b80c187db3e8d5f0aec6987f1cb2fca2df952d))
+    - register PMUv3p5 and PMUv3p7 bits with the FEATURE_AVAILABILITY call ([2bec665](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2bec665f464b1c211eac594b333656b1dfa4b3da))
+
+  - **Translation Tables**
+
+    - zeromem to clear all tables ([aaacde4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/aaacde46826df1dd4a119b2a31ff626adbce5653))
+    - remove xlat_mpu ([23302d4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/23302d4a53700a7e6b80a897626bee0d67fad028))
+
+  - **C Standard Library**
+
+    - add const qualifier ([b71d082](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b71d0827aeef53d0ad561da212a7deb102f48c45))
+    - explicitly check operators precedence ([277d7dd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/277d7dd6c192f350bc80ccbb65c36562e59f8e07))
+    - make sure __init functions are garbage collected ([53644fa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/53644fa8221b5c7b726beeda78b253f39abe479b))
+    - remove __Nonnull type specifier ([7ce483e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7ce483e17cf14ee285a348d0f0081c89793d010b))
+    - typecast expressions to match data type ([dd0d433](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dd0d433197d470e1f50ab28f128ff336e021799f))
+    - typecast operands to match data type ([26cc285](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/26cc2854609978fcd6b0450e750b3b319b2468fa))
+
+  - **Locks**
+
+    - add missing curly braces ([bd7ad5e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bd7ad5e684aafd12c9c5873e4776c4a14e5e5dc0))
+
+  - **PSA**
+
+    - guard Crypto APIs with CRYPTO_SUPPORT ([8a41106](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8a41106c83961029c2d251f390c091d398c100a6))
+    - increase psa-mbedtls heap size for rsa ([52d2934](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/52d293456097beef6a3346b244d4e84f78ef2615))
+
+  - **Firmware Handoff**
+
+    - correct 8-bit modulo csum calculation ([5ca0241](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5ca0241c7ac7fc07188281058e052044e8f9ec36))
+    - fix message formatting of hex values ([24e1ae2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/24e1ae2f0ed3e2c2be680aad6e88313661bf57ee))
+    - fix register convention in opteed ([c0688c5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c0688c55bb8b924f1b660ffca1b33bd65cab9990))
+    - remove XFERLIST_TB_FW_CONFIG ([18be2db](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/18be2dbe001162b424e52072dee74c9b7613a4f2))
+
+- **Drivers**
+
+  - **Console**
+
+    - add missing curly braces ([9ded5e8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9ded5e8d8be4a5f1f3219742c3790c13156378d8))
+    - typecast expressions to match data type ([97eefd9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/97eefd9989aeb2ce2093e873ceab535df9559a59))
+
+  - **Delay Timer**
+
+    - create unique variable name ([472cccb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/472cccb5f94e26ad72b8a52ab2614203230be20f))
+
+  - **MMC**
+
+    - fix the length of the ocr defines ([e02d365](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e02d365ad9c4102cadb2d8886e3aed327a7512c9))
+    - fix the length of the response type ([7b4b3f2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7b4b3f243ad3ef099de9aa09a526e7ecccc09c04))
+
+  - **GUID Partition Tables Support**
+
+    - fix MBR header load ([2fac89d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2fac89d1267e81e1f4bf0eacf9ea8dbacf80aacb))
+    - initialise the mbr_entry variable ([ec48d52](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ec48d52e7890d8e27d1b4419a6a8952d7db777cc))
+
+  - **Arm**
+
+    - add missing curly braces ([03c6bb0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/03c6bb0e3822e05da002c69086357c81f853d6f5))
+    - align essential type categories ([bec4a2c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bec4a2c9c3919c4a3012c7a10f4fa75a861f8150))
+    - typecast expression to match data type ([0f76d0d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0f76d0d57ec700b835e1715200f4520fde1c11c4))
+    - typecast expressions to match data type ([edecc70](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/edecc70331ec5e7583972f66f0e8dc6cf039c686))
+
+    - **GIC**
+
+      - quote the correct flag on error ([df21ca0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/df21ca08e65b2aeb575e54b155fce1e32908eae6))
+
+      - **GICv3**
+
+        - do not assume redistributors are powered down ([57f2d00](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/57f2d009fb198181c53f768233f76087ab918ce1))
+
+    - **SMMU**
+
+      - set root port CR0 GPCEN before ACCESSEN ([8cc9724](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8cc972421faf02cfdd4fea1a21fabe6e9d96e2a3))
+
+  - **Renesas**
+
+    - **R-Car3**
+
+      - disable A/B loader support by default ([1a57115](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1a5711519a8e685d3db43620623f0f616317cfe9))
+
+  - **ST**
+
+    - **ST PMIC**
+
+      - remove deadcode from STPMIC2 driver ([bdbbf48](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bdbbf48f4db6fa64079efcd284955a3bf629b705))
+
+- **Miscellaneous**
+
+  - **AArch32**
+
+    - avoid using r12 to store boot params ([af61b50](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/af61b50c1077b6d936c8ed741c1d0b8e43eb2b19))
+
+  - **FDTs**
+
+    - **ST**
+
+      - **STM32MP1**
+
+        - re-enable RTC clock ([33573ea](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/33573ea6842198cfdb5b3fdd320db9e2045855e9))
+
+        - **STM32MP15**
+
+          - update clocks config for prtt1x board family ([5aeb003](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5aeb0031558b4a9ccff9f097ae651d42d7b850a2))
+
+      - **STM32MP2**
+
+        - fix SDMMC slew rate ([575d6dd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/575d6dd7af3644f7c3c9cb34e3fb57d951695023))
+
+  - **Security**
+
+    - add CVE-2024-7881 mitigation to Cortex-X3 ([b0521a1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b0521a164a8d61c95968e728df9af52be1a48553))
+    - add CVE-2024-7881 mitigation to Cortex-X4 ([6ce6aca](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6ce6acac911f11979a6cd2ee9cc9041f189c6ec7))
+    - add CVE-2024-7881 mitigation to Cortex-X925 ([520c220](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/520c2207b96d31adf508edc068bb97cd01d98da4))
+    - add CVE-2024-7881 mitigation to Neoverse-V2 ([56bb1d1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/56bb1d172ccee56e984559de69e8ebd8683d491b))
+    - add CVE-2024-7881 mitigation to Neoverse-V3 ([037a15f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/037a15f5c72e856b8739a2159bd0fe1fe69e1d5b))
+    - add support in cpu_ops for CVE-2024-7881 ([4caef42](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4caef42a94b4efe97b09764a7257f701ab7ff3b8))
+    - apply SMCCC_ARCH_WORKAROUND_4 to affected cpus ([8ae6b1a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8ae6b1ad6c9c57b09b6d4e7ae3cbdf3aed6455b1))
+    - enable WORKAROUND_CVE_2024_7881 build option ([2372179](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2372179484741aa81d5451b20748520677205c71))
+
+  - **SDEI**
+
+    - return SDEI_EINVAL if signaling state is incorrect ([b142ede](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b142ede74ceb5fc0b2908d0e7e8e2b2b27b6b1f6))
+
+  - **TBBR**
+
+    - remove tbbr_cot_bl1_r64.c ([a2328f2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a2328f2eac83aa9bc10f89d9141ab9bd66338400))
+
+- **Documentation**
+
+  - fix the indent and the build command for MT8188 ([cef56a5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cef56a5c6b42b4518af8c48f48a8790542ce3930))
+  - put INIT_UNUSED_NS_EL2 docs back ([4557c0c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4557c0c001ba296328e6292a5a2c973581fbeb47))
+  - update the instrumentation procedure ([9b65ffe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9b65ffefd673fb2781b808024d13039151c17668))
+
+- **Build System**
+
+  - do not force PLAT in plat_helpers.mk ([422b181](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/422b181faf2fd740e08cf881880015ea47b0cb67))
+  - enable fp during fp save/restore ([5141de1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5141de14432aba7a775c0dd19ecba766d224ec39))
+  - handle invalid spd build options ([a0effb9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a0effb91897ff41871cbe2366a54c6e2339246d8))
+  - include platform mk earlier ([696ed16](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/696ed16877a121d07a766af5bb4f8d73a8ac01ae))
+  - run sp_mk_gen.py with poetry ([dd81623](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dd816235771e19df1fd04ef2c6f1c6d11e429fd5))
+  - update clang target for aarch64 ([af8947f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/af8947fe17d3a29a47573ab0537d121d3653b53e))
+
+- **Tools**
+
+  - change data type to size_t for doimage ([fbf6555](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fbf6555790ad6de635ebf9e5581c840496166306))
+
+  - **NXP Tools**
+
+    - fix create_pbl buildroot build ([634c7d8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/634c7d8172b7965cf4f5d7d6470a25956ac06ab4))
+    - fix2 create_pbl buildroot build ([bfe7f80](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bfe7f8018947a960c287f6d8f5ac1efece7261b4))
+
+  - **Certificate Creation Tool**
+
+    - add default keysize to Brainpool ECDSA ([0da16fe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0da16fe32f41387f4ad32e96a939c67a3dc8e611))
+    - load openSSL configuration before PKCS11 operations ([785c2c3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/785c2c3e8671aa69269bccd3ee968bebd3777a9f))
+
+  - **Firmware Encryption Tool**
+
+    - put build_msg under LOG_LEVEL flag ([7640df6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7640df6f1ef392d664d16aa4d49c67a24421adce))
+
+  - **Renesas Tools**
+
+    - **R-Car Layout Tool**
+
+      - fix tool build ([72f4b70](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/72f4b70e8e8e656d88bda77605f73076474f5a55))
+
+  - **Transfer List Compiler**
+
+    - add void entries to align data ([03c2660](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/03c2660f7556957262c41032064716414572833c))
+    - pass the flags from client interface ([537a25e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/537a25ef7ff6fc95221c70c9543404049143353d))
+    - relax entry addition from YAML files ([f0e15dd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f0e15ddca303322764e17524396cb2da2c1c5ccc))
+
+- **Dependencies**
+
+  - remove deprecated husky commands ([b47dddd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b47dddd061e92054c3b2096fc8aa9688bfef68d6))
+
 ## [2.12.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.11.0..refs/tags/v2.12.0) (2024-11-19)
 
 The threat model for context management and the asymmetric CPU extension support
@@ -10792,7 +11989,7 @@
 
 ______________________________________________________________________
 
-*Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.*
 
 [mbed tls releases]: https://tls.mbed.org/tech-updates/releases
 [pr#1002]: https://github.com/ARM-software/arm-trusted-firmware/pull/1002#issuecomment-312650193

diff --git a/docs/components/ven-el3-service.rst b/docs/components/ven-el3-service.rst
index 13449ba..8be1b39 100644
--- a/docs/components/ven-el3-service.rst
+++ b/docs/components/ven-el3-service.rst

@@ -32,9 +32,13 @@
 +-----------------------------------+ Measurement Framework | | 2 - 15 are reserved for future expansion. |
 | 0xC7000020 - 0xC700002F (SMC64)   | (PMF)                 |                                             |
 +-----------------------------------+-----------------------+---------------------------------------------+
-| 0x87000030 - 0x8700FFFF (SMC32)   | Reserved              | | reserved for future expansion             |
+| 0x87000030 - 0x8700003F (SMC32)   | ACS (Architecture     | | 0 in use.                                 |
++-----------------------------------+ Compliance Suite) SMC | | 1 - 15 are reserved for future expansion. |
+| 0xC7000030 - 0xC700003F (SMC64)   | handler               |                                             |
++-----------------------------------+-----------------------+---------------------------------------------+
+| 0x87000040 - 0x8700FFFF (SMC32)   | Reserved              | | reserved for future expansion             |
 +-----------------------------------+                       |                                             |
-| 0xC7000030 - 0xC700FFFF (SMC64)   |                       |                                             |
+| 0xC7000040 - 0xC700FFFF (SMC64)   |                       |                                             |
 +-----------------------------------+-----------------------+---------------------------------------------+
 
 Source definitions for vendor-specific EL3 Monitor Service Calls used by TF-A are located in
@@ -45,6 +49,8 @@
 +============================+============================+================================+
 |                          1 |                          0 | Added Debugfs and PMF services.|
 +----------------------------+----------------------------+--------------------------------+
+|                          1 |                          1 | Added ACS SMC handler services.|
++----------------------------+----------------------------+--------------------------------+
 
 *Table 1: Showing different versions of Vendor-specific service and changes done with each version*
 
@@ -71,8 +77,16 @@
 The optional DebugFS interface is accessed through Vendor specific EL3 service. Refer
 to :ref:`DebugFS interface` documentation for further details and usage.
 
+Architecture Compliance Suite (ACS) SMC handler
+-----------------------------------------------
+
+The Architecture Compliance Suite (ACS) SMC handler allows callers to branch
+to their ACS EL3 code based on their respective use-cases.
+For more details on System ACS, `System ACS`_.
+
 --------------
 
-*Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.*
 
+.. _System ACS: https://developer.arm.com/Architectures/Architectural%20Compliance%20Suite
 .. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest

diff --git a/docs/conf.py b/docs/conf.py
index 3a7264f..6e08030 100644
--- a/docs/conf.py
+++ b/docs/conf.py

@@ -1,6 +1,6 @@
 # -*- coding: utf-8 -*-
 #
-# Copyright (c) 2019-2024, Arm Limited. All rights reserved.
+# Copyright (c) 2019-2025, Arm Limited. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -14,8 +14,8 @@
 
 project = "Trusted Firmware-A"
 author = "Trusted Firmware-A contributors"
-version = "2.12.0"
-release = "2.12.0"
+version = "2.13.0"
+release = "2.13.0"
 
 # -- General configuration ---------------------------------------------------
 

diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 117372f..e11f8c0 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst

@@ -573,6 +573,18 @@
 
 For Cortex-A710, the following errata build flags are defined :
 
+-  ``ERRATA_A710_1901946``: This applies errata 1901946 workaround to
+   Cortex-A710 CPU. This needs to be enabled only for revision r1p0. It has
+   been fixed in r2p0.
+
+-  ``ERRATA_A710_1916945``: This applies errata 1916945 workaround to
+   Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0.
+   It has been fixed in r2p0.
+
+-  ``ERRATA_A710_1917258``: This applies errata 1917258 workaround to
+   Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0.
+   It has been fixed in r2p0.
+
 -  ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to
    Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
    r2p0 of the CPU. It is still open.
@@ -1049,6 +1061,12 @@
    please note that this workaround results in increased DSU power consumption
    on idle.
 
+-  ``ERRATA_DSU_2900952``: This applies errata 2900952 workaround for the
+   affected DSU-120 configurations. This erratum applies to some r2p0
+   implementations and is fixed in r2p1. The affected r2p0 implementations
+   are determined by reading the IMP_CLUSTERREVIDR_EL1[1] register bit
+   and making sure it's clear.
+
 CPU Specific optimizations
 --------------------------
 

diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 32daf1e..e80f3d1 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst

@@ -481,6 +481,11 @@
    the values 0 to 2, to align  with the ``ENABLE_FEAT`` mechanism.
    Default value is ``0``.
 
+ - ``ENABLE_FEAT_GCIE``: Boolean value to enable support for the GICv5 CPU
+   interface (see ``USE_GIC_DRIVER`` for the IRI). GICv5 and GICv3 are mutually
+   exclusive, so the ``ENABLE_FEAT`` mechanism is currently not supported.
+   Default value is ``0``.
+
 -  ``ENABLE_FEAT_THE``: Numeric value to enable support for FEAT_THE
    (Translation Hardening Extension) at EL2 and below, setting the bit
    SCR_EL3.RCWMASKEn in EL3 to allow access to RCWMASK_EL1 and RCWSMASK_EL1
@@ -1196,11 +1201,6 @@
    cluster platforms). If this option is enabled, then warm boot path
    enables D-caches immediately after enabling MMU. This option defaults to 0.
 
--  ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory
-   tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The
-   default value of this flag is ``no``. Note this option must be enabled only
-   for ARM architecture greater than Armv8.5-A.
-
 -  ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT``
    speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``.
    The default value of this flag is ``0``.
@@ -1313,6 +1313,7 @@
 
  - ``3``: use the GICv3 driver. See the next section on how to further configure
    it. Use this option for GICv4 implementations.
+ - ``5``: use the EXPERIMENTAL GICv5 driver. Requires ``ENABLE_FEAT_GCIE=1``.
 
  For GIC driver versions other than ``1``, deciding when to save and restore GIC
  context on a power domain state transition, as well as any GIC actions outside
@@ -1509,6 +1510,11 @@
    information using HOB defined in `Platform Initialization specification`_.
    This defaults to ``0``.
 
+-  ``ENABLE_ACS_SMC``: When set to ``1``, this enables support for ACS SMC
+   handler code to handle SMC calls from the Architecture Compliance Suite. The
+   handler is intentionally empty to reserve the SMC section and allow
+   project-specific implementations in future ACS use cases.
+
 Firmware update options
 ~~~~~~~~~~~~~~~~~~~~~~~
 

diff --git a/docs/getting_started/docs-build.rst b/docs/getting_started/docs-build.rst
index 54e29dd..e11da77 100644
--- a/docs/getting_started/docs-build.rst
+++ b/docs/getting_started/docs-build.rst

@@ -42,7 +42,7 @@
 
 .. code:: shell
 
-   poetry run make doc
+   make doc
 
 Output from the build process will be placed in: ``docs/build/html``.
 
@@ -55,7 +55,7 @@
 
 .. code:: shell
 
-   poetry run make -C docs help
+   make -C docs help
 
 To build the documentation in PDF format, additionally ensure that the following
 packages are installed:
@@ -80,9 +80,10 @@
 Building rendered documentation from Poetry's virtual environment
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-The command ``poetry run`` used in the steps above executes the input command
-from inside the project's virtual environment. The easiest way to activate this
-virtual environment is with the ``poetry shell`` command.
+If Poetry is installed, the ``doc`` target wraps its build steps with ``poetry
+run``, which runs the specified command within the project's virtual
+environment. The easiest way to activate this environment manually is by using
+the ``poetry shell`` command.
 
 Running ``poetry shell`` from the directory containing this project, activates
 the same virtual environment. This creates a sub-shell through which you can
@@ -91,7 +92,7 @@
 .. code:: shell
 
     poetry shell
-    make doc
+    make -C docs html
 
 Type ``exit`` to deactivate the virtual environment and exit this new shell. For
 other use cases, please see the official `Poetry`_ documentation.
@@ -121,7 +122,7 @@
 
 --------------
 
-*Copyright (c) 2019-2024, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2025, Arm Limited. All rights reserved.*
 
 .. _Sphinx: http://www.sphinx-doc.org/en/master/
 .. _Poetry: https://python-poetry.org/docs/

diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
index da7a2c3..66c278e 100644
--- a/docs/getting_started/prerequisites.rst
+++ b/docs/getting_started/prerequisites.rst

@@ -182,6 +182,44 @@
 You can read more about Git hooks in the *githooks* page of the Git
 documentation, available `here <https://git-scm.com/docs/githooks>`_.
 
+.. _git_submodules:
+
+Cloning Additional Git Submodules
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Some dependencies in TF-A, such as Transfer List Library ``libtl``, are managed
+using Git submodules. Submodules allow external repositories to be included
+within the main project while maintaining their own commit history.
+
+Initial Clone with Submodules
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+If you're cloning the repository for the first time, run the following commands
+to initialize and fetch all submodules:
+
+.. code-block:: bash
+
+   git clone --recurse-submodules "https://git.trustedfirmware.org/TF-A/trusted-firmware-a"
+
+This ensures all submodules (including ``libtl``) are correctly checked out.
+
+Updating Submodules
+^^^^^^^^^^^^^^^^^^^
+
+If the project updates the reference to a submodule (e.g., points to a new
+commit of ``libtl``), you can update your local copy by running:
+
+.. code-block:: bash
+
+   git pull
+   git submodule update --init --recursive
+
+To fetch the latest commits from all submodules, you can use:
+
+.. code-block:: bash
+
+   git submodule update --remote
+
 --------------
 
 *Copyright (c) 2021-2025, Arm Limited. All rights reserved.*

diff --git a/docs/license.rst b/docs/license.rst
index e35b9bb..05458b9 100644
--- a/docs/license.rst
+++ b/docs/license.rst

@@ -119,6 +119,15 @@
    -  ``include/lib/hob/mmram.h``
    -  ``include/lib/hob/mpinfo.h``
 
+- Some source files originating from the `mbed OS`_ project.
+  These files are licensed under the Apache License, Version 2.0, which is a
+  permissive license compatible with BSD-3-Clause. Any contributions to this
+  code must also be made under the terms of `Apache License 2.0`_.
+  These files are:
+
+   -  ``tools/memory/memory/mapsummary.py``
+   -  ``tools/memory/memory/mapsummary_flamegraph.hmtl``
+
 .. _FreeBSD: http://www.freebsd.org
 .. _Linux MIT license: https://raw.githubusercontent.com/torvalds/linux/master/LICENSES/preferred/MIT
 .. _SCC: http://www.simple-cc.org/
@@ -126,3 +135,4 @@
 .. _Apache License 2.0: https://www.apache.org/licenses/LICENSE-2.0.txt
 .. _pydevicetree: https://pypi.org/project/pydevicetree/
 .. _edk2: https://github.com/tianocore/edk2
+.. _mbed OS: https://github.com/ARMmbed/mbed-os/

diff --git a/docs/plat/arm/fvp/fvp-build-options.rst b/docs/plat/arm/fvp/fvp-build-options.rst
index 79dc0dc..3d87494 100644
--- a/docs/plat/arm/fvp/fvp-build-options.rst
+++ b/docs/plat/arm/fvp/fvp-build-options.rst

@@ -27,6 +27,7 @@
 
    -  ``FVP_GICV2`` : The GICv2 only driver is selected
    -  ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
+   -  ``FVP_GICV5`` : The GICv5 only driver is selected
 
 -  ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled
    to DTB and packaged in FIP as the HW_CONFIG. See :ref:`Firmware Design` for
@@ -41,6 +42,9 @@
    HW_CONFIG blob instead of the DTS file. This option is useful to override
    the default HW_CONFIG selected by the build system.
 
+-  ``FVP_HW_CONFIG_ADDR`` : Specify the memory address in which to load the
+   HW_CONFIG. The default value is ``0x82000000``.
+
 -  ``FVP_GICR_REGION_PROTECTION``: Mark the redistributor pages of
    inactive/fused CPU cores as read-only. The default value of this option
    is ``0``, which means the redistributor pages of all CPU cores are marked

diff --git a/docs/plat/arm/fvp/fvp-specific-configs.rst b/docs/plat/arm/fvp/fvp-specific-configs.rst
index 0f51e4b..9608969 100644
--- a/docs/plat/arm/fvp/fvp-specific-configs.rst
+++ b/docs/plat/arm/fvp/fvp-specific-configs.rst

@@ -241,6 +241,34 @@
    (Default) For use with Foundation FVP with Base memory map configuration
    and Linux GICv3 support.
 
+GICv5 Support
+^^^^^^^^^^^^^
+
+GICv5 support in TF-A is currently **experimental** and provided only for early
+development and testing purposes. A simplified build configuration is available
+to allow booting the Linux kernel as a BL33 payload on the FVP platform.
+
+Key notes:
+
+- The support is **not production-ready** and is intended to assist with
+  upstream kernel development and validation.
+- The device tree bindings are **not finalized**; support has been validated
+  only with a **custom device tree**.
+- Use this configuration at your own discretion, understanding that the design
+  and register usage may change in future revisions.
+
+This configuration is **temporary** and may be removed once full GICv5 support
+is integrated upstream.
+
+.. code:: shell
+
+    make PLAT=fvp DEBUG=1                       \
+    CTX_INCLUDE_AARCH32_REGS=0                  \
+    FVP_USE_GIC_DRIVER=FVP_GICV5                \
+    ARM_LINUX_KERNEL_AS_BL33=1                  \
+    PRELOADED_BL33_BASE=0x84000000              \
+    FVP_HW_CONFIG_DTS=<PROVIDE_YOUR_OWN_DT>     \
+
 --------------
 
 *Copyright (c) 2019-2024, Arm Limited. All rights reserved.*

diff --git a/docs/plat/st/stm32mp2.rst b/docs/plat/st/stm32mp2.rst
index 87bb6a5..e64b989 100644
--- a/docs/plat/st/stm32mp2.rst
+++ b/docs/plat/st/stm32mp2.rst

@@ -12,6 +12,43 @@
 STM32MP2 Versions
 -----------------
 
+Here are the variants for STM32MP2:
+- STM32MP21
+- STM32MP23
+- STM32MP25
+
+STM32MP21 Versions
+~~~~~~~~~~~~~~~~~~
+The STM32MP21 series is available in 3 different lines which are pin-to-pin compatible:
+
+- STM32MP215: Single Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD - CSI - LTDC
+- STM32MP213: Single Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
+- STM32MP211: Single Cortex-A35 + Cortex-M33 - 1x Ethernet
+
+Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
+
+- A      Basic + Cortex-A35 @ 1.2GHz
+- C      Secure Boot + HW Crypto + Cortex-A35 @ 1.2GHz
+- D      Basic + Cortex-A35 @ 1.5GHz
+- F      Secure Boot + HW Crypto + Cortex-A35 @ 1.5GHz
+
+STM32MP23 Versions
+~~~~~~~~~~~~~~~~~~
+The STM32MP23 series is available in 3 different lines which are pin-to-pin compatible:
+
+- STM32MP235: Dual Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD - H264 - 3D GPU - AI / NN - LVDS / DSI
+- STM32MP233: Dual Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
+- STM32MP231: Single Cortex-A35 + Cortex-M33 - 1x Ethernet
+
+Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
+
+- A      Basic + Cortex-A35 @ 1.2GHz
+- C      Secure Boot + HW Crypto + Cortex-A35 @ 1.2GHz
+- D      Basic + Cortex-A35 @ 1.5GHz
+- F      Secure Boot + HW Crypto + Cortex-A35 @ 1.5GHz
+
+STM32MP25 Versions
+~~~~~~~~~~~~~~~~~~
 The STM32MP25 series is available in 4 different lines which are pin-to-pin compatible:
 
 - STM32MP257: Dual Cortex-A35 cores, Cortex-M33 core - 3x Ethernet (2+1 switch) - 3x CAN FD – H264 - 3D GPU – AI / NN - LVDS
@@ -70,6 +107,10 @@
 
 - | ``STM32MP_DDR_FIP_IO_STORAGE``: to store DDR firmware in FIP.
   | Default: 1
+- | ``STM32MP21``: to select STM32MP21 variant configuration.
+  | Default: 0
+- | ``STM32MP23``: to select STM32MP23 variant configuration.
+  | Default: 0
 - | ``STM32MP25``: to select STM32MP25 variant configuration.
   | Default: 1
 
@@ -154,4 +195,4 @@
 .. _STM32MP2 part number codification: https://wiki.st.com/stm32mpu/wiki/STM32MP25_microprocessor#Part_number_codification
 .. _STMicroelectronics DDR PHY github: https://github.com/STMicroelectronics/stm32-ddr-phy-binary
 
-*Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved*
+*Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved*

diff --git a/docs/plat/xilinx-versal-net.rst b/docs/plat/xilinx-versal-net.rst
index d22a46d..acb67a6 100644
--- a/docs/plat/xilinx-versal-net.rst
+++ b/docs/plat/xilinx-versal-net.rst

@@ -24,6 +24,11 @@
 make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal_net VERSAL_NET_CONSOLE=dcc bl31
 ```
 
+To build TF-A with SDEI_SUPPORT:
+```bash
+make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal_net SDEI_SUPPORT=1 bl31
+```
+
 Xilinx Versal NET platform specific build options
 -------------------------------------------------
 

diff --git a/docs/plat/xilinx-versal.rst b/docs/plat/xilinx-versal.rst
index 7185d91..a654a0b 100644
--- a/docs/plat/xilinx-versal.rst
+++ b/docs/plat/xilinx-versal.rst

@@ -59,6 +59,57 @@
     -   `6`   : SGI 6 (Default)
     -   `7`   : SGI 7
 
+Configurable Stack Size
+-----------------------
+
+The stack size in TF-A for the Versal platform is configurable.
+The custom package can define the desired stack size as per the requirement in
+the makefile as follows:
+
+.. code-block:: shell
+
+    PLATFORM_STACK_SIZE := <value>
+
+    $(eval $(call add_define,PLATFORM_STACK_SIZE))
+
+CUSTOM SIP Service Support
+--------------------------
+
+- Dedicated SMC FID ``VERSAL_SIP_SVC_CUSTOM(0x82002000)`` (32-bit) /
+  ``(0xC2002000)`` (64-bit) is used by a custom package for providing
+  CUSTOM SIP service.
+
+- By default, the platform provides a bare minimum definition for
+  ``custom_smc_handler`` in this service.
+
+- To use this service, the custom package should implement its own SMC handler
+  named ``custom_smc_handler``. Once the custom package is included in the
+  TF-A build, its definition of ``custom_smc_handler`` is enabled.
+
+Custom Package Makefile Fragment Inclusion in TF-A Build
+--------------------------------------------------------
+
+- Custom package is not directly part of the TF-A source.
+
+- ``<CUSTOM_PKG_PATH>`` is the location where the user clones a
+  custom package locally.
+
+- The custom package must implement a makefile fragment named
+  ``custom_pkg.mk`` so it can be included in the TF-A build.
+
+- ``custom_pkg.mk`` should specify all the rules to include custom package
+  specific header files, dependent libraries, and source files that are
+  required to be part of the TF-A build.
+
+- When ``<CUSTOM_PKG_PATH>`` is specified in the TF-A build command,
+  ``custom_pkg.mk`` is included from ``<CUSTOM_PKG_PATH>``.
+
+- Example TF-A build command:
+
+.. code-block:: shell
+
+    make CROSS_COMPILE=aarch64-none-elf- PLAT=versal RESET_TO_BL31=1 bl31 CUSTOM_PKG_PATH=<...>
+
 # PLM->TF-A Parameter Passing
 ------------------------------
 The PLM populates a data structure with image information for the TF-A. The TF-A

diff --git a/docs/process/commit-style.rst b/docs/process/commit-style.rst
index c287599..97b4b44 100644
--- a/docs/process/commit-style.rst
+++ b/docs/process/commit-style.rst

@@ -36,6 +36,9 @@
 
     [optional footer(s)]
 
+Note that the type, the scope and the first letter of the description (also
+called subject by the commitlint checker) must be lower case.
+
 The following example commit message demonstrates the use of the
 ``refactor`` type and the ``amu`` scope:
 
@@ -144,7 +147,7 @@
 
 --------------
 
-*Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2021-2025, Arm Limited and Contributors. All rights reserved.*
 
 .. _Conventional Commits: https://www.conventionalcommits.org/en/v1.0.0
 .. _Gerrit Change-Ids documentation: https://review.trustedfirmware.org/Documentation/user-changeid.html

diff --git a/docs/tools/memory-layout-tool.rst b/docs/tools/memory-layout-tool.rst
index d9c358d..0a447c5 100644
--- a/docs/tools/memory-layout-tool.rst
+++ b/docs/tools/memory-layout-tool.rst

@@ -41,7 +41,7 @@
 
 .. code:: shell
 
-    $ poetry run memory -s
+    $ poetry run memory symbols
     build-path: build/fvp/release
     Virtual Address Map:
                +------------__BL1_RAM_END__------------+---------------------------------------+
@@ -116,14 +116,14 @@
 Memory Footprint
 ~~~~~~~~~~~~~~~~
 
-The tool enables users to view static memory consumption. When the options
-``-f``, or ``--footprint`` are provided, the script analyses the ELF binaries in
-the build path to generate a table (per memory type), showing memory allocation
-and usage. This is the default output generated by the tool.
+The tool enables users to view static memory consumption. When the ``footprint``
+command is provided, the script analyses the ELF binaries in the build path to
+generate a table (per memory type), showing memory allocation and usage. This is
+the default output generated by the tool.
 
 .. code:: shell
 
-    $ poetry run memory -f
+    $ poetry run memory footprint
     build-path: build/fvp/release
     +----------------------------------------------------------------------------+
     |                         Memory Usage (bytes) [RAM]                         |
@@ -150,13 +150,13 @@
 Memory Tree
 ~~~~~~~~~~~
 
-A hierarchical view of the memory layout can be produced by passing the option
-``-t`` or ``--tree`` to the tool. This gives the start, end, and size of each
-module, their ELF segments as well as sections.
+A hierarchical view of the memory layout can be produced by passing the ``tree``
+command to the tool. This gives the start, end, and size of each module, their
+ELF segments as well as sections.
 
 .. code:: shell
 
-    $ poetry run memory -t
+    $ poetry run memory tree
     build-path: build/fvp/release
     name                                       start        end       size
     bl1                                            0    400c000    400c000
@@ -209,7 +209,7 @@
 
 .. code::
 
-    $ poetry run memory -t --depth 2
+    $ poetry run memory tree --depth 2
     build-path: build/fvp/release
     name                          start        end       size
     bl1                               0    400c000    400c000
@@ -229,6 +229,169 @@
     ├── 00                      4003000    4010000       d000
     └── 01                      4010000    4021000      11000
 
+Memory Summary
+~~~~~~~~~~~~~~
+
+The tool provides a by-translation-unit summary of the sizes (``text``, ``bss``,
+``data``) contributed by each translation unit or group of translation units.
+For example, to print a table of an FVP build, with a path depth of 3:
+
+.. code::
+
+   $ poetry run memory summary build/fvp/debug/bl1/bl1.map  -d 3
+    | Module                                 |         .text |       .data |          .bss |
+    |----------------------------------------|---------------|-------------|---------------|
+    | [fill]                                 |   3204(+3204) |       0(+0) |       97(+97) |
+    | bl1/aem_generic.o                      |         0(+0) |       0(+0) |         0(+0) |
+    | bl1/arm_bl1_fwu.o                      |     224(+224) |     80(+80) |         0(+0) |
+    | bl1/arm_bl1_setup.o                    |     608(+608) |       0(+0) |       17(+17) |
+    | bl1/arm_common.o                       |     116(+116) |       0(+0) |         0(+0) |
+    | bl1/arm_console.o                      |     116(+116) |       0(+0) |       40(+40) |
+    | bl1/arm_dev_rotpk.o                    |         0(+0) |       0(+0) |         0(+0) |
+    | bl1/arm_dyn_cfg.o                      |     276(+276) |       0(+0) |   7184(+7184) |
+    | bl1/arm_dyn_cfg_helpers.o              |     364(+364) |       0(+0) |         0(+0) |
+    | bl1/arm_err.o                          |       12(+12) |       0(+0) |         0(+0) |
+    | bl1/arm_fconf_io.o                     |         0(+0) |   952(+952) |         0(+0) |
+    | bl1/arm_helpers.o                      |       44(+44) |       0(+0) |         0(+0) |
+    | bl1/arm_io_storage.o                   |     480(+480) |       0(+0) |       32(+32) |
+    | bl1/auth_mod.o                         |   1288(+1288) |       0(+0) |         0(+0) |
+    | bl1/backtrace.o                        |     444(+444) |       0(+0) |         0(+0) |
+    | bl1/bl1_arch_setup.o                   |       16(+16) |       0(+0) |         0(+0) |
+    | bl1/bl1_context_mgmt.o                 |     340(+340) |       0(+0) |   1392(+1392) |
+    | bl1/bl1_entrypoint.o                   |     236(+236) |       0(+0) |         0(+0) |
+    | bl1/bl1_exceptions.o                   |   2240(+2240) |       0(+0) |         0(+0) |
+    | bl1/bl1_fwu.o                          |   2188(+2188) |     44(+44) |         0(+0) |
+    | bl1/bl1_main.o                         |     620(+620) |       0(+0) |         0(+0) |
+    | bl1/bl_common.o                        |     772(+772) |       0(+0) |         4(+4) |
+    | bl1/board_arm_helpers.o                |       44(+44) |       0(+0) |         0(+0) |
+    | bl1/board_arm_trusted_boot.o           |       44(+44) |     16(+16) |         0(+0) |
+    | bl1/cache_helpers.o                    |     112(+112) |       0(+0) |         0(+0) |
+    | bl1/cci.o                              |     408(+408) |       0(+0) |       24(+24) |
+    | bl1/context.o                          |     348(+348) |       0(+0) |         0(+0) |
+    | bl1/context_mgmt.o                     |   1692(+1692) |       0(+0) |       48(+48) |
+    | bl1/cortex_a35.o                       |       96(+96) |       0(+0) |         0(+0) |
+    | bl1/cortex_a53.o                       |     248(+248) |       0(+0) |         0(+0) |
+    | bl1/cortex_a57.o                       |     384(+384) |       0(+0) |         0(+0) |
+    | bl1/cortex_a72.o                       |     356(+356) |       0(+0) |         0(+0) |
+    | bl1/cortex_a73.o                       |     304(+304) |       0(+0) |         0(+0) |
+    | bl1/cpu_helpers.o                      |     200(+200) |       0(+0) |         0(+0) |
+    | bl1/crypto_mod.o                       |     380(+380) |       0(+0) |         0(+0) |
+    | bl1/debug.o                            |     224(+224) |       0(+0) |         0(+0) |
+    | bl1/delay_timer.o                      |       64(+64) |       0(+0) |         8(+8) |
+    | bl1/enable_mmu.o                       |     112(+112) |       0(+0) |         0(+0) |
+    | bl1/errata_report.o                    |     564(+564) |       0(+0) |         0(+0) |
+    | bl1/fconf.o                            |     148(+148) |       0(+0) |         0(+0) |
+    | bl1/fconf_dyn_cfg_getter.o             |     656(+656) |     32(+32) |     144(+144) |
+    | bl1/fconf_tbbr_getter.o                |     332(+332) |       0(+0) |       24(+24) |
+    | bl1/fdt_wrappers.o                     |     452(+452) |       0(+0) |         0(+0) |
+    | bl1/fvp_bl1_setup.o                    |     168(+168) |       0(+0) |         0(+0) |
+    | bl1/fvp_common.o                       |     512(+512) |       0(+0) |         8(+8) |
+    | bl1/fvp_cpu_pwr.o                      |     136(+136) |       0(+0) |         0(+0) |
+    | bl1/fvp_err.o                          |       44(+44) |       0(+0) |         0(+0) |
+    | bl1/fvp_helpers.o                      |     148(+148) |       0(+0) |         0(+0) |
+    | bl1/fvp_io_storage.o                   |     228(+228) |       0(+0) |       16(+16) |
+    | bl1/fvp_trusted_boot.o                 |     292(+292) |       0(+0) |         0(+0) |
+    | bl1/generic_delay_timer.o              |     136(+136) |       0(+0) |       16(+16) |
+    | bl1/img_parser_mod.o                   |     588(+588) |       0(+0) |       20(+20) |
+    | bl1/io_fip.o                           |   1332(+1332) |       0(+0) |     100(+100) |
+    | bl1/io_memmap.o                        |     736(+736) |     16(+16) |       32(+32) |
+    | bl1/io_semihosting.o                   |     648(+648) |     16(+16) |         0(+0) |
+    | bl1/io_storage.o                       |   1268(+1268) |       0(+0) |     104(+104) |
+    | bl1/mbedtls_common.o                   |     208(+208) |       0(+0) |         4(+4) |
+    | bl1/mbedtls_crypto.o                   |     636(+636) |       0(+0) |         0(+0) |
+    | bl1/mbedtls_x509_parser.o              |   1588(+1588) |       0(+0) |     120(+120) |
+    | bl1/misc_helpers.o                     |     392(+392) |       0(+0) |         0(+0) |
+    | bl1/multi_console.o                    |     528(+528) |       1(+1) |         8(+8) |
+    | bl1/pl011_console.o                    |     308(+308) |       0(+0) |         0(+0) |
+    | bl1/plat_bl1_common.o                  |     208(+208) |       0(+0) |         0(+0) |
+    | bl1/plat_bl_common.o                   |       40(+40) |       0(+0) |         0(+0) |
+    | bl1/plat_common.o                      |       48(+48) |       0(+0) |         8(+8) |
+    | bl1/plat_log_common.o                  |       48(+48) |       0(+0) |         0(+0) |
+    | bl1/plat_tbbr.o                        |     128(+128) |       0(+0) |         0(+0) |
+    | bl1/platform_helpers.o                 |       12(+12) |       0(+0) |         0(+0) |
+    | bl1/platform_up_stack.o                |       16(+16) |       0(+0) |         0(+0) |
+    | bl1/semihosting.o                      |     352(+352) |       0(+0) |         0(+0) |
+    | bl1/semihosting_call.o                 |         8(+8) |       0(+0) |         0(+0) |
+    | bl1/smmu_v3.o                          |     296(+296) |       0(+0) |         0(+0) |
+    | bl1/sp805.o                            |       64(+64) |       0(+0) |         0(+0) |
+    | bl1/tbbr_cot_bl1.o                     |         0(+0) |     48(+48) |     156(+156) |
+    | bl1/tbbr_cot_common.o                  |         0(+0) |   144(+144) |     306(+306) |
+    | bl1/tbbr_img_desc.o                    |         0(+0) |   768(+768) |         0(+0) |
+    | bl1/tf_log.o                           |     200(+200) |       4(+4) |         0(+0) |
+    | bl1/xlat_tables_arch.o                 |     736(+736) |       0(+0) |         0(+0) |
+    | bl1/xlat_tables_context.o              |     192(+192) |     96(+96) |   1296(+1296) |
+    | bl1/xlat_tables_core.o                 |   2112(+2112) |       0(+0) |         0(+0) |
+    | bl1/xlat_tables_utils.o                |         8(+8) |       0(+0) |         0(+0) |
+    | lib/libc.a/assert.o                    |       48(+48) |       0(+0) |         0(+0) |
+    | lib/libc.a/exit.o                      |       64(+64) |       0(+0) |         8(+8) |
+    | lib/libc.a/memchr.o                    |       44(+44) |       0(+0) |         0(+0) |
+    | lib/libc.a/memcmp.o                    |       52(+52) |       0(+0) |         0(+0) |
+    | lib/libc.a/memcpy.o                    |       32(+32) |       0(+0) |         0(+0) |
+    | lib/libc.a/memmove.o                   |       52(+52) |       0(+0) |         0(+0) |
+    | lib/libc.a/memset.o                    |     140(+140) |       0(+0) |         0(+0) |
+    | lib/libc.a/printf.o                    |   1532(+1532) |       0(+0) |         0(+0) |
+    | lib/libc.a/snprintf.o                  |   1748(+1748) |       0(+0) |         0(+0) |
+    | lib/libc.a/strcmp.o                    |       44(+44) |       0(+0) |         0(+0) |
+    | lib/libc.a/strlen.o                    |       28(+28) |       0(+0) |         0(+0) |
+    | lib/libfdt.a/fdt.o                     |   1460(+1460) |       0(+0) |         0(+0) |
+    | lib/libfdt.a/fdt_ro.o                  |   1392(+1392) |       0(+0) |         0(+0) |
+    | lib/libfdt.a/fdt_wip.o                 |     244(+244) |       0(+0) |         0(+0) |
+    | lib/libmbedtls.a/asn1parse.o           |     956(+956) |       0(+0) |         0(+0) |
+    | lib/libmbedtls.a/bignum.o              |   6796(+6796) |       0(+0) |         0(+0) |
+    | lib/libmbedtls.a/bignum_core.o         |   3252(+3252) |       0(+0) |         0(+0) |
+    | lib/libmbedtls.a/constant_time.o       |     280(+280) |       0(+0) |         8(+8) |
+    | lib/libmbedtls.a/md.o                  |     504(+504) |       0(+0) |         0(+0) |
+    | lib/libmbedtls.a/memory_buffer_alloc.o |   1264(+1264) |       0(+0) |       40(+40) |
+    | lib/libmbedtls.a/oid.o                 |     752(+752) |       0(+0) |         0(+0) |
+    | lib/libmbedtls.a/pk.o                  |     872(+872) |       0(+0) |         0(+0) |
+    | lib/libmbedtls.a/pk_wrap.o             |     848(+848) |       0(+0) |         0(+0) |
+    | lib/libmbedtls.a/pkparse.o             |     516(+516) |       0(+0) |         0(+0) |
+    | lib/libmbedtls.a/platform.o            |       92(+92) |     24(+24) |         0(+0) |
+    | lib/libmbedtls.a/platform_util.o       |       96(+96) |       0(+0) |         0(+0) |
+    | lib/libmbedtls.a/rsa.o                 |   6588(+6588) |       0(+0) |         0(+0) |
+    | lib/libmbedtls.a/rsa_alt_helpers.o     |   2340(+2340) |       0(+0) |         0(+0) |
+    | lib/libmbedtls.a/sha256.o              |   1448(+1448) |       0(+0) |         0(+0) |
+    | lib/libmbedtls.a/x509.o                |   1028(+1028) |       0(+0) |         0(+0) |
+    | Subtotals                              | 69632(+69632) | 2241(+2241) | 11264(+11264) |
+    Total Static RAM memory (data + bss): 13505(+13505) bytes
+    Total Flash memory (text + data): 71873(+71873) bytes
+
+A delta between two images can be generated by passing the ``--old`` option with
+a path to the previous map file.
+
+For example:
+
+.. code::
+
+    $ poetry run memory summary ../maps/fvp-tbb-mbedtls/bl1.map --old ../maps/fvp-tbb-mbedtls/bl1.map.old -d 1
+    | Module    |         .text |    .data |         .bss |
+    |-----------|---------------|----------|--------------|
+    | [fill]    |    780(-2424) |    0(+0) |    321(+224) |
+    | bl1       |   32024(+108) | 2217(+0) |    11111(+0) |
+    | lib       | 45020(+10508) |   24(+0) |  1880(+1824) |
+    | Subtotals |  77824(+8192) | 2241(+0) | 13312(+2048) |
+    Total Static RAM memory (data + bss): 15553(+2048) bytes
+    Total Flash memory (text + data): 80065(+8192) bytes
+
+Note that since the old map file includes the required suffix, specifying the
+``--old`` argument is optional here.
+
+Under some circumstances, some executables are padded to meet certain
+alignments, such as a 4KB page boundary, and excluding that padding can provide
+more helpful diffs. Taking the last example, and adding the ``-e`` argument
+yields such a summary:
+
+.. code::
+
+    $ poetry run memory summary ../maps/fvp-tbb-mbedtls/bl1.map --old ../maps/fvp-tbb-mbedtls/bl1.map.old  -d 1 -e
+    | Module    |         .text |    .data |         .bss |
+    |-----------|---------------|----------|--------------|
+    | bl1       |   32024(+108) | 2217(+0) |    11111(+0) |
+    | lib       | 45020(+10508) |   24(+0) |  1880(+1824) |
+    | Subtotals | 77044(+10616) | 2241(+0) | 12991(+1824) |
+    Total Static RAM memory (data + bss): 15232(+1824) bytes
+    Total Flash memory (text + data): 79285(+10616) bytes
+
 --------------
 
 *Copyright (c) 2023-2025, Arm Limited. All rights reserved.*

diff --git a/drivers/arm/gic/gic.mk b/drivers/arm/gic/gic.mk
index ad30984..8b28f21 100644
--- a/drivers/arm/gic/gic.mk
+++ b/drivers/arm/gic/gic.mk

@@ -4,7 +4,7 @@
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
-GIC_REVISIONS_ := 1 2 3
+GIC_REVISIONS_ := 1 2 3 5
 ifeq ($(filter $(USE_GIC_DRIVER),$(GIC_REVISIONS_)),)
 $(error USE_GIC_DRIVER can only be one of $(GIC_REVISIONS_))
 endif
@@ -19,6 +19,18 @@
 GIC_SOURCES	:=	${GICV3_SOURCES}			\
 			drivers/arm/gic/v3/gicv3_base.c	\
 			plat/common/plat_gicv3.c
+else ifeq (${USE_GIC_DRIVER},5)
+ifneq (${ENABLE_FEAT_GCIE},1)
+$(error USE_GIC_DRIVER=5 requires ENABLE_FEAT_GCIE=1)
+endif
+$(warning GICv5 support is experimental!)
+GIC_SOURCES	:=	drivers/arm/gicv5/gicv5_iri.c		\
+			plat/common/plat_gicv5.c
+endif
+
+ifneq (${ENABLE_FEAT_GCIE},0)
+GIC_SOURCES	+=	drivers/arm/gicv5/gicv5_cpuif.c		\
+			drivers/arm/gicv5/gicv5_main.c
 endif
 
 ifeq ($(ARCH),aarch64)

diff --git a/drivers/arm/gicv5/gicv5_cpuif.c b/drivers/arm/gicv5/gicv5_cpuif.c
new file mode 100644
index 0000000..eb17206
--- /dev/null
+++ b/drivers/arm/gicv5/gicv5_cpuif.c

@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/arm/gic.h>
+#include <drivers/arm/gicv5.h>
+
+void gic_cpuif_enable(unsigned int cpu_idx)
+{
+}
+
+void gic_cpuif_disable(unsigned int cpu_idx)
+{
+}
+
+void gic_pcpu_init(unsigned int cpu_idx)
+{
+	gicv5_enable_ppis();
+}
+
+void gic_pcpu_off(unsigned int cpu_idx)
+{
+}
+

diff --git a/drivers/arm/gicv5/gicv5_iri.c b/drivers/arm/gicv5/gicv5_iri.c
new file mode 100644
index 0000000..049f3f0
--- /dev/null
+++ b/drivers/arm/gicv5/gicv5_iri.c

@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <cdefs.h>
+#include <drivers/arm/gic.h>
+#include <drivers/arm/gicv5.h>
+
+#if USE_GIC_DRIVER != 5
+#error "This file should only be used with USE_GIC_DRIVER=5"
+#endif
+
+void __init gic_init(unsigned int cpu_idx)
+{
+	gicv5_driver_init();
+}
+
+void gic_save(void)
+{
+}
+
+void gic_resume(void)
+{
+}

diff --git a/drivers/arm/gicv5/gicv5_main.c b/drivers/arm/gicv5/gicv5_main.c
new file mode 100644
index 0000000..803a96d
--- /dev/null
+++ b/drivers/arm/gicv5/gicv5_main.c

@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <cdefs.h>
+
+#include <arch.h>
+#include <arch_features.h>
+#include <arch_helpers.h>
+
+#include <bl31/interrupt_mgmt.h>
+#include <common/debug.h>
+#include <drivers/arm/gicv5.h>
+
+/*
+ * Check for a bad platform configuration.
+ * Not expected to be called on release builds.
+ */
+static inline bool probe_component(uintptr_t base_addr, uint8_t component)
+{
+	uint32_t aidr = read_iri_aidr(base_addr);
+
+	if (EXTRACT(IRI_AIDR_COMPONENT, aidr) != component) {
+		ERROR("GICv5 frame belongs to wrong component\n");
+		return false;
+	}
+
+	if (EXTRACT(IRI_AIDR_ARCH_MAJOR, aidr) != IRI_AIDR_ARCH_MAJOR_V5) {
+		ERROR("Bad GICv5 major version\n");
+		return false;
+	}
+
+	/* there was a bump in architecture and we've not updated the driver */
+	assert(EXTRACT(IRI_AIDR_ARCH_MINOR, aidr) == IRI_AIDR_ARCH_MINOR_P0);
+
+	return true;
+}
+
+static inline bool iwb_domain_supported(uint32_t idr0, uint8_t domain)
+{
+	return (EXTRACT(IWB_IDR0_DOMAINS, idr0) & (1U << domain)) != 0U;
+}
+
+static void iwb_configure_domainr(uintptr_t base_addr, struct gicv5_wire_props wire)
+{
+	uint32_t reg_offset = (wire.id % 16U) * 2U;
+	uint32_t reg_index = wire.id / 16U;
+	uint32_t val = read_iwb_wdomainr(base_addr, reg_index) &
+		       ~(IWB_WDOMAINR_DOMAINX_MASK << reg_offset);
+
+	write_iwb_wdomainr(base_addr, reg_index, val | wire.domain << reg_offset);
+}
+
+static void iwb_configure_wtmr(uintptr_t base_addr, struct gicv5_wire_props wire)
+{
+	uint32_t reg_offset = wire.id % 32U;
+	uint32_t reg_index = wire.id / 32U;
+	uint32_t val = read_iwb_wtmr(base_addr, reg_index) & ~(1U << reg_offset);
+
+	write_iwb_wtmr(base_addr, reg_index, val | wire.tm << reg_offset);
+}
+
+static void iwb_enable(const struct gicv5_iwb *config)
+{
+	uintptr_t base_addr = config->config_frame;
+	uint32_t idr0;
+	uint16_t num_regs;
+
+	assert(probe_component(base_addr, IRI_AIDR_COMPONENT_IWB));
+
+	idr0 = read_iwb_idr0(base_addr);
+	num_regs = EXTRACT(IWB_IDR0_IWRANGE, idr0) + 1U;
+
+	/* initialise all wires as disabled */
+	for (int i = 0U; i < num_regs; i++) {
+		write_iwb_wenabler(base_addr, i, 0U);
+	}
+
+	/* default all wires to the NS domain */
+	for (int i = 0U; i < num_regs * 2; i++) {
+		write_iwb_wdomainr(base_addr, i, 0x55555555);
+	}
+
+	for (uint32_t i = 0U; i < config->num_wires; i++) {
+		assert(iwb_domain_supported(idr0, config->wires[i].domain));
+		assert(config->wires[i].id <= num_regs * 32);
+
+		iwb_configure_domainr(base_addr, config->wires[i]);
+		iwb_configure_wtmr(base_addr, config->wires[i]);
+	}
+
+	write_iwb_cr0(base_addr, IWB_CR0_IWBEN_BIT);
+	WAIT_FOR_IDLE_IWB_WENABLE_STATUSR(base_addr);
+	WAIT_FOR_IDLE_IWB_WDOMAIN_STATUSR(base_addr);
+	WAIT_FOR_IDLE_IWB_CR0(base_addr);
+}
+
+static void irs_configure_wire(uintptr_t base_addr, uint32_t wire, uint8_t domain)
+{
+	write_irs_spi_selr(base_addr, wire);
+	WAIT_FOR_VIDLE_IRS_SPI_STATUSR(base_addr);
+
+	write_irs_spi_domainr(base_addr, domain);
+	WAIT_FOR_VIDLE_IRS_SPI_STATUSR(base_addr);
+}
+
+static void irs_enable(const struct gicv5_irs *config)
+{
+	uint32_t spi_base, spi_range;
+	uintptr_t base_addr = config->el3_config_frame;
+
+	spi_base  = EXTRACT(IRS_IDR7_SPI_BASE, read_irs_idr7(base_addr));
+	spi_range = EXTRACT(IRS_IDR6_SPI_IRS_RANGE, read_irs_idr6(base_addr));
+
+	assert(probe_component(base_addr, IRI_AIDR_COMPONENT_IRS));
+
+	if (spi_range == 0U) {
+		assert(config->num_spis == 0U);
+	}
+
+	/* default all wires to the NS domain */
+	for (uint32_t i = spi_base; i < spi_base + spi_range; i++) {
+		irs_configure_wire(base_addr, i, INTDMN_NS);
+	}
+
+	for (uint32_t i = 0U; i < config->num_spis; i++) {
+		assert((config->spis[i].id >= spi_base) &&
+		       (config->spis[i].id < spi_base + spi_range));
+
+		irs_configure_wire(base_addr, config->spis[i].id, config->spis[i].domain);
+
+		/* don't (can't) configure TM of wires for other domains */
+		if (config->spis[i].domain == INTDMN_EL3) {
+			write_irs_spi_cfgr(base_addr, config->spis[i].tm);
+			WAIT_FOR_VIDLE_IRS_SPI_STATUSR(base_addr);
+		}
+	}
+}
+
+void __init gicv5_driver_init(void)
+{
+	for (size_t i = 0U; i < plat_gicv5_driver_data.num_iwbs; i++) {
+		iwb_enable(&plat_gicv5_driver_data.iwbs[i]);
+	}
+
+	for (size_t i = 0U; i < plat_gicv5_driver_data.num_irss; i++) {
+		irs_enable(&plat_gicv5_driver_data.irss[i]);
+	}
+}
+
+/*
+ * There exists a theoretical configuration where FEAT_RME is enabled
+ * without using TrustZone (i.e., no Secure world present). Currently,
+ * there is no reliable mechanism to detect this scenario at runtime.
+ *
+ * TODO: Add support for this configuration in the future if required.
+ */
+bool gicv5_has_interrupt_type(unsigned int type)
+{
+	switch (type) {
+	case INTR_TYPE_EL3:
+	case INTR_TYPE_S_EL1:
+	case INTR_TYPE_NS:
+		return true;
+	case INTR_TYPE_RL:
+		return is_feat_rme_supported();
+	default:
+		return false;
+	}
+}
+
+uint8_t gicv5_get_pending_interrupt_type(void)
+{
+	/* there is no pending interrupt expected */
+	return INTR_TYPE_INVAL;
+}
+
+/* TODO: these will probably end up contexted. Make Linux work for now */
+void gicv5_enable_ppis(void)
+{
+	uint64_t domainr = 0U;
+
+	/* the only ones described in the device tree at the moment */
+	write_icc_ppi_domainr(domainr, PPI_PMUIRQ,	INTDMN_NS);
+	write_icc_ppi_domainr(domainr, PPI_GICMNT,	INTDMN_NS);
+	write_icc_ppi_domainr(domainr, PPI_CNTHP,	INTDMN_NS);
+	write_icc_ppi_domainr(domainr, PPI_CNTV,	INTDMN_NS);
+	write_icc_ppi_domainr(domainr, PPI_CNTPS,	INTDMN_NS);
+	write_icc_ppi_domainr(domainr, PPI_CNTP,	INTDMN_NS);
+
+	write_icc_ppi_domainr0_el3(domainr);
+}

diff --git a/drivers/imx/usdhc/imx_usdhc.c b/drivers/imx/usdhc/imx_usdhc.c
index 49dfc07..f6a27dc 100644
--- a/drivers/imx/usdhc/imx_usdhc.c
+++ b/drivers/imx/usdhc/imx_usdhc.c

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright 2025 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -14,9 +15,22 @@
 #include <drivers/delay_timer.h>
 #include <drivers/mmc.h>
 #include <lib/mmio.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
 
 #include <imx_usdhc.h>
 
+/* These masks represent the commands which involve a data transfer. */
+#define ADTC_MASK_SD			(BIT_32(6U) | BIT_32(17U) | BIT_32(18U) |\
+					 BIT_32(24U) | BIT_32(25U))
+#define ADTC_MASK_ACMD			(BIT_64(51U))
+
+struct imx_usdhc_device_data {
+	uint32_t addr;
+	uint32_t blk_size;
+	uint32_t blks;
+	bool valid;
+};
+
 static void imx_usdhc_initialize(void);
 static int imx_usdhc_send_cmd(struct mmc_cmd *cmd);
 static int imx_usdhc_set_ios(unsigned int clk, unsigned int width);
@@ -34,27 +48,85 @@
 };
 
 static imx_usdhc_params_t imx_usdhc_params;
+static struct imx_usdhc_device_data imx_usdhc_data;
+
+static bool imx_usdhc_is_buf_valid(void)
+{
+	return imx_usdhc_data.valid;
+}
+
+static bool imx_usdhc_is_buf_multiblk(void)
+{
+	return imx_usdhc_data.blks > 1U;
+}
+
+static void imx_usdhc_inval_buf_data(void)
+{
+	imx_usdhc_data.valid = false;
+}
+
+static int imx_usdhc_save_buf_data(uintptr_t buf, size_t size)
+{
+	uint32_t block_size;
+	uint64_t blks;
+
+	if (size <= MMC_BLOCK_SIZE) {
+		block_size = (uint32_t)size;
+	} else {
+		block_size = MMC_BLOCK_SIZE;
+	}
+
+	if (buf > UINT32_MAX) {
+		return -EOVERFLOW;
+	}
+
+	imx_usdhc_data.addr = (uint32_t)buf;
+	imx_usdhc_data.blk_size = block_size;
+	blks = size / block_size;
+	imx_usdhc_data.blks = (uint32_t)blks;
+
+	imx_usdhc_data.valid = true;
+
+	return 0;
+}
+
+static void imx_usdhc_write_buf_data(void)
+{
+	uintptr_t reg_base = imx_usdhc_params.reg_base;
+	uint32_t addr, blks, blk_size;
+
+	addr = imx_usdhc_data.addr;
+	blks = imx_usdhc_data.blks;
+	blk_size = imx_usdhc_data.blk_size;
+
+	mmio_write_32(reg_base + DSADDR, addr);
+	mmio_write_32(reg_base + BLKATT, BLKATT_BLKCNT(blks) |
+		      BLKATT_BLKSIZE(blk_size));
+}
 
 #define IMX7_MMC_SRC_CLK_RATE (200 * 1000 * 1000)
-static void imx_usdhc_set_clk(int clk)
+static void imx_usdhc_set_clk(unsigned int clk)
 {
-	int div = 1;
-	int pre_div = 1;
 	unsigned int sdhc_clk = IMX7_MMC_SRC_CLK_RATE;
 	uintptr_t reg_base = imx_usdhc_params.reg_base;
+	unsigned int pre_div = 1U, div = 1U;
 
 	assert(clk > 0);
 
 	while (sdhc_clk / (16 * pre_div) > clk && pre_div < 256)
 		pre_div *= 2;
 
-	while (sdhc_clk / div > clk && div < 16)
+	while (((sdhc_clk / (div * pre_div)) > clk) && (div < 16U)) {
 		div++;
+	}
 
 	pre_div >>= 1;
 	div -= 1;
 	clk = (pre_div << 8) | (div << 4);
 
+	while ((mmio_read_32(reg_base + PSTATE) & PSTATE_SDSTB) == 0U) {
+	}
+
 	mmio_clrbits32(reg_base + VENDSPEC, VENDSPEC_CARD_CLKEN);
 	mmio_clrsetbits32(reg_base + SYSCTRL, SYSCTRL_CLOCK_MASK, clk);
 	udelay(10000);
@@ -107,15 +179,85 @@
 
 #define FSL_CMD_RETRIES	1000
 
+static bool is_data_transfer_to_card(const struct mmc_cmd *cmd)
+{
+	unsigned int cmd_idx = cmd->cmd_idx;
+
+	return (cmd_idx == MMC_CMD(24)) || (cmd_idx == MMC_CMD(25));
+}
+
+static bool is_data_transfer_cmd(const struct mmc_cmd *cmd)
+{
+	uintptr_t reg_base = imx_usdhc_params.reg_base;
+	unsigned int cmd_idx = cmd->cmd_idx;
+	uint32_t xfer_type;
+
+	xfer_type = mmio_read_32(reg_base + XFERTYPE);
+
+	if (XFERTYPE_GET_CMD(xfer_type) == MMC_CMD(55)) {
+		return (ADTC_MASK_ACMD & BIT_64(cmd_idx)) != 0ULL;
+	}
+
+	if ((ADTC_MASK_SD & BIT_32(cmd->cmd_idx)) != 0U) {
+		return true;
+	}
+
+	return false;
+}
+
+static int get_xfr_type(const struct mmc_cmd *cmd, bool data, uint32_t *xfertype)
+{
+	*xfertype = XFERTYPE_CMD(cmd->cmd_idx);
+
+	switch (cmd->resp_type) {
+	case MMC_RESPONSE_R2:
+		*xfertype |= XFERTYPE_RSPTYP_136;
+		*xfertype |= XFERTYPE_CCCEN;
+		break;
+	case MMC_RESPONSE_R4:
+		*xfertype |= XFERTYPE_RSPTYP_48;
+		break;
+	case MMC_RESPONSE_R6:
+		*xfertype |= XFERTYPE_RSPTYP_48;
+		*xfertype |= XFERTYPE_CICEN;
+		*xfertype |= XFERTYPE_CCCEN;
+		break;
+	case MMC_RESPONSE_R1B:
+		*xfertype |= XFERTYPE_RSPTYP_48_BUSY;
+		*xfertype |= XFERTYPE_CICEN;
+		*xfertype |= XFERTYPE_CCCEN;
+		break;
+	default:
+		ERROR("Invalid CMD response: %u\n", cmd->resp_type);
+		return -EINVAL;
+	}
+
+	if (data) {
+		*xfertype |= XFERTYPE_DPSEL;
+	}
+
+	return 0;
+}
+
 static int imx_usdhc_send_cmd(struct mmc_cmd *cmd)
 {
 	uintptr_t reg_base = imx_usdhc_params.reg_base;
-	unsigned int xfertype = 0, mixctl = 0, multiple = 0, data = 0, err = 0;
 	unsigned int state, flags = INTSTATEN_CC | INTSTATEN_CTOE;
+	unsigned int mixctl = 0;
 	unsigned int cmd_retries = 0;
+	uint32_t xfertype;
+	bool data;
+	int err = 0;
 
 	assert(cmd);
 
+	data = is_data_transfer_cmd(cmd);
+
+	err = get_xfr_type(cmd, data, &xfertype);
+	if (err != 0) {
+		return err;
+	}
+
 	/* clear all irq status */
 	mmio_write_32(reg_base + INTSTAT, 0xffffffff);
 
@@ -128,56 +270,23 @@
 		;
 
 	mmio_write_32(reg_base + INTSIGEN, 0);
-	udelay(1000);
-
-	switch (cmd->cmd_idx) {
-	case MMC_CMD(12):
-		xfertype |= XFERTYPE_CMDTYP_ABORT;
-		break;
-	case MMC_CMD(18):
-		multiple = 1;
-		/* for read op */
-		/* fallthrough */
-	case MMC_CMD(17):
-	case MMC_CMD(8):
-		mixctl |= MIXCTRL_DTDSEL;
-		data = 1;
-		break;
-	case MMC_CMD(25):
-		multiple = 1;
-		/* for data op flag */
-		/* fallthrough */
-	case MMC_CMD(24):
-		data = 1;
-		break;
-	default:
-		break;
-	}
-
-	if (multiple) {
-		mixctl |= MIXCTRL_MSBSEL;
-		mixctl |= MIXCTRL_BCEN;
-	}
 
 	if (data) {
-		xfertype |= XFERTYPE_DPSEL;
 		mixctl |= MIXCTRL_DMAEN;
 	}
 
-	if (cmd->resp_type & MMC_RSP_48 && cmd->resp_type != MMC_RESPONSE_R2)
-		xfertype |= XFERTYPE_RSPTYP_48;
-	else if (cmd->resp_type & MMC_RSP_136)
-		xfertype |= XFERTYPE_RSPTYP_136;
-	else if (cmd->resp_type & MMC_RSP_BUSY)
-		xfertype |= XFERTYPE_RSPTYP_48_BUSY;
-
-	if (cmd->resp_type & MMC_RSP_CMD_IDX)
-		xfertype |= XFERTYPE_CICEN;
+	if (!is_data_transfer_to_card(cmd)) {
+		mixctl |= MIXCTRL_DTDSEL;
+	}
 
-	if (cmd->resp_type & MMC_RSP_CRC)
-		xfertype |= XFERTYPE_CCCEN;
+	if ((cmd->cmd_idx != MMC_CMD(55)) && imx_usdhc_is_buf_valid()) {
+		if (imx_usdhc_is_buf_multiblk()) {
+			mixctl |= MIXCTRL_MSBSEL | MIXCTRL_BCEN;
+		}
 
-	xfertype |= XFERTYPE_CMD(cmd->cmd_idx);
+		imx_usdhc_write_buf_data();
+		imx_usdhc_inval_buf_data();
+	}
 
 	/* Send the command */
 	mmio_write_32(reg_base + CMDARG, cmd->cmd_arg);
@@ -269,17 +378,13 @@
 
 static int imx_usdhc_prepare(int lba, uintptr_t buf, size_t size)
 {
-	uintptr_t reg_base = imx_usdhc_params.reg_base;
-
-	mmio_write_32(reg_base + DSADDR, buf);
-	mmio_write_32(reg_base + BLKATT,
-		      (size / MMC_BLOCK_SIZE) << 16 | MMC_BLOCK_SIZE);
-
-	return 0;
+	flush_dcache_range(buf, size);
+	return imx_usdhc_save_buf_data(buf, size);
 }
 
 static int imx_usdhc_read(int lba, uintptr_t buf, size_t size)
 {
+	inv_dcache_range(buf, size);
 	return 0;
 }
 
@@ -291,13 +396,24 @@
 void imx_usdhc_init(imx_usdhc_params_t *params,
 		    struct mmc_device_info *mmc_dev_info)
 {
+	int ret __maybe_unused;
+
 	assert((params != 0) &&
 	       ((params->reg_base & MMC_BLOCK_MASK) == 0) &&
-	       (params->clk_rate > 0) &&
 	       ((params->bus_width == MMC_BUS_WIDTH_1) ||
 		(params->bus_width == MMC_BUS_WIDTH_4) ||
 		(params->bus_width == MMC_BUS_WIDTH_8)));
 
+#if PLAT_XLAT_TABLES_DYNAMIC
+	ret = mmap_add_dynamic_region(params->reg_base, params->reg_base,
+				      PAGE_SIZE,
+				      MT_DEVICE | MT_RW | MT_SECURE);
+	if (ret != 0) {
+		ERROR("Failed to map the uSDHC registers\n");
+		panic();
+	}
+#endif
+
 	memcpy(&imx_usdhc_params, params, sizeof(imx_usdhc_params_t));
 	mmc_init(&imx_usdhc_ops, params->clk_rate, params->bus_width,
 		 params->flags, mmc_dev_info);

diff --git a/drivers/imx/usdhc/imx_usdhc.h b/drivers/imx/usdhc/imx_usdhc.h
index e063316..bb0ef01 100644
--- a/drivers/imx/usdhc/imx_usdhc.h
+++ b/drivers/imx/usdhc/imx_usdhc.h

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright 2025 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,8 +12,8 @@
 
 typedef struct imx_usdhc_params {
 	uintptr_t	reg_base;
-	int		clk_rate;
-	int		bus_width;
+	unsigned int	clk_rate;
+	unsigned int	bus_width;
 	unsigned int	flags;
 } imx_usdhc_params_t;
 
@@ -20,115 +21,119 @@
 		    struct mmc_device_info *mmc_dev_info);
 
 /* iMX MMC registers definition */
-#define DSADDR			0x000
-#define BLKATT			0x004
-#define CMDARG			0x008
-#define CMDRSP0			0x010
-#define CMDRSP1			0x014
-#define CMDRSP2			0x018
-#define CMDRSP3			0x01c
+#define DSADDR			0x000U
+#define BLKATT			0x004U
+#define BLKATT_BLKCNT(x)	(((x) << 16U) & GENMASK_32(31U, 16U))
+#define BLKATT_BLKSIZE(x)	((x) & GENMASK_32(12U, 0U))
+#define CMDARG			0x008U
+#define CMDRSP0			0x010U
+#define CMDRSP1			0x014U
+#define CMDRSP2			0x018U
+#define CMDRSP3			0x01cU
 
-#define XFERTYPE		0x00c
-#define XFERTYPE_CMD(x)		(((x) & 0x3f) << 24)
-#define XFERTYPE_CMDTYP_ABORT	(3 << 22)
-#define XFERTYPE_DPSEL		BIT(21)
-#define XFERTYPE_CICEN		BIT(20)
-#define XFERTYPE_CCCEN		BIT(19)
-#define XFERTYPE_RSPTYP_136	BIT(16)
-#define XFERTYPE_RSPTYP_48	BIT(17)
-#define XFERTYPE_RSPTYP_48_BUSY	(BIT(16) | BIT(17))
+#define XFERTYPE		0x00cU
+#define XFERTYPE_CMD(x)		(((x) & 0x3fU) << 24U)
+#define XFERTYPE_GET_CMD(x)	(((x) & GENMASK_32(29U, 24U)) >> 24U)
+#define XFERTYPE_CMDTYP_ABORT	(3U << 22U)
+#define XFERTYPE_DPSEL		BIT_32(21U)
+#define XFERTYPE_CICEN		BIT_32(20U)
+#define XFERTYPE_CCCEN		BIT_32(19U)
+#define XFERTYPE_RSPTYP_136	BIT_32(16U)
+#define XFERTYPE_RSPTYP_48	BIT_32(17U)
+#define XFERTYPE_RSPTYP_48_BUSY	(BIT_32(16U) | BIT_32(17U))
 
-#define PSTATE			0x024
-#define PSTATE_DAT0		BIT(24)
-#define PSTATE_DLA		BIT(2)
-#define PSTATE_CDIHB		BIT(1)
-#define PSTATE_CIHB		BIT(0)
+#define PSTATE			0x024U
+#define PSTATE_DAT0		BIT_32(24U)
+#define PSTATE_SDSTB		BIT_32(3U)
+#define PSTATE_DLA		BIT_32(2U)
+#define PSTATE_CDIHB		BIT_32(1U)
+#define PSTATE_CIHB		BIT_32(0U)
 
-#define PROTCTRL		0x028
-#define PROTCTRL_LE		BIT(5)
-#define PROTCTRL_WIDTH_4	BIT(1)
-#define PROTCTRL_WIDTH_8	BIT(2)
-#define PROTCTRL_WIDTH_MASK	0x6
+#define PROTCTRL		0x028U
+#define PROTCTRL_LE		BIT_32(5U)
+#define PROTCTRL_WIDTH_4	BIT_32(1U)
+#define PROTCTRL_WIDTH_8	BIT_32(2U)
+#define PROTCTRL_WIDTH_MASK	0x6U
 
-#define SYSCTRL			0x02c
-#define SYSCTRL_RSTD		BIT(26)
-#define SYSCTRL_RSTC		BIT(25)
-#define SYSCTRL_RSTA		BIT(24)
-#define SYSCTRL_CLOCK_MASK	0x0000fff0
-#define SYSCTRL_TIMEOUT_MASK	0x000f0000
-#define SYSCTRL_TIMEOUT(x)	((0xf & (x)) << 16)
+#define SYSCTRL			0x02cU
+#define SYSCTRL_RSTD		BIT_32(26U)
+#define SYSCTRL_RSTC		BIT_32(25U)
+#define SYSCTRL_RSTA		BIT_32(24U)
+#define SYSCTRL_CLOCK_MASK	GENMASK_32(15U, 4U)
+#define SYSCTRL_TIMEOUT_MASK	GENMASK_32(19U, 16U)
+#define SYSCTRL_TIMEOUT(x)	((0xfU & (x)) << 16U)
 
-#define INTSTAT			0x030
-#define INTSTAT_DMAE		BIT(28)
-#define INTSTAT_DEBE		BIT(22)
-#define INTSTAT_DCE		BIT(21)
-#define INTSTAT_DTOE		BIT(20)
-#define INTSTAT_CIE		BIT(19)
-#define INTSTAT_CEBE		BIT(18)
-#define INTSTAT_CCE		BIT(17)
-#define INTSTAT_DINT		BIT(3)
-#define INTSTAT_BGE		BIT(2)
-#define INTSTAT_TC		BIT(1)
-#define INTSTAT_CC		BIT(0)
+#define INTSTAT			0x030U
+#define INTSTAT_DMAE		BIT_32(28U)
+#define INTSTAT_DEBE		BIT_32(22U)
+#define INTSTAT_DCE		BIT_32(21U)
+#define INTSTAT_DTOE		BIT_32(20U)
+#define INTSTAT_CIE		BIT_32(19U)
+#define INTSTAT_CEBE		BIT_32(18U)
+#define INTSTAT_CCE		BIT_32(17U)
+#define INTSTAT_DINT		BIT_32(3U)
+#define INTSTAT_BGE		BIT_32(2U)
+#define INTSTAT_TC		BIT_32(1U)
+#define INTSTAT_CC		BIT_32(0U)
 #define CMD_ERR			(INTSTAT_CIE | INTSTAT_CEBE | INTSTAT_CCE)
 #define DATA_ERR		(INTSTAT_DMAE | INTSTAT_DEBE | INTSTAT_DCE | \
 				 INTSTAT_DTOE)
 #define DATA_COMPLETE		(INTSTAT_DINT | INTSTAT_TC)
 
-#define INTSTATEN		0x034
-#define INTSTATEN_DEBE		BIT(22)
-#define INTSTATEN_DCE		BIT(21)
-#define INTSTATEN_DTOE		BIT(20)
-#define INTSTATEN_CIE		BIT(19)
-#define INTSTATEN_CEBE		BIT(18)
-#define INTSTATEN_CCE		BIT(17)
-#define INTSTATEN_CTOE		BIT(16)
-#define INTSTATEN_CINT		BIT(8)
-#define INTSTATEN_BRR		BIT(5)
-#define INTSTATEN_BWR		BIT(4)
-#define INTSTATEN_DINT		BIT(3)
-#define INTSTATEN_TC		BIT(1)
-#define INTSTATEN_CC		BIT(0)
+#define INTSTATEN		0x034U
+#define INTSTATEN_DEBE		BIT_32(22U)
+#define INTSTATEN_DCE		BIT_32(21U)
+#define INTSTATEN_DTOE		BIT_32(20U)
+#define INTSTATEN_CIE		BIT_32(19U)
+#define INTSTATEN_CEBE		BIT_32(18U)
+#define INTSTATEN_CCE		BIT_32(17U)
+#define INTSTATEN_CTOE		BIT_32(16U)
+#define INTSTATEN_CINT		BIT_32(8U)
+#define INTSTATEN_BRR		BIT_32(5U)
+#define INTSTATEN_BWR		BIT_32(4U)
+#define INTSTATEN_DINT		BIT_32(3U)
+#define INTSTATEN_TC		BIT_32(1U)
+#define INTSTATEN_CC		BIT_32(0U)
 #define EMMC_INTSTATEN_BITS	(INTSTATEN_CC | INTSTATEN_TC | INTSTATEN_DINT | \
 				 INTSTATEN_BWR | INTSTATEN_BRR | INTSTATEN_CINT | \
 				 INTSTATEN_CTOE | INTSTATEN_CCE | INTSTATEN_CEBE | \
 				 INTSTATEN_CIE | INTSTATEN_DTOE | INTSTATEN_DCE | \
 				 INTSTATEN_DEBE)
 
-#define INTSIGEN		0x038
+#define INTSIGEN		0x038U
 
-#define WATERMARKLEV		0x044
-#define WMKLV_RD_MASK		0xff
-#define WMKLV_WR_MASK		0x00ff0000
+#define WATERMARKLEV		0x044U
+#define WMKLV_RD_MASK		GENMASK_32(7U, 0U)
+#define WMKLV_WR_MASK		GENMASK_32(23U, 16U)
 #define WMKLV_MASK		(WMKLV_RD_MASK | WMKLV_WR_MASK)
 
-#define MIXCTRL			0x048
-#define MIXCTRL_MSBSEL		BIT(5)
-#define MIXCTRL_DTDSEL		BIT(4)
-#define MIXCTRL_DDREN		BIT(3)
-#define MIXCTRL_AC12EN		BIT(2)
-#define MIXCTRL_BCEN		BIT(1)
-#define MIXCTRL_DMAEN		BIT(0)
-#define MIXCTRL_DATMASK		0x7f
+#define MIXCTRL			0x048U
+#define MIXCTRL_MSBSEL		BIT_32(5U)
+#define MIXCTRL_DTDSEL		BIT_32(4U)
+#define MIXCTRL_DDREN		BIT_32(3U)
+#define MIXCTRL_AC12EN		BIT_32(2U)
+#define MIXCTRL_BCEN		BIT_32(1U)
+#define MIXCTRL_DMAEN		BIT_32(0U)
+#define MIXCTRL_DATMASK		0x7fU
 
-#define DLLCTRL			0x060
+#define DLLCTRL			0x060U
 
-#define CLKTUNECTRLSTS		0x068
+#define CLKTUNECTRLSTS		0x068U
 
-#define VENDSPEC		0x0c0
-#define VENDSPEC_RSRV1		BIT(29)
-#define VENDSPEC_CARD_CLKEN	BIT(14)
-#define VENDSPEC_PER_CLKEN	BIT(13)
-#define VENDSPEC_AHB_CLKEN	BIT(12)
-#define VENDSPEC_IPG_CLKEN	BIT(11)
-#define VENDSPEC_AC12_CHKBUSY	BIT(3)
-#define VENDSPEC_EXTDMA		BIT(0)
+#define VENDSPEC		0x0c0U
+#define VENDSPEC_RSRV1		BIT_32(29U)
+#define VENDSPEC_CARD_CLKEN	BIT_32(14U)
+#define VENDSPEC_PER_CLKEN	BIT_32(13U)
+#define VENDSPEC_AHB_CLKEN	BIT_32(12U)
+#define VENDSPEC_IPG_CLKEN	BIT_32(11U)
+#define VENDSPEC_AC12_CHKBUSY	BIT_32(3U)
+#define VENDSPEC_EXTDMA		BIT_32(0U)
 #define VENDSPEC_INIT		(VENDSPEC_RSRV1	| VENDSPEC_CARD_CLKEN | \
 				 VENDSPEC_PER_CLKEN | VENDSPEC_AHB_CLKEN | \
 				 VENDSPEC_IPG_CLKEN | VENDSPEC_AC12_CHKBUSY | \
 				 VENDSPEC_EXTDMA)
 
-#define MMCBOOT			0x0c4
+#define MMCBOOT			0x0c4U
 
 #define mmio_clrsetbits32(addr, clear, set)	mmio_write_32(addr, (mmio_read_32(addr) & ~(clear)) | (set))
 #define mmio_clrbits32(addr, clear)		mmio_write_32(addr, mmio_read_32(addr) & ~(clear))

diff --git a/drivers/st/bsec/bsec3.c b/drivers/st/bsec/bsec3.c
index 3fdaf16..03d8928 100644
--- a/drivers/st/bsec/bsec3.c
+++ b/drivers/st/bsec/bsec3.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2024-2025, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -30,18 +30,6 @@
 #define BSEC_OTP_BANK_SHIFT		U(5)
 #define BSEC_TIMEOUT_VALUE		U(0x800000) /* ~7sec @1.2GHz */
 
-/* Magic use to indicated valid SHADOW = 'B' 'S' 'E' 'C' */
-#define BSEC_MAGIC			U(0x42534543)
-
-#define OTP_MAX_SIZE			(STM32MP2_OTP_MAX_ID + U(1))
-
-struct bsec_shadow {
-	uint32_t magic;
-	uint32_t state;
-	uint32_t value[OTP_MAX_SIZE];
-	uint32_t status[OTP_MAX_SIZE];
-};
-
 static uint32_t otp_bank(uint32_t otp)
 {
 	if (otp > STM32MP2_OTP_MAX_ID) {
@@ -167,7 +155,7 @@
 		ERROR("BSEC reset critical error 0x%x\n", status);
 		panic();
 	}
-	if ((status & BSEC_OTPSR_FUSEOK) != BSEC_OTPSR_FUSEOK) {
+	if ((status & BSEC_OTPSR_INIT_DONE) != BSEC_OTPSR_INIT_DONE) {
 		ERROR("BSEC reset critical error 0x%x\n", status);
 		panic();
 	}
@@ -467,8 +455,8 @@
 	uint32_t status = bsec_get_status();
 	uint32_t bsec_sr = mmio_read_32(BSEC_BASE + BSEC_SR);
 
-	if ((status & BSEC_OTPSR_FUSEOK) == BSEC_OTPSR_FUSEOK) {
-		/* NVSTATE is only valid if FUSEOK */
+	if ((status & BSEC_OTPSR_INIT_DONE) == BSEC_OTPSR_INIT_DONE) {
+		/* NVSTATE is only valid if INIT_DONE */
 		uint32_t nvstates = (bsec_sr & BSEC_SR_NVSTATE_MASK) >> BSEC_SR_NVSTATE_SHIFT;
 
 		if (nvstates == BSEC_SR_NVSTATE_OPEN) {

diff --git a/drivers/st/clk/clk-stm32mp2.c b/drivers/st/clk/clk-stm32mp2.c
index 12839f1..1266e00 100644
--- a/drivers/st/clk/clk-stm32mp2.c
+++ b/drivers/st/clk/clk-stm32mp2.c

@@ -105,7 +105,9 @@
 	_SPDIFSYMB,
 	_CK_PLL1,
 	_CK_PLL2,
+#if !STM32MP21
 	_CK_PLL3,
+#endif /* !STM32MP21 */
 	_CK_PLL4,
 	_CK_PLL5,
 	_CK_PLL6,
@@ -180,6 +182,9 @@
 	_CK_ICN_APB2,
 	_CK_ICN_APB3,
 	_CK_ICN_APB4,
+#if STM32MP21
+	_CK_ICN_APB5,
+#endif /* STM32MP21 */
 	_CK_ICN_APBDBG,
 	_CK_BKPSRAM,
 	_CK_BSEC,
@@ -200,51 +205,82 @@
 	_CK_GPIOG,
 	_CK_GPIOH,
 	_CK_GPIOI,
+#if !STM32MP21
 	_CK_GPIOJ,
 	_CK_GPIOK,
+#endif /* !STM32MP21 */
 	_CK_GPIOZ,
+#if STM32MP21
+	_CK_HASH1,
+	_CK_HASH2,
+#else /* STM32MP21 */
 	_CK_HASH,
+#endif /* STM32MP21 */
 	_CK_I2C1,
 	_CK_I2C2,
+#if !STM32MP23
 	_CK_I2C3,
+#endif /* !STM32MP23 */
+#if STM32MP25
 	_CK_I2C4,
 	_CK_I2C5,
 	_CK_I2C6,
+#endif /* STM32MP25 */
+#if !STM32MP21
 	_CK_I2C7,
 	_CK_I2C8,
+#endif /* !STM32MP21 */
 	_CK_IWDG1,
 	_CK_IWDG2,
 	_CK_OSPI1,
+#if !STM32MP21
 	_CK_OSPI2,
 	_CK_OSPIIOM,
+#endif /* !STM32MP21 */
 	_CK_PKA,
 	_CK_RETRAM,
+#if STM32MP21
+	_CK_RNG1,
+	_CK_RNG2,
+#else /* STM32MP21 */
 	_CK_RNG,
+#endif /* STM32MP21 */
 	_CK_RTC,
 	_CK_SAES,
 	_CK_SDMMC1,
 	_CK_SDMMC2,
 	_CK_SRAM1,
+#if !STM32MP21
 	_CK_SRAM2,
+#endif /* !STM32MP21 */
 	_CK_STGEN,
 	_CK_SYSCPU1,
 	_CK_SYSRAM,
 	_CK_UART4,
 	_CK_UART5,
 	_CK_UART7,
+#if STM32MP25
 	_CK_UART8,
 	_CK_UART9,
+#endif /* STM32MP25 */
 	_CK_USART1,
 	_CK_USART2,
 	_CK_USART3,
 	_CK_USART6,
+#if STM32MP21
+	_CK_USBHEHCI,
+	_CK_USBHOHCI,
+#else /* STM32MP21 */
 	_CK_USB2EHCI,
 	_CK_USB2OHCI,
+#endif /* STM32MP21 */
 	_CK_USB2PHY1,
 	_CK_USB2PHY2,
+#if !STM32MP21
 	_CK_USB3DR,
 	_CK_USB3PCIEPHY,
 	_CK_USBTC,
+#endif /* !STM32MP21 */
 
 	CK_LAST
 };
@@ -271,6 +307,7 @@
 	_CK_FLEXGEN_58, _CK_HSE
 };
 
+#if !STM32MP21
 static const uint16_t usb3pciphy_src[] = {
 	_CK_FLEXGEN_34, _CK_HSE
 };
@@ -278,6 +315,7 @@
 static const uint16_t d3per_src[] = {
 	_CK_MSI, _CK_LSI, _CK_LSE
 };
+#endif /* !STM32MP21 */
 
 #define MUX_CONF(id, src, _offset, _shift, _witdh)[id] = {\
 	.id_parents	= src,\
@@ -290,7 +328,7 @@
 	},\
 }
 
-static const struct parent_cfg parent_mp25[] = {
+static const struct parent_cfg parent_mp2[] = {
 	MUX_CONF(MUX_MUXSEL0, muxsel_src, RCC_MUXSELCFGR, 0, 2),
 	MUX_CONF(MUX_MUXSEL1, muxsel_src, RCC_MUXSELCFGR, 4, 2),
 	MUX_CONF(MUX_MUXSEL2, muxsel_src, RCC_MUXSELCFGR, 8, 2),
@@ -303,8 +341,10 @@
 	MUX_CONF(MUX_RTC, rtc_src, RCC_BDCR, 16, 2),
 	MUX_CONF(MUX_USB2PHY1, usb2phy1_src, RCC_USB2PHY1CFGR, 15, 1),
 	MUX_CONF(MUX_USB2PHY2, usb2phy2_src, RCC_USB2PHY2CFGR, 15, 1),
+#if !STM32MP21
 	MUX_CONF(MUX_USB3PCIEPHY, usb3pciphy_src, RCC_USB3PCIEPHYCFGR, 15, 1),
 	MUX_CONF(MUX_D3PER, d3per_src, RCC_D3DCR, 16, 2),
+#endif /* !STM32MP21 */
 };
 
 /* GATES */
@@ -324,15 +364,26 @@
 	GATE_SYSRAM,
 	GATE_RETRAM,
 	GATE_SRAM1,
+#if !STM32MP21
 	GATE_SRAM2,
+#endif /* !STM32MP21 */
 
 	GATE_DDRPHYC,
 	GATE_SYSCPU1,
 	GATE_CRC,
+#if !STM32MP21
 	GATE_OSPIIOM,
+#endif /* !STM32MP21 */
 	GATE_BKPSRAM,
+#if STM32MP21
+	GATE_HASH1,
+	GATE_HASH2,
+	GATE_RNG1,
+	GATE_RNG2,
+#else /* STM32MP21 */
 	GATE_HASH,
 	GATE_RNG,
+#endif /* STM32MP21 */
 	GATE_CRYP1,
 	GATE_CRYP2,
 	GATE_SAES,
@@ -347,18 +398,27 @@
 	GATE_GPIOG,
 	GATE_GPIOH,
 	GATE_GPIOI,
+#if !STM32MP21
 	GATE_GPIOJ,
 	GATE_GPIOK,
+#endif /* !STM32MP21 */
 	GATE_GPIOZ,
 	GATE_RTC,
 
 	GATE_DDRCP,
 
 	/* WARNING 2 CLOCKS FOR ONE GATE */
+#if STM32MP21
+	GATE_USBHOHCI,
+	GATE_USBHEHCI,
+#else /* STM32MP21 */
 	GATE_USB2OHCI,
 	GATE_USB2EHCI,
+#endif /* STM32MP21 */
 
+#if !STM32MP21
 	GATE_USB3DR,
+#endif /* !STM32MP21 */
 
 	GATE_BSEC,
 	GATE_IWDG1,
@@ -373,22 +433,34 @@
 	GATE_UART5,
 	GATE_I2C1,
 	GATE_I2C2,
+#if !STM32MP23
 	GATE_I2C3,
+#endif /* !STM32MP23 */
+#if STM32MP25
 	GATE_I2C5,
 	GATE_I2C4,
 	GATE_I2C6,
+#endif /* STM32MP25 */
+#if !STM32MP21
 	GATE_I2C7,
+#endif /* !STM32MP21 */
 	GATE_USART1,
 	GATE_USART6,
 	GATE_UART7,
+#if STM32MP25
 	GATE_UART8,
 	GATE_UART9,
+#endif /* STM32MP25 */
 	GATE_STGEN,
+#if !STM32MP21
 	GATE_USB3PCIEPHY,
 	GATE_USBTC,
 	GATE_I2C8,
+#endif /* !STM32MP21 */
 	GATE_OSPI1,
+#if !STM32MP21
 	GATE_OSPI2,
+#endif /* !STM32MP21 */
 	GATE_FMC,
 	GATE_SDMMC1,
 	GATE_SDMMC2,
@@ -403,30 +475,57 @@
 	.set_clr	= (_offset_clr),\
 }
 
-static const struct gate_cfg gates_mp25[LAST_GATE] = {
+static const struct gate_cfg gates_mp2[LAST_GATE] = {
 	GATE_CFG(GATE_LSE,		RCC_BDCR,		0,	0),
+#if STM32MP21
+	GATE_CFG(GATE_LSI,		RCC_LSICR,		0,	0),
+#else /* STM32MP21 */
 	GATE_CFG(GATE_LSI,		RCC_BDCR,		9,	0),
+#endif /* STM32MP21 */
 	GATE_CFG(GATE_RTCCK,		RCC_BDCR,		20,	0),
 	GATE_CFG(GATE_HSI,		RCC_OCENSETR,		0,	1),
 	GATE_CFG(GATE_HSE,		RCC_OCENSETR,		8,	1),
+#if STM32MP21
+	GATE_CFG(GATE_MSI,		RCC_OCENSETR,		2,	0),
+#else /* STM32MP21 */
 	GATE_CFG(GATE_MSI,		RCC_D3DCR,		0,	0),
+#endif /* STM32MP21 */
 
+#if STM32MP21
+	GATE_CFG(GATE_LSI_RDY,		RCC_LSICR,		1,	0),
+#else /* STM32MP21 */
 	GATE_CFG(GATE_LSI_RDY,		RCC_BDCR,		10,	0),
+#endif /* STM32MP21 */
 	GATE_CFG(GATE_LSE_RDY,		RCC_BDCR,		2,	0),
+#if STM32MP21
+	GATE_CFG(GATE_MSI_RDY,		RCC_OCRDYR,		2,	0),
+#else /* STM32MP21 */
 	GATE_CFG(GATE_MSI_RDY,		RCC_D3DCR,		2,	0),
+#endif /* STM32MP21 */
 	GATE_CFG(GATE_HSE_RDY,		RCC_OCRDYR,		8,	0),
 	GATE_CFG(GATE_HSI_RDY,		RCC_OCRDYR,		0,	0),
 	GATE_CFG(GATE_SYSRAM,		RCC_SYSRAMCFGR,		1,	0),
 	GATE_CFG(GATE_RETRAM,		RCC_RETRAMCFGR,		1,	0),
 	GATE_CFG(GATE_SRAM1,		RCC_SRAM1CFGR,		1,	0),
+#if !STM32MP21
 	GATE_CFG(GATE_SRAM2,		RCC_SRAM2CFGR,		1,	0),
+#endif /* !STM32MP21 */
 	GATE_CFG(GATE_DDRPHYC,		RCC_DDRPHYCAPBCFGR,	1,	0),
 	GATE_CFG(GATE_SYSCPU1,		RCC_SYSCPU1CFGR,	1,	0),
 	GATE_CFG(GATE_CRC,		RCC_CRCCFGR,		1,	0),
+#if !STM32MP21
 	GATE_CFG(GATE_OSPIIOM,		RCC_OSPIIOMCFGR,	1,	0),
+#endif /* !STM32MP21 */
 	GATE_CFG(GATE_BKPSRAM,		RCC_BKPSRAMCFGR,	1,	0),
+#if STM32MP21
+	GATE_CFG(GATE_HASH1,		RCC_HASH1CFGR,		1,	0),
+	GATE_CFG(GATE_HASH2,		RCC_HASH2CFGR,		1,	0),
+	GATE_CFG(GATE_RNG1,		RCC_RNG1CFGR,		1,	0),
+	GATE_CFG(GATE_RNG2,		RCC_RNG2CFGR,		1,	0),
+#else /* STM32MP21 */
 	GATE_CFG(GATE_HASH,		RCC_HASHCFGR,		1,	0),
 	GATE_CFG(GATE_RNG,		RCC_RNGCFGR,		1,	0),
+#endif /* STM32MP21 */
 	GATE_CFG(GATE_CRYP1,		RCC_CRYP1CFGR,		1,	0),
 	GATE_CFG(GATE_CRYP2,		RCC_CRYP2CFGR,		1,	0),
 	GATE_CFG(GATE_SAES,		RCC_SAESCFGR,		1,	0),
@@ -440,16 +539,23 @@
 	GATE_CFG(GATE_GPIOG,		RCC_GPIOGCFGR,		1,	0),
 	GATE_CFG(GATE_GPIOH,		RCC_GPIOHCFGR,		1,	0),
 	GATE_CFG(GATE_GPIOI,		RCC_GPIOICFGR,		1,	0),
+#if !STM32MP21
 	GATE_CFG(GATE_GPIOJ,		RCC_GPIOJCFGR,		1,	0),
 	GATE_CFG(GATE_GPIOK,		RCC_GPIOKCFGR,		1,	0),
+#endif /* !STM32MP21 */
 	GATE_CFG(GATE_GPIOZ,		RCC_GPIOZCFGR,		1,	0),
 	GATE_CFG(GATE_RTC,		RCC_RTCCFGR,		1,	0),
 	GATE_CFG(GATE_DDRCP,		RCC_DDRCPCFGR,		1,	0),
 
 	/* WARNING 2 CLOCKS FOR ONE GATE */
+#if STM32MP21
+	GATE_CFG(GATE_USBHOHCI,		RCC_USBHCFGR,		1,	0),
+	GATE_CFG(GATE_USBHEHCI,		RCC_USBHCFGR,		1,	0),
+#else /* STM32MP21 */
 	GATE_CFG(GATE_USB2OHCI,		RCC_USB2CFGR,		1,	0),
 	GATE_CFG(GATE_USB2EHCI,		RCC_USB2CFGR,		1,	0),
 	GATE_CFG(GATE_USB3DR,		RCC_USB3DRCFGR,		1,	0),
+#endif /* STM32MP21 */
 	GATE_CFG(GATE_BSEC,		RCC_BSECCFGR,		1,	0),
 	GATE_CFG(GATE_IWDG1,		RCC_IWDG1CFGR,		1,	0),
 	GATE_CFG(GATE_IWDG2,		RCC_IWDG2CFGR,		1,	0),
@@ -461,22 +567,34 @@
 	GATE_CFG(GATE_UART5,		RCC_UART5CFGR,		1,	0),
 	GATE_CFG(GATE_I2C1,		RCC_I2C1CFGR,		1,	0),
 	GATE_CFG(GATE_I2C2,		RCC_I2C2CFGR,		1,	0),
+#if !STM32MP23
 	GATE_CFG(GATE_I2C3,		RCC_I2C3CFGR,		1,	0),
+#endif /* !STM32MP23 */
+#if STM32MP25
 	GATE_CFG(GATE_I2C5,		RCC_I2C5CFGR,		1,	0),
 	GATE_CFG(GATE_I2C4,		RCC_I2C4CFGR,		1,	0),
 	GATE_CFG(GATE_I2C6,		RCC_I2C6CFGR,		1,	0),
+#endif /* STM32MP25 */
+#if !STM32MP21
 	GATE_CFG(GATE_I2C7,		RCC_I2C7CFGR,		1,	0),
+#endif /* !STM32MP21 */
 	GATE_CFG(GATE_USART1,		RCC_USART1CFGR,		1,	0),
 	GATE_CFG(GATE_USART6,		RCC_USART6CFGR,		1,	0),
 	GATE_CFG(GATE_UART7,		RCC_UART7CFGR,		1,	0),
+#if STM32MP25
 	GATE_CFG(GATE_UART8,		RCC_UART8CFGR,		1,	0),
 	GATE_CFG(GATE_UART9,		RCC_UART9CFGR,		1,	0),
+#endif /* STM32MP25 */
 	GATE_CFG(GATE_STGEN,		RCC_STGENCFGR,		1,	0),
+#if !STM32MP21
 	GATE_CFG(GATE_USB3PCIEPHY,	RCC_USB3PCIEPHYCFGR,	1,	0),
 	GATE_CFG(GATE_USBTC,		RCC_USBTCCFGR,		1,	0),
 	GATE_CFG(GATE_I2C8,		RCC_I2C8CFGR,		1,	0),
+#endif /* !STM32MP21 */
 	GATE_CFG(GATE_OSPI1,		RCC_OSPI1CFGR,		1,	0),
+#if !STM32MP21
 	GATE_CFG(GATE_OSPI2,		RCC_OSPI2CFGR,		1,	0),
+#endif /* !STM32MP21 */
 	GATE_CFG(GATE_FMC,		RCC_FMCCFGR,		1,	0),
 	GATE_CFG(GATE_SDMMC1,		RCC_SDMMC1CFGR,		1,	0),
 	GATE_CFG(GATE_SDMMC2,		RCC_SDMMC2CFGR,		1,	0),
@@ -499,11 +617,14 @@
 		.bitrdy	= _bitrdy,\
 }
 
-static const struct div_cfg dividers_mp25[] = {
+static const struct div_cfg dividers_mp2[] = {
 	DIV_CFG(DIV_APB1, RCC_APB1DIVR, 0, 3, 0, apb_div_table, 31),
 	DIV_CFG(DIV_APB2, RCC_APB2DIVR, 0, 3, 0, apb_div_table, 31),
 	DIV_CFG(DIV_APB3, RCC_APB3DIVR, 0, 3, 0, apb_div_table, 31),
 	DIV_CFG(DIV_APB4, RCC_APB4DIVR, 0, 3, 0, apb_div_table, 31),
+#if STM32MP21
+	DIV_CFG(DIV_APB5, RCC_APB5DIVR, 0, 3, 0, apb_div_table, 31),
+#endif /* STM32MP21 */
 	DIV_CFG(DIV_APBDBG, RCC_APBDBGDIVR, 0, 3, 0, apb_div_table, 31),
 	DIV_CFG(DIV_LSMCU, RCC_LSMCUDIVR, 0, 1, 0, NULL, 31),
 	DIV_CFG(DIV_RTC, RCC_RTCDIVR, 0, 6, 0, NULL, 0),
@@ -520,7 +641,7 @@
 	NB_OSCILLATOR
 };
 
-static struct clk_oscillator_data stm32mp25_osc_data[] = {
+static struct clk_oscillator_data stm32mp2_osc_data[] = {
 	OSCILLATOR(OSC_HSI, _CK_HSI, "clk-hsi", GATE_HSI, GATE_HSI_RDY,
 		   NULL, NULL, NULL),
 
@@ -551,7 +672,7 @@
 static const char *clk_stm32_get_oscillator_name(enum stm32_osc id)
 {
 	if (id < NB_OSCILLATOR) {
-		return stm32mp25_osc_data[id].name;
+		return stm32mp2_osc_data[id].name;
 	}
 
 	return NULL;
@@ -590,10 +711,12 @@
 		.reg_pllxcfgr1 = (_reg),\
 	}
 
-static const struct stm32_clk_pll stm32mp25_clk_pll[_PLL_NB] = {
+static const struct stm32_clk_pll stm32mp2_clk_pll[_PLL_NB] = {
 	CLK_PLL_CFG(_PLL1, _CK_PLL1, A35_SS_CHGCLKREQ),
 	CLK_PLL_CFG(_PLL2, _CK_PLL2, RCC_PLL2CFGR1),
+#if !STM32MP21
 	CLK_PLL_CFG(_PLL3, _CK_PLL3, RCC_PLL3CFGR1),
+#endif /* !STM32MP21 */
 	CLK_PLL_CFG(_PLL4, _CK_PLL4, RCC_PLL4CFGR1),
 	CLK_PLL_CFG(_PLL5, _CK_PLL5, RCC_PLL5CFGR1),
 	CLK_PLL_CFG(_PLL6, _CK_PLL6, RCC_PLL6CFGR1),
@@ -603,7 +726,7 @@
 
 static const struct stm32_clk_pll *clk_stm32_pll_data(unsigned int idx)
 {
-	return &stm32mp25_clk_pll[idx];
+	return &stm32mp2_clk_pll[idx];
 }
 
 static unsigned long clk_get_pll_fvco(struct stm32_clk_priv *priv,
@@ -958,6 +1081,7 @@
 #define RCC_16_MHZ	UL(16000000)
 
 #ifdef IMAGE_BL2
+#if !STM32MP21
 static int clk_stm32_osc_msi_set_rate(struct stm32_clk_priv *priv, int id, unsigned long rate,
 				      unsigned long prate)
 {
@@ -982,12 +1106,16 @@
 
 	return ret;
 }
+#endif /* !STM32MP21 */
 #endif /* IMAGE_BL2 */
 
 static unsigned long clk_stm32_osc_msi_recalc_rate(struct stm32_clk_priv *priv,
 						   int id __unused,
 						   unsigned long prate __unused)
 {
+#if STM32MP21
+	return RCC_16_MHZ;
+#else /* STM32MP21 */
 	uintptr_t address = priv->base + RCC_BDCR;
 
 	if ((mmio_read_32(address) & RCC_BDCR_MSIFREQSEL) == 0U) {
@@ -995,6 +1123,7 @@
 	} else {
 		return RCC_16_MHZ;
 	}
+#endif /* STM32MP21 */
 }
 
 static const struct stm32_clk_ops clk_stm32_osc_msi_ops = {
@@ -1039,10 +1168,10 @@
 	STM32_OSC_MSI_OPS,
 	STM32_RTC_OPS,
 
-	MP25_LAST_OPS
+	MP2_LAST_OPS
 };
 
-static const struct stm32_clk_ops *ops_array_mp25[MP25_LAST_OPS] = {
+static const struct stm32_clk_ops *ops_array_mp2[MP2_LAST_OPS] = {
 	[NO_OPS] =  NULL,
 	[FIXED_FACTOR_OPS] = &clk_fixed_factor_ops,
 	[GATE_OPS] = &clk_gate_ops,
@@ -1061,7 +1190,7 @@
 	[STM32_RTC_OPS] = &clk_stm32_rtc_ops
 };
 
-static const struct clk_stm32 stm32mp25_clk[CK_LAST] = {
+static const struct clk_stm32 stm32mp2_clk[CK_LAST] = {
 	CLK_FIXED_RATE(_CK_0_MHZ, _NO_ID, RCC_0_MHZ),
 
 	/* ROOT CLOCKS */
@@ -1081,7 +1210,9 @@
 	CLK_PLL1(_CK_PLL1, PLL1_CK, MUX(MUX_MUXSEL5), _PLL1, 0),
 
 	CLK_PLL(_CK_PLL2, PLL2_CK, MUX(MUX_MUXSEL6), _PLL2, 0),
+#if !STM32MP21
 	CLK_PLL(_CK_PLL3, PLL3_CK, MUX(MUX_MUXSEL7), _PLL3, 0),
+#endif /* !STM32MP21 */
 	CLK_PLL(_CK_PLL4, PLL4_CK, MUX(MUX_MUXSEL0), _PLL4, 0),
 	CLK_PLL(_CK_PLL5, PLL5_CK, MUX(MUX_MUXSEL1), _PLL5, 0),
 	CLK_PLL(_CK_PLL6, PLL6_CK, MUX(MUX_MUXSEL2), _PLL6, 0),
@@ -1158,21 +1289,35 @@
 	STM32_DIV(_CK_ICN_APB2, CK_ICN_APB2, _CK_ICN_LS_MCU, 0, DIV_APB2),
 	STM32_DIV(_CK_ICN_APB3, CK_ICN_APB3, _CK_ICN_LS_MCU, 0, DIV_APB3),
 	STM32_DIV(_CK_ICN_APB4, CK_ICN_APB4, _CK_ICN_LS_MCU, 0, DIV_APB4),
+#if STM32MP21
+	STM32_DIV(_CK_ICN_APB5, CK_ICN_APB5, _CK_ICN_LS_MCU, 0, DIV_APB5),
+#endif /* STM32MP21 */
 	STM32_DIV(_CK_ICN_APBDBG, CK_ICN_APBDBG, _CK_ICN_LS_MCU, 0, DIV_APBDBG),
 
 	/* KERNEL CLOCK */
 	STM32_GATE(_CK_SYSRAM, CK_BUS_SYSRAM, _CK_ICN_HS_MCU, 0, GATE_SYSRAM),
 	STM32_GATE(_CK_RETRAM, CK_BUS_RETRAM, _CK_ICN_HS_MCU, 0, GATE_RETRAM),
 	STM32_GATE(_CK_SRAM1, CK_BUS_SRAM1, _CK_ICN_HS_MCU, CLK_IS_CRITICAL, GATE_SRAM1),
+#if !STM32MP21
 	STM32_GATE(_CK_SRAM2, CK_BUS_SRAM2, _CK_ICN_HS_MCU, CLK_IS_CRITICAL, GATE_SRAM2),
+#endif /* !STM32MP21 */
 
 	STM32_GATE(_CK_DDRPHYC, CK_BUS_DDRPHYC, _CK_ICN_LS_MCU, 0, GATE_DDRPHYC),
 	STM32_GATE(_CK_SYSCPU1, CK_BUS_SYSCPU1, _CK_ICN_LS_MCU, 0, GATE_SYSCPU1),
 	STM32_GATE(_CK_CRC, CK_BUS_CRC, _CK_ICN_LS_MCU, 0, GATE_CRC),
+#if !STM32MP21
 	STM32_GATE(_CK_OSPIIOM, CK_BUS_OSPIIOM, _CK_ICN_LS_MCU, 0, GATE_OSPIIOM),
+#endif /* !STM32MP21 */
 	STM32_GATE(_CK_BKPSRAM, CK_BUS_BKPSRAM, _CK_ICN_LS_MCU, 0, GATE_BKPSRAM),
+#if STM32MP21
+	STM32_GATE(_CK_HASH1, CK_BUS_HASH1, _CK_ICN_LS_MCU, 0, GATE_HASH1),
+	STM32_GATE(_CK_HASH2, CK_BUS_HASH2, _CK_ICN_LS_MCU, 0, GATE_HASH2),
+	STM32_GATE(_CK_RNG1, CK_BUS_RNG1, _CK_ICN_LS_MCU, 0, GATE_RNG1),
+	STM32_GATE(_CK_RNG2, CK_BUS_RNG2, _CK_ICN_LS_MCU, 0, GATE_RNG2),
+#else /* STM32MP21 */
 	STM32_GATE(_CK_HASH, CK_BUS_HASH, _CK_ICN_LS_MCU, 0, GATE_HASH),
 	STM32_GATE(_CK_RNG, CK_BUS_RNG, _CK_ICN_LS_MCU, 0, GATE_RNG),
+#endif /* STM32MP21 */
 	STM32_GATE(_CK_CRYP1, CK_BUS_CRYP1, _CK_ICN_LS_MCU, 0, GATE_CRYP1),
 	STM32_GATE(_CK_CRYP2, CK_BUS_CRYP2, _CK_ICN_LS_MCU, 0, GATE_CRYP2),
 	STM32_GATE(_CK_SAES, CK_BUS_SAES, _CK_ICN_LS_MCU, 0, GATE_SAES),
@@ -1187,18 +1332,27 @@
 	STM32_GATE(_CK_GPIOG, CK_BUS_GPIOG, _CK_ICN_LS_MCU, 0, GATE_GPIOG),
 	STM32_GATE(_CK_GPIOH, CK_BUS_GPIOH, _CK_ICN_LS_MCU, 0, GATE_GPIOH),
 	STM32_GATE(_CK_GPIOI, CK_BUS_GPIOI, _CK_ICN_LS_MCU, 0, GATE_GPIOI),
+#if !STM32MP21
 	STM32_GATE(_CK_GPIOJ, CK_BUS_GPIOJ, _CK_ICN_LS_MCU, 0, GATE_GPIOJ),
 	STM32_GATE(_CK_GPIOK, CK_BUS_GPIOK, _CK_ICN_LS_MCU, 0, GATE_GPIOK),
+#endif /* !STM32MP21 */
 	STM32_GATE(_CK_GPIOZ, CK_BUS_GPIOZ, _CK_ICN_LS_MCU, 0, GATE_GPIOZ),
 	STM32_GATE(_CK_RTC, CK_BUS_RTC, _CK_ICN_LS_MCU, 0, GATE_RTC),
 
 	STM32_GATE(_CK_DDRCP, CK_BUS_DDR, _CK_ICN_DDR, 0, GATE_DDRCP),
 
 	/* WARNING 2 CLOCKS FOR ONE GATE */
+#if STM32MP21
+	STM32_GATE(_CK_USBHOHCI, CK_BUS_USBHOHCI, _CK_ICN_HSL, 0, GATE_USBHOHCI),
+	STM32_GATE(_CK_USBHEHCI, CK_BUS_USBHEHCI, _CK_ICN_HSL, 0, GATE_USBHEHCI),
+#else /* STM32MP21 */
 	STM32_GATE(_CK_USB2OHCI, CK_BUS_USB2OHCI, _CK_ICN_HSL, 0, GATE_USB2OHCI),
 	STM32_GATE(_CK_USB2EHCI, CK_BUS_USB2EHCI, _CK_ICN_HSL, 0, GATE_USB2EHCI),
+#endif /* STM32MP21 */
 
+#if !STM32MP21
 	STM32_GATE(_CK_USB3DR, CK_BUS_USB3DR, _CK_ICN_HSL, 0, GATE_USB3DR),
+#endif /* !STM32MP21 */
 
 	STM32_GATE(_CK_BSEC, CK_BUS_BSEC, _CK_ICN_APB3, 0, GATE_BSEC),
 	STM32_GATE(_CK_IWDG1, CK_BUS_IWDG1, _CK_ICN_APB3, 0, GATE_IWDG1),
@@ -1211,24 +1365,41 @@
 	STM32_GATE(_CK_UART4, CK_KER_UART4, _CK_FLEXGEN_08, 0, GATE_UART4),
 	STM32_GATE(_CK_USART3, CK_KER_USART3, _CK_FLEXGEN_09, 0, GATE_USART3),
 	STM32_GATE(_CK_UART5, CK_KER_UART5, _CK_FLEXGEN_09, 0, GATE_UART5),
+#if STM32MP21
+	STM32_GATE(_CK_I2C1, CK_KER_I2C1, _CK_FLEXGEN_13, 0, GATE_I2C1),
+	STM32_GATE(_CK_I2C2, CK_KER_I2C2, _CK_FLEXGEN_13, 0, GATE_I2C2),
+	STM32_GATE(_CK_USART1, CK_KER_USART1, _CK_FLEXGEN_18, 0, GATE_USART1),
+	STM32_GATE(_CK_USART6, CK_KER_USART6, _CK_FLEXGEN_19, 0, GATE_USART6),
+	STM32_GATE(_CK_UART7, CK_KER_UART7, _CK_FLEXGEN_20, 0, GATE_UART7),
+	STM32_GATE(_CK_I2C3, CK_KER_I2C3, _CK_FLEXGEN_38, 0, GATE_I2C3),
+#else /* STM32MP21 */
 	STM32_GATE(_CK_I2C1, CK_KER_I2C1, _CK_FLEXGEN_12, 0, GATE_I2C1),
 	STM32_GATE(_CK_I2C2, CK_KER_I2C2, _CK_FLEXGEN_12, 0, GATE_I2C2),
+#if STM32MP25
 	STM32_GATE(_CK_I2C3, CK_KER_I2C3, _CK_FLEXGEN_13, 0, GATE_I2C3),
 	STM32_GATE(_CK_I2C5, CK_KER_I2C5, _CK_FLEXGEN_13, 0, GATE_I2C5),
 	STM32_GATE(_CK_I2C4, CK_KER_I2C4, _CK_FLEXGEN_14, 0, GATE_I2C4),
 	STM32_GATE(_CK_I2C6, CK_KER_I2C6, _CK_FLEXGEN_14, 0, GATE_I2C6),
+#endif /* STM32MP25 */
 	STM32_GATE(_CK_I2C7, CK_KER_I2C7, _CK_FLEXGEN_15, 0, GATE_I2C7),
 	STM32_GATE(_CK_USART1, CK_KER_USART1, _CK_FLEXGEN_19, 0, GATE_USART1),
 	STM32_GATE(_CK_USART6, CK_KER_USART6, _CK_FLEXGEN_20, 0, GATE_USART6),
 	STM32_GATE(_CK_UART7, CK_KER_UART7, _CK_FLEXGEN_21, 0, GATE_UART7),
+#if STM32MP25
 	STM32_GATE(_CK_UART8, CK_KER_UART8, _CK_FLEXGEN_21, 0, GATE_UART8),
 	STM32_GATE(_CK_UART9, CK_KER_UART9, _CK_FLEXGEN_22, 0, GATE_UART9),
+#endif /* STM32MP25 */
+#endif /* STM32MP21 */
 	STM32_GATE(_CK_STGEN, CK_KER_STGEN, _CK_FLEXGEN_33, 0, GATE_STGEN),
+#if !STM32MP21
 	STM32_GATE(_CK_USB3PCIEPHY, CK_KER_USB3PCIEPHY, _CK_FLEXGEN_34, 0, GATE_USB3PCIEPHY),
 	STM32_GATE(_CK_USBTC, CK_KER_USBTC, _CK_FLEXGEN_35, 0, GATE_USBTC),
 	STM32_GATE(_CK_I2C8, CK_KER_I2C8, _CK_FLEXGEN_38, 0, GATE_I2C8),
+#endif /* !STM32MP21 */
 	STM32_GATE(_CK_OSPI1, CK_KER_OSPI1, _CK_FLEXGEN_48, 0, GATE_OSPI1),
+#if !STM32MP21
 	STM32_GATE(_CK_OSPI2, CK_KER_OSPI2, _CK_FLEXGEN_49, 0, GATE_OSPI2),
+#endif /* !STM32MP21 */
 	STM32_GATE(_CK_FMC, CK_KER_FMC, _CK_FLEXGEN_50, 0, GATE_FMC),
 	STM32_GATE(_CK_SDMMC1, CK_KER_SDMMC1, _CK_FLEXGEN_51, 0, GATE_SDMMC1),
 	STM32_GATE(_CK_SDMMC2, CK_KER_SDMMC2, _CK_FLEXGEN_52, 0, GATE_SDMMC2),
@@ -1240,7 +1411,9 @@
 	CLKSRC_CA35SS,
 	CLKSRC_PLL1,
 	CLKSRC_PLL2,
+#if !STM32MP21
 	CLKSRC_PLL3,
+#endif /* !STM32MP21 */
 	CLKSRC_PLL4,
 	CLKSRC_PLL5,
 	CLKSRC_PLL6,
@@ -1656,6 +1829,11 @@
 	int err;
 
 	for (i = _PLL1; i < _PLL_NB; i++) {
+#if STM32MP21
+		if (i == _PLL3) {
+			continue;
+		}
+#endif
 		err = clk_stm32_pll_init(priv, i);
 		if (err) {
 			return err;
@@ -1886,6 +2064,7 @@
 
 static void stm32_enable_oscillator_msi(struct stm32_clk_priv *priv)
 {
+#if !STM32MP21
 	struct stm32_clk_platdata *pdata = priv->pdata;
 	struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_MSI];
 	int err;
@@ -1896,6 +2075,7 @@
 			    osci->freq / 1000000U);
 		panic();
 	}
+#endif /* !STM32MP21 */
 
 	_clk_stm32_enable(priv, _CK_MSI);
 }
@@ -2204,6 +2384,11 @@
 		int subnode = 0;
 		int err = 0;
 
+#if STM32MP21
+		if (i == _PLL3) {
+			continue;
+		}
+#endif
 		snprintf(name, sizeof(name), "st,pll-%u", i + 1);
 
 		subnode = fdt_subnode_offset(fdt, node, name);
@@ -2266,49 +2451,53 @@
 }
 #endif /* IMAGE_BL2 */
 
-static struct stm32_osci_dt_cfg mp25_osci[NB_OSCILLATOR];
+static struct stm32_osci_dt_cfg mp2_osci[NB_OSCILLATOR];
 
-static struct stm32_pll_dt_cfg mp25_pll[_PLL_NB];
+static struct stm32_pll_dt_cfg mp2_pll[_PLL_NB];
 
 #define DT_FLEXGEN_CLK_MAX	64
-static uint32_t mp25_flexgen[DT_FLEXGEN_CLK_MAX];
+static uint32_t mp2_flexgen[DT_FLEXGEN_CLK_MAX];
 
+#if STM32MP21
+#define DT_BUS_CLK_MAX		7
+#else /* STM32MP21 */
 #define DT_BUS_CLK_MAX		6
-static uint32_t mp25_busclk[DT_BUS_CLK_MAX];
+#endif /* STM32MP21 */
+static uint32_t mp2_busclk[DT_BUS_CLK_MAX];
 
 #define DT_KERNEL_CLK_MAX	20
-static uint32_t mp25_kernelclk[DT_KERNEL_CLK_MAX];
+static uint32_t mp2_kernelclk[DT_KERNEL_CLK_MAX];
 
-static struct stm32_clk_platdata stm32mp25_pdata = {
-	.osci = mp25_osci,
+static struct stm32_clk_platdata stm32mp2_pdata = {
+	.osci = mp2_osci,
 	.nosci = NB_OSCILLATOR,
-	.pll = mp25_pll,
+	.pll = mp2_pll,
 	.npll = _PLL_NB,
-	.flexgen = mp25_flexgen,
+	.flexgen = mp2_flexgen,
 	.nflexgen = DT_FLEXGEN_CLK_MAX,
-	.busclk	= mp25_busclk,
+	.busclk	= mp2_busclk,
 	.nbusclk = DT_BUS_CLK_MAX,
-	.kernelclk = mp25_kernelclk,
+	.kernelclk = mp2_kernelclk,
 	.nkernelclk = DT_KERNEL_CLK_MAX,
 };
 
-static uint8_t refcounts_mp25[CK_LAST];
+static uint8_t refcounts_mp2[CK_LAST];
 
-static struct stm32_clk_priv stm32mp25_clock_data = {
+static struct stm32_clk_priv stm32mp2_clock_data = {
 	.base		= RCC_BASE,
-	.num		= ARRAY_SIZE(stm32mp25_clk),
-	.clks		= stm32mp25_clk,
-	.parents	= parent_mp25,
-	.nb_parents	= ARRAY_SIZE(parent_mp25),
-	.gates		= gates_mp25,
-	.nb_gates	= ARRAY_SIZE(gates_mp25),
-	.div		= dividers_mp25,
-	.nb_div		= ARRAY_SIZE(dividers_mp25),
-	.osci_data	= stm32mp25_osc_data,
-	.nb_osci_data	= ARRAY_SIZE(stm32mp25_osc_data),
-	.gate_refcounts	= refcounts_mp25,
-	.pdata		= &stm32mp25_pdata,
-	.ops_array	= ops_array_mp25,
+	.num		= ARRAY_SIZE(stm32mp2_clk),
+	.clks		= stm32mp2_clk,
+	.parents	= parent_mp2,
+	.nb_parents	= ARRAY_SIZE(parent_mp2),
+	.gates		= gates_mp2,
+	.nb_gates	= ARRAY_SIZE(gates_mp2),
+	.div		= dividers_mp2,
+	.nb_div		= ARRAY_SIZE(dividers_mp2),
+	.osci_data	= stm32mp2_osc_data,
+	.nb_osci_data	= ARRAY_SIZE(stm32mp2_osc_data),
+	.gate_refcounts	= refcounts_mp2,
+	.pdata		= &stm32mp2_pdata,
+	.ops_array	= ops_array_mp2,
 };
 
 int stm32mp2_clk_init(void)
@@ -2317,13 +2506,13 @@
 	int ret;
 
 #ifdef IMAGE_BL2
-	ret = stm32_clk_parse_fdt(&stm32mp25_pdata);
+	ret = stm32_clk_parse_fdt(&stm32mp2_pdata);
 	if (ret != 0) {
 		return ret;
 	}
 #endif
 
-	ret = clk_stm32_init(&stm32mp25_clock_data, base);
+	ret = clk_stm32_init(&stm32mp2_clock_data, base);
 	if (ret != 0) {
 		return ret;
 	}

diff --git a/drivers/st/crypto/stm32_saes.c b/drivers/st/crypto/stm32_saes.c
index f4da571..547ff89 100644
--- a/drivers/st/crypto/stm32_saes.c
+++ b/drivers/st/crypto/stm32_saes.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2022-2025, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -211,9 +211,11 @@
 	uint64_t timeout;
 
 	/* Reset IP */
-	mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
-	udelay(SAES_RESET_DELAY);
-	mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
+	if ((mmio_read_32(ctx->base + _SAES_SR) & _SAES_SR_BUSY) != _SAES_SR_BUSY) {
+		mmio_setbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
+		udelay(SAES_RESET_DELAY);
+		mmio_clrbits_32(ctx->base + _SAES_CR, _SAES_CR_IPRST);
+	}
 
 	timeout = timeout_init_us(SAES_TIMEOUT_US);
 	while ((mmio_read_32(ctx->base + _SAES_SR) & _SAES_SR_BUSY) == _SAES_SR_BUSY) {

diff --git a/drivers/st/ddr/stm32mp2_ddr_helpers.c b/drivers/st/ddr/stm32mp2_ddr_helpers.c
index a2a4082..8efb7cf 100644
--- a/drivers/st/ddr/stm32mp2_ddr_helpers.c
+++ b/drivers/st/ddr/stm32mp2_ddr_helpers.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2024-2025, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -363,8 +363,6 @@
 	mmio_write_32(stm32mp_rcc_base() + RCC_DDRCPCFGR,
 		      RCC_DDRCPCFGR_DDRCPLPEN | RCC_DDRCPCFGR_DDRCPEN);
 
-	/* TODO: check if ddr_sr_exit_loop() is needed here */
-
 	return 0;
 }
 
@@ -390,13 +388,6 @@
 	return ddr_sr_exit_loop();
 }
 
-uint32_t ddr_get_io_calibration_val(void)
-{
-	/* TODO create related service */
-
-	return 0U;
-}
-
 int ddr_sr_entry(bool standby)
 {
 	int ret = -EINVAL;

diff --git a/drivers/st/ddr/stm32mp2_ram.c b/drivers/st/ddr/stm32mp2_ram.c
index 95f05e7..2b0e317 100644
--- a/drivers/st/ddr/stm32mp2_ram.c
+++ b/drivers/st/ddr/stm32mp2_ram.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2021-2025, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  */
@@ -142,9 +142,6 @@
 			ERROR("DDR rw test: can't access memory @ 0x%lx\n", uret);
 			panic();
 		}
-
-		/* TODO Restore area overwritten by training */
-		//stm32_restore_ddr_training_area();
 	} else {
 		size_t retsize;
 

diff --git a/drivers/st/ddr/stm32mp_ddr.c b/drivers/st/ddr/stm32mp_ddr.c
index 98968d5..4aa5c73 100644
--- a/drivers/st/ddr/stm32mp_ddr.c
+++ b/drivers/st/ddr/stm32mp_ddr.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2022-2024, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2022-2025, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -44,7 +44,7 @@
 			      ddr_registers[type].name, i);
 			panic();
 		} else {
-#if !STM32MP13 && !STM32MP15
+#ifdef STM32MP2X
 			if (desc[i].qd) {
 				stm32mp_ddr_start_sw_done(priv->ctl);
 			}
@@ -52,7 +52,7 @@
 			value = *((uint32_t *)((uintptr_t)param +
 					       desc[i].par_offset));
 			mmio_write_32(ptr, value);
-#if !STM32MP13 && !STM32MP15
+#ifdef STM32MP2X
 			if (desc[i].qd) {
 				stm32mp_ddr_wait_sw_done_ack(priv->ctl);
 			}
@@ -277,9 +277,9 @@
 	/* Toggle rfshctl3.refresh_update_level */
 	rfshctl3 = mmio_read_32((uintptr_t)&ctl->rfshctl3);
 	if ((rfshctl3 & refresh_update_level) == refresh_update_level) {
-		mmio_setbits_32((uintptr_t)&ctl->rfshctl3, refresh_update_level);
-	} else {
 		mmio_clrbits_32((uintptr_t)&ctl->rfshctl3, refresh_update_level);
+	} else {
+		mmio_setbits_32((uintptr_t)&ctl->rfshctl3, refresh_update_level);
 		refresh_update_level = 0U;
 	}
 
@@ -293,7 +293,7 @@
 		if (timeout_elapsed(timeout)) {
 			panic();
 		}
-	} while ((rfshctl3 & DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL) != refresh_update_level);
+	} while ((rfshctl3 & DDRCTRL_RFSHCTL3_REFRESH_UPDATE_LEVEL) == refresh_update_level);
 
 	VERBOSE("[0x%lx] rfshctl3 = 0x%x\n", (uintptr_t)&ctl->rfshctl3, rfshctl3);
 }

diff --git a/drivers/st/gpio/stm32_gpio.c b/drivers/st/gpio/stm32_gpio.c
index 44d7c09..2d64de3 100644
--- a/drivers/st/gpio/stm32_gpio.c
+++ b/drivers/st/gpio/stm32_gpio.c

@@ -282,7 +282,7 @@
 
 	clk_disable(clock);
 
-#if STM32MP13 || STM32MP15
+#ifdef STM32MP1X
 	if (status == DT_SECURE) {
 		stm32mp_register_secure_gpio(bank, pin);
 #if !IMAGE_BL2

diff --git a/drivers/st/iwdg/stm32_iwdg.c b/drivers/st/iwdg/stm32_iwdg.c
index 74451d7..3d78c20 100644
--- a/drivers/st/iwdg/stm32_iwdg.c
+++ b/drivers/st/iwdg/stm32_iwdg.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2025, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -33,7 +33,6 @@
 	uintptr_t base;
 	unsigned long clock;
 	uint8_t flags;
-	int num_irq;
 };
 
 static struct stm32_iwdg_instance stm32_iwdg[IWDG_MAX_INSTANCE];

diff --git a/drivers/st/mmc/stm32_sdmmc2.c b/drivers/st/mmc/stm32_sdmmc2.c
index 66988d7..e07d9e7 100644
--- a/drivers/st/mmc/stm32_sdmmc2.c
+++ b/drivers/st/mmc/stm32_sdmmc2.c

@@ -129,7 +129,7 @@
 #define DT_SDMMC2_COMPAT		"st,stm32-sdmmc2"
 #endif
 
-#if STM32MP13 || STM32MP15
+#ifdef STM32MP1X
 #define SDMMC_FIFO_SIZE			64U
 #else
 #define SDMMC_FIFO_SIZE			1024U

diff --git a/drivers/st/regulator/regulator_fixed.c b/drivers/st/regulator/regulator_fixed.c
index 6c9d3b1..6b14b5d 100644
--- a/drivers/st/regulator/regulator_fixed.c
+++ b/drivers/st/regulator/regulator_fixed.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2023, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2021-2025, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -21,7 +21,6 @@
 
 struct fixed_data {
 	char name[FIXED_NAME_LEN];
-	uint16_t volt;
 	struct regul_description desc;
 };
 

diff --git a/fdts/fvp-base-psci-common.dtsi b/fdts/fvp-base-psci-common.dtsi
index bdb0229..2a128d8 100644
--- a/fdts/fvp-base-psci-common.dtsi
+++ b/fdts/fvp-base-psci-common.dtsi

@@ -29,10 +29,7 @@
 
 	chosen {
 		stdout-path = "serial0:115200n8";
-/* SPM_MM doesn't like this */
-#if SPM_MM == 0
 		bootargs = "console=ttyAMA0 earlycon=pl011,0x1c090000 root=/dev/vda ip=on";
-#endif
 	};
 
 	aliases {

diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index e8c4054..b607945 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h

@@ -91,6 +91,17 @@
 #define SERROR_EXCEPTION	0x180
 
 /*******************************************************************************
+ * Encodings for GICv5 EL3 system registers
+ ******************************************************************************/
+#define ICC_PPI_DOMAINR0_EL3	S3_6_C12_C8_4
+#define ICC_PPI_DOMAINR1_EL3	S3_6_C12_C8_5
+#define ICC_PPI_DOMAINR2_EL3	S3_6_C12_C8_6
+#define ICC_PPI_DOMAINR3_EL3	S3_6_C12_C8_7
+
+#define ICC_PPI_DOMAINR_FIELD_MASK		ULL(0x3)
+#define ICC_PPI_DOMAINR_COUNT			(32)
+
+/*******************************************************************************
  * Definitions for CPU system register interface to GICv3
  ******************************************************************************/
 #define ICC_IGRPEN1_EL1		S3_0_C12_C12_7
@@ -504,6 +515,11 @@
 #define SME2_IMPLEMENTED			ULL(0x2)
 #define SME_NOT_IMPLEMENTED			ULL(0x0)
 
+/* ID_AA64PFR2_EL1 definitions */
+#define ID_AA64PFR2_EL1				S3_0_C0_C4_2
+#define ID_AA64PFR2_EL1_GCIE_SHIFT		12
+#define ID_AA64PFR2_EL1_GCIE_MASK		ULL(0xf)
+
 /* ID_PFR1_EL1 definitions */
 #define ID_PFR1_VIRTEXT_SHIFT	U(12)
 #define ID_PFR1_VIRTEXT_MASK	U(0xf)
@@ -620,7 +636,11 @@
 #define CPACR_EL1_SMEN_MASK	ULL(0x3)
 
 /* SCR definitions */
+#if ENABLE_FEAT_GCIE
+#define SCR_RES1_BITS		((U(1) << 4) | (U(1) << 5) | SCR_FIQ_BIT)
+#else
 #define SCR_RES1_BITS		((U(1) << 4) | (U(1) << 5))
+#endif
 #define SCR_NSE_SHIFT		U(62)
 #define SCR_FGTEN2_BIT		(UL(1) << 59)
 #define SCR_NSE_BIT		(ULL(1) << SCR_NSE_SHIFT)

diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index 757ce06..77355cd 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h

@@ -520,4 +520,11 @@
 
 CREATE_FEATURE_SUPPORTED(feat_mtpmu, is_feat_mtpmu_present, DISABLE_MTPMU)
 
+/*************************************************************************
+ * Function to identify the presence of FEAT_GCIE (GICv5 CPU interface
+ * extension).
+ ************************************************************************/
+CREATE_FEATURE_FUNCS(feat_gcie, id_aa64pfr2_el1, ID_AA64PFR2_EL1_GCIE_SHIFT,
+		     ID_AA64PFR2_EL1_GCIE_MASK, 1U, ENABLE_FEAT_GCIE)
+
 #endif /* ARCH_FEATURES_H */

diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index c885424..a59c531 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h

@@ -559,6 +559,12 @@
 DEFINE_SYSREG_RW_FUNCS(dacr32_el2)
 DEFINE_SYSREG_RW_FUNCS(ifsr32_el2)
 
+/* GICv5 System Registers */
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_domainr0_el3, ICC_PPI_DOMAINR0_EL3)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_domainr1_el3, ICC_PPI_DOMAINR1_EL3)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_domainr2_el3, ICC_PPI_DOMAINR2_EL3)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_ppi_domainr3_el3, ICC_PPI_DOMAINR3_EL3)
+
 /* GICv3 System Registers */
 
 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1)

diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index fce0f2c..ee5d8d9 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S

@@ -65,7 +65,11 @@
 	 * ---------------------------------------------------------------------
 	 */
 	bl	plat_my_core_pos
-	bl	_cpu_data_by_index
+	/* index into the cpu_data */
+	mov_imm	x1, CPU_DATA_SIZE
+	mul	x0, x0, x1
+	adr_l	x1, percpu_data
+	add	x0, x0, x1
 	msr	tpidr_el3, x0
 #endif /* IMAGE_BL31 */
 

diff --git a/include/bl31/interrupt_mgmt.h b/include/bl31/interrupt_mgmt.h
index 8b9dfb6..e228495 100644
--- a/include/bl31/interrupt_mgmt.h
+++ b/include/bl31/interrupt_mgmt.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -16,7 +16,8 @@
 #define INTR_TYPE_S_EL1			U(0)
 #define INTR_TYPE_EL3			U(1)
 #define INTR_TYPE_NS			U(2)
-#define MAX_INTR_TYPES			U(3)
+#define INTR_TYPE_RL			U(3)
+#define MAX_INTR_TYPES			U(4)
 #define INTR_TYPE_INVAL			MAX_INTR_TYPES
 
 /* Interrupt routing modes */

diff --git a/include/drivers/arm/gicv5.h b/include/drivers/arm/gicv5.h
new file mode 100644
index 0000000..d01d24b
--- /dev/null
+++ b/include/drivers/arm/gicv5.h

@@ -0,0 +1,216 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef GICV5_H
+#define GICV5_H
+
+#ifndef __ASSEMBLER__
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <lib/mmio.h>
+#endif
+
+#include <lib/utils_def.h>
+
+/* Interrupt Domain definitions */
+#define INTDMN_S				0
+#define INTDMN_NS				1
+#define INTDMN_EL3				2
+#define INTDMN_RL				3
+
+/* Trigger modes */
+#define TM_EDGE					0
+#define TM_LEVEL				1
+
+/* Architected PPI numbers */
+#define PPI_TRBIRQ				31
+#define PPI_CNTP				30
+#define PPI_CNTPS				29
+#define PPI_CNTHV				28
+#define PPI_CNTV				27
+#define PPI_CNTHP				26
+#define PPI_GICMNT				25
+#define PPI_CTIIRQ				24
+#define PPI_PMUIRQ				23
+#define PPI_COMMIRQ				22
+#define PPI_PMBIRQ				21
+#define PPI_CNTHPS				20
+#define PPI_CNTHVS				19
+#define PPI_DB_NS				2
+#define PPI_DB_RL				1
+#define PPI_DB_S				0
+
+/* Register fields common to all IRI components.
+ * They have the same name and offset in every config frame */
+#define IRI_AIDR_COMPONENT_SHIFT		8
+#define IRI_AIDR_COMPONENT_WIDTH		4
+#define IRI_AIDR_COMPONENT_IRS			0
+#define IRI_AIDR_COMPONENT_ITS			1
+#define IRI_AIDR_COMPONENT_IWB			2
+#define IRI_AIDR_ARCH_MAJOR_SHIFT		4
+#define IRI_AIDR_ARCH_MAJOR_WIDTH		4
+#define IRI_AIDR_ARCH_MAJOR_V5			0
+#define IRI_AIDR_ARCH_MINOR_SHIFT		0
+#define IRI_AIDR_ARCH_MINOR_WIDTH		4
+#define IRI_AIDR_ARCH_MINOR_P0			0
+
+/* IRS register fields */
+#define IRS_IDR6_SPI_IRS_RANGE_SHIFT		0
+#define IRS_IDR6_SPI_IRS_RANGE_WIDTH		24
+#define IRS_IDR7_SPI_BASE_SHIFT			0
+#define IRS_IDR7_SPI_BASE_WIDTH			24
+
+#define IRS_SPI_STATUSR_IDLE_BIT		BIT(0)
+#define IRS_SPI_STATUSR_V_BIT			BIT(1)
+
+/* IWB register fields */
+#define IWB_IDR0_DOMAINS_SHIFT			11
+#define IWB_IDR0_DOMAINS_WIDTH			4
+#define IWB_IDR0_IWRANGE_SHIFT			0
+#define IWB_IDR0_IWRANGE_WIDTH			10
+
+#define IWB_CR0_IWBEN_BIT			BIT(0)
+#define IWB_CR0_IDLE_BIT			BIT(1)
+
+#define IWB_WENABLE_STATUSR_IDLE_BIT		BIT(0)
+#define IWB_WDOMAIN_STATUSR_IDLE_BIT		BIT(0)
+
+#define IWB_WDOMAINR_DOMAINX_MASK		0x3
+
+#ifndef __ASSEMBLER__
+
+#define _PPI_FIELD_SHIFT(_REG, _ppi_id)						\
+	((_ppi_id % (ICC_PPI_##_REG##_COUNT)) * (64 / ICC_PPI_##_REG##_COUNT))
+
+#define write_icc_ppi_domainr(_var, _ppi_id, _value)				\
+	do {									\
+		_var |=  (uint64_t)_value << _PPI_FIELD_SHIFT(DOMAINR, _ppi_id);\
+	} while (false)
+
+
+#define DEFINE_GICV5_MMIO_WRITE_FUNC(_name, _offset)				\
+static inline void write_##_name(uintptr_t base, uint32_t val)			\
+{										\
+	mmio_write_32(base + _offset, val);					\
+}
+
+#define DEFINE_GICV5_MMIO_READ_FUNC(_name, _offset)				\
+static inline uint32_t read_##_name(uintptr_t base)				\
+{										\
+	return mmio_read_32(base + _offset);					\
+}
+
+#define DEFINE_GICV5_MMIO_WRITE_INDEXED_FUNC(_name, _offset)			\
+static inline void write_##_name(uintptr_t base, uint16_t index, uint32_t val)	\
+{										\
+	mmio_write_32(base + _offset + (index * sizeof(uint32_t)), val);	\
+}
+
+#define DEFINE_GICV5_MMIO_READ_INDEXED_FUNC(_name, _offset)			\
+static inline uint32_t read_##_name(uintptr_t base, uint16_t index)		\
+{										\
+	return mmio_read_32(base + _offset + (index * sizeof(uint32_t)));	\
+}
+
+#define DEFINE_GICV5_MMIO_RW_FUNCS(_name, _offset)				\
+	DEFINE_GICV5_MMIO_READ_FUNC(_name, _offset)				\
+	DEFINE_GICV5_MMIO_WRITE_FUNC(_name, _offset)
+
+#define DEFINE_GICV5_MMIO_RW_INDEXED_FUNCS(_name, _offset)			\
+	DEFINE_GICV5_MMIO_READ_INDEXED_FUNC(_name, _offset)			\
+	DEFINE_GICV5_MMIO_WRITE_INDEXED_FUNC(_name, _offset)
+
+DEFINE_GICV5_MMIO_READ_FUNC(iri_aidr,			0x44)
+
+DEFINE_GICV5_MMIO_READ_FUNC(iwb_idr0,			0x00)
+DEFINE_GICV5_MMIO_RW_FUNCS( iwb_cr0,			0x80)
+DEFINE_GICV5_MMIO_READ_FUNC(iwb_wenable_statusr,	0xc0)
+DEFINE_GICV5_MMIO_READ_FUNC(iwb_wdomain_statusr,	0xc4)
+DEFINE_GICV5_MMIO_RW_INDEXED_FUNCS(iwb_wenabler,	0x2000)
+DEFINE_GICV5_MMIO_RW_INDEXED_FUNCS(iwb_wtmr,		0x4000)
+DEFINE_GICV5_MMIO_RW_INDEXED_FUNCS(iwb_wdomainr,	0x6000)
+
+DEFINE_GICV5_MMIO_READ_FUNC(irs_idr6,			0x0018)
+DEFINE_GICV5_MMIO_READ_FUNC(irs_idr7,			0x001c)
+DEFINE_GICV5_MMIO_RW_FUNCS( irs_spi_selr,		0x0108)
+DEFINE_GICV5_MMIO_RW_FUNCS( irs_spi_domainr,		0x010c)
+DEFINE_GICV5_MMIO_RW_FUNCS( irs_spi_cfgr,		0x0114)
+DEFINE_GICV5_MMIO_READ_FUNC(irs_spi_statusr,		0x0118)
+
+#define WAIT_FOR_IDLE(base, reg, reg_up)					\
+	do {									\
+		while ((read_##reg(base) & reg_up##_IDLE_BIT) == 0U) {}		\
+	} while (0)
+
+/* wait for IDLE but also check the V bit was set */
+#define WAIT_FOR_VIDLE(base, reg, reg_up)					\
+	do {									\
+		uint32_t val;							\
+		while (((val = read_##reg(base)) & reg_up##_IDLE_BIT) == 0U) {}	\
+		assert((val & reg##_V_BIT) != 0U);				\
+	} while (0)
+
+#define WAIT_FOR_VIDLE_IRS_SPI_STATUSR(base)					\
+	WAIT_FOR_IDLE(base, irs_spi_statusr, IRS_SPI_STATUSR)
+
+#define WAIT_FOR_IDLE_IWB_WENABLE_STATUSR(base)					\
+	WAIT_FOR_IDLE(base, iwb_wenable_statusr, IWB_WENABLE_STATUSR)
+#define WAIT_FOR_IDLE_IWB_WDOMAIN_STATUSR(base)					\
+	WAIT_FOR_IDLE(base, iwb_wdomain_statusr, IWB_WDOMAIN_STATUSR)
+#define WAIT_FOR_IDLE_IWB_CR0(base)						\
+	WAIT_FOR_IDLE(base, iwb_cr0, IWB_CR0)
+
+#define WIRE_PROP_DESC(_id, _domain, _tm) \
+	{ \
+		.id = (_id), \
+		.domain = (_domain), \
+		.tm = (_tm), \
+	}
+
+struct gicv5_wire_props {
+	/* continuous wire ID as seen by the attached component */
+	uint32_t id;
+	/* use the INTDMN_XYZ macros */
+	uint8_t domain:2;
+	/* use the TM_XYZ (eg. TM_EDGE) macros */
+	uint8_t tm:1;
+};
+
+/* to describe every IRS in the system */
+struct gicv5_irs {
+	/* mapped device nGnRnE by the platform*/
+	uintptr_t el3_config_frame;
+	struct gicv5_wire_props *spis;
+	uint32_t num_spis;
+};
+
+/*
+ * to describe every IWB in the system where EL3 is the MPPAS. IWBs that have
+ * another world as an MPPAS need not be included
+ */
+struct gicv5_iwb {
+	/* mapped device nGnRnE by the platform*/
+	uintptr_t config_frame;
+	struct gicv5_wire_props *wires;
+	uint32_t num_wires;
+};
+
+struct gicv5_driver_data {
+	struct gicv5_irs *irss;
+	struct gicv5_iwb *iwbs;
+	uint32_t num_irss;
+	uint32_t num_iwbs;
+};
+
+extern const struct gicv5_driver_data plat_gicv5_driver_data;
+
+void gicv5_driver_init();
+uint8_t gicv5_get_pending_interrupt_type(void);
+bool gicv5_has_interrupt_type(unsigned int type);
+void gicv5_enable_ppis();
+#endif /* __ASSEMBLER__ */
+#endif /* GICV5_H */

diff --git a/include/drivers/st/bsec3_reg.h b/include/drivers/st/bsec3_reg.h
index 177e30b..4263f76 100644
--- a/include/drivers/st/bsec3_reg.h
+++ b/include/drivers/st/bsec3_reg.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2024-2025, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -84,7 +84,7 @@
 
 /* BSEC_OTPSR register fields */
 #define BSEC_OTPSR_BUSY			BIT_32(0)
-#define BSEC_OTPSR_FUSEOK		BIT_32(1)
+#define BSEC_OTPSR_INIT_DONE		BIT_32(1)
 #define BSEC_OTPSR_HIDEUP		BIT_32(2)
 #define BSEC_OTPSR_OTPNVIR		BIT_32(4)
 #define BSEC_OTPSR_OTPERR		BIT_32(5)

diff --git a/include/drivers/st/stm32mp21_pwr.h b/include/drivers/st/stm32mp21_pwr.h
new file mode 100644
index 0000000..570f079
--- /dev/null
+++ b/include/drivers/st/stm32mp21_pwr.h

@@ -0,0 +1,416 @@
+/*
+ * Copyright (c) 2025, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP21_PWR_H
+#define STM32MP21_PWR_H
+
+#include <lib/utils_def.h>
+
+#define PWR_CR1					U(0x00)
+#define PWR_CR2					U(0x04)
+#define PWR_CR3					U(0x08)
+#define PWR_CR7					U(0x18)
+#define PWR_CR8					U(0x1C)
+#define PWR_CR9					U(0x20)
+#define PWR_CR10				U(0x24)
+#define PWR_CR11				U(0x28)
+#define PWR_BDCR				U(0x38)
+#define PWR_CPU1CR				U(0x40)
+#define PWR_CPU2CR				U(0x44)
+#define PWR_D1CR				U(0x4C)
+#define PWR_D2CR				U(0x50)
+#define PWR_WKUPCR1				U(0x60)
+#define PWR_WKUPCR2				U(0x64)
+#define PWR_WKUPCR3				U(0x68)
+#define PWR_WKUPCR4				U(0x6C)
+#define PWR_WKUPCR5				U(0x70)
+#define PWR_WKUPCR6				U(0x74)
+#define PWR_RSECCFGR				U(0x100)
+#define PWR_RPRIVCFGR				U(0x104)
+#define PWR_R0CIDCFGR				U(0x108)
+#define PWR_R1CIDCFGR				U(0x10C)
+#define PWR_R2CIDCFGR				U(0x110)
+#define PWR_R3CIDCFGR				U(0x114)
+#define PWR_R4CIDCFGR				U(0x118)
+#define PWR_R5CIDCFGR				U(0x11C)
+#define PWR_R6CIDCFGR				U(0x120)
+#define PWR_WIOSECCFGR				U(0x180)
+#define PWR_WIOPRIVCFGR				U(0x184)
+#define PWR_WIO1CIDCFGR				U(0x188)
+#define PWR_WIO1SEMCR				U(0x18C)
+#define PWR_WIO2CIDCFGR				U(0x190)
+#define PWR_WIO2SEMCR				U(0x194)
+#define PWR_WIO3CIDCFGR				U(0x198)
+#define PWR_WIO3SEMCR				U(0x19C)
+#define PWR_WIO4CIDCFGR				U(0x1A0)
+#define PWR_WIO4SEMCR				U(0x1A4)
+#define PWR_WIO5CIDCFGR				U(0x1A8)
+#define PWR_WIO5SEMCR				U(0x1AC)
+#define PWR_WIO6CIDCFGR				U(0x1B0)
+#define PWR_WIO6SEMCR				U(0x1B4)
+#define PWR_CPU1D1SR				U(0x200)
+#define PWR_CPU2D2SR				U(0x204)
+#define PWR_DBGR				U(0x308)
+#define PWR_VERR				U(0x3F4)
+#define PWR_IPIDR				U(0x3F8)
+#define PWR_SIDR				U(0x3FC)
+
+/* PWR_CR1 register fields */
+#define PWR_CR1_VDDIO3VMEN			BIT(0)
+#define PWR_CR1_USB33VMEN			BIT(2)
+#define PWR_CR1_AVMEN				BIT(4)
+#define PWR_CR1_VDDIO3SV			BIT(8)
+#define PWR_CR1_USB33SV				BIT(10)
+#define PWR_CR1_ASV				BIT(12)
+#define PWR_CR1_VDDIO3RDY			BIT(16)
+#define PWR_CR1_USB33RDY			BIT(18)
+#define PWR_CR1_ARDY				BIT(20)
+#define PWR_CR1_VDDIOVRSEL			BIT(24)
+#define PWR_CR1_VDDIO3VRSEL			BIT(25)
+#define PWR_CR1_GPVMO				BIT(31)
+
+/* PWR_CR2 register fields */
+#define PWR_CR2_MONEN				BIT(0)
+#define PWR_CR2_VBATL				BIT(8)
+#define PWR_CR2_VBATH				BIT(9)
+#define PWR_CR2_TEMPL				BIT(10)
+#define PWR_CR2_TEMPH				BIT(11)
+
+/* PWR_CR3 register fields */
+#define PWR_CR3_PVDEN				BIT(0)
+#define PWR_CR3_PVDO				BIT(8)
+
+/* PWR_CR7 register fields */
+#define PWR_CR7_VDDIO2VMEN			BIT(0)
+#define PWR_CR7_VDDIO2SV			BIT(8)
+#define PWR_CR7_VDDIO2RDY			BIT(16)
+#define PWR_CR7_VDDIO2VRSEL			BIT(24)
+#define PWR_CR7_VDDIO2VRSTBY			BIT(25)
+
+/* PWR_CR8 register fields */
+#define PWR_CR8_VDDIO1VMEN			BIT(0)
+#define PWR_CR8_VDDIO1SV			BIT(8)
+#define PWR_CR8_VDDIO1RDY			BIT(16)
+#define PWR_CR8_VDDIO1VRSEL			BIT(24)
+#define PWR_CR8_VDDIO1VRSTBY			BIT(25)
+
+/* PWR_CR9 register fields */
+#define PWR_CR9_BKPRBSEN			BIT(0)
+
+/* PWR_CR10 register fields */
+#define PWR_CR10_RETRBSEN_MASK			GENMASK_32(1, 0)
+#define PWR_CR10_RETRBSEN_SHIFT			0
+#define PWR_CR10_RETRBSEN_DISABLE		0U
+#define PWR_CR10_RETRBSEN_STANDBY_VBAT		1U
+#define PWR_CR10_RETRBSEN_STANDBY		2U
+
+/* PWR_CR11 register fields */
+#define PWR_CR11_DDRRETDIS			BIT(0)
+
+/* PWR_BDCR register fields */
+#define PWR_BDCR_DBP				BIT(0)
+
+/* PWR_CPU1CR register fields */
+#define PWR_CPU1CR_PDDS_D2			BIT(0)
+#define PWR_CPU1CR_PDDS_D1			BIT(1)
+#define PWR_CPU1CR_VBF				BIT(4)
+#define PWR_CPU1CR_STOPF			BIT(5)
+#define PWR_CPU1CR_SBF				BIT(6)
+#define PWR_CPU1CR_SBF_D1			BIT(7)
+#define PWR_CPU1CR_CSSF				BIT(9)
+#define PWR_CPU1CR_STANDBYWFIL2			BIT(15)
+#define PWR_CPU1CR_LPDS_D1			BIT(16)
+#define PWR_CPU1CR_LVDS_D1			BIT(17)
+
+/* PWR_CPU2CR register fields */
+#define PWR_CPU2CR_PDDS_D2			BIT(0)
+#define PWR_CPU2CR_VBF				BIT(4)
+#define PWR_CPU2CR_STOPF			BIT(5)
+#define PWR_CPU2CR_SBF				BIT(6)
+#define PWR_CPU2CR_SBF_D2			BIT(7)
+#define PWR_CPU2CR_CSSF				BIT(9)
+#define PWR_CPU2CR_DEEPSLEEP			BIT(15)
+#define PWR_CPU2CR_LPDS_D2			BIT(16)
+#define PWR_CPU2CR_LVDS_D2			BIT(17)
+
+/* PWR_D1CR register fields */
+#define PWR_D1CR_LPCFG_D1			BIT(0)
+#define PWR_D1CR_POPL_D1_MASK			GENMASK_32(12, 8)
+#define PWR_D1CR_POPL_D1_SHIFT			8
+
+/* PWR_D2CR register fields */
+#define PWR_D2CR_LPCFG_D2			BIT(0)
+#define PWR_D2CR_POPL_D2_MASK			GENMASK_32(12, 8)
+#define PWR_D2CR_POPL_D2_SHIFT			8
+#define PWR_D2CR_LPLVDLY_D2_MASK		GENMASK_32(18, 16)
+#define PWR_D2CR_LPLVDLY_D2_SHIFT		16
+#define PWR_D2CR_PODH_D2_MASK			GENMASK_32(27, 24)
+#define PWR_D2CR_PODH_D2_SHIFT			24
+
+/* PWR_WKUPCR1 register fields */
+#define PWR_WKUPCR1_WKUPC			BIT(0)
+#define PWR_WKUPCR1_WKUPP			BIT(8)
+#define PWR_WKUPCR1_WKUPPUPD_MASK		GENMASK_32(13, 12)
+#define PWR_WKUPCR1_WKUPPUPD_SHIFT		12
+#define PWR_WKUPCR1_WKUPENCPU1			BIT(16)
+#define PWR_WKUPCR1_WKUPENCPU2			BIT(17)
+#define PWR_WKUPCR1_WKUPF			BIT(31)
+
+/* PWR_WKUPCR2 register fields */
+#define PWR_WKUPCR2_WKUPC			BIT(0)
+#define PWR_WKUPCR2_WKUPP			BIT(8)
+#define PWR_WKUPCR2_WKUPPUPD_MASK		GENMASK_32(13, 12)
+#define PWR_WKUPCR2_WKUPPUPD_SHIFT		12
+#define PWR_WKUPCR2_WKUPENCPU1			BIT(16)
+#define PWR_WKUPCR2_WKUPENCPU2			BIT(17)
+#define PWR_WKUPCR2_WKUPF			BIT(31)
+
+/* PWR_WKUPCR3 register fields */
+#define PWR_WKUPCR3_WKUPC			BIT(0)
+#define PWR_WKUPCR3_WKUPP			BIT(8)
+#define PWR_WKUPCR3_WKUPPUPD_MASK		GENMASK_32(13, 12)
+#define PWR_WKUPCR3_WKUPPUPD_SHIFT		12
+#define PWR_WKUPCR3_WKUPENCPU1			BIT(16)
+#define PWR_WKUPCR3_WKUPENCPU2			BIT(17)
+#define PWR_WKUPCR3_WKUPF			BIT(31)
+
+/* PWR_WKUPCR4 register fields */
+#define PWR_WKUPCR4_WKUPC			BIT(0)
+#define PWR_WKUPCR4_WKUPP			BIT(8)
+#define PWR_WKUPCR4_WKUPPUPD_MASK		GENMASK_32(13, 12)
+#define PWR_WKUPCR4_WKUPPUPD_SHIFT		12
+#define PWR_WKUPCR4_WKUPENCPU1			BIT(16)
+#define PWR_WKUPCR4_WKUPENCPU2			BIT(17)
+#define PWR_WKUPCR4_WKUPF			BIT(31)
+
+/* PWR_WKUPCR5 register fields */
+#define PWR_WKUPCR5_WKUPC			BIT(0)
+#define PWR_WKUPCR5_WKUPP			BIT(8)
+#define PWR_WKUPCR5_WKUPPUPD_MASK		GENMASK_32(13, 12)
+#define PWR_WKUPCR5_WKUPPUPD_SHIFT		12
+#define PWR_WKUPCR5_WKUPENCPU1			BIT(16)
+#define PWR_WKUPCR5_WKUPENCPU2			BIT(17)
+#define PWR_WKUPCR5_WKUPF			BIT(31)
+
+/* PWR_WKUPCR6 register fields */
+#define PWR_WKUPCR6_WKUPC			BIT(0)
+#define PWR_WKUPCR6_WKUPP			BIT(8)
+#define PWR_WKUPCR6_WKUPPUPD_MASK		GENMASK_32(13, 12)
+#define PWR_WKUPCR6_WKUPPUPD_SHIFT		12
+#define PWR_WKUPCR6_WKUPENCPU1			BIT(16)
+#define PWR_WKUPCR6_WKUPENCPU2			BIT(17)
+#define PWR_WKUPCR6_WKUPF			BIT(31)
+
+/* PWR_RSECCFGR register fields */
+#define PWR_RSECCFGR_RSEC0			BIT(0)
+#define PWR_RSECCFGR_RSEC1			BIT(1)
+#define PWR_RSECCFGR_RSEC2			BIT(2)
+#define PWR_RSECCFGR_RSEC3			BIT(3)
+#define PWR_RSECCFGR_RSEC4			BIT(4)
+#define PWR_RSECCFGR_RSEC5			BIT(5)
+#define PWR_RSECCFGR_RSEC6			BIT(6)
+
+/* PWR_RPRIVCFGR register fields */
+#define PWR_RPRIVCFGR_RPRIV0			BIT(0)
+#define PWR_RPRIVCFGR_RPRIV1			BIT(1)
+#define PWR_RPRIVCFGR_RPRIV2			BIT(2)
+#define PWR_RPRIVCFGR_RPRIV3			BIT(3)
+#define PWR_RPRIVCFGR_RPRIV4			BIT(4)
+#define PWR_RPRIVCFGR_RPRIV5			BIT(5)
+#define PWR_RPRIVCFGR_RPRIV6			BIT(6)
+
+/* PWR_R0CIDCFGR register fields */
+#define PWR_R0CIDCFGR_CFEN			BIT(0)
+#define PWR_R0CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define PWR_R0CIDCFGR_SCID_SHIFT		4
+
+/* PWR_R1CIDCFGR register fields */
+#define PWR_R1CIDCFGR_CFEN			BIT(0)
+#define PWR_R1CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define PWR_R1CIDCFGR_SCID_SHIFT		4
+
+/* PWR_R2CIDCFGR register fields */
+#define PWR_R2CIDCFGR_CFEN			BIT(0)
+#define PWR_R2CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define PWR_R2CIDCFGR_SCID_SHIFT		4
+
+/* PWR_R3CIDCFGR register fields */
+#define PWR_R3CIDCFGR_CFEN			BIT(0)
+#define PWR_R3CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define PWR_R3CIDCFGR_SCID_SHIFT		4
+
+/* PWR_R4CIDCFGR register fields */
+#define PWR_R4CIDCFGR_CFEN			BIT(0)
+#define PWR_R4CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define PWR_R4CIDCFGR_SCID_SHIFT		4
+
+/* PWR_R5CIDCFGR register fields */
+#define PWR_R5CIDCFGR_CFEN			BIT(0)
+#define PWR_R5CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define PWR_R5CIDCFGR_SCID_SHIFT		4
+
+/* PWR_R6CIDCFGR register fields */
+#define PWR_R6CIDCFGR_CFEN			BIT(0)
+#define PWR_R6CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define PWR_R6CIDCFGR_SCID_SHIFT		4
+
+/* PWR_WIOSECCFGR register fields */
+#define PWR_WIOSECCFGR_WIOSEC1			BIT(0)
+#define PWR_WIOSECCFGR_WIOSEC2			BIT(1)
+#define PWR_WIOSECCFGR_WIOSEC3			BIT(2)
+#define PWR_WIOSECCFGR_WIOSEC4			BIT(3)
+#define PWR_WIOSECCFGR_WIOSEC5			BIT(4)
+#define PWR_WIOSECCFGR_WIOSEC6			BIT(5)
+
+/* PWR_WIOPRIVCFGR register fields */
+#define PWR_WIOPRIVCFGR_WIOPRIV1		BIT(0)
+#define PWR_WIOPRIVCFGR_WIOPRIV2		BIT(1)
+#define PWR_WIOPRIVCFGR_WIOPRIV3		BIT(2)
+#define PWR_WIOPRIVCFGR_WIOPRIV4		BIT(3)
+#define PWR_WIOPRIVCFGR_WIOPRIV5		BIT(4)
+#define PWR_WIOPRIVCFGR_WIOPRIV6		BIT(5)
+
+/* PWR_WIO1CIDCFGR register fields */
+#define PWR_WIO1CIDCFGR_CFEN			BIT(0)
+#define PWR_WIO1CIDCFGR_SEM_EN			BIT(1)
+#define PWR_WIO1CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define PWR_WIO1CIDCFGR_SCID_SHIFT		4
+#define PWR_WIO1CIDCFGR_SEMWLC0			BIT(16)
+#define PWR_WIO1CIDCFGR_SEMWLC1			BIT(17)
+#define PWR_WIO1CIDCFGR_SEMWLC2			BIT(18)
+#define PWR_WIO1CIDCFGR_SEMWLC3			BIT(19)
+#define PWR_WIO1CIDCFGR_SEMWLC4			BIT(20)
+#define PWR_WIO1CIDCFGR_SEMWLC5			BIT(21)
+#define PWR_WIO1CIDCFGR_SEMWLC6			BIT(22)
+#define PWR_WIO1CIDCFGR_SEMWLC7			BIT(23)
+
+/* PWR_WIO1SEMCR register fields */
+#define PWR_WIO1SEMCR_SEM_MUTEX			BIT(0)
+#define PWR_WIO1SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define PWR_WIO1SEMCR_SEMCID_SHIFT		4
+
+/* PWR_WIO2CIDCFGR register fields */
+#define PWR_WIO2CIDCFGR_CFEN			BIT(0)
+#define PWR_WIO2CIDCFGR_SEM_EN			BIT(1)
+#define PWR_WIO2CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define PWR_WIO2CIDCFGR_SCID_SHIFT		4
+#define PWR_WIO2CIDCFGR_SEMWLC0			BIT(16)
+#define PWR_WIO2CIDCFGR_SEMWLC1			BIT(17)
+#define PWR_WIO2CIDCFGR_SEMWLC2			BIT(18)
+#define PWR_WIO2CIDCFGR_SEMWLC3			BIT(19)
+#define PWR_WIO2CIDCFGR_SEMWLC4			BIT(20)
+#define PWR_WIO2CIDCFGR_SEMWLC5			BIT(21)
+#define PWR_WIO2CIDCFGR_SEMWLC6			BIT(22)
+#define PWR_WIO2CIDCFGR_SEMWLC7			BIT(23)
+
+/* PWR_WIO2SEMCR register fields */
+#define PWR_WIO2SEMCR_SEM_MUTEX			BIT(0)
+#define PWR_WIO2SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define PWR_WIO2SEMCR_SEMCID_SHIFT		4
+
+/* PWR_WIO3CIDCFGR register fields */
+#define PWR_WIO3CIDCFGR_CFEN			BIT(0)
+#define PWR_WIO3CIDCFGR_SEM_EN			BIT(1)
+#define PWR_WIO3CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define PWR_WIO3CIDCFGR_SCID_SHIFT		4
+#define PWR_WIO3CIDCFGR_SEMWLC0			BIT(16)
+#define PWR_WIO3CIDCFGR_SEMWLC1			BIT(17)
+#define PWR_WIO3CIDCFGR_SEMWLC2			BIT(18)
+#define PWR_WIO3CIDCFGR_SEMWLC3			BIT(19)
+#define PWR_WIO3CIDCFGR_SEMWLC4			BIT(20)
+#define PWR_WIO3CIDCFGR_SEMWLC5			BIT(21)
+#define PWR_WIO3CIDCFGR_SEMWLC6			BIT(22)
+#define PWR_WIO3CIDCFGR_SEMWLC7			BIT(23)
+
+/* PWR_WIO3SEMCR register fields */
+#define PWR_WIO3SEMCR_SEM_MUTEX			BIT(0)
+#define PWR_WIO3SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define PWR_WIO3SEMCR_SEMCID_SHIFT		4
+
+/* PWR_WIO4CIDCFGR register fields */
+#define PWR_WIO4CIDCFGR_CFEN			BIT(0)
+#define PWR_WIO4CIDCFGR_SEM_EN			BIT(1)
+#define PWR_WIO4CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define PWR_WIO4CIDCFGR_SCID_SHIFT		4
+#define PWR_WIO4CIDCFGR_SEMWLC0			BIT(16)
+#define PWR_WIO4CIDCFGR_SEMWLC1			BIT(17)
+#define PWR_WIO4CIDCFGR_SEMWLC2			BIT(18)
+#define PWR_WIO4CIDCFGR_SEMWLC3			BIT(19)
+#define PWR_WIO4CIDCFGR_SEMWLC4			BIT(20)
+#define PWR_WIO4CIDCFGR_SEMWLC5			BIT(21)
+#define PWR_WIO4CIDCFGR_SEMWLC6			BIT(22)
+#define PWR_WIO4CIDCFGR_SEMWLC7			BIT(23)
+
+/* PWR_WIO4SEMCR register fields */
+#define PWR_WIO4SEMCR_SEM_MUTEX			BIT(0)
+#define PWR_WIO4SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define PWR_WIO4SEMCR_SEMCID_SHIFT		4
+
+/* PWR_WIO5CIDCFGR register fields */
+#define PWR_WIO5CIDCFGR_CFEN			BIT(0)
+#define PWR_WIO5CIDCFGR_SEM_EN			BIT(1)
+#define PWR_WIO5CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define PWR_WIO5CIDCFGR_SCID_SHIFT		4
+#define PWR_WIO5CIDCFGR_SEMWLC0			BIT(16)
+#define PWR_WIO5CIDCFGR_SEMWLC1			BIT(17)
+#define PWR_WIO5CIDCFGR_SEMWLC2			BIT(18)
+#define PWR_WIO5CIDCFGR_SEMWLC3			BIT(19)
+#define PWR_WIO5CIDCFGR_SEMWLC4			BIT(20)
+#define PWR_WIO5CIDCFGR_SEMWLC5			BIT(21)
+#define PWR_WIO5CIDCFGR_SEMWLC6			BIT(22)
+#define PWR_WIO5CIDCFGR_SEMWLC7			BIT(23)
+
+/* PWR_WIO5SEMCR register fields */
+#define PWR_WIO5SEMCR_SEM_MUTEX			BIT(0)
+#define PWR_WIO5SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define PWR_WIO5SEMCR_SEMCID_SHIFT		4
+
+/* PWR_WIO6CIDCFGR register fields */
+#define PWR_WIO6CIDCFGR_CFEN			BIT(0)
+#define PWR_WIO6CIDCFGR_SEM_EN			BIT(1)
+#define PWR_WIO6CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define PWR_WIO6CIDCFGR_SCID_SHIFT		4
+#define PWR_WIO6CIDCFGR_SEMWLC0			BIT(16)
+#define PWR_WIO6CIDCFGR_SEMWLC1			BIT(17)
+#define PWR_WIO6CIDCFGR_SEMWLC2			BIT(18)
+#define PWR_WIO6CIDCFGR_SEMWLC3			BIT(19)
+#define PWR_WIO6CIDCFGR_SEMWLC4			BIT(20)
+#define PWR_WIO6CIDCFGR_SEMWLC5			BIT(21)
+#define PWR_WIO6CIDCFGR_SEMWLC6			BIT(22)
+#define PWR_WIO6CIDCFGR_SEMWLC7			BIT(23)
+
+/* PWR_WIO6SEMCR register fields */
+#define PWR_WIO6SEMCR_SEM_MUTEX			BIT(0)
+#define PWR_WIO6SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define PWR_WIO6SEMCR_SEMCID_SHIFT		4
+
+/* PWR_CPU1D1SR register fields */
+#define PWR_CPU1D1SR_HOLD_BOOT			BIT(0)
+#define PWR_CPU1D1SR_CSTATE_MASK		GENMASK_32(3, 2)
+#define PWR_CPU1D1SR_CSTATE_SHIFT		2
+#define PWR_CPU1D1SR_DSTATE_MASK		GENMASK_32(10, 8)
+#define PWR_CPU1D1SR_DSTATE_SHIFT		8
+
+/* PWR_CPU2D2SR register fields */
+#define PWR_CPU2D2SR_HOLD_BOOT			BIT(0)
+#define PWR_CPU2D2SR_WFBEN			BIT(1)
+#define PWR_CPU2D2SR_CSTATE_MASK		GENMASK_32(3, 2)
+#define PWR_CPU2D2SR_CSTATE_SHIFT		2
+#define PWR_CPU2D2SR_DSTATE_MASK		GENMASK_32(10, 8)
+#define PWR_CPU2D2SR_DSTATE_SHIFT		8
+
+/* PWR_DBGR register fields */
+#define PWR_DBGR_VDDIOKRETRAM			BIT(16)
+#define PWR_DBGR_VDDIOKBKPRAM			BIT(17)
+
+/* PWR_VERR register fields */
+#define PWR_VERR_MINREV_MASK			GENMASK_32(3, 0)
+#define PWR_VERR_MINREV_SHIFT			0
+#define PWR_VERR_MAJREV_MASK			GENMASK_32(7, 4)
+#define PWR_VERR_MAJREV_SHIFT			4
+
+#endif /* STM32MP21_PWR_H */
+

diff --git a/include/drivers/st/stm32mp21_rcc.h b/include/drivers/st/stm32mp21_rcc.h
new file mode 100644
index 0000000..a3787d0
--- /dev/null
+++ b/include/drivers/st/stm32mp21_rcc.h

@@ -0,0 +1,4668 @@
+/*
+ * Copyright (c) 2025, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP21_RCC_H
+#define STM32MP21_RCC_H
+
+#include <lib/utils_def.h>
+
+#define RCC_SECCFGR0				U(0x0)
+#define RCC_SECCFGR1				U(0x4)
+#define RCC_SECCFGR2				U(0x8)
+#define RCC_SECCFGR3				U(0xC)
+#define RCC_PRIVCFGR0				U(0x10)
+#define RCC_PRIVCFGR1				U(0x14)
+#define RCC_PRIVCFGR2				U(0x18)
+#define RCC_PRIVCFGR3				U(0x1C)
+#define RCC_RCFGLOCKR0				U(0x20)
+#define RCC_RCFGLOCKR1				U(0x24)
+#define RCC_RCFGLOCKR2				U(0x28)
+#define RCC_RCFGLOCKR3				U(0x2C)
+#define RCC_R0CIDCFGR				U(0x30)
+#define RCC_R0SEMCR				U(0x34)
+#define RCC_R1CIDCFGR				U(0x38)
+#define RCC_R1SEMCR				U(0x3C)
+#define RCC_R2CIDCFGR				U(0x40)
+#define RCC_R2SEMCR				U(0x44)
+#define RCC_R3CIDCFGR				U(0x48)
+#define RCC_R3SEMCR				U(0x4C)
+#define RCC_R4CIDCFGR				U(0x50)
+#define RCC_R4SEMCR				U(0x54)
+#define RCC_R5CIDCFGR				U(0x58)
+#define RCC_R5SEMCR				U(0x5C)
+#define RCC_R6CIDCFGR				U(0x60)
+#define RCC_R6SEMCR				U(0x64)
+#define RCC_R7CIDCFGR				U(0x68)
+#define RCC_R7SEMCR				U(0x6C)
+#define RCC_R8CIDCFGR				U(0x70)
+#define RCC_R8SEMCR				U(0x74)
+#define RCC_R9CIDCFGR				U(0x78)
+#define RCC_R9SEMCR				U(0x7C)
+#define RCC_R10CIDCFGR				U(0x80)
+#define RCC_R10SEMCR				U(0x84)
+#define RCC_R11CIDCFGR				U(0x88)
+#define RCC_R11SEMCR				U(0x8C)
+#define RCC_R12CIDCFGR				U(0x90)
+#define RCC_R12SEMCR				U(0x94)
+#define RCC_R13CIDCFGR				U(0x98)
+#define RCC_R13SEMCR				U(0x9C)
+#define RCC_R14CIDCFGR				U(0xA0)
+#define RCC_R14SEMCR				U(0xA4)
+#define RCC_R15CIDCFGR				U(0xA8)
+#define RCC_R15SEMCR				U(0xAC)
+#define RCC_R16CIDCFGR				U(0xB0)
+#define RCC_R16SEMCR				U(0xB4)
+#define RCC_R17CIDCFGR				U(0xB8)
+#define RCC_R17SEMCR				U(0xBC)
+#define RCC_R18CIDCFGR				U(0xC0)
+#define RCC_R18SEMCR				U(0xC4)
+#define RCC_R19CIDCFGR				U(0xC8)
+#define RCC_R19SEMCR				U(0xCC)
+#define RCC_R20CIDCFGR				U(0xD0)
+#define RCC_R20SEMCR				U(0xD4)
+#define RCC_R21CIDCFGR				U(0xD8)
+#define RCC_R21SEMCR				U(0xDC)
+#define RCC_R22CIDCFGR				U(0xE0)
+#define RCC_R22SEMCR				U(0xE4)
+#define RCC_R23CIDCFGR				U(0xE8)
+#define RCC_R23SEMCR				U(0xEC)
+#define RCC_R24CIDCFGR				U(0xF0)
+#define RCC_R24SEMCR				U(0xF4)
+#define RCC_R25CIDCFGR				U(0xF8)
+#define RCC_R25SEMCR				U(0xFC)
+#define RCC_R26CIDCFGR				U(0x100)
+#define RCC_R26SEMCR				U(0x104)
+#define RCC_R27CIDCFGR				U(0x108)
+#define RCC_R27SEMCR				U(0x10C)
+#define RCC_R28CIDCFGR				U(0x110)
+#define RCC_R28SEMCR				U(0x114)
+#define RCC_R29CIDCFGR				U(0x118)
+#define RCC_R29SEMCR				U(0x11C)
+#define RCC_R30CIDCFGR				U(0x120)
+#define RCC_R30SEMCR				U(0x124)
+#define RCC_R31CIDCFGR				U(0x128)
+#define RCC_R31SEMCR				U(0x12C)
+#define RCC_R32CIDCFGR				U(0x130)
+#define RCC_R32SEMCR				U(0x134)
+#define RCC_R33CIDCFGR				U(0x138)
+#define RCC_R33SEMCR				U(0x13C)
+#define RCC_R34CIDCFGR				U(0x140)
+#define RCC_R34SEMCR				U(0x144)
+#define RCC_R35CIDCFGR				U(0x148)
+#define RCC_R35SEMCR				U(0x14C)
+#define RCC_R36CIDCFGR				U(0x150)
+#define RCC_R36SEMCR				U(0x154)
+#define RCC_R37CIDCFGR				U(0x158)
+#define RCC_R37SEMCR				U(0x15C)
+#define RCC_R38CIDCFGR				U(0x160)
+#define RCC_R38SEMCR				U(0x164)
+#define RCC_R39CIDCFGR				U(0x168)
+#define RCC_R39SEMCR				U(0x16C)
+#define RCC_R40CIDCFGR				U(0x170)
+#define RCC_R40SEMCR				U(0x174)
+#define RCC_R41CIDCFGR				U(0x178)
+#define RCC_R41SEMCR				U(0x17C)
+#define RCC_R42CIDCFGR				U(0x180)
+#define RCC_R42SEMCR				U(0x184)
+#define RCC_R43CIDCFGR				U(0x188)
+#define RCC_R43SEMCR				U(0x18C)
+#define RCC_R44CIDCFGR				U(0x190)
+#define RCC_R44SEMCR				U(0x194)
+#define RCC_R45CIDCFGR				U(0x198)
+#define RCC_R45SEMCR				U(0x19C)
+#define RCC_R46CIDCFGR				U(0x1A0)
+#define RCC_R46SEMCR				U(0x1A4)
+#define RCC_R47CIDCFGR				U(0x1A8)
+#define RCC_R47SEMCR				U(0x1AC)
+#define RCC_R48CIDCFGR				U(0x1B0)
+#define RCC_R48SEMCR				U(0x1B4)
+#define RCC_R49CIDCFGR				U(0x1B8)
+#define RCC_R49SEMCR				U(0x1BC)
+#define RCC_R50CIDCFGR				U(0x1C0)
+#define RCC_R50SEMCR				U(0x1C4)
+#define RCC_R51CIDCFGR				U(0x1C8)
+#define RCC_R51SEMCR				U(0x1CC)
+#define RCC_R52CIDCFGR				U(0x1D0)
+#define RCC_R52SEMCR				U(0x1D4)
+#define RCC_R53CIDCFGR				U(0x1D8)
+#define RCC_R53SEMCR				U(0x1DC)
+#define RCC_R54CIDCFGR				U(0x1E0)
+#define RCC_R54SEMCR				U(0x1E4)
+#define RCC_R55CIDCFGR				U(0x1E8)
+#define RCC_R55SEMCR				U(0x1EC)
+#define RCC_R56CIDCFGR				U(0x1F0)
+#define RCC_R56SEMCR				U(0x1F4)
+#define RCC_R57CIDCFGR				U(0x1F8)
+#define RCC_R57SEMCR				U(0x1FC)
+#define RCC_R58CIDCFGR				U(0x200)
+#define RCC_R58SEMCR				U(0x204)
+#define RCC_R59CIDCFGR				U(0x208)
+#define RCC_R59SEMCR				U(0x20C)
+#define RCC_R60CIDCFGR				U(0x210)
+#define RCC_R60SEMCR				U(0x214)
+#define RCC_R61CIDCFGR				U(0x218)
+#define RCC_R61SEMCR				U(0x21C)
+#define RCC_R62CIDCFGR				U(0x220)
+#define RCC_R62SEMCR				U(0x224)
+#define RCC_R63CIDCFGR				U(0x228)
+#define RCC_R63SEMCR				U(0x22C)
+#define RCC_R64CIDCFGR				U(0x230)
+#define RCC_R64SEMCR				U(0x234)
+#define RCC_R65CIDCFGR				U(0x238)
+#define RCC_R65SEMCR				U(0x23C)
+#define RCC_R66CIDCFGR				U(0x240)
+#define RCC_R66SEMCR				U(0x244)
+#define RCC_R67CIDCFGR				U(0x248)
+#define RCC_R67SEMCR				U(0x24C)
+#define RCC_R68CIDCFGR				U(0x250)
+#define RCC_R68SEMCR				U(0x254)
+#define RCC_R69CIDCFGR				U(0x258)
+#define RCC_R69SEMCR				U(0x25C)
+#define RCC_R70CIDCFGR				U(0x260)
+#define RCC_R70SEMCR				U(0x264)
+#define RCC_R71CIDCFGR				U(0x268)
+#define RCC_R71SEMCR				U(0x26C)
+#define RCC_R72CIDCFGR				U(0x270)
+#define RCC_R72SEMCR				U(0x274)
+#define RCC_R73CIDCFGR				U(0x278)
+#define RCC_R73SEMCR				U(0x27C)
+#define RCC_R74CIDCFGR				U(0x280)
+#define RCC_R74SEMCR				U(0x284)
+#define RCC_R75CIDCFGR				U(0x288)
+#define RCC_R75SEMCR				U(0x28C)
+#define RCC_R76CIDCFGR				U(0x290)
+#define RCC_R76SEMCR				U(0x294)
+#define RCC_R77CIDCFGR				U(0x298)
+#define RCC_R77SEMCR				U(0x29C)
+#define RCC_R78CIDCFGR				U(0x2A0)
+#define RCC_R78SEMCR				U(0x2A4)
+#define RCC_R79CIDCFGR				U(0x2A8)
+#define RCC_R79SEMCR				U(0x2AC)
+#define RCC_R80CIDCFGR				U(0x2B0)
+#define RCC_R80SEMCR				U(0x2B4)
+#define RCC_R81CIDCFGR				U(0x2B8)
+#define RCC_R81SEMCR				U(0x2BC)
+#define RCC_R82CIDCFGR				U(0x2C0)
+#define RCC_R82SEMCR				U(0x2C4)
+#define RCC_R83CIDCFGR				U(0x2C8)
+#define RCC_R83SEMCR				U(0x2CC)
+#define RCC_R84CIDCFGR				U(0x2D0)
+#define RCC_R84SEMCR				U(0x2D4)
+#define RCC_R85CIDCFGR				U(0x2D8)
+#define RCC_R85SEMCR				U(0x2DC)
+#define RCC_R86CIDCFGR				U(0x2E0)
+#define RCC_R86SEMCR				U(0x2E4)
+#define RCC_R87CIDCFGR				U(0x2E8)
+#define RCC_R87SEMCR				U(0x2EC)
+#define RCC_R88CIDCFGR				U(0x2F0)
+#define RCC_R88SEMCR				U(0x2F4)
+#define RCC_R89CIDCFGR				U(0x2F8)
+#define RCC_R89SEMCR				U(0x2FC)
+#define RCC_R90CIDCFGR				U(0x300)
+#define RCC_R90SEMCR				U(0x304)
+#define RCC_R91CIDCFGR				U(0x308)
+#define RCC_R91SEMCR				U(0x30C)
+#define RCC_R92CIDCFGR				U(0x310)
+#define RCC_R92SEMCR				U(0x314)
+#define RCC_R93CIDCFGR				U(0x318)
+#define RCC_R93SEMCR				U(0x31C)
+#define RCC_R94CIDCFGR				U(0x320)
+#define RCC_R94SEMCR				U(0x324)
+#define RCC_R95CIDCFGR				U(0x328)
+#define RCC_R95SEMCR				U(0x32C)
+#define RCC_R96CIDCFGR				U(0x330)
+#define RCC_R96SEMCR				U(0x334)
+#define RCC_R97CIDCFGR				U(0x338)
+#define RCC_R97SEMCR				U(0x33C)
+#define RCC_R98CIDCFGR				U(0x340)
+#define RCC_R98SEMCR				U(0x344)
+#define RCC_R99CIDCFGR				U(0x348)
+#define RCC_R99SEMCR				U(0x34C)
+#define RCC_R100CIDCFGR				U(0x350)
+#define RCC_R100SEMCR				U(0x354)
+#define RCC_R101CIDCFGR				U(0x358)
+#define RCC_R101SEMCR				U(0x35C)
+#define RCC_R102CIDCFGR				U(0x360)
+#define RCC_R102SEMCR				U(0x364)
+#define RCC_R103CIDCFGR				U(0x368)
+#define RCC_R103SEMCR				U(0x36C)
+#define RCC_R104CIDCFGR				U(0x370)
+#define RCC_R104SEMCR				U(0x374)
+#define RCC_R105CIDCFGR				U(0x378)
+#define RCC_R105SEMCR				U(0x37C)
+#define RCC_R106CIDCFGR				U(0x380)
+#define RCC_R106SEMCR				U(0x384)
+#define RCC_R107CIDCFGR				U(0x388)
+#define RCC_R107SEMCR				U(0x38C)
+#define RCC_R108CIDCFGR				U(0x390)
+#define RCC_R108SEMCR				U(0x394)
+#define RCC_R109CIDCFGR				U(0x398)
+#define RCC_R109SEMCR				U(0x39C)
+#define RCC_R110CIDCFGR				U(0x3A0)
+#define RCC_R110SEMCR				U(0x3A4)
+#define RCC_R111CIDCFGR				U(0x3A8)
+#define RCC_R111SEMCR				U(0x3AC)
+#define RCC_R112CIDCFGR				U(0x3B0)
+#define RCC_R112SEMCR				U(0x3B4)
+#define RCC_R113CIDCFGR				U(0x3B8)
+#define RCC_R113SEMCR				U(0x3BC)
+#define RCC_GRSTCSETR				U(0x400)
+#define RCC_C1RSTCSETR				U(0x404)
+#define RCC_C2RSTCSETR				U(0x40C)
+#define RCC_HWRSTSCLRR				U(0x410)
+#define RCC_C1HWRSTSCLRR			U(0x414)
+#define RCC_C2HWRSTSCLRR			U(0x418)
+#define RCC_C1BOOTRSTSSETR			U(0x41C)
+#define RCC_C1BOOTRSTSCLRR			U(0x420)
+#define RCC_C2BOOTRSTSSETR			U(0x424)
+#define RCC_C2BOOTRSTSCLRR			U(0x428)
+#define RCC_C1SREQSETR				U(0x42C)
+#define RCC_C1SREQCLRR				U(0x430)
+#define RCC_CPUBOOTCR				U(0x434)
+#define RCC_STBYBOOTCR				U(0x438)
+#define RCC_LEGBOOTCR				U(0x43C)
+#define RCC_BDCR				U(0x440)
+#define RCC_RDCR				U(0x44C)
+#define RCC_C1MSRDCR				U(0x450)
+#define RCC_PWRLPDLYCR				U(0x454)
+#define RCC_C1CIESETR				U(0x458)
+#define RCC_C1CIFCLRR				U(0x45C)
+#define RCC_C2CIESETR				U(0x460)
+#define RCC_C2CIFCLRR				U(0x464)
+#define RCC_IWDGC1FZSETR			U(0x468)
+#define RCC_IWDGC1FZCLRR			U(0x46C)
+#define RCC_IWDGC1CFGSETR			U(0x470)
+#define RCC_IWDGC1CFGCLRR			U(0x474)
+#define RCC_IWDGC2FZSETR			U(0x478)
+#define RCC_IWDGC2FZCLRR			U(0x47C)
+#define RCC_IWDGC2CFGSETR			U(0x480)
+#define RCC_IWDGC2CFGCLRR			U(0x484)
+#define RCC_MCO1CFGR				U(0x488)
+#define RCC_MCO2CFGR				U(0x48C)
+#define RCC_OCENSETR				U(0x490)
+#define RCC_OCENCLRR				U(0x494)
+#define RCC_OCRDYR				U(0x498)
+#define RCC_HSICFGR				U(0x49C)
+#define RCC_MSICFGR				U(0x4A0)
+#define RCC_LSICR				U(0x4A4)
+#define RCC_RTCDIVR				U(0x4A8)
+#define RCC_APB1DIVR				U(0x4AC)
+#define RCC_APB2DIVR				U(0x4B0)
+#define RCC_APB3DIVR				U(0x4B4)
+#define RCC_APB4DIVR				U(0x4B8)
+#define RCC_APB5DIVR				U(0x4BC)
+#define RCC_APBDBGDIVR				U(0x4C0)
+#define RCC_TIMG1PRER				U(0x4C8)
+#define RCC_TIMG2PRER				U(0x4CC)
+#define RCC_LSMCUDIVR				U(0x4D0)
+#define RCC_DDRCPCFGR				U(0x4D4)
+#define RCC_DDRCAPBCFGR				U(0x4D8)
+#define RCC_DDRPHYCAPBCFGR			U(0x4DC)
+#define RCC_DDRPHYCCFGR				U(0x4E0)
+#define RCC_DDRCFGR				U(0x4E4)
+#define RCC_DDRITFCFGR				U(0x4E8)
+#define RCC_SYSRAMCFGR				U(0x4F0)
+#define RCC_SRAM1CFGR				U(0x4F8)
+#define RCC_RETRAMCFGR				U(0x500)
+#define RCC_BKPSRAMCFGR				U(0x504)
+#define RCC_OSPI1CFGR				U(0x514)
+#define RCC_FMCCFGR				U(0x51C)
+#define RCC_DBGCFGR				U(0x520)
+#define RCC_STMCFGR				U(0x524)
+#define RCC_ETRCFGR				U(0x528)
+#define RCC_GPIOACFGR				U(0x52C)
+#define RCC_GPIOBCFGR				U(0x530)
+#define RCC_GPIOCCFGR				U(0x534)
+#define RCC_GPIODCFGR				U(0x538)
+#define RCC_GPIOECFGR				U(0x53C)
+#define RCC_GPIOFCFGR				U(0x540)
+#define RCC_GPIOGCFGR				U(0x544)
+#define RCC_GPIOHCFGR				U(0x548)
+#define RCC_GPIOICFGR				U(0x54C)
+#define RCC_GPIOZCFGR				U(0x558)
+#define RCC_HPDMA1CFGR				U(0x55C)
+#define RCC_HPDMA2CFGR				U(0x560)
+#define RCC_HPDMA3CFGR				U(0x564)
+#define RCC_IPCC1CFGR				U(0x570)
+#define RCC_RTCCFGR				U(0x578)
+#define RCC_SYSCPU1CFGR				U(0x580)
+#define RCC_BSECCFGR				U(0x584)
+#define RCC_PLL2CFGR1				U(0x590)
+#define RCC_PLL2CFGR2				U(0x594)
+#define RCC_PLL2CFGR3				U(0x598)
+#define RCC_PLL2CFGR4				U(0x59C)
+#define RCC_PLL2CFGR5				U(0x5A0)
+#define RCC_PLL2CFGR6				U(0x5A8)
+#define RCC_PLL2CFGR7				U(0x5AC)
+#define RCC_HSIFMONCR				U(0x5E0)
+#define RCC_HSIFVALR				U(0x5E4)
+#define RCC_MSIFMONCR				U(0x5E8)
+#define RCC_MSIFVALR				U(0x5EC)
+#define RCC_TIM1CFGR				U(0x700)
+#define RCC_TIM2CFGR				U(0x704)
+#define RCC_TIM3CFGR				U(0x708)
+#define RCC_TIM4CFGR				U(0x70C)
+#define RCC_TIM5CFGR				U(0x710)
+#define RCC_TIM6CFGR				U(0x714)
+#define RCC_TIM7CFGR				U(0x718)
+#define RCC_TIM8CFGR				U(0x71C)
+#define RCC_TIM10CFGR				U(0x720)
+#define RCC_TIM11CFGR				U(0x724)
+#define RCC_TIM12CFGR				U(0x728)
+#define RCC_TIM13CFGR				U(0x72C)
+#define RCC_TIM14CFGR				U(0x730)
+#define RCC_TIM15CFGR				U(0x734)
+#define RCC_TIM16CFGR				U(0x738)
+#define RCC_TIM17CFGR				U(0x73C)
+#define RCC_LPTIM1CFGR				U(0x744)
+#define RCC_LPTIM2CFGR				U(0x748)
+#define RCC_LPTIM3CFGR				U(0x74C)
+#define RCC_LPTIM4CFGR				U(0x750)
+#define RCC_LPTIM5CFGR				U(0x754)
+#define RCC_SPI1CFGR				U(0x758)
+#define RCC_SPI2CFGR				U(0x75C)
+#define RCC_SPI3CFGR				U(0x760)
+#define RCC_SPI4CFGR				U(0x764)
+#define RCC_SPI5CFGR				U(0x768)
+#define RCC_SPI6CFGR				U(0x76C)
+#define RCC_SPDIFRXCFGR				U(0x778)
+#define RCC_USART1CFGR				U(0x77C)
+#define RCC_USART2CFGR				U(0x780)
+#define RCC_USART3CFGR				U(0x784)
+#define RCC_UART4CFGR				U(0x788)
+#define RCC_UART5CFGR				U(0x78C)
+#define RCC_USART6CFGR				U(0x790)
+#define RCC_UART7CFGR				U(0x794)
+#define RCC_LPUART1CFGR				U(0x7A0)
+#define RCC_I2C1CFGR				U(0x7A4)
+#define RCC_I2C2CFGR				U(0x7A8)
+#define RCC_I2C3CFGR				U(0x7AC)
+#define RCC_SAI1CFGR				U(0x7C4)
+#define RCC_SAI2CFGR				U(0x7C8)
+#define RCC_SAI3CFGR				U(0x7CC)
+#define RCC_SAI4CFGR				U(0x7D0)
+#define RCC_MDF1CFGR				U(0x7D8)
+#define RCC_FDCANCFGR				U(0x7E0)
+#define RCC_HDPCFGR				U(0x7E4)
+#define RCC_ADC1CFGR				U(0x7E8)
+#define RCC_ADC2CFGR				U(0x7EC)
+#define RCC_ETH1CFGR				U(0x7F0)
+#define RCC_ETH2CFGR				U(0x7F4)
+#define RCC_USBHCFGR				U(0x7FC)
+#define RCC_USB2PHY1CFGR			U(0x800)
+#define RCC_OTGCFGR				U(0x808)
+#define RCC_USB2PHY2CFGR			U(0x80C)
+#define RCC_STGENCFGR				U(0x824)
+#define RCC_SDMMC1CFGR				U(0x830)
+#define RCC_SDMMC2CFGR				U(0x834)
+#define RCC_SDMMC3CFGR				U(0x838)
+#define RCC_LTDCCFGR				U(0x840)
+#define RCC_CSICFGR				U(0x858)
+#define RCC_DCMIPPCFGR				U(0x85C)
+#define RCC_DCMIPSSICFGR			U(0x860)
+#define RCC_RNG1CFGR				U(0x870)
+#define RCC_RNG2CFGR				U(0x874)
+#define RCC_PKACFGR				U(0x878)
+#define RCC_SAESCFGR				U(0x87C)
+#define RCC_HASH1CFGR				U(0x880)
+#define RCC_HASH2CFGR				U(0x884)
+#define RCC_CRYP1CFGR				U(0x888)
+#define RCC_CRYP2CFGR				U(0x88C)
+#define RCC_IWDG1CFGR				U(0x894)
+#define RCC_IWDG2CFGR				U(0x898)
+#define RCC_IWDG3CFGR				U(0x89C)
+#define RCC_IWDG4CFGR				U(0x8A0)
+#define RCC_WWDG1CFGR				U(0x8A4)
+#define RCC_VREFCFGR				U(0x8AC)
+#define RCC_DTSCFGR				U(0x8B0)
+#define RCC_CRCCFGR				U(0x8B4)
+#define RCC_SERCCFGR				U(0x8B8)
+#define RCC_DDRPERFMCFGR			U(0x8C0)
+#define RCC_I3C1CFGR				U(0x8C8)
+#define RCC_I3C2CFGR				U(0x8CC)
+#define RCC_I3C3CFGR				U(0x8D0)
+#define RCC_MUXSELCFGR				U(0x1000)
+#define RCC_XBAR0CFGR				U(0x1018)
+#define RCC_XBAR1CFGR				U(0x101C)
+#define RCC_XBAR2CFGR				U(0x1020)
+#define RCC_XBAR3CFGR				U(0x1024)
+#define RCC_XBAR4CFGR				U(0x1028)
+#define RCC_XBAR5CFGR				U(0x102C)
+#define RCC_XBAR6CFGR				U(0x1030)
+#define RCC_XBAR7CFGR				U(0x1034)
+#define RCC_XBAR8CFGR				U(0x1038)
+#define RCC_XBAR9CFGR				U(0x103C)
+#define RCC_XBAR10CFGR				U(0x1040)
+#define RCC_XBAR11CFGR				U(0x1044)
+#define RCC_XBAR12CFGR				U(0x1048)
+#define RCC_XBAR13CFGR				U(0x104C)
+#define RCC_XBAR14CFGR				U(0x1050)
+#define RCC_XBAR15CFGR				U(0x1054)
+#define RCC_XBAR16CFGR				U(0x1058)
+#define RCC_XBAR17CFGR				U(0x105C)
+#define RCC_XBAR18CFGR				U(0x1060)
+#define RCC_XBAR19CFGR				U(0x1064)
+#define RCC_XBAR20CFGR				U(0x1068)
+#define RCC_XBAR21CFGR				U(0x106C)
+#define RCC_XBAR22CFGR				U(0x1070)
+#define RCC_XBAR23CFGR				U(0x1074)
+#define RCC_XBAR24CFGR				U(0x1078)
+#define RCC_XBAR25CFGR				U(0x107C)
+#define RCC_XBAR26CFGR				U(0x1080)
+#define RCC_XBAR27CFGR				U(0x1084)
+#define RCC_XBAR28CFGR				U(0x1088)
+#define RCC_XBAR29CFGR				U(0x108C)
+#define RCC_XBAR30CFGR				U(0x1090)
+#define RCC_XBAR31CFGR				U(0x1094)
+#define RCC_XBAR32CFGR				U(0x1098)
+#define RCC_XBAR33CFGR				U(0x109C)
+#define RCC_XBAR34CFGR				U(0x10A0)
+#define RCC_XBAR35CFGR				U(0x10A4)
+#define RCC_XBAR36CFGR				U(0x10A8)
+#define RCC_XBAR37CFGR				U(0x10AC)
+#define RCC_XBAR38CFGR				U(0x10B0)
+#define RCC_XBAR39CFGR				U(0x10B4)
+#define RCC_XBAR40CFGR				U(0x10B8)
+#define RCC_XBAR41CFGR				U(0x10BC)
+#define RCC_XBAR42CFGR				U(0x10C0)
+#define RCC_XBAR43CFGR				U(0x10C4)
+#define RCC_XBAR44CFGR				U(0x10C8)
+#define RCC_XBAR45CFGR				U(0x10CC)
+#define RCC_XBAR46CFGR				U(0x10D0)
+#define RCC_XBAR47CFGR				U(0x10D4)
+#define RCC_XBAR48CFGR				U(0x10D8)
+#define RCC_XBAR49CFGR				U(0x10DC)
+#define RCC_XBAR50CFGR				U(0x10E0)
+#define RCC_XBAR51CFGR				U(0x10E4)
+#define RCC_XBAR52CFGR				U(0x10E8)
+#define RCC_XBAR53CFGR				U(0x10EC)
+#define RCC_XBAR54CFGR				U(0x10F0)
+#define RCC_XBAR55CFGR				U(0x10F4)
+#define RCC_XBAR56CFGR				U(0x10F8)
+#define RCC_XBAR57CFGR				U(0x10FC)
+#define RCC_XBAR58CFGR				U(0x1100)
+#define RCC_XBAR59CFGR				U(0x1104)
+#define RCC_XBAR60CFGR				U(0x1108)
+#define RCC_XBAR61CFGR				U(0x110C)
+#define RCC_XBAR62CFGR				U(0x1110)
+#define RCC_XBAR63CFGR				U(0x1114)
+#define RCC_PREDIV0CFGR				U(0x1118)
+#define RCC_PREDIV1CFGR				U(0x111C)
+#define RCC_PREDIV2CFGR				U(0x1120)
+#define RCC_PREDIV3CFGR				U(0x1124)
+#define RCC_PREDIV4CFGR				U(0x1128)
+#define RCC_PREDIV5CFGR				U(0x112C)
+#define RCC_PREDIV6CFGR				U(0x1130)
+#define RCC_PREDIV7CFGR				U(0x1134)
+#define RCC_PREDIV8CFGR				U(0x1138)
+#define RCC_PREDIV9CFGR				U(0x113C)
+#define RCC_PREDIV10CFGR			U(0x1140)
+#define RCC_PREDIV11CFGR			U(0x1144)
+#define RCC_PREDIV12CFGR			U(0x1148)
+#define RCC_PREDIV13CFGR			U(0x114C)
+#define RCC_PREDIV14CFGR			U(0x1150)
+#define RCC_PREDIV15CFGR			U(0x1154)
+#define RCC_PREDIV16CFGR			U(0x1158)
+#define RCC_PREDIV17CFGR			U(0x115C)
+#define RCC_PREDIV18CFGR			U(0x1160)
+#define RCC_PREDIV19CFGR			U(0x1164)
+#define RCC_PREDIV20CFGR			U(0x1168)
+#define RCC_PREDIV21CFGR			U(0x116C)
+#define RCC_PREDIV22CFGR			U(0x1170)
+#define RCC_PREDIV23CFGR			U(0x1174)
+#define RCC_PREDIV24CFGR			U(0x1178)
+#define RCC_PREDIV25CFGR			U(0x117C)
+#define RCC_PREDIV26CFGR			U(0x1180)
+#define RCC_PREDIV27CFGR			U(0x1184)
+#define RCC_PREDIV28CFGR			U(0x1188)
+#define RCC_PREDIV29CFGR			U(0x118C)
+#define RCC_PREDIV30CFGR			U(0x1190)
+#define RCC_PREDIV31CFGR			U(0x1194)
+#define RCC_PREDIV32CFGR			U(0x1198)
+#define RCC_PREDIV33CFGR			U(0x119C)
+#define RCC_PREDIV34CFGR			U(0x11A0)
+#define RCC_PREDIV35CFGR			U(0x11A4)
+#define RCC_PREDIV36CFGR			U(0x11A8)
+#define RCC_PREDIV37CFGR			U(0x11AC)
+#define RCC_PREDIV38CFGR			U(0x11B0)
+#define RCC_PREDIV39CFGR			U(0x11B4)
+#define RCC_PREDIV40CFGR			U(0x11B8)
+#define RCC_PREDIV41CFGR			U(0x11BC)
+#define RCC_PREDIV42CFGR			U(0x11C0)
+#define RCC_PREDIV43CFGR			U(0x11C4)
+#define RCC_PREDIV44CFGR			U(0x11C8)
+#define RCC_PREDIV45CFGR			U(0x11CC)
+#define RCC_PREDIV46CFGR			U(0x11D0)
+#define RCC_PREDIV47CFGR			U(0x11D4)
+#define RCC_PREDIV48CFGR			U(0x11D8)
+#define RCC_PREDIV49CFGR			U(0x11DC)
+#define RCC_PREDIV50CFGR			U(0x11E0)
+#define RCC_PREDIV51CFGR			U(0x11E4)
+#define RCC_PREDIV52CFGR			U(0x11E8)
+#define RCC_PREDIV53CFGR			U(0x11EC)
+#define RCC_PREDIV54CFGR			U(0x11F0)
+#define RCC_PREDIV55CFGR			U(0x11F4)
+#define RCC_PREDIV56CFGR			U(0x11F8)
+#define RCC_PREDIV57CFGR			U(0x11FC)
+#define RCC_PREDIV58CFGR			U(0x1200)
+#define RCC_PREDIV59CFGR			U(0x1204)
+#define RCC_PREDIV60CFGR			U(0x1208)
+#define RCC_PREDIV61CFGR			U(0x120C)
+#define RCC_PREDIV62CFGR			U(0x1210)
+#define RCC_PREDIV63CFGR			U(0x1214)
+#define RCC_PREDIVSR1				U(0x1218)
+#define RCC_PREDIVSR2				U(0x121C)
+#define RCC_FINDIV0CFGR				U(0x1224)
+#define RCC_FINDIV1CFGR				U(0x1228)
+#define RCC_FINDIV2CFGR				U(0x122C)
+#define RCC_FINDIV3CFGR				U(0x1230)
+#define RCC_FINDIV4CFGR				U(0x1234)
+#define RCC_FINDIV5CFGR				U(0x1238)
+#define RCC_FINDIV6CFGR				U(0x123C)
+#define RCC_FINDIV7CFGR				U(0x1240)
+#define RCC_FINDIV8CFGR				U(0x1244)
+#define RCC_FINDIV9CFGR				U(0x1248)
+#define RCC_FINDIV10CFGR			U(0x124C)
+#define RCC_FINDIV11CFGR			U(0x1250)
+#define RCC_FINDIV12CFGR			U(0x1254)
+#define RCC_FINDIV13CFGR			U(0x1258)
+#define RCC_FINDIV14CFGR			U(0x125C)
+#define RCC_FINDIV15CFGR			U(0x1260)
+#define RCC_FINDIV16CFGR			U(0x1264)
+#define RCC_FINDIV17CFGR			U(0x1268)
+#define RCC_FINDIV18CFGR			U(0x126C)
+#define RCC_FINDIV19CFGR			U(0x1270)
+#define RCC_FINDIV20CFGR			U(0x1274)
+#define RCC_FINDIV21CFGR			U(0x1278)
+#define RCC_FINDIV22CFGR			U(0x127C)
+#define RCC_FINDIV23CFGR			U(0x1280)
+#define RCC_FINDIV24CFGR			U(0x1284)
+#define RCC_FINDIV25CFGR			U(0x1288)
+#define RCC_FINDIV26CFGR			U(0x128C)
+#define RCC_FINDIV27CFGR			U(0x1290)
+#define RCC_FINDIV28CFGR			U(0x1294)
+#define RCC_FINDIV29CFGR			U(0x1298)
+#define RCC_FINDIV30CFGR			U(0x129C)
+#define RCC_FINDIV31CFGR			U(0x12A0)
+#define RCC_FINDIV32CFGR			U(0x12A4)
+#define RCC_FINDIV33CFGR			U(0x12A8)
+#define RCC_FINDIV34CFGR			U(0x12AC)
+#define RCC_FINDIV35CFGR			U(0x12B0)
+#define RCC_FINDIV36CFGR			U(0x12B4)
+#define RCC_FINDIV37CFGR			U(0x12B8)
+#define RCC_FINDIV38CFGR			U(0x12BC)
+#define RCC_FINDIV39CFGR			U(0x12C0)
+#define RCC_FINDIV40CFGR			U(0x12C4)
+#define RCC_FINDIV41CFGR			U(0x12C8)
+#define RCC_FINDIV42CFGR			U(0x12CC)
+#define RCC_FINDIV43CFGR			U(0x12D0)
+#define RCC_FINDIV44CFGR			U(0x12D4)
+#define RCC_FINDIV45CFGR			U(0x12D8)
+#define RCC_FINDIV46CFGR			U(0x12DC)
+#define RCC_FINDIV47CFGR			U(0x12E0)
+#define RCC_FINDIV48CFGR			U(0x12E4)
+#define RCC_FINDIV49CFGR			U(0x12E8)
+#define RCC_FINDIV50CFGR			U(0x12EC)
+#define RCC_FINDIV51CFGR			U(0x12F0)
+#define RCC_FINDIV52CFGR			U(0x12F4)
+#define RCC_FINDIV53CFGR			U(0x12F8)
+#define RCC_FINDIV54CFGR			U(0x12FC)
+#define RCC_FINDIV55CFGR			U(0x1300)
+#define RCC_FINDIV56CFGR			U(0x1304)
+#define RCC_FINDIV57CFGR			U(0x1308)
+#define RCC_FINDIV58CFGR			U(0x130C)
+#define RCC_FINDIV59CFGR			U(0x1310)
+#define RCC_FINDIV60CFGR			U(0x1314)
+#define RCC_FINDIV61CFGR			U(0x1318)
+#define RCC_FINDIV62CFGR			U(0x131C)
+#define RCC_FINDIV63CFGR			U(0x1320)
+#define RCC_FINDIVSR1				U(0x1324)
+#define RCC_FINDIVSR2				U(0x1328)
+#define RCC_FCALCOBS0CFGR			U(0x1340)
+#define RCC_FCALCOBS1CFGR			U(0x1344)
+#define RCC_FCALCREFCFGR			U(0x1348)
+#define RCC_FCALCCR1				U(0x134C)
+#define RCC_FCALCCR2				U(0x1354)
+#define RCC_FCALCSR				U(0x1358)
+#define RCC_PLL4CFGR1				U(0x1360)
+#define RCC_PLL4CFGR2				U(0x1364)
+#define RCC_PLL4CFGR3				U(0x1368)
+#define RCC_PLL4CFGR4				U(0x136C)
+#define RCC_PLL4CFGR5				U(0x1370)
+#define RCC_PLL4CFGR6				U(0x1378)
+#define RCC_PLL4CFGR7				U(0x137C)
+#define RCC_PLL5CFGR1				U(0x1388)
+#define RCC_PLL5CFGR2				U(0x138C)
+#define RCC_PLL5CFGR3				U(0x1390)
+#define RCC_PLL5CFGR4				U(0x1394)
+#define RCC_PLL5CFGR5				U(0x1398)
+#define RCC_PLL5CFGR6				U(0x13A0)
+#define RCC_PLL5CFGR7				U(0x13A4)
+#define RCC_PLL6CFGR1				U(0x13B0)
+#define RCC_PLL6CFGR2				U(0x13B4)
+#define RCC_PLL6CFGR3				U(0x13B8)
+#define RCC_PLL6CFGR4				U(0x13BC)
+#define RCC_PLL6CFGR5				U(0x13C0)
+#define RCC_PLL6CFGR6				U(0x13C8)
+#define RCC_PLL6CFGR7				U(0x13CC)
+#define RCC_PLL7CFGR1				U(0x13D8)
+#define RCC_PLL7CFGR2				U(0x13DC)
+#define RCC_PLL7CFGR3				U(0x13E0)
+#define RCC_PLL7CFGR4				U(0x13E4)
+#define RCC_PLL7CFGR5				U(0x13E8)
+#define RCC_PLL7CFGR6				U(0x13F0)
+#define RCC_PLL7CFGR7				U(0x13F4)
+#define RCC_PLL8CFGR1				U(0x1400)
+#define RCC_PLL8CFGR2				U(0x1404)
+#define RCC_PLL8CFGR3				U(0x1408)
+#define RCC_PLL8CFGR4				U(0x140C)
+#define RCC_PLL8CFGR5				U(0x1410)
+#define RCC_PLL8CFGR6				U(0x1418)
+#define RCC_PLL8CFGR7				U(0x141C)
+#define RCC_VERR				U(0xFFF4)
+#define RCC_IDR					U(0xFFF8)
+#define RCC_SIDR				U(0xFFFC)
+
+/* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
+#define RCC_MP_ENCLRR_OFFSET			U(4)
+
+/* RCC_SECCFGR3 register fields */
+#define RCC_SECCFGR3_SEC_MASK			GENMASK_32(17, 0)
+#define RCC_SECCFGR3_SEC_SHIFT			0
+
+/* RCC_PRIVCFGR3 register fields */
+#define RCC_PRIVCFGR3_PRIV_MASK			GENMASK_32(17, 0)
+#define RCC_PRIVCFGR3_PRIV_SHIFT		0
+
+/* RCC_RCFGLOCKR3 register fields */
+#define RCC_RCFGLOCKR3_RLOCK_MASK		GENMASK_32(17, 0)
+#define RCC_RCFGLOCKR3_RLOCK_SHIFT		0
+
+/* RCC_R0CIDCFGR register fields */
+#define RCC_R0CIDCFGR_CFEN			BIT(0)
+#define RCC_R0CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R0CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define RCC_R0CIDCFGR_SCID_SHIFT		4
+#define RCC_R0CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R0CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R0SEMCR register fields */
+#define RCC_R0SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R0SEMCR_SEMCID_MASK			GENMASK_32(6, 4)
+#define RCC_R0SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R1CIDCFGR register fields */
+#define RCC_R1CIDCFGR_CFEN			BIT(0)
+#define RCC_R1CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R1CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define RCC_R1CIDCFGR_SCID_SHIFT		4
+#define RCC_R1CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R1CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R1SEMCR register fields */
+#define RCC_R1SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R1SEMCR_SEMCID_MASK			GENMASK_32(6, 4)
+#define RCC_R1SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R2CIDCFGR register fields */
+#define RCC_R2CIDCFGR_CFEN			BIT(0)
+#define RCC_R2CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R2CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define RCC_R2CIDCFGR_SCID_SHIFT		4
+#define RCC_R2CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R2CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R2SEMCR register fields */
+#define RCC_R2SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R2SEMCR_SEMCID_MASK			GENMASK_32(6, 4)
+#define RCC_R2SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R3CIDCFGR register fields */
+#define RCC_R3CIDCFGR_CFEN			BIT(0)
+#define RCC_R3CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R3CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define RCC_R3CIDCFGR_SCID_SHIFT		4
+#define RCC_R3CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R3CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R3SEMCR register fields */
+#define RCC_R3SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R3SEMCR_SEMCID_MASK			GENMASK_32(6, 4)
+#define RCC_R3SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R4CIDCFGR register fields */
+#define RCC_R4CIDCFGR_CFEN			BIT(0)
+#define RCC_R4CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R4CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define RCC_R4CIDCFGR_SCID_SHIFT		4
+#define RCC_R4CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R4CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R4SEMCR register fields */
+#define RCC_R4SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R4SEMCR_SEMCID_MASK			GENMASK_32(6, 4)
+#define RCC_R4SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R5CIDCFGR register fields */
+#define RCC_R5CIDCFGR_CFEN			BIT(0)
+#define RCC_R5CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R5CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define RCC_R5CIDCFGR_SCID_SHIFT		4
+#define RCC_R5CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R5CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R5SEMCR register fields */
+#define RCC_R5SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R5SEMCR_SEMCID_MASK			GENMASK_32(6, 4)
+#define RCC_R5SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R6CIDCFGR register fields */
+#define RCC_R6CIDCFGR_CFEN			BIT(0)
+#define RCC_R6CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R6CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define RCC_R6CIDCFGR_SCID_SHIFT		4
+#define RCC_R6CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R6CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R6SEMCR register fields */
+#define RCC_R6SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R6SEMCR_SEMCID_MASK			GENMASK_32(6, 4)
+#define RCC_R6SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R7CIDCFGR register fields */
+#define RCC_R7CIDCFGR_CFEN			BIT(0)
+#define RCC_R7CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R7CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define RCC_R7CIDCFGR_SCID_SHIFT		4
+#define RCC_R7CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R7CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R7SEMCR register fields */
+#define RCC_R7SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R7SEMCR_SEMCID_MASK			GENMASK_32(6, 4)
+#define RCC_R7SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R8CIDCFGR register fields */
+#define RCC_R8CIDCFGR_CFEN			BIT(0)
+#define RCC_R8CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R8CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define RCC_R8CIDCFGR_SCID_SHIFT		4
+#define RCC_R8CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R8CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R8SEMCR register fields */
+#define RCC_R8SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R8SEMCR_SEMCID_MASK			GENMASK_32(6, 4)
+#define RCC_R8SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R9CIDCFGR register fields */
+#define RCC_R9CIDCFGR_CFEN			BIT(0)
+#define RCC_R9CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R9CIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define RCC_R9CIDCFGR_SCID_SHIFT		4
+#define RCC_R9CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R9CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R9SEMCR register fields */
+#define RCC_R9SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R9SEMCR_SEMCID_MASK			GENMASK_32(6, 4)
+#define RCC_R9SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R10CIDCFGR register fields */
+#define RCC_R10CIDCFGR_CFEN			BIT(0)
+#define RCC_R10CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R10CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R10CIDCFGR_SCID_SHIFT		4
+#define RCC_R10CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R10CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R10SEMCR register fields */
+#define RCC_R10SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R10SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R10SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R11CIDCFGR register fields */
+#define RCC_R11CIDCFGR_CFEN			BIT(0)
+#define RCC_R11CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R11CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R11CIDCFGR_SCID_SHIFT		4
+#define RCC_R11CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R11CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R11SEMCR register fields */
+#define RCC_R11SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R11SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R11SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R12CIDCFGR register fields */
+#define RCC_R12CIDCFGR_CFEN			BIT(0)
+#define RCC_R12CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R12CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R12CIDCFGR_SCID_SHIFT		4
+#define RCC_R12CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R12CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R12SEMCR register fields */
+#define RCC_R12SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R12SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R12SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R13CIDCFGR register fields */
+#define RCC_R13CIDCFGR_CFEN			BIT(0)
+#define RCC_R13CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R13CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R13CIDCFGR_SCID_SHIFT		4
+#define RCC_R13CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R13CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R13SEMCR register fields */
+#define RCC_R13SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R13SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R13SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R14CIDCFGR register fields */
+#define RCC_R14CIDCFGR_CFEN			BIT(0)
+#define RCC_R14CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R14CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R14CIDCFGR_SCID_SHIFT		4
+#define RCC_R14CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R14CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R14SEMCR register fields */
+#define RCC_R14SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R14SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R14SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R15CIDCFGR register fields */
+#define RCC_R15CIDCFGR_CFEN			BIT(0)
+#define RCC_R15CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R15CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R15CIDCFGR_SCID_SHIFT		4
+#define RCC_R15CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R15CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R15SEMCR register fields */
+#define RCC_R15SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R15SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R15SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R16CIDCFGR register fields */
+#define RCC_R16CIDCFGR_CFEN			BIT(0)
+#define RCC_R16CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R16CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R16CIDCFGR_SCID_SHIFT		4
+#define RCC_R16CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R16CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R16SEMCR register fields */
+#define RCC_R16SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R16SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R16SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R17CIDCFGR register fields */
+#define RCC_R17CIDCFGR_CFEN			BIT(0)
+#define RCC_R17CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R17CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R17CIDCFGR_SCID_SHIFT		4
+#define RCC_R17CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R17CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R17SEMCR register fields */
+#define RCC_R17SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R17SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R17SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R18CIDCFGR register fields */
+#define RCC_R18CIDCFGR_CFEN			BIT(0)
+#define RCC_R18CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R18CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R18CIDCFGR_SCID_SHIFT		4
+#define RCC_R18CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R18CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R18SEMCR register fields */
+#define RCC_R18SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R18SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R18SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R19CIDCFGR register fields */
+#define RCC_R19CIDCFGR_CFEN			BIT(0)
+#define RCC_R19CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R19CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R19CIDCFGR_SCID_SHIFT		4
+#define RCC_R19CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R19CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R19SEMCR register fields */
+#define RCC_R19SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R19SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R19SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R20CIDCFGR register fields */
+#define RCC_R20CIDCFGR_CFEN			BIT(0)
+#define RCC_R20CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R20CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R20CIDCFGR_SCID_SHIFT		4
+#define RCC_R20CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R20CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R20SEMCR register fields */
+#define RCC_R20SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R20SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R20SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R21CIDCFGR register fields */
+#define RCC_R21CIDCFGR_CFEN			BIT(0)
+#define RCC_R21CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R21CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R21CIDCFGR_SCID_SHIFT		4
+#define RCC_R21CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R21CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R21SEMCR register fields */
+#define RCC_R21SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R21SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R21SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R22CIDCFGR register fields */
+#define RCC_R22CIDCFGR_CFEN			BIT(0)
+#define RCC_R22CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R22CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R22CIDCFGR_SCID_SHIFT		4
+#define RCC_R22CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R22CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R22SEMCR register fields */
+#define RCC_R22SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R22SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R22SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R23CIDCFGR register fields */
+#define RCC_R23CIDCFGR_CFEN			BIT(0)
+#define RCC_R23CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R23CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R23CIDCFGR_SCID_SHIFT		4
+#define RCC_R23CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R23CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R23SEMCR register fields */
+#define RCC_R23SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R23SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R23SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R24CIDCFGR register fields */
+#define RCC_R24CIDCFGR_CFEN			BIT(0)
+#define RCC_R24CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R24CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R24CIDCFGR_SCID_SHIFT		4
+#define RCC_R24CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R24CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R24SEMCR register fields */
+#define RCC_R24SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R24SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R24SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R25CIDCFGR register fields */
+#define RCC_R25CIDCFGR_CFEN			BIT(0)
+#define RCC_R25CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R25CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R25CIDCFGR_SCID_SHIFT		4
+#define RCC_R25CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R25CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R25SEMCR register fields */
+#define RCC_R25SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R25SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R25SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R26CIDCFGR register fields */
+#define RCC_R26CIDCFGR_CFEN			BIT(0)
+#define RCC_R26CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R26CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R26CIDCFGR_SCID_SHIFT		4
+#define RCC_R26CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R26CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R26SEMCR register fields */
+#define RCC_R26SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R26SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R26SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R27CIDCFGR register fields */
+#define RCC_R27CIDCFGR_CFEN			BIT(0)
+#define RCC_R27CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R27CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R27CIDCFGR_SCID_SHIFT		4
+#define RCC_R27CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R27CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R27SEMCR register fields */
+#define RCC_R27SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R27SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R27SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R28CIDCFGR register fields */
+#define RCC_R28CIDCFGR_CFEN			BIT(0)
+#define RCC_R28CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R28CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R28CIDCFGR_SCID_SHIFT		4
+#define RCC_R28CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R28CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R28SEMCR register fields */
+#define RCC_R28SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R28SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R28SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R29CIDCFGR register fields */
+#define RCC_R29CIDCFGR_CFEN			BIT(0)
+#define RCC_R29CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R29CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R29CIDCFGR_SCID_SHIFT		4
+#define RCC_R29CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R29CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R29SEMCR register fields */
+#define RCC_R29SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R29SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R29SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R30CIDCFGR register fields */
+#define RCC_R30CIDCFGR_CFEN			BIT(0)
+#define RCC_R30CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R30CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R30CIDCFGR_SCID_SHIFT		4
+#define RCC_R30CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R30CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R30SEMCR register fields */
+#define RCC_R30SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R30SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R30SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R31CIDCFGR register fields */
+#define RCC_R31CIDCFGR_CFEN			BIT(0)
+#define RCC_R31CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R31CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R31CIDCFGR_SCID_SHIFT		4
+#define RCC_R31CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R31CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R31SEMCR register fields */
+#define RCC_R31SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R31SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R31SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R32CIDCFGR register fields */
+#define RCC_R32CIDCFGR_CFEN			BIT(0)
+#define RCC_R32CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R32CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R32CIDCFGR_SCID_SHIFT		4
+#define RCC_R32CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R32CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R32SEMCR register fields */
+#define RCC_R32SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R32SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R32SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R33CIDCFGR register fields */
+#define RCC_R33CIDCFGR_CFEN			BIT(0)
+#define RCC_R33CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R33CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R33CIDCFGR_SCID_SHIFT		4
+#define RCC_R33CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R33CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R33SEMCR register fields */
+#define RCC_R33SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R33SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R33SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R34CIDCFGR register fields */
+#define RCC_R34CIDCFGR_CFEN			BIT(0)
+#define RCC_R34CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R34CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R34CIDCFGR_SCID_SHIFT		4
+#define RCC_R34CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R34CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R34SEMCR register fields */
+#define RCC_R34SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R34SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R34SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R35CIDCFGR register fields */
+#define RCC_R35CIDCFGR_CFEN			BIT(0)
+#define RCC_R35CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R35CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R35CIDCFGR_SCID_SHIFT		4
+#define RCC_R35CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R35CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R35SEMCR register fields */
+#define RCC_R35SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R35SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R35SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R36CIDCFGR register fields */
+#define RCC_R36CIDCFGR_CFEN			BIT(0)
+#define RCC_R36CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R36CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R36CIDCFGR_SCID_SHIFT		4
+#define RCC_R36CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R36CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R36SEMCR register fields */
+#define RCC_R36SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R36SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R36SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R37CIDCFGR register fields */
+#define RCC_R37CIDCFGR_CFEN			BIT(0)
+#define RCC_R37CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R37CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R37CIDCFGR_SCID_SHIFT		4
+#define RCC_R37CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R37CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R37SEMCR register fields */
+#define RCC_R37SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R37SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R37SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R38CIDCFGR register fields */
+#define RCC_R38CIDCFGR_CFEN			BIT(0)
+#define RCC_R38CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R38CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R38CIDCFGR_SCID_SHIFT		4
+#define RCC_R38CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R38CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R38SEMCR register fields */
+#define RCC_R38SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R38SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R38SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R39CIDCFGR register fields */
+#define RCC_R39CIDCFGR_CFEN			BIT(0)
+#define RCC_R39CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R39CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R39CIDCFGR_SCID_SHIFT		4
+#define RCC_R39CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R39CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R39SEMCR register fields */
+#define RCC_R39SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R39SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R39SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R40CIDCFGR register fields */
+#define RCC_R40CIDCFGR_CFEN			BIT(0)
+#define RCC_R40CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R40CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R40CIDCFGR_SCID_SHIFT		4
+#define RCC_R40CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R40CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R40SEMCR register fields */
+#define RCC_R40SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R40SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R40SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R41CIDCFGR register fields */
+#define RCC_R41CIDCFGR_CFEN			BIT(0)
+#define RCC_R41CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R41CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R41CIDCFGR_SCID_SHIFT		4
+#define RCC_R41CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R41CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R41SEMCR register fields */
+#define RCC_R41SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R41SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R41SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R42CIDCFGR register fields */
+#define RCC_R42CIDCFGR_CFEN			BIT(0)
+#define RCC_R42CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R42CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R42CIDCFGR_SCID_SHIFT		4
+#define RCC_R42CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R42CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R42SEMCR register fields */
+#define RCC_R42SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R42SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R42SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R43CIDCFGR register fields */
+#define RCC_R43CIDCFGR_CFEN			BIT(0)
+#define RCC_R43CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R43CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R43CIDCFGR_SCID_SHIFT		4
+#define RCC_R43CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R43CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R43SEMCR register fields */
+#define RCC_R43SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R43SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R43SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R44CIDCFGR register fields */
+#define RCC_R44CIDCFGR_CFEN			BIT(0)
+#define RCC_R44CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R44CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R44CIDCFGR_SCID_SHIFT		4
+#define RCC_R44CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R44CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R44SEMCR register fields */
+#define RCC_R44SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R44SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R44SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R45CIDCFGR register fields */
+#define RCC_R45CIDCFGR_CFEN			BIT(0)
+#define RCC_R45CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R45CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R45CIDCFGR_SCID_SHIFT		4
+#define RCC_R45CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R45CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R45SEMCR register fields */
+#define RCC_R45SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R45SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R45SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R46CIDCFGR register fields */
+#define RCC_R46CIDCFGR_CFEN			BIT(0)
+#define RCC_R46CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R46CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R46CIDCFGR_SCID_SHIFT		4
+#define RCC_R46CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R46CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R46SEMCR register fields */
+#define RCC_R46SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R46SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R46SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R47CIDCFGR register fields */
+#define RCC_R47CIDCFGR_CFEN			BIT(0)
+#define RCC_R47CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R47CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R47CIDCFGR_SCID_SHIFT		4
+#define RCC_R47CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R47CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R47SEMCR register fields */
+#define RCC_R47SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R47SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R47SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R48CIDCFGR register fields */
+#define RCC_R48CIDCFGR_CFEN			BIT(0)
+#define RCC_R48CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R48CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R48CIDCFGR_SCID_SHIFT		4
+#define RCC_R48CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R48CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R48SEMCR register fields */
+#define RCC_R48SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R48SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R48SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R49CIDCFGR register fields */
+#define RCC_R49CIDCFGR_CFEN			BIT(0)
+#define RCC_R49CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R49CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R49CIDCFGR_SCID_SHIFT		4
+#define RCC_R49CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R49CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R49SEMCR register fields */
+#define RCC_R49SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R49SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R49SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R50CIDCFGR register fields */
+#define RCC_R50CIDCFGR_CFEN			BIT(0)
+#define RCC_R50CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R50CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R50CIDCFGR_SCID_SHIFT		4
+#define RCC_R50CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R50CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R50SEMCR register fields */
+#define RCC_R50SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R50SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R50SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R51CIDCFGR register fields */
+#define RCC_R51CIDCFGR_CFEN			BIT(0)
+#define RCC_R51CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R51CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R51CIDCFGR_SCID_SHIFT		4
+#define RCC_R51CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R51CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R51SEMCR register fields */
+#define RCC_R51SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R51SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R51SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R52CIDCFGR register fields */
+#define RCC_R52CIDCFGR_CFEN			BIT(0)
+#define RCC_R52CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R52CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R52CIDCFGR_SCID_SHIFT		4
+#define RCC_R52CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R52CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R52SEMCR register fields */
+#define RCC_R52SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R52SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R52SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R53CIDCFGR register fields */
+#define RCC_R53CIDCFGR_CFEN			BIT(0)
+#define RCC_R53CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R53CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R53CIDCFGR_SCID_SHIFT		4
+#define RCC_R53CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R53CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R53SEMCR register fields */
+#define RCC_R53SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R53SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R53SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R54CIDCFGR register fields */
+#define RCC_R54CIDCFGR_CFEN			BIT(0)
+#define RCC_R54CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R54CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R54CIDCFGR_SCID_SHIFT		4
+#define RCC_R54CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R54CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R54SEMCR register fields */
+#define RCC_R54SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R54SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R54SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R55CIDCFGR register fields */
+#define RCC_R55CIDCFGR_CFEN			BIT(0)
+#define RCC_R55CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R55CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R55CIDCFGR_SCID_SHIFT		4
+#define RCC_R55CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R55CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R55SEMCR register fields */
+#define RCC_R55SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R55SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R55SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R56CIDCFGR register fields */
+#define RCC_R56CIDCFGR_CFEN			BIT(0)
+#define RCC_R56CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R56CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R56CIDCFGR_SCID_SHIFT		4
+#define RCC_R56CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R56CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R56SEMCR register fields */
+#define RCC_R56SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R56SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R56SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R57CIDCFGR register fields */
+#define RCC_R57CIDCFGR_CFEN			BIT(0)
+#define RCC_R57CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R57CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R57CIDCFGR_SCID_SHIFT		4
+#define RCC_R57CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R57CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R57SEMCR register fields */
+#define RCC_R57SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R57SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R57SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R58CIDCFGR register fields */
+#define RCC_R58CIDCFGR_CFEN			BIT(0)
+#define RCC_R58CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R58CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R58CIDCFGR_SCID_SHIFT		4
+#define RCC_R58CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R58CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R58SEMCR register fields */
+#define RCC_R58SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R58SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R58SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R59CIDCFGR register fields */
+#define RCC_R59CIDCFGR_CFEN			BIT(0)
+#define RCC_R59CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R59CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R59CIDCFGR_SCID_SHIFT		4
+#define RCC_R59CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R59CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R59SEMCR register fields */
+#define RCC_R59SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R59SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R59SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R60CIDCFGR register fields */
+#define RCC_R60CIDCFGR_CFEN			BIT(0)
+#define RCC_R60CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R60CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R60CIDCFGR_SCID_SHIFT		4
+#define RCC_R60CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R60CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R60SEMCR register fields */
+#define RCC_R60SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R60SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R60SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R61CIDCFGR register fields */
+#define RCC_R61CIDCFGR_CFEN			BIT(0)
+#define RCC_R61CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R61CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R61CIDCFGR_SCID_SHIFT		4
+#define RCC_R61CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R61CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R61SEMCR register fields */
+#define RCC_R61SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R61SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R61SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R62CIDCFGR register fields */
+#define RCC_R62CIDCFGR_CFEN			BIT(0)
+#define RCC_R62CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R62CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R62CIDCFGR_SCID_SHIFT		4
+#define RCC_R62CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R62CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R62SEMCR register fields */
+#define RCC_R62SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R62SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R62SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R63CIDCFGR register fields */
+#define RCC_R63CIDCFGR_CFEN			BIT(0)
+#define RCC_R63CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R63CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R63CIDCFGR_SCID_SHIFT		4
+#define RCC_R63CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R63CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R63SEMCR register fields */
+#define RCC_R63SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R63SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R63SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R64CIDCFGR register fields */
+#define RCC_R64CIDCFGR_CFEN			BIT(0)
+#define RCC_R64CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R64CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R64CIDCFGR_SCID_SHIFT		4
+#define RCC_R64CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R64CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R64SEMCR register fields */
+#define RCC_R64SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R64SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R64SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R65CIDCFGR register fields */
+#define RCC_R65CIDCFGR_CFEN			BIT(0)
+#define RCC_R65CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R65CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R65CIDCFGR_SCID_SHIFT		4
+#define RCC_R65CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R65CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R65SEMCR register fields */
+#define RCC_R65SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R65SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R65SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R66CIDCFGR register fields */
+#define RCC_R66CIDCFGR_CFEN			BIT(0)
+#define RCC_R66CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R66CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R66CIDCFGR_SCID_SHIFT		4
+#define RCC_R66CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R66CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R66SEMCR register fields */
+#define RCC_R66SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R66SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R66SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R67CIDCFGR register fields */
+#define RCC_R67CIDCFGR_CFEN			BIT(0)
+#define RCC_R67CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R67CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R67CIDCFGR_SCID_SHIFT		4
+#define RCC_R67CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R67CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R67SEMCR register fields */
+#define RCC_R67SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R67SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R67SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R68CIDCFGR register fields */
+#define RCC_R68CIDCFGR_CFEN			BIT(0)
+#define RCC_R68CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R68CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R68CIDCFGR_SCID_SHIFT		4
+#define RCC_R68CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R68CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R68SEMCR register fields */
+#define RCC_R68SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R68SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R68SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R69CIDCFGR register fields */
+#define RCC_R69CIDCFGR_CFEN			BIT(0)
+#define RCC_R69CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R69CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R69CIDCFGR_SCID_SHIFT		4
+#define RCC_R69CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R69CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R69SEMCR register fields */
+#define RCC_R69SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R69SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R69SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R70CIDCFGR register fields */
+#define RCC_R70CIDCFGR_CFEN			BIT(0)
+#define RCC_R70CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R70CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R70CIDCFGR_SCID_SHIFT		4
+#define RCC_R70CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R70CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R70SEMCR register fields */
+#define RCC_R70SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R70SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R70SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R71CIDCFGR register fields */
+#define RCC_R71CIDCFGR_CFEN			BIT(0)
+#define RCC_R71CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R71CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R71CIDCFGR_SCID_SHIFT		4
+#define RCC_R71CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R71CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R71SEMCR register fields */
+#define RCC_R71SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R71SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R71SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R72CIDCFGR register fields */
+#define RCC_R72CIDCFGR_CFEN			BIT(0)
+#define RCC_R72CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R72CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R72CIDCFGR_SCID_SHIFT		4
+#define RCC_R72CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R72CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R72SEMCR register fields */
+#define RCC_R72SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R72SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R72SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R73CIDCFGR register fields */
+#define RCC_R73CIDCFGR_CFEN			BIT(0)
+#define RCC_R73CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R73CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R73CIDCFGR_SCID_SHIFT		4
+#define RCC_R73CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R73CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R73SEMCR register fields */
+#define RCC_R73SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R73SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R73SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R74CIDCFGR register fields */
+#define RCC_R74CIDCFGR_CFEN			BIT(0)
+#define RCC_R74CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R74CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R74CIDCFGR_SCID_SHIFT		4
+#define RCC_R74CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R74CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R74SEMCR register fields */
+#define RCC_R74SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R74SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R74SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R75CIDCFGR register fields */
+#define RCC_R75CIDCFGR_CFEN			BIT(0)
+#define RCC_R75CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R75CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R75CIDCFGR_SCID_SHIFT		4
+#define RCC_R75CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R75CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R75SEMCR register fields */
+#define RCC_R75SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R75SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R75SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R76CIDCFGR register fields */
+#define RCC_R76CIDCFGR_CFEN			BIT(0)
+#define RCC_R76CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R76CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R76CIDCFGR_SCID_SHIFT		4
+#define RCC_R76CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R76CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R76SEMCR register fields */
+#define RCC_R76SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R76SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R76SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R77CIDCFGR register fields */
+#define RCC_R77CIDCFGR_CFEN			BIT(0)
+#define RCC_R77CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R77CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R77CIDCFGR_SCID_SHIFT		4
+#define RCC_R77CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R77CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R77SEMCR register fields */
+#define RCC_R77SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R77SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R77SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R78CIDCFGR register fields */
+#define RCC_R78CIDCFGR_CFEN			BIT(0)
+#define RCC_R78CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R78CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R78CIDCFGR_SCID_SHIFT		4
+#define RCC_R78CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R78CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R78SEMCR register fields */
+#define RCC_R78SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R78SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R78SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R79CIDCFGR register fields */
+#define RCC_R79CIDCFGR_CFEN			BIT(0)
+#define RCC_R79CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R79CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R79CIDCFGR_SCID_SHIFT		4
+#define RCC_R79CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R79CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R79SEMCR register fields */
+#define RCC_R79SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R79SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R79SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R80CIDCFGR register fields */
+#define RCC_R80CIDCFGR_CFEN			BIT(0)
+#define RCC_R80CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R80CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R80CIDCFGR_SCID_SHIFT		4
+#define RCC_R80CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R80CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R80SEMCR register fields */
+#define RCC_R80SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R80SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R80SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R81CIDCFGR register fields */
+#define RCC_R81CIDCFGR_CFEN			BIT(0)
+#define RCC_R81CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R81CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R81CIDCFGR_SCID_SHIFT		4
+#define RCC_R81CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R81CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R81SEMCR register fields */
+#define RCC_R81SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R81SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R81SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R82CIDCFGR register fields */
+#define RCC_R82CIDCFGR_CFEN			BIT(0)
+#define RCC_R82CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R82CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R82CIDCFGR_SCID_SHIFT		4
+#define RCC_R82CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R82CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R82SEMCR register fields */
+#define RCC_R82SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R82SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R82SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R83CIDCFGR register fields */
+#define RCC_R83CIDCFGR_CFEN			BIT(0)
+#define RCC_R83CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R83CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R83CIDCFGR_SCID_SHIFT		4
+#define RCC_R83CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R83CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R83SEMCR register fields */
+#define RCC_R83SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R83SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R83SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R84CIDCFGR register fields */
+#define RCC_R84CIDCFGR_CFEN			BIT(0)
+#define RCC_R84CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R84CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R84CIDCFGR_SCID_SHIFT		4
+#define RCC_R84CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R84CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R84SEMCR register fields */
+#define RCC_R84SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R84SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R84SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R85CIDCFGR register fields */
+#define RCC_R85CIDCFGR_CFEN			BIT(0)
+#define RCC_R85CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R85CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R85CIDCFGR_SCID_SHIFT		4
+#define RCC_R85CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R85CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R85SEMCR register fields */
+#define RCC_R85SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R85SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R85SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R86CIDCFGR register fields */
+#define RCC_R86CIDCFGR_CFEN			BIT(0)
+#define RCC_R86CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R86CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R86CIDCFGR_SCID_SHIFT		4
+#define RCC_R86CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R86CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R86SEMCR register fields */
+#define RCC_R86SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R86SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R86SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R87CIDCFGR register fields */
+#define RCC_R87CIDCFGR_CFEN			BIT(0)
+#define RCC_R87CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R87CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R87CIDCFGR_SCID_SHIFT		4
+#define RCC_R87CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R87CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R87SEMCR register fields */
+#define RCC_R87SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R87SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R87SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R88CIDCFGR register fields */
+#define RCC_R88CIDCFGR_CFEN			BIT(0)
+#define RCC_R88CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R88CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R88CIDCFGR_SCID_SHIFT		4
+#define RCC_R88CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R88CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R88SEMCR register fields */
+#define RCC_R88SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R88SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R88SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R89CIDCFGR register fields */
+#define RCC_R89CIDCFGR_CFEN			BIT(0)
+#define RCC_R89CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R89CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R89CIDCFGR_SCID_SHIFT		4
+#define RCC_R89CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R89CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R89SEMCR register fields */
+#define RCC_R89SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R89SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R89SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R90CIDCFGR register fields */
+#define RCC_R90CIDCFGR_CFEN			BIT(0)
+#define RCC_R90CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R90CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R90CIDCFGR_SCID_SHIFT		4
+#define RCC_R90CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R90CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R90SEMCR register fields */
+#define RCC_R90SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R90SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R90SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R91CIDCFGR register fields */
+#define RCC_R91CIDCFGR_CFEN			BIT(0)
+#define RCC_R91CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R91CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R91CIDCFGR_SCID_SHIFT		4
+#define RCC_R91CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R91CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R91SEMCR register fields */
+#define RCC_R91SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R91SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R91SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R92CIDCFGR register fields */
+#define RCC_R92CIDCFGR_CFEN			BIT(0)
+#define RCC_R92CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R92CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R92CIDCFGR_SCID_SHIFT		4
+#define RCC_R92CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R92CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R92SEMCR register fields */
+#define RCC_R92SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R92SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R92SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R93CIDCFGR register fields */
+#define RCC_R93CIDCFGR_CFEN			BIT(0)
+#define RCC_R93CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R93CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R93CIDCFGR_SCID_SHIFT		4
+#define RCC_R93CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R93CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R93SEMCR register fields */
+#define RCC_R93SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R93SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R93SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R94CIDCFGR register fields */
+#define RCC_R94CIDCFGR_CFEN			BIT(0)
+#define RCC_R94CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R94CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R94CIDCFGR_SCID_SHIFT		4
+#define RCC_R94CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R94CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R94SEMCR register fields */
+#define RCC_R94SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R94SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R94SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R95CIDCFGR register fields */
+#define RCC_R95CIDCFGR_CFEN			BIT(0)
+#define RCC_R95CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R95CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R95CIDCFGR_SCID_SHIFT		4
+#define RCC_R95CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R95CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R95SEMCR register fields */
+#define RCC_R95SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R95SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R95SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R96CIDCFGR register fields */
+#define RCC_R96CIDCFGR_CFEN			BIT(0)
+#define RCC_R96CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R96CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R96CIDCFGR_SCID_SHIFT		4
+#define RCC_R96CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R96CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R96SEMCR register fields */
+#define RCC_R96SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R96SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R96SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R97CIDCFGR register fields */
+#define RCC_R97CIDCFGR_CFEN			BIT(0)
+#define RCC_R97CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R97CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R97CIDCFGR_SCID_SHIFT		4
+#define RCC_R97CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R97CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R97SEMCR register fields */
+#define RCC_R97SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R97SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R97SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R98CIDCFGR register fields */
+#define RCC_R98CIDCFGR_CFEN			BIT(0)
+#define RCC_R98CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R98CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R98CIDCFGR_SCID_SHIFT		4
+#define RCC_R98CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R98CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R98SEMCR register fields */
+#define RCC_R98SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R98SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R98SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R99CIDCFGR register fields */
+#define RCC_R99CIDCFGR_CFEN			BIT(0)
+#define RCC_R99CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R99CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R99CIDCFGR_SCID_SHIFT		4
+#define RCC_R99CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R99CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R99SEMCR register fields */
+#define RCC_R99SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R99SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R99SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R100CIDCFGR register fields */
+#define RCC_R100CIDCFGR_CFEN			BIT(0)
+#define RCC_R100CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R100CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R100CIDCFGR_SCID_SHIFT		4
+#define RCC_R100CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R100CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R100SEMCR register fields */
+#define RCC_R100SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R100SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R100SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R101CIDCFGR register fields */
+#define RCC_R101CIDCFGR_CFEN			BIT(0)
+#define RCC_R101CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R101CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R101CIDCFGR_SCID_SHIFT		4
+#define RCC_R101CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R101CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R101SEMCR register fields */
+#define RCC_R101SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R101SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R101SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R102CIDCFGR register fields */
+#define RCC_R102CIDCFGR_CFEN			BIT(0)
+#define RCC_R102CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R102CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R102CIDCFGR_SCID_SHIFT		4
+#define RCC_R102CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R102CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R102SEMCR register fields */
+#define RCC_R102SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R102SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R102SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R103CIDCFGR register fields */
+#define RCC_R103CIDCFGR_CFEN			BIT(0)
+#define RCC_R103CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R103CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R103CIDCFGR_SCID_SHIFT		4
+#define RCC_R103CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R103CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R103SEMCR register fields */
+#define RCC_R103SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R103SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R103SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R104CIDCFGR register fields */
+#define RCC_R104CIDCFGR_CFEN			BIT(0)
+#define RCC_R104CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R104CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R104CIDCFGR_SCID_SHIFT		4
+#define RCC_R104CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R104CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R104SEMCR register fields */
+#define RCC_R104SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R104SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R104SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R105CIDCFGR register fields */
+#define RCC_R105CIDCFGR_CFEN			BIT(0)
+#define RCC_R105CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R105CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R105CIDCFGR_SCID_SHIFT		4
+#define RCC_R105CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R105CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R105SEMCR register fields */
+#define RCC_R105SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R105SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R105SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R106CIDCFGR register fields */
+#define RCC_R106CIDCFGR_CFEN			BIT(0)
+#define RCC_R106CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R106CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R106CIDCFGR_SCID_SHIFT		4
+#define RCC_R106CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R106CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R106SEMCR register fields */
+#define RCC_R106SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R106SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R106SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R107CIDCFGR register fields */
+#define RCC_R107CIDCFGR_CFEN			BIT(0)
+#define RCC_R107CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R107CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R107CIDCFGR_SCID_SHIFT		4
+#define RCC_R107CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R107CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R107SEMCR register fields */
+#define RCC_R107SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R107SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R107SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R108CIDCFGR register fields */
+#define RCC_R108CIDCFGR_CFEN			BIT(0)
+#define RCC_R108CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R108CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R108CIDCFGR_SCID_SHIFT		4
+#define RCC_R108CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R108CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R108SEMCR register fields */
+#define RCC_R108SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R108SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R108SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R109CIDCFGR register fields */
+#define RCC_R109CIDCFGR_CFEN			BIT(0)
+#define RCC_R109CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R109CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R109CIDCFGR_SCID_SHIFT		4
+#define RCC_R109CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R109CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R109SEMCR register fields */
+#define RCC_R109SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R109SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R109SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R110CIDCFGR register fields */
+#define RCC_R110CIDCFGR_CFEN			BIT(0)
+#define RCC_R110CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R110CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R110CIDCFGR_SCID_SHIFT		4
+#define RCC_R110CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R110CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R110SEMCR register fields */
+#define RCC_R110SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R110SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R110SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R111CIDCFGR register fields */
+#define RCC_R111CIDCFGR_CFEN			BIT(0)
+#define RCC_R111CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R111CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R111CIDCFGR_SCID_SHIFT		4
+#define RCC_R111CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R111CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R111SEMCR register fields */
+#define RCC_R111SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R111SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R111SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R112CIDCFGR register fields */
+#define RCC_R112CIDCFGR_CFEN			BIT(0)
+#define RCC_R112CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R112CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R112CIDCFGR_SCID_SHIFT		4
+#define RCC_R112CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R112CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R112SEMCR register fields */
+#define RCC_R112SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R112SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R112SEMCR_SEMCID_SHIFT		4
+
+/* RCC_R113CIDCFGR register fields */
+#define RCC_R113CIDCFGR_CFEN			BIT(0)
+#define RCC_R113CIDCFGR_SEM_EN			BIT(1)
+#define RCC_R113CIDCFGR_SCID_MASK		GENMASK_32(6, 4)
+#define RCC_R113CIDCFGR_SCID_SHIFT		4
+#define RCC_R113CIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_R113CIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_R113SEMCR register fields */
+#define RCC_R113SEMCR_SEM_MUTEX			BIT(0)
+#define RCC_R113SEMCR_SEMCID_MASK		GENMASK_32(6, 4)
+#define RCC_R113SEMCR_SEMCID_SHIFT		4
+
+/* RCC_RxCIDCFGR register fields */
+#define RCC_RxCIDCFGR_CFEN			BIT(0)
+#define RCC_RxCIDCFGR_SEM_EN			BIT(1)
+#define RCC_RxCIDCFGR_SCID_MASK			GENMASK_32(6, 4)
+#define RCC_RxCIDCFGR_SCID_SHIFT		4
+#define RCC_RxCIDCFGR_SEMWLC_MASK		GENMASK_32(23, 16)
+#define RCC_RxCIDCFGR_SEMWLC_SHIFT		16
+
+/* RCC_RxSEMCR register fields */
+#define RCC_RxSEMCR_SEM_MUTEX			BIT(0)
+#define RCC_RxSEMCR_SEMCID_MASK			GENMASK_32(6, 4)
+#define RCC_RxSEMCR_SEMCID_SHIFT		4
+
+/* RCC_GRSTCSETR register fields */
+#define RCC_GRSTCSETR_SYSRST			BIT(0)
+
+/* RCC_C1RSTCSETR register fields */
+#define RCC_C1RSTCSETR_C1RST			BIT(0)
+
+/* RCC_C2RSTCSETR register fields */
+#define RCC_C2RSTCSETR_C2RST			BIT(0)
+
+/* RCC_CxRSTCSETR register fields */
+#define RCC_CxRSTCSETR_CxRST			BIT(0)
+
+/* RCC_HWRSTSCLRR register fields */
+#define RCC_HWRSTSCLRR_PORRSTF			BIT(0)
+#define RCC_HWRSTSCLRR_BORRSTF			BIT(1)
+#define RCC_HWRSTSCLRR_PADRSTF			BIT(2)
+#define RCC_HWRSTSCLRR_HCSSRSTF			BIT(3)
+#define RCC_HWRSTSCLRR_VCORERSTF		BIT(4)
+#define RCC_HWRSTSCLRR_SYSC1RSTF		BIT(5)
+#define RCC_HWRSTSCLRR_SYSC2RSTF		BIT(6)
+#define RCC_HWRSTSCLRR_IWDG1SYSRSTF		BIT(7)
+#define RCC_HWRSTSCLRR_IWDG2SYSRSTF		BIT(8)
+#define RCC_HWRSTSCLRR_IWDG3SYSRSTF		BIT(9)
+#define RCC_HWRSTSCLRR_IWDG4SYSRSTF		BIT(10)
+#define RCC_HWRSTSCLRR_RETCRCERRRSTF		BIT(12)
+#define RCC_HWRSTSCLRR_RETECCFAILCRCRSTF	BIT(13)
+#define RCC_HWRSTSCLRR_RETECCFAILRESTRSTF	BIT(14)
+
+/* RCC_C1HWRSTSCLRR register fields */
+#define RCC_C1HWRSTSCLRR_VCPURSTF		BIT(0)
+#define RCC_C1HWRSTSCLRR_C1RSTF			BIT(1)
+
+/* RCC_C2HWRSTSCLRR register fields */
+#define RCC_C2HWRSTSCLRR_C2RSTF			BIT(0)
+
+/* RCC_C1BOOTRSTSSETR register fields */
+#define RCC_C1BOOTRSTSSETR_PORRSTF		BIT(0)
+#define RCC_C1BOOTRSTSSETR_BORRSTF		BIT(1)
+#define RCC_C1BOOTRSTSSETR_PADRSTF		BIT(2)
+#define RCC_C1BOOTRSTSSETR_HCSSRSTF		BIT(3)
+#define RCC_C1BOOTRSTSSETR_VCORERSTF		BIT(4)
+#define RCC_C1BOOTRSTSSETR_VCPURSTF		BIT(5)
+#define RCC_C1BOOTRSTSSETR_SYSC1RSTF		BIT(6)
+#define RCC_C1BOOTRSTSSETR_SYSC2RSTF		BIT(7)
+#define RCC_C1BOOTRSTSSETR_IWDG1SYSRSTF		BIT(8)
+#define RCC_C1BOOTRSTSSETR_IWDG2SYSRSTF		BIT(9)
+#define RCC_C1BOOTRSTSSETR_IWDG3SYSRSTF		BIT(10)
+#define RCC_C1BOOTRSTSSETR_IWDG4SYSRSTF		BIT(11)
+#define RCC_C1BOOTRSTSSETR_C1RSTF		BIT(13)
+#define RCC_C1BOOTRSTSSETR_RETCRCERRRSTF	BIT(17)
+#define RCC_C1BOOTRSTSSETR_RETECCFAILCRCRSTF	BIT(18)
+#define RCC_C1BOOTRSTSSETR_RETECCFAILRESTRSTF	BIT(19)
+#define RCC_C1BOOTRSTSSETR_STBYC1RSTF		BIT(20)
+#define RCC_C1BOOTRSTSSETR_D1STBYRSTF		BIT(22)
+#define RCC_C1BOOTRSTSSETR_D2STBYRSTF		BIT(23)
+
+/* RCC_C1BOOTRSTSCLRR register fields */
+#define RCC_C1BOOTRSTSCLRR_PORRSTF		BIT(0)
+#define RCC_C1BOOTRSTSCLRR_BORRSTF		BIT(1)
+#define RCC_C1BOOTRSTSCLRR_PADRSTF		BIT(2)
+#define RCC_C1BOOTRSTSCLRR_HCSSRSTF		BIT(3)
+#define RCC_C1BOOTRSTSCLRR_VCORERSTF		BIT(4)
+#define RCC_C1BOOTRSTSCLRR_VCPURSTF		BIT(5)
+#define RCC_C1BOOTRSTSCLRR_SYSC1RSTF		BIT(6)
+#define RCC_C1BOOTRSTSCLRR_SYSC2RSTF		BIT(7)
+#define RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF		BIT(8)
+#define RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF		BIT(9)
+#define RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF		BIT(10)
+#define RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF		BIT(11)
+#define RCC_C1BOOTRSTSCLRR_C1RSTF		BIT(13)
+#define RCC_C1BOOTRSTSCLRR_RETCRCERRRSTF	BIT(17)
+#define RCC_C1BOOTRSTSCLRR_RETECCFAILCRCRSTF	BIT(18)
+#define RCC_C1BOOTRSTSCLRR_RETECCFAILRESTRSTF	BIT(19)
+#define RCC_C1BOOTRSTSCLRR_STBYC1RSTF		BIT(20)
+#define RCC_C1BOOTRSTSCLRR_D1STBYRSTF		BIT(22)
+#define RCC_C1BOOTRSTSCLRR_D2STBYRSTF		BIT(23)
+
+#define RCC_C1BOOTRSTSCLRR_IWDGXSYSRSTF (RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF | \
+					 RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF | \
+					 RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF | \
+					 RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF)
+
+/* RCC_C2BOOTRSTSSETR register fields */
+#define RCC_C2BOOTRSTSSETR_PORRSTF		BIT(0)
+#define RCC_C2BOOTRSTSSETR_BORRSTF		BIT(1)
+#define RCC_C2BOOTRSTSSETR_PADRSTF		BIT(2)
+#define RCC_C2BOOTRSTSSETR_HCSSRSTF		BIT(3)
+#define RCC_C2BOOTRSTSSETR_VCORERSTF		BIT(4)
+#define RCC_C2BOOTRSTSSETR_SYSC1RSTF		BIT(6)
+#define RCC_C2BOOTRSTSSETR_SYSC2RSTF		BIT(7)
+#define RCC_C2BOOTRSTSSETR_IWDG1SYSRSTF		BIT(8)
+#define RCC_C2BOOTRSTSSETR_IWDG2SYSRSTF		BIT(9)
+#define RCC_C2BOOTRSTSSETR_IWDG3SYSRSTF		BIT(10)
+#define RCC_C2BOOTRSTSSETR_IWDG4SYSRSTF		BIT(11)
+#define RCC_C2BOOTRSTSSETR_C2RSTF		BIT(14)
+#define RCC_C2BOOTRSTSSETR_RETCRCERRRSTF	BIT(17)
+#define RCC_C2BOOTRSTSSETR_RETECCFAILCRCRSTF	BIT(18)
+#define RCC_C2BOOTRSTSSETR_RETECCFAILRESTRSTF	BIT(19)
+#define RCC_C2BOOTRSTSSETR_STBYC2RSTF		BIT(21)
+#define RCC_C2BOOTRSTSSETR_D2STBYRSTF		BIT(23)
+
+/* RCC_C2BOOTRSTSCLRR register fields */
+#define RCC_C2BOOTRSTSCLRR_PORRSTF		BIT(0)
+#define RCC_C2BOOTRSTSCLRR_BORRSTF		BIT(1)
+#define RCC_C2BOOTRSTSCLRR_PADRSTF		BIT(2)
+#define RCC_C2BOOTRSTSCLRR_HCSSRSTF		BIT(3)
+#define RCC_C2BOOTRSTSCLRR_VCORERSTF		BIT(4)
+#define RCC_C2BOOTRSTSCLRR_SYSC1RSTF		BIT(6)
+#define RCC_C2BOOTRSTSCLRR_SYSC2RSTF		BIT(7)
+#define RCC_C2BOOTRSTSCLRR_IWDG1SYSRSTF		BIT(8)
+#define RCC_C2BOOTRSTSCLRR_IWDG2SYSRSTF		BIT(9)
+#define RCC_C2BOOTRSTSCLRR_IWDG3SYSRSTF		BIT(10)
+#define RCC_C2BOOTRSTSCLRR_IWDG4SYSRSTF		BIT(11)
+#define RCC_C2BOOTRSTSCLRR_C2RSTF		BIT(14)
+#define RCC_C2BOOTRSTSCLRR_RETCRCERRRSTF	BIT(17)
+#define RCC_C2BOOTRSTSCLRR_RETECCFAILCRCRSTF	BIT(18)
+#define RCC_C2BOOTRSTSCLRR_RETECCFAILRESTRSTF	BIT(19)
+#define RCC_C2BOOTRSTSCLRR_STBYC2RSTF		BIT(21)
+#define RCC_C2BOOTRSTSCLRR_D2STBYRSTF		BIT(23)
+
+/* RCC_C1SREQSETR register fields */
+#define RCC_C1SREQSETR_STPREQ_P0		BIT(0)
+#define RCC_C1SREQSETR_STPREQ_P1		BIT(1)
+#define RCC_C1SREQSETR_STPREQ_MASK		GENMASK_32(1, 0)
+#define RCC_C1SREQSETR_ESLPREQ			BIT(16)
+
+/* RCC_C1SREQCLRR register fields */
+#define RCC_C1SREQCLRR_STPREQ_P0		BIT(0)
+#define RCC_C1SREQCLRR_STPREQ_P1		BIT(1)
+#define RCC_C1SREQCLRR_STPREQ_MASK		GENMASK_32(1, 0)
+#define RCC_C1SREQCLRR_ESLPREQ			BIT(16)
+
+/* RCC_CPUBOOTCR register fields */
+#define RCC_CPUBOOTCR_BOOT_CPU2			BIT(0)
+#define RCC_CPUBOOTCR_BOOT_CPU1			BIT(1)
+
+/* RCC_STBYBOOTCR register fields */
+#define RCC_STBYBOOTCR_CPU_BEN_SEL		BIT(1)
+#define RCC_STBYBOOTCR_COLD_CPU2		BIT(2)
+#define RCC_STBYBOOTCR_CPU2_HW_BEN		BIT(4)
+#define RCC_STBYBOOTCR_CPU1_HW_BEN		BIT(5)
+#define RCC_STBYBOOTCR_RET_CRCERR_RSTEN		BIT(8)
+
+/* RCC_LEGBOOTCR register fields */
+#define RCC_LEGBOOTCR_LEGACY_BEN		BIT(0)
+
+/* RCC_BDCR register fields */
+#define RCC_BDCR_LSEON				BIT(0)
+#define RCC_BDCR_LSEBYP				BIT(1)
+#define RCC_BDCR_LSERDY				BIT(2)
+#define RCC_BDCR_LSEDIGBYP			BIT(3)
+#define RCC_BDCR_LSEDRV_MASK			GENMASK_32(5, 4)
+#define RCC_BDCR_LSEDRV_SHIFT			4
+#define RCC_BDCR_LSECSSON			BIT(6)
+#define RCC_BDCR_LSEGFON			BIT(7)
+#define RCC_BDCR_LSECSSD			BIT(8)
+#define RCC_BDCR_RTCSRC_MASK			GENMASK_32(17, 16)
+#define RCC_BDCR_RTCSRC_SHIFT			16
+#define RCC_BDCR_RTCCKEN			BIT(20)
+#define RCC_BDCR_VSWRST				BIT(31)
+
+/* RCC_RDCR register fields */
+#define RCC_RDCR_MRD_MASK			GENMASK_32(20, 16)
+#define RCC_RDCR_MRD_SHIFT			16
+#define RCC_RDCR_EADLY_MASK			GENMASK_32(27, 24)
+#define RCC_RDCR_EADLY_SHIFT			24
+
+/* RCC_C1MSRDCR register fields */
+#define RCC_C1MSRDCR_C1MSRD_MASK		GENMASK_32(4, 0)
+#define RCC_C1MSRDCR_C1MSRD_SHIFT		0
+#define RCC_C1MSRDCR_C1MSRST			BIT(8)
+
+/* RCC_PWRLPDLYCR register fields */
+#define RCC_PWRLPDLYCR_PWRLP_DLY_MASK		GENMASK_32(21, 0)
+#define RCC_PWRLPDLYCR_PWRLP_DLY_SHIFT		0
+#define RCC_PWRLPDLYCR_CPU2TMPSKP		BIT(24)
+
+/* RCC_C1CIESETR register fields */
+#define RCC_C1CIESETR_LSIRDYIE			BIT(0)
+#define RCC_C1CIESETR_LSERDYIE			BIT(1)
+#define RCC_C1CIESETR_HSIRDYIE			BIT(2)
+#define RCC_C1CIESETR_HSERDYIE			BIT(3)
+#define RCC_C1CIESETR_MSIRDYIE			BIT(4)
+#define RCC_C1CIESETR_PLL1RDYIE			BIT(5)
+#define RCC_C1CIESETR_PLL2RDYIE			BIT(6)
+#define RCC_C1CIESETR_PLL3RDYIE			BIT(7)
+#define RCC_C1CIESETR_PLL4RDYIE			BIT(8)
+#define RCC_C1CIESETR_PLL5RDYIE			BIT(9)
+#define RCC_C1CIESETR_PLL6RDYIE			BIT(10)
+#define RCC_C1CIESETR_PLL7RDYIE			BIT(11)
+#define RCC_C1CIESETR_PLL8RDYIE			BIT(12)
+#define RCC_C1CIESETR_LSECSSIE			BIT(16)
+#define RCC_C1CIESETR_WKUPIE			BIT(20)
+
+/* RCC_C1CIFCLRR register fields */
+#define RCC_C1CIFCLRR_LSIRDYF			BIT(0)
+#define RCC_C1CIFCLRR_LSERDYF			BIT(1)
+#define RCC_C1CIFCLRR_HSIRDYF			BIT(2)
+#define RCC_C1CIFCLRR_HSERDYF			BIT(3)
+#define RCC_C1CIFCLRR_MSIRDYF			BIT(4)
+#define RCC_C1CIFCLRR_PLL1RDYF			BIT(5)
+#define RCC_C1CIFCLRR_PLL2RDYF			BIT(6)
+#define RCC_C1CIFCLRR_PLL3RDYF			BIT(7)
+#define RCC_C1CIFCLRR_PLL4RDYF			BIT(8)
+#define RCC_C1CIFCLRR_PLL5RDYF			BIT(9)
+#define RCC_C1CIFCLRR_PLL6RDYF			BIT(10)
+#define RCC_C1CIFCLRR_PLL7RDYF			BIT(11)
+#define RCC_C1CIFCLRR_PLL8RDYF			BIT(12)
+#define RCC_C1CIFCLRR_LSECSSF			BIT(16)
+#define RCC_C1CIFCLRR_WKUPF			BIT(20)
+
+/* RCC_C2CIESETR register fields */
+#define RCC_C2CIESETR_LSIRDYIE			BIT(0)
+#define RCC_C2CIESETR_LSERDYIE			BIT(1)
+#define RCC_C2CIESETR_HSIRDYIE			BIT(2)
+#define RCC_C2CIESETR_HSERDYIE			BIT(3)
+#define RCC_C2CIESETR_MSIRDYIE			BIT(4)
+#define RCC_C2CIESETR_PLL1RDYIE			BIT(5)
+#define RCC_C2CIESETR_PLL2RDYIE			BIT(6)
+#define RCC_C2CIESETR_PLL3RDYIE			BIT(7)
+#define RCC_C2CIESETR_PLL4RDYIE			BIT(8)
+#define RCC_C2CIESETR_PLL5RDYIE			BIT(9)
+#define RCC_C2CIESETR_PLL6RDYIE			BIT(10)
+#define RCC_C2CIESETR_PLL7RDYIE			BIT(11)
+#define RCC_C2CIESETR_PLL8RDYIE			BIT(12)
+#define RCC_C2CIESETR_LSECSSIE			BIT(16)
+#define RCC_C2CIESETR_WKUPIE			BIT(20)
+
+/* RCC_C2CIFCLRR register fields */
+#define RCC_C2CIFCLRR_LSIRDYF			BIT(0)
+#define RCC_C2CIFCLRR_LSERDYF			BIT(1)
+#define RCC_C2CIFCLRR_HSIRDYF			BIT(2)
+#define RCC_C2CIFCLRR_HSERDYF			BIT(3)
+#define RCC_C2CIFCLRR_MSIRDYF			BIT(4)
+#define RCC_C2CIFCLRR_PLL1RDYF			BIT(5)
+#define RCC_C2CIFCLRR_PLL2RDYF			BIT(6)
+#define RCC_C2CIFCLRR_PLL3RDYF			BIT(7)
+#define RCC_C2CIFCLRR_PLL4RDYF			BIT(8)
+#define RCC_C2CIFCLRR_PLL5RDYF			BIT(9)
+#define RCC_C2CIFCLRR_PLL6RDYF			BIT(10)
+#define RCC_C2CIFCLRR_PLL7RDYF			BIT(11)
+#define RCC_C2CIFCLRR_PLL8RDYF			BIT(12)
+#define RCC_C2CIFCLRR_LSECSSF			BIT(16)
+#define RCC_C2CIFCLRR_WKUPF			BIT(20)
+
+/* RCC_CxCIESETR register fields */
+#define RCC_CxCIESETR_LSIRDYIE			BIT(0)
+#define RCC_CxCIESETR_LSERDYIE			BIT(1)
+#define RCC_CxCIESETR_HSIRDYIE			BIT(2)
+#define RCC_CxCIESETR_HSERDYIE			BIT(3)
+#define RCC_CxCIESETR_CSIRDYIE			BIT(4)
+#define RCC_CxCIESETR_SHSIRDYIE			BIT(5)
+#define RCC_CxCIESETR_PLL1RDYIE			BIT(6)
+#define RCC_CxCIESETR_PLL2RDYIE			BIT(7)
+#define RCC_CxCIESETR_PLL3RDYIE			BIT(8)
+#define RCC_CxCIESETR_PLL4RDYIE			BIT(9)
+#define RCC_CxCIESETR_PLL5RDYIE			BIT(10)
+#define RCC_CxCIESETR_PLL6RDYIE			BIT(11)
+#define RCC_CxCIESETR_PLL7RDYIE			BIT(12)
+#define RCC_CxCIESETR_PLL8RDYIE			BIT(13)
+#define RCC_CxCIESETR_LSECSSIE			BIT(16)
+#define RCC_CxCIESETR_WKUPIE			BIT(20)
+
+/* RCC_CxCIFCLRR register fields */
+#define RCC_CxCIFCLRR_LSIRDYF			BIT(0)
+#define RCC_CxCIFCLRR_LSERDYF			BIT(1)
+#define RCC_CxCIFCLRR_HSIRDYF			BIT(2)
+#define RCC_CxCIFCLRR_HSERDYF			BIT(3)
+#define RCC_CxCIFCLRR_CSIRDYF			BIT(4)
+#define RCC_CxCIFCLRR_SHSIRDYF			BIT(5)
+#define RCC_CxCIFCLRR_PLL1RDYF			BIT(6)
+#define RCC_CxCIFCLRR_PLL2RDYF			BIT(7)
+#define RCC_CxCIFCLRR_PLL3RDYF			BIT(8)
+#define RCC_CxCIFCLRR_PLL4RDYF			BIT(9)
+#define RCC_CxCIFCLRR_PLL5RDYF			BIT(10)
+#define RCC_CxCIFCLRR_PLL6RDYF			BIT(11)
+#define RCC_CxCIFCLRR_PLL7RDYF			BIT(12)
+#define RCC_CxCIFCLRR_PLL8RDYF			BIT(13)
+#define RCC_CxCIFCLRR_LSECSSF			BIT(16)
+#define RCC_CxCIFCLRR_WKUPF			BIT(20)
+
+/* RCC_IWDGC1FZSETR register fields */
+#define RCC_IWDGC1FZSETR_FZ_IWDG1		BIT(0)
+#define RCC_IWDGC1FZSETR_FZ_IWDG2		BIT(1)
+
+/* RCC_IWDGC1FZCLRR register fields */
+#define RCC_IWDGC1FZCLRR_FZ_IWDG1		BIT(0)
+#define RCC_IWDGC1FZCLRR_FZ_IWDG2		BIT(1)
+
+/* RCC_IWDGC1CFGSETR register fields */
+#define RCC_IWDGC1CFGSETR_IWDG1_SYSRSTEN	BIT(0)
+#define RCC_IWDGC1CFGSETR_IWDG2_SYSRSTEN	BIT(2)
+#define RCC_IWDGC1CFGSETR_IWDG2_KERRST		BIT(18)
+
+/* RCC_IWDGC1CFGCLRR register fields */
+#define RCC_IWDGC1CFGCLRR_IWDG1_SYSRSTEN	BIT(0)
+#define RCC_IWDGC1CFGCLRR_IWDG2_SYSRSTEN	BIT(2)
+#define RCC_IWDGC1CFGCLRR_IWDG2_KERRST		BIT(18)
+
+/* RCC_IWDGC2FZSETR register fields */
+#define RCC_IWDGC2FZSETR_FZ_IWDG3		BIT(0)
+#define RCC_IWDGC2FZSETR_FZ_IWDG4		BIT(1)
+
+/* RCC_IWDGC2FZCLRR register fields */
+#define RCC_IWDGC2FZCLRR_FZ_IWDG3		BIT(0)
+#define RCC_IWDGC2FZCLRR_FZ_IWDG4		BIT(1)
+
+/* RCC_IWDGC2CFGSETR register fields */
+#define RCC_IWDGC2CFGSETR_IWDG3_SYSRSTEN	BIT(0)
+#define RCC_IWDGC2CFGSETR_IWDG4_SYSRSTEN	BIT(2)
+#define RCC_IWDGC2CFGSETR_IWDG4_KERRST		BIT(18)
+
+/* RCC_IWDGC2CFGCLRR register fields */
+#define RCC_IWDGC2CFGCLRR_IWDG3_SYSRSTEN	BIT(0)
+#define RCC_IWDGC2CFGCLRR_IWDG4_SYSRSTEN	BIT(2)
+#define RCC_IWDGC2CFGCLRR_IWDG4_KERRST		BIT(18)
+
+/* RCC_MCO1CFGR register fields */
+#define RCC_MCO1CFGR_MCO1SEL			BIT(0)
+#define RCC_MCO1CFGR_MCO1ON			BIT(8)
+
+/* RCC_MCO2CFGR register fields */
+#define RCC_MCO2CFGR_MCO2SEL			BIT(0)
+#define RCC_MCO2CFGR_MCO2ON			BIT(8)
+
+/* RCC_MCOxCFGR register fields */
+#define RCC_MCOxCFGR_MCOxSEL			BIT(0)
+#define RCC_MCOxCFGR_MCOxON			BIT(8)
+
+/* RCC_OCENSETR register fields */
+#define RCC_OCENSETR_HSION			BIT(0)
+#define RCC_OCENSETR_HSIKERON			BIT(1)
+#define RCC_OCENSETR_MSION			BIT(2)
+#define RCC_OCENSETR_MSIKERON			BIT(3)
+#define RCC_OCENSETR_HSEDIV2ON			BIT(5)
+#define RCC_OCENSETR_HSEDIV2BYP			BIT(6)
+#define RCC_OCENSETR_HSEDIGBYP			BIT(7)
+#define RCC_OCENSETR_HSEON			BIT(8)
+#define RCC_OCENSETR_HSEKERON			BIT(9)
+#define RCC_OCENSETR_HSEBYP			BIT(10)
+#define RCC_OCENSETR_HSECSSON			BIT(11)
+
+/* RCC_OCENCLRR register fields */
+#define RCC_OCENCLRR_HSION			BIT(0)
+#define RCC_OCENCLRR_HSIKERON			BIT(1)
+#define RCC_OCENCLRR_MSION			BIT(2)
+#define RCC_OCENCLRR_MSIKERON			BIT(3)
+#define RCC_OCENCLRR_HSEDIV2ON			BIT(5)
+#define RCC_OCENCLRR_HSEDIV2BYP			BIT(6)
+#define RCC_OCENCLRR_HSEDIGBYP			BIT(7)
+#define RCC_OCENCLRR_HSEON			BIT(8)
+#define RCC_OCENCLRR_HSEKERON			BIT(9)
+#define RCC_OCENCLRR_HSEBYP			BIT(10)
+
+/* RCC_OCRDYR register fields */
+#define RCC_OCRDYR_HSIRDY			BIT(0)
+#define RCC_OCRDYR_MSIRDY			BIT(2)
+#define RCC_OCRDYR_HSERDY			BIT(8)
+#define RCC_OCRDYR_CKREST			BIT(25)
+
+/* RCC_HSICFGR register fields */
+#define RCC_HSICFGR_HSITRIM_MASK		GENMASK_32(14, 8)
+#define RCC_HSICFGR_HSITRIM_SHIFT		8
+#define RCC_HSICFGR_HSICAL_MASK			GENMASK_32(24, 16)
+#define RCC_HSICFGR_HSICAL_SHIFT		16
+
+/* RCC_MSICFGR register fields */
+#define RCC_MSICFGR_MSITRIM_MASK		GENMASK_32(12, 8)
+#define RCC_MSICFGR_MSITRIM_SHIFT		8
+#define RCC_MSICFGR_MSICAL_MASK			GENMASK_32(23, 16)
+#define RCC_MSICFGR_MSICAL_SHIFT		16
+
+/* RCC_LSICR register fields */
+#define RCC_LSICR_LSION				BIT(0)
+#define RCC_LSICR_LSIRDY			BIT(1)
+
+/* RCC_RTCDIVR register fields */
+#define RCC_RTCDIVR_RTCDIV_MASK			GENMASK_32(5, 0)
+#define RCC_RTCDIVR_RTCDIV_SHIFT		0
+
+/* RCC_APB1DIVR register fields */
+#define RCC_APB1DIVR_APB1DIV_MASK		GENMASK_32(2, 0)
+#define RCC_APB1DIVR_APB1DIV_SHIFT		0
+#define RCC_APB1DIVR_APB1DIVRDY			BIT(31)
+
+/* RCC_APB2DIVR register fields */
+#define RCC_APB2DIVR_APB2DIV_MASK		GENMASK_32(2, 0)
+#define RCC_APB2DIVR_APB2DIV_SHIFT		0
+#define RCC_APB2DIVR_APB2DIVRDY			BIT(31)
+
+/* RCC_APB3DIVR register fields */
+#define RCC_APB3DIVR_APB3DIV_MASK		GENMASK_32(2, 0)
+#define RCC_APB3DIVR_APB3DIV_SHIFT		0
+#define RCC_APB3DIVR_APB3DIVRDY			BIT(31)
+
+/* RCC_APB4DIVR register fields */
+#define RCC_APB4DIVR_APB4DIV_MASK		GENMASK_32(2, 0)
+#define RCC_APB4DIVR_APB4DIV_SHIFT		0
+#define RCC_APB4DIVR_APB4DIVRDY			BIT(31)
+
+/* RCC_APB5DIVR register fields */
+#define RCC_APB5DIVR_APB5DIV_MASK		GENMASK_32(2, 0)
+#define RCC_APB5DIVR_APB5DIV_SHIFT		0
+#define RCC_APB5DIVR_APB5DIVRDY			BIT(31)
+
+/* RCC_APBDBGDIVR register fields */
+#define RCC_APBDBGDIVR_APBDBGDIV_MASK		GENMASK_32(2, 0)
+#define RCC_APBDBGDIVR_APBDBGDIV_SHIFT		0
+#define RCC_APBDBGDIVR_APBDBGDIVRDY		BIT(31)
+
+/* RCC_APBxDIVR register fields */
+#define RCC_APBxDIVR_APBxDIV_MASK		GENMASK_32(2, 0)
+#define RCC_APBxDIVR_APBxDIV_SHIFT		0
+#define RCC_APBxDIVR_APBxDIVRDY			BIT(31)
+
+/* RCC_TIMG1PRER register fields */
+#define RCC_TIMG1PRER_TIMG1PRE			BIT(0)
+#define RCC_TIMG1PRER_TIMG1PRERDY		BIT(31)
+
+/* RCC_TIMG2PRER register fields */
+#define RCC_TIMG2PRER_TIMG2PRE			BIT(0)
+#define RCC_TIMG2PRER_TIMG2PRERDY		BIT(31)
+
+/* RCC_TIMGxPRER register fields */
+#define RCC_TIMGxPRER_TIMGxPRE			BIT(0)
+#define RCC_TIMGxPRER_TIMGxPRERDY		BIT(31)
+
+/* RCC_LSMCUDIVR register fields */
+#define RCC_LSMCUDIVR_LSMCUDIV			BIT(0)
+#define RCC_LSMCUDIVR_LSMCUDIVRDY		BIT(31)
+
+/* RCC_DDRCPCFGR register fields */
+#define RCC_DDRCPCFGR_DDRCPRST			BIT(0)
+#define RCC_DDRCPCFGR_DDRCPEN			BIT(1)
+#define RCC_DDRCPCFGR_DDRCPLPEN			BIT(2)
+
+/* RCC_DDRCAPBCFGR register fields */
+#define RCC_DDRCAPBCFGR_DDRCAPBRST		BIT(0)
+#define RCC_DDRCAPBCFGR_DDRCAPBEN		BIT(1)
+#define RCC_DDRCAPBCFGR_DDRCAPBLPEN		BIT(2)
+
+/* RCC_DDRPHYCAPBCFGR register fields */
+#define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBRST	BIT(0)
+#define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBEN		BIT(1)
+#define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBLPEN	BIT(2)
+
+/* RCC_DDRPHYCCFGR register fields */
+#define RCC_DDRPHYCCFGR_DDRPHYCEN		BIT(1)
+
+/* RCC_DDRCFGR register fields */
+#define RCC_DDRCFGR_DDRCFGRST			BIT(0)
+#define RCC_DDRCFGR_DDRCFGEN			BIT(1)
+#define RCC_DDRCFGR_DDRCFGLPEN			BIT(2)
+
+/* RCC_DDRITFCFGR register fields */
+#define RCC_DDRITFCFGR_DDRRST			BIT(0)
+#define RCC_DDRITFCFGR_DDRCKMOD_MASK		GENMASK_32(5, 4)
+#define RCC_DDRITFCFGR_DDRCKMOD_SHIFT		4
+#define RCC_DDRITFCFGR_DDRCKMOD_HSR		BIT(5)
+#define RCC_DDRITFCFGR_DDRSHR			BIT(8)
+#define RCC_DDRITFCFGR_DDRPHYDLP		BIT(16)
+
+/* RCC_SYSRAMCFGR register fields */
+#define RCC_SYSRAMCFGR_SYSRAMEN			BIT(1)
+#define RCC_SYSRAMCFGR_SYSRAMLPEN		BIT(2)
+
+/* RCC_SRAM1CFGR register fields */
+#define RCC_SRAM1CFGR_SRAM1EN			BIT(1)
+#define RCC_SRAM1CFGR_SRAM1LPEN			BIT(2)
+
+/* RCC_RETRAMCFGR register fields */
+#define RCC_RETRAMCFGR_RETRAMEN			BIT(1)
+#define RCC_RETRAMCFGR_RETRAMLPEN		BIT(2)
+
+/* RCC_BKPSRAMCFGR register fields */
+#define RCC_BKPSRAMCFGR_BKPSRAMEN		BIT(1)
+#define RCC_BKPSRAMCFGR_BKPSRAMLPEN		BIT(2)
+
+/* RCC_OSPI1CFGR register fields */
+#define RCC_OSPI1CFGR_OSPI1RST			BIT(0)
+#define RCC_OSPI1CFGR_OSPI1EN			BIT(1)
+#define RCC_OSPI1CFGR_OSPI1LPEN			BIT(2)
+#define RCC_OSPI1CFGR_OTFDEC1RST		BIT(8)
+#define RCC_OSPI1CFGR_OSPI1DLLRST		BIT(16)
+
+/* RCC_OSPIxCFGR register fields */
+#define RCC_OSPIxCFGR_OSPIxRST			BIT(0)
+#define RCC_OSPIxCFGR_OSPIxEN			BIT(1)
+#define RCC_OSPIxCFGR_OSPIxLPEN			BIT(2)
+#define RCC_OSPIxCFGR_OTFDECxRST		BIT(8)
+#define RCC_OSPIxCFGR_OSPIxDLLRST		BIT(16)
+
+/* RCC_FMCCFGR register fields */
+#define RCC_FMCCFGR_FMCRST			BIT(0)
+#define RCC_FMCCFGR_FMCEN			BIT(1)
+#define RCC_FMCCFGR_FMCLPEN			BIT(2)
+
+/* RCC_DBGCFGR register fields */
+#define RCC_DBGCFGR_DBGEN			BIT(8)
+#define RCC_DBGCFGR_TRACEEN			BIT(9)
+#define RCC_DBGCFGR_DBGMCUEN			BIT(10)
+#define RCC_DBGCFGR_DBGRST			BIT(12)
+
+/* RCC_STMCFGR register fields */
+#define RCC_STMCFGR_STMEN			BIT(1)
+#define RCC_STMCFGR_STMLPEN			BIT(2)
+
+/* RCC_ETRCFGR register fields */
+#define RCC_ETRCFGR_ETREN			BIT(1)
+#define RCC_ETRCFGR_ETRLPEN			BIT(2)
+
+/* RCC_GPIOACFGR register fields */
+#define RCC_GPIOACFGR_GPIOARST			BIT(0)
+#define RCC_GPIOACFGR_GPIOAEN			BIT(1)
+#define RCC_GPIOACFGR_GPIOALPEN			BIT(2)
+
+/* RCC_GPIOBCFGR register fields */
+#define RCC_GPIOBCFGR_GPIOBRST			BIT(0)
+#define RCC_GPIOBCFGR_GPIOBEN			BIT(1)
+#define RCC_GPIOBCFGR_GPIOBLPEN			BIT(2)
+
+/* RCC_GPIOCCFGR register fields */
+#define RCC_GPIOCCFGR_GPIOCRST			BIT(0)
+#define RCC_GPIOCCFGR_GPIOCEN			BIT(1)
+#define RCC_GPIOCCFGR_GPIOCLPEN			BIT(2)
+
+/* RCC_GPIODCFGR register fields */
+#define RCC_GPIODCFGR_GPIODRST			BIT(0)
+#define RCC_GPIODCFGR_GPIODEN			BIT(1)
+#define RCC_GPIODCFGR_GPIODLPEN			BIT(2)
+
+/* RCC_GPIOECFGR register fields */
+#define RCC_GPIOECFGR_GPIOERST			BIT(0)
+#define RCC_GPIOECFGR_GPIOEEN			BIT(1)
+#define RCC_GPIOECFGR_GPIOELPEN			BIT(2)
+
+/* RCC_GPIOFCFGR register fields */
+#define RCC_GPIOFCFGR_GPIOFRST			BIT(0)
+#define RCC_GPIOFCFGR_GPIOFEN			BIT(1)
+#define RCC_GPIOFCFGR_GPIOFLPEN			BIT(2)
+
+/* RCC_GPIOGCFGR register fields */
+#define RCC_GPIOGCFGR_GPIOGRST			BIT(0)
+#define RCC_GPIOGCFGR_GPIOGEN			BIT(1)
+#define RCC_GPIOGCFGR_GPIOGLPEN			BIT(2)
+
+/* RCC_GPIOHCFGR register fields */
+#define RCC_GPIOHCFGR_GPIOHRST			BIT(0)
+#define RCC_GPIOHCFGR_GPIOHEN			BIT(1)
+#define RCC_GPIOHCFGR_GPIOHLPEN			BIT(2)
+
+/* RCC_GPIOICFGR register fields */
+#define RCC_GPIOICFGR_GPIOIRST			BIT(0)
+#define RCC_GPIOICFGR_GPIOIEN			BIT(1)
+#define RCC_GPIOICFGR_GPIOILPEN			BIT(2)
+
+/* RCC_GPIOZCFGR register fields */
+#define RCC_GPIOZCFGR_GPIOZRST			BIT(0)
+#define RCC_GPIOZCFGR_GPIOZEN			BIT(1)
+#define RCC_GPIOZCFGR_GPIOZLPEN			BIT(2)
+
+/* RCC_GPIOxCFGR register fields */
+#define RCC_GPIOxCFGR_GPIOxRST			BIT(0)
+#define RCC_GPIOxCFGR_GPIOxEN			BIT(1)
+#define RCC_GPIOxCFGR_GPIOxLPEN			BIT(2)
+#define RCC_GPIOxCFGR_GPIOxAMEN			BIT(3)
+
+/* RCC_HPDMA1CFGR register fields */
+#define RCC_HPDMA1CFGR_HPDMA1RST		BIT(0)
+#define RCC_HPDMA1CFGR_HPDMA1EN			BIT(1)
+#define RCC_HPDMA1CFGR_HPDMA1LPEN		BIT(2)
+
+/* RCC_HPDMA2CFGR register fields */
+#define RCC_HPDMA2CFGR_HPDMA2RST		BIT(0)
+#define RCC_HPDMA2CFGR_HPDMA2EN			BIT(1)
+#define RCC_HPDMA2CFGR_HPDMA2LPEN		BIT(2)
+
+/* RCC_HPDMA3CFGR register fields */
+#define RCC_HPDMA3CFGR_HPDMA3RST		BIT(0)
+#define RCC_HPDMA3CFGR_HPDMA3EN			BIT(1)
+#define RCC_HPDMA3CFGR_HPDMA3LPEN		BIT(2)
+
+/* RCC_HPDMAxCFGR register fields */
+#define RCC_HPDMAxCFGR_HPDMAxRST		BIT(0)
+#define RCC_HPDMAxCFGR_HPDMAxEN			BIT(1)
+#define RCC_HPDMAxCFGR_HPDMAxLPEN		BIT(2)
+
+/* RCC_IPCC1CFGR register fields */
+#define RCC_IPCC1CFGR_IPCC1RST			BIT(0)
+#define RCC_IPCC1CFGR_IPCC1EN			BIT(1)
+#define RCC_IPCC1CFGR_IPCC1LPEN			BIT(2)
+
+/* RCC_RTCCFGR register fields */
+#define RCC_RTCCFGR_RTCEN			BIT(1)
+#define RCC_RTCCFGR_RTCLPEN			BIT(2)
+
+/* RCC_SYSCPU1CFGR register fields */
+#define RCC_SYSCPU1CFGR_SYSCPU1EN		BIT(1)
+#define RCC_SYSCPU1CFGR_SYSCPU1LPEN		BIT(2)
+
+/* RCC_BSECCFGR register fields */
+#define RCC_BSECCFGR_BSECEN			BIT(1)
+#define RCC_BSECCFGR_BSECLPEN			BIT(2)
+
+/* RCC_PLL2CFGR1 register fields */
+#define RCC_PLL2CFGR1_SSMODRST			BIT(0)
+#define RCC_PLL2CFGR1_PLLEN			BIT(8)
+#define RCC_PLL2CFGR1_PLLRDY			BIT(24)
+#define RCC_PLL2CFGR1_CKREFST			BIT(28)
+
+/* RCC_PLL2CFGR2 register fields */
+#define RCC_PLL2CFGR2_FREFDIV_MASK		GENMASK_32(5, 0)
+#define RCC_PLL2CFGR2_FREFDIV_SHIFT		0
+#define RCC_PLL2CFGR2_FBDIV_MASK		GENMASK_32(27, 16)
+#define RCC_PLL2CFGR2_FBDIV_SHIFT		16
+
+/* RCC_PLL2CFGR3 register fields */
+#define RCC_PLL2CFGR3_FRACIN_MASK		GENMASK_32(23, 0)
+#define RCC_PLL2CFGR3_FRACIN_SHIFT		0
+#define RCC_PLL2CFGR3_DOWNSPREAD		BIT(24)
+#define RCC_PLL2CFGR3_DACEN			BIT(25)
+#define RCC_PLL2CFGR3_SSCGDIS			BIT(26)
+
+/* RCC_PLL2CFGR4 register fields */
+#define RCC_PLL2CFGR4_DSMEN			BIT(8)
+#define RCC_PLL2CFGR4_FOUTPOSTDIVEN		BIT(9)
+#define RCC_PLL2CFGR4_BYPASS			BIT(10)
+
+/* RCC_PLL2CFGR5 register fields */
+#define RCC_PLL2CFGR5_DIVVAL_MASK		GENMASK_32(3, 0)
+#define RCC_PLL2CFGR5_DIVVAL_SHIFT		0
+#define RCC_PLL2CFGR5_SPREAD_MASK		GENMASK_32(20, 16)
+#define RCC_PLL2CFGR5_SPREAD_SHIFT		16
+
+/* RCC_PLL2CFGR6 register fields */
+#define RCC_PLL2CFGR6_POSTDIV1_MASK		GENMASK_32(2, 0)
+#define RCC_PLL2CFGR6_POSTDIV1_SHIFT		0
+
+/* RCC_PLL2CFGR7 register fields */
+#define RCC_PLL2CFGR7_POSTDIV2_MASK		GENMASK_32(2, 0)
+#define RCC_PLL2CFGR7_POSTDIV2_SHIFT		0
+
+/* RCC_PLLxCFGR1 register fields */
+#define RCC_PLLxCFGR1_SSMODRST			BIT(0)
+#define RCC_PLLxCFGR1_PLLEN			BIT(8)
+#define RCC_PLLxCFGR1_PLLRDY			BIT(24)
+#define RCC_PLLxCFGR1_CKREFST			BIT(28)
+
+/* RCC_PLLxCFGR2 register fields */
+#define RCC_PLLxCFGR2_FREFDIV_MASK		GENMASK_32(5, 0)
+#define RCC_PLLxCFGR2_FREFDIV_SHIFT		0
+#define RCC_PLLxCFGR2_FBDIV_MASK		GENMASK_32(27, 16)
+#define RCC_PLLxCFGR2_FBDIV_SHIFT		16
+
+/* RCC_PLLxCFGR3 register fields */
+#define RCC_PLLxCFGR3_FRACIN_MASK		GENMASK_32(23, 0)
+#define RCC_PLLxCFGR3_FRACIN_SHIFT		0
+#define RCC_PLLxCFGR3_DOWNSPREAD		BIT(24)
+#define RCC_PLLxCFGR3_DACEN			BIT(25)
+#define RCC_PLLxCFGR3_SSCGDIS			BIT(26)
+
+/* RCC_PLLxCFGR4 register fields */
+#define RCC_PLLxCFGR4_DSMEN			BIT(8)
+#define RCC_PLLxCFGR4_FOUTPOSTDIVEN		BIT(9)
+#define RCC_PLLxCFGR4_BYPASS			BIT(10)
+
+/* RCC_PLLxCFGR5 register fields */
+#define RCC_PLLxCFGR5_DIVVAL_MASK		GENMASK_32(3, 0)
+#define RCC_PLLxCFGR5_DIVVAL_SHIFT		0
+#define RCC_PLLxCFGR5_SPREAD_MASK		GENMASK_32(20, 16)
+#define RCC_PLLxCFGR5_SPREAD_SHIFT		16
+
+/* RCC_PLLxCFGR6 register fields */
+#define RCC_PLLxCFGR6_POSTDIV1_MASK		GENMASK_32(2, 0)
+#define RCC_PLLxCFGR6_POSTDIV1_SHIFT		0
+
+/* RCC_PLLxCFGR7 register fields */
+#define RCC_PLLxCFGR7_POSTDIV2_MASK		GENMASK_32(2, 0)
+#define RCC_PLLxCFGR7_POSTDIV2_SHIFT		0
+
+/* RCC_HSIFMONCR register fields */
+#define RCC_HSIFMONCR_HSIREF_MASK		GENMASK_32(10, 0)
+#define RCC_HSIFMONCR_HSIREF_SHIFT		0
+#define RCC_HSIFMONCR_HSIMONEN			BIT(15)
+#define RCC_HSIFMONCR_HSIDEV_MASK		GENMASK_32(21, 16)
+#define RCC_HSIFMONCR_HSIDEV_SHIFT		16
+#define RCC_HSIFMONCR_HSIMONIE			BIT(30)
+#define RCC_HSIFMONCR_HSIMONF			BIT(31)
+
+/* RCC_HSIFVALR register fields */
+#define RCC_HSIFVALR_HSIVAL_MASK		GENMASK_32(10, 0)
+#define RCC_HSIFVALR_HSIVAL_SHIFT		0
+
+/* RCC_MSIFMONCR register fields */
+#define RCC_MSIFMONCR_MSIREF_MASK		GENMASK_32(8, 0)
+#define RCC_MSIFMONCR_MSIREF_SHIFT		0
+#define RCC_MSIFMONCR_MSIMONEN			BIT(15)
+#define RCC_MSIFMONCR_MSIDEV_MASK		GENMASK_32(20, 16)
+#define RCC_MSIFMONCR_MSIDEV_SHIFT		16
+#define RCC_MSIFMONCR_MSIMONIE			BIT(30)
+#define RCC_MSIFMONCR_MSIMONF			BIT(31)
+
+/* RCC_MSIFVALR register fields */
+#define RCC_MSIFVALR_MSIVAL_MASK		GENMASK_32(8, 0)
+#define RCC_MSIFVALR_MSIVAL_SHIFT		0
+
+/* RCC_TIM1CFGR register fields */
+#define RCC_TIM1CFGR_TIM1RST			BIT(0)
+#define RCC_TIM1CFGR_TIM1EN			BIT(1)
+#define RCC_TIM1CFGR_TIM1LPEN			BIT(2)
+
+/* RCC_TIM2CFGR register fields */
+#define RCC_TIM2CFGR_TIM2RST			BIT(0)
+#define RCC_TIM2CFGR_TIM2EN			BIT(1)
+#define RCC_TIM2CFGR_TIM2LPEN			BIT(2)
+
+/* RCC_TIM3CFGR register fields */
+#define RCC_TIM3CFGR_TIM3RST			BIT(0)
+#define RCC_TIM3CFGR_TIM3EN			BIT(1)
+#define RCC_TIM3CFGR_TIM3LPEN			BIT(2)
+
+/* RCC_TIM4CFGR register fields */
+#define RCC_TIM4CFGR_TIM4RST			BIT(0)
+#define RCC_TIM4CFGR_TIM4EN			BIT(1)
+#define RCC_TIM4CFGR_TIM4LPEN			BIT(2)
+
+/* RCC_TIM5CFGR register fields */
+#define RCC_TIM5CFGR_TIM5RST			BIT(0)
+#define RCC_TIM5CFGR_TIM5EN			BIT(1)
+#define RCC_TIM5CFGR_TIM5LPEN			BIT(2)
+
+/* RCC_TIM6CFGR register fields */
+#define RCC_TIM6CFGR_TIM6RST			BIT(0)
+#define RCC_TIM6CFGR_TIM6EN			BIT(1)
+#define RCC_TIM6CFGR_TIM6LPEN			BIT(2)
+
+/* RCC_TIM7CFGR register fields */
+#define RCC_TIM7CFGR_TIM7RST			BIT(0)
+#define RCC_TIM7CFGR_TIM7EN			BIT(1)
+#define RCC_TIM7CFGR_TIM7LPEN			BIT(2)
+
+/* RCC_TIM8CFGR register fields */
+#define RCC_TIM8CFGR_TIM8RST			BIT(0)
+#define RCC_TIM8CFGR_TIM8EN			BIT(1)
+#define RCC_TIM8CFGR_TIM8LPEN			BIT(2)
+
+/* RCC_TIM10CFGR register fields */
+#define RCC_TIM10CFGR_TIM10RST			BIT(0)
+#define RCC_TIM10CFGR_TIM10EN			BIT(1)
+#define RCC_TIM10CFGR_TIM10LPEN			BIT(2)
+
+/* RCC_TIM11CFGR register fields */
+#define RCC_TIM11CFGR_TIM11RST			BIT(0)
+#define RCC_TIM11CFGR_TIM11EN			BIT(1)
+#define RCC_TIM11CFGR_TIM11LPEN			BIT(2)
+
+/* RCC_TIM12CFGR register fields */
+#define RCC_TIM12CFGR_TIM12RST			BIT(0)
+#define RCC_TIM12CFGR_TIM12EN			BIT(1)
+#define RCC_TIM12CFGR_TIM12LPEN			BIT(2)
+
+/* RCC_TIM13CFGR register fields */
+#define RCC_TIM13CFGR_TIM13RST			BIT(0)
+#define RCC_TIM13CFGR_TIM13EN			BIT(1)
+#define RCC_TIM13CFGR_TIM13LPEN			BIT(2)
+
+/* RCC_TIM14CFGR register fields */
+#define RCC_TIM14CFGR_TIM14RST			BIT(0)
+#define RCC_TIM14CFGR_TIM14EN			BIT(1)
+#define RCC_TIM14CFGR_TIM14LPEN			BIT(2)
+
+/* RCC_TIM15CFGR register fields */
+#define RCC_TIM15CFGR_TIM15RST			BIT(0)
+#define RCC_TIM15CFGR_TIM15EN			BIT(1)
+#define RCC_TIM15CFGR_TIM15LPEN			BIT(2)
+
+/* RCC_TIM16CFGR register fields */
+#define RCC_TIM16CFGR_TIM16RST			BIT(0)
+#define RCC_TIM16CFGR_TIM16EN			BIT(1)
+#define RCC_TIM16CFGR_TIM16LPEN			BIT(2)
+
+/* RCC_TIM17CFGR register fields */
+#define RCC_TIM17CFGR_TIM17RST			BIT(0)
+#define RCC_TIM17CFGR_TIM17EN			BIT(1)
+#define RCC_TIM17CFGR_TIM17LPEN			BIT(2)
+
+/* RCC_LPTIM1CFGR register fields */
+#define RCC_LPTIM1CFGR_LPTIM1RST		BIT(0)
+#define RCC_LPTIM1CFGR_LPTIM1EN			BIT(1)
+#define RCC_LPTIM1CFGR_LPTIM1LPEN		BIT(2)
+
+/* RCC_LPTIM2CFGR register fields */
+#define RCC_LPTIM2CFGR_LPTIM2RST		BIT(0)
+#define RCC_LPTIM2CFGR_LPTIM2EN			BIT(1)
+#define RCC_LPTIM2CFGR_LPTIM2LPEN		BIT(2)
+
+/* RCC_LPTIM3CFGR register fields */
+#define RCC_LPTIM3CFGR_LPTIM3RST		BIT(0)
+#define RCC_LPTIM3CFGR_LPTIM3EN			BIT(1)
+#define RCC_LPTIM3CFGR_LPTIM3LPEN		BIT(2)
+
+/* RCC_LPTIM4CFGR register fields */
+#define RCC_LPTIM4CFGR_LPTIM4RST		BIT(0)
+#define RCC_LPTIM4CFGR_LPTIM4EN			BIT(1)
+#define RCC_LPTIM4CFGR_LPTIM4LPEN		BIT(2)
+
+/* RCC_LPTIM5CFGR register fields */
+#define RCC_LPTIM5CFGR_LPTIM5RST		BIT(0)
+#define RCC_LPTIM5CFGR_LPTIM5EN			BIT(1)
+#define RCC_LPTIM5CFGR_LPTIM5LPEN		BIT(2)
+
+/* RCC_LPTIMxCFGR register fields */
+#define RCC_LPTIMxCFGR_LPTIMxRST		BIT(0)
+#define RCC_LPTIMxCFGR_LPTIMxEN			BIT(1)
+#define RCC_LPTIMxCFGR_LPTIMxLPEN		BIT(2)
+#define RCC_LPTIMxCFGR_LPTIMxAMEN		BIT(3)
+
+/* RCC_SPI1CFGR register fields */
+#define RCC_SPI1CFGR_SPI1RST			BIT(0)
+#define RCC_SPI1CFGR_SPI1EN			BIT(1)
+#define RCC_SPI1CFGR_SPI1LPEN			BIT(2)
+
+/* RCC_SPI2CFGR register fields */
+#define RCC_SPI2CFGR_SPI2RST			BIT(0)
+#define RCC_SPI2CFGR_SPI2EN			BIT(1)
+#define RCC_SPI2CFGR_SPI2LPEN			BIT(2)
+
+/* RCC_SPI3CFGR register fields */
+#define RCC_SPI3CFGR_SPI3RST			BIT(0)
+#define RCC_SPI3CFGR_SPI3EN			BIT(1)
+#define RCC_SPI3CFGR_SPI3LPEN			BIT(2)
+
+/* RCC_SPI4CFGR register fields */
+#define RCC_SPI4CFGR_SPI4RST			BIT(0)
+#define RCC_SPI4CFGR_SPI4EN			BIT(1)
+#define RCC_SPI4CFGR_SPI4LPEN			BIT(2)
+
+/* RCC_SPI5CFGR register fields */
+#define RCC_SPI5CFGR_SPI5RST			BIT(0)
+#define RCC_SPI5CFGR_SPI5EN			BIT(1)
+#define RCC_SPI5CFGR_SPI5LPEN			BIT(2)
+
+/* RCC_SPI6CFGR register fields */
+#define RCC_SPI6CFGR_SPI6RST			BIT(0)
+#define RCC_SPI6CFGR_SPI6EN			BIT(1)
+#define RCC_SPI6CFGR_SPI6LPEN			BIT(2)
+
+/* RCC_SPIxCFGR register fields */
+#define RCC_SPIxCFGR_SPIxRST			BIT(0)
+#define RCC_SPIxCFGR_SPIxEN			BIT(1)
+#define RCC_SPIxCFGR_SPIxLPEN			BIT(2)
+#define RCC_SPIxCFGR_SPIxAMEN			BIT(3)
+
+/* RCC_SPDIFRXCFGR register fields */
+#define RCC_SPDIFRXCFGR_SPDIFRXRST		BIT(0)
+#define RCC_SPDIFRXCFGR_SPDIFRXEN		BIT(1)
+#define RCC_SPDIFRXCFGR_SPDIFRXLPEN		BIT(2)
+
+/* RCC_USART1CFGR register fields */
+#define RCC_USART1CFGR_USART1RST		BIT(0)
+#define RCC_USART1CFGR_USART1EN			BIT(1)
+#define RCC_USART1CFGR_USART1LPEN		BIT(2)
+
+/* RCC_USART2CFGR register fields */
+#define RCC_USART2CFGR_USART2RST		BIT(0)
+#define RCC_USART2CFGR_USART2EN			BIT(1)
+#define RCC_USART2CFGR_USART2LPEN		BIT(2)
+
+/* RCC_USART3CFGR register fields */
+#define RCC_USART3CFGR_USART3RST		BIT(0)
+#define RCC_USART3CFGR_USART3EN			BIT(1)
+#define RCC_USART3CFGR_USART3LPEN		BIT(2)
+
+/* RCC_UART4CFGR register fields */
+#define RCC_UART4CFGR_UART4RST			BIT(0)
+#define RCC_UART4CFGR_UART4EN			BIT(1)
+#define RCC_UART4CFGR_UART4LPEN			BIT(2)
+
+/* RCC_UART5CFGR register fields */
+#define RCC_UART5CFGR_UART5RST			BIT(0)
+#define RCC_UART5CFGR_UART5EN			BIT(1)
+#define RCC_UART5CFGR_UART5LPEN			BIT(2)
+
+/* RCC_USART6CFGR register fields */
+#define RCC_USART6CFGR_USART6RST		BIT(0)
+#define RCC_USART6CFGR_USART6EN			BIT(1)
+#define RCC_USART6CFGR_USART6LPEN		BIT(2)
+
+/* RCC_UART7CFGR register fields */
+#define RCC_UART7CFGR_UART7RST			BIT(0)
+#define RCC_UART7CFGR_UART7EN			BIT(1)
+#define RCC_UART7CFGR_UART7LPEN			BIT(2)
+
+/* RCC_USARTxCFGR register fields */
+#define RCC_USARTxCFGR_USARTxRST		BIT(0)
+#define RCC_USARTxCFGR_USARTxEN			BIT(1)
+#define RCC_USARTxCFGR_USARTxLPEN		BIT(2)
+
+/* RCC_UARTxCFGR register fields */
+#define RCC_UARTxCFGR_UARTxRST			BIT(0)
+#define RCC_UARTxCFGR_UARTxEN			BIT(1)
+#define RCC_UARTxCFGR_UARTxLPEN			BIT(2)
+
+/* RCC_LPUART1CFGR register fields */
+#define RCC_LPUART1CFGR_LPUART1RST		BIT(0)
+#define RCC_LPUART1CFGR_LPUART1EN		BIT(1)
+#define RCC_LPUART1CFGR_LPUART1LPEN		BIT(2)
+
+/* RCC_I2C1CFGR register fields */
+#define RCC_I2C1CFGR_I2C1RST			BIT(0)
+#define RCC_I2C1CFGR_I2C1EN			BIT(1)
+#define RCC_I2C1CFGR_I2C1LPEN			BIT(2)
+
+/* RCC_I2C2CFGR register fields */
+#define RCC_I2C2CFGR_I2C2RST			BIT(0)
+#define RCC_I2C2CFGR_I2C2EN			BIT(1)
+#define RCC_I2C2CFGR_I2C2LPEN			BIT(2)
+
+/* RCC_I2C3CFGR register fields */
+#define RCC_I2C3CFGR_I2C3RST			BIT(0)
+#define RCC_I2C3CFGR_I2C3EN			BIT(1)
+#define RCC_I2C3CFGR_I2C3LPEN			BIT(2)
+
+/* RCC_I2CxCFGR register fields */
+#define RCC_I2CxCFGR_I2CxRST			BIT(0)
+#define RCC_I2CxCFGR_I2CxEN			BIT(1)
+#define RCC_I2CxCFGR_I2CxLPEN			BIT(2)
+#define RCC_I2CxCFGR_I2CxAMEN			BIT(3)
+
+/* RCC_SAI1CFGR register fields */
+#define RCC_SAI1CFGR_SAI1RST			BIT(0)
+#define RCC_SAI1CFGR_SAI1EN			BIT(1)
+#define RCC_SAI1CFGR_SAI1LPEN			BIT(2)
+
+/* RCC_SAI2CFGR register fields */
+#define RCC_SAI2CFGR_SAI2RST			BIT(0)
+#define RCC_SAI2CFGR_SAI2EN			BIT(1)
+#define RCC_SAI2CFGR_SAI2LPEN			BIT(2)
+
+/* RCC_SAI3CFGR register fields */
+#define RCC_SAI3CFGR_SAI3RST			BIT(0)
+#define RCC_SAI3CFGR_SAI3EN			BIT(1)
+#define RCC_SAI3CFGR_SAI3LPEN			BIT(2)
+
+/* RCC_SAI4CFGR register fields */
+#define RCC_SAI4CFGR_SAI4RST			BIT(0)
+#define RCC_SAI4CFGR_SAI4EN			BIT(1)
+#define RCC_SAI4CFGR_SAI4LPEN			BIT(2)
+
+/* RCC_SAIxCFGR register fields */
+#define RCC_SAIxCFGR_SAIxRST			BIT(0)
+#define RCC_SAIxCFGR_SAIxEN			BIT(1)
+#define RCC_SAIxCFGR_SAIxLPEN			BIT(2)
+
+/* RCC_MDF1CFGR register fields */
+#define RCC_MDF1CFGR_MDF1RST			BIT(0)
+#define RCC_MDF1CFGR_MDF1EN			BIT(1)
+#define RCC_MDF1CFGR_MDF1LPEN			BIT(2)
+
+/* RCC_FDCANCFGR register fields */
+#define RCC_FDCANCFGR_FDCANRST			BIT(0)
+#define RCC_FDCANCFGR_FDCANEN			BIT(1)
+#define RCC_FDCANCFGR_FDCANLPEN			BIT(2)
+
+/* RCC_HDPCFGR register fields */
+#define RCC_HDPCFGR_HDPRST			BIT(0)
+#define RCC_HDPCFGR_HDPEN			BIT(1)
+
+/* RCC_ADC1CFGR register fields */
+#define RCC_ADC1CFGR_ADC1RST			BIT(0)
+#define RCC_ADC1CFGR_ADC1EN			BIT(1)
+#define RCC_ADC1CFGR_ADC1LPEN			BIT(2)
+#define RCC_ADC1CFGR_ADC1KERSEL			BIT(12)
+
+/* RCC_ADC2CFGR register fields */
+#define RCC_ADC2CFGR_ADC2RST			BIT(0)
+#define RCC_ADC2CFGR_ADC2EN			BIT(1)
+#define RCC_ADC2CFGR_ADC2LPEN			BIT(2)
+#define RCC_ADC2CFGR_ADC2KERSEL_MASK		GENMASK_32(13, 12)
+#define RCC_ADC2CFGR_ADC2KERSEL_SHIFT		12
+
+/* RCC_ETH1CFGR register fields */
+#define RCC_ETH1CFGR_ETH1RST			BIT(0)
+#define RCC_ETH1CFGR_ETH1MACEN			BIT(1)
+#define RCC_ETH1CFGR_ETH1MACLPEN		BIT(2)
+#define RCC_ETH1CFGR_ETH1STPEN			BIT(4)
+#define RCC_ETH1CFGR_ETH1EN			BIT(5)
+#define RCC_ETH1CFGR_ETH1LPEN			BIT(6)
+#define RCC_ETH1CFGR_ETH1TXEN			BIT(8)
+#define RCC_ETH1CFGR_ETH1TXLPEN			BIT(9)
+#define RCC_ETH1CFGR_ETH1RXEN			BIT(10)
+#define RCC_ETH1CFGR_ETH1RXLPEN			BIT(11)
+
+/* RCC_ETH2CFGR register fields */
+#define RCC_ETH2CFGR_ETH2RST			BIT(0)
+#define RCC_ETH2CFGR_ETH2MACEN			BIT(1)
+#define RCC_ETH2CFGR_ETH2MACLPEN		BIT(2)
+#define RCC_ETH2CFGR_ETH2STPEN			BIT(4)
+#define RCC_ETH2CFGR_ETH2EN			BIT(5)
+#define RCC_ETH2CFGR_ETH2LPEN			BIT(6)
+#define RCC_ETH2CFGR_ETH2TXEN			BIT(8)
+#define RCC_ETH2CFGR_ETH2TXLPEN			BIT(9)
+#define RCC_ETH2CFGR_ETH2RXEN			BIT(10)
+#define RCC_ETH2CFGR_ETH2RXLPEN			BIT(11)
+
+/* RCC_ETHxCFGR register fields */
+#define RCC_ETHxCFGR_ETHxRST			BIT(0)
+#define RCC_ETHxCFGR_ETHxMACEN			BIT(1)
+#define RCC_ETHxCFGR_ETHxMACLPEN		BIT(2)
+#define RCC_ETHxCFGR_ETHxSTPEN			BIT(4)
+#define RCC_ETHxCFGR_ETHxEN			BIT(5)
+#define RCC_ETHxCFGR_ETHxLPEN			BIT(6)
+#define RCC_ETHxCFGR_ETHxTXEN			BIT(8)
+#define RCC_ETHxCFGR_ETHxTXLPEN			BIT(9)
+#define RCC_ETHxCFGR_ETHxRXEN			BIT(10)
+#define RCC_ETHxCFGR_ETHxRXLPEN			BIT(11)
+
+/* RCC_USBHCFGR register fields */
+#define RCC_USBHCFGR_USBHRST			BIT(0)
+#define RCC_USBHCFGR_USBHEN			BIT(1)
+#define RCC_USBHCFGR_USBHLPEN			BIT(2)
+#define RCC_USBHCFGR_USBHSTPEN			BIT(4)
+
+/* RCC_USB2PHY1CFGR register fields */
+#define RCC_USB2PHY1CFGR_USB2PHY1RST		BIT(0)
+#define RCC_USB2PHY1CFGR_USB2PHY1EN		BIT(1)
+#define RCC_USB2PHY1CFGR_USB2PHY1LPEN		BIT(2)
+#define RCC_USB2PHY1CFGR_USB2PHY1STPEN		BIT(4)
+#define RCC_USB2PHY1CFGR_USB2PHY1CKREFSEL	BIT(15)
+
+/* RCC_OTGCFGR register fields */
+#define RCC_OTGCFGR_OTGRST			BIT(0)
+#define RCC_OTGCFGR_OTGEN			BIT(1)
+#define RCC_OTGCFGR_OTGLPEN			BIT(2)
+
+/* RCC_USB2PHY2CFGR register fields */
+#define RCC_USB2PHY2CFGR_USB2PHY2RST		BIT(0)
+#define RCC_USB2PHY2CFGR_USB2PHY2EN		BIT(1)
+#define RCC_USB2PHY2CFGR_USB2PHY2LPEN		BIT(2)
+#define RCC_USB2PHY2CFGR_USB2PHY2STPEN		BIT(4)
+#define RCC_USB2PHY2CFGR_USB2PHY2CKREFSEL	BIT(15)
+
+/* RCC_USB2PHYxCFGR register fields */
+#define RCC_USB2PHYxCFGR_USB2PHY1RST		BIT(0)
+#define RCC_USB2PHYxCFGR_USB2PHY1EN		BIT(1)
+#define RCC_USB2PHYxCFGR_USB2PHY1LPEN		BIT(2)
+#define RCC_USB2PHYxCFGR_USB2PHY1STPEN		BIT(4)
+#define RCC_USB2PHYxCFGR_USB2PHY1CKREFSEL	BIT(15)
+
+/* RCC_STGENCFGR register fields */
+#define RCC_STGENCFGR_STGENEN			BIT(1)
+#define RCC_STGENCFGR_STGENLPEN			BIT(2)
+#define RCC_STGENCFGR_STGENSTPEN		BIT(4)
+
+/* RCC_SDMMC1CFGR register fields */
+#define RCC_SDMMC1CFGR_SDMMC1RST		BIT(0)
+#define RCC_SDMMC1CFGR_SDMMC1EN			BIT(1)
+#define RCC_SDMMC1CFGR_SDMMC1LPEN		BIT(2)
+#define RCC_SDMMC1CFGR_SDMMC1DLLRST		BIT(16)
+
+/* RCC_SDMMC2CFGR register fields */
+#define RCC_SDMMC2CFGR_SDMMC2RST		BIT(0)
+#define RCC_SDMMC2CFGR_SDMMC2EN			BIT(1)
+#define RCC_SDMMC2CFGR_SDMMC2LPEN		BIT(2)
+#define RCC_SDMMC2CFGR_SDMMC2DLLRST		BIT(16)
+
+/* RCC_SDMMC3CFGR register fields */
+#define RCC_SDMMC3CFGR_SDMMC3RST		BIT(0)
+#define RCC_SDMMC3CFGR_SDMMC3EN			BIT(1)
+#define RCC_SDMMC3CFGR_SDMMC3LPEN		BIT(2)
+#define RCC_SDMMC3CFGR_SDMMC3DLLRST		BIT(16)
+
+/* RCC_SDMMCxCFGR register fields */
+#define RCC_SDMMCxCFGR_SDMMC1RST		BIT(0)
+#define RCC_SDMMCxCFGR_SDMMC1EN			BIT(1)
+#define RCC_SDMMCxCFGR_SDMMC1LPEN		BIT(2)
+#define RCC_SDMMCxCFGR_SDMMC1DLLRST		BIT(16)
+
+/* RCC_LTDCCFGR register fields */
+#define RCC_LTDCCFGR_LTDCRST			BIT(0)
+#define RCC_LTDCCFGR_LTDCEN			BIT(1)
+#define RCC_LTDCCFGR_LTDCLPEN			BIT(2)
+
+/* RCC_CSICFGR register fields */
+#define RCC_CSICFGR_CSIRST			BIT(0)
+#define RCC_CSICFGR_CSIEN			BIT(1)
+#define RCC_CSICFGR_CSILPEN			BIT(2)
+
+/* RCC_DCMIPPCFGR register fields */
+#define RCC_DCMIPPCFGR_DCMIPPRST		BIT(0)
+#define RCC_DCMIPPCFGR_DCMIPPEN			BIT(1)
+#define RCC_DCMIPPCFGR_DCMIPPLPEN		BIT(2)
+
+/* RCC_DCMIPSSICFGR register fields */
+#define RCC_DCMIPSSICFGR_DCMIPSSIRST		BIT(0)
+#define RCC_DCMIPSSICFGR_DCMIPSSIEN		BIT(1)
+#define RCC_DCMIPSSICFGR_DCMIPSSILPEN		BIT(2)
+
+/* RCC_RNG1CFGR register fields */
+#define RCC_RNG1CFGR_RNG1RST			BIT(0)
+#define RCC_RNG1CFGR_RNG1EN			BIT(1)
+#define RCC_RNG1CFGR_RNG1LPEN			BIT(2)
+
+/* RCC_RNG2CFGR register fields */
+#define RCC_RNG2CFGR_RNG2RST			BIT(0)
+#define RCC_RNG2CFGR_RNG2EN			BIT(1)
+#define RCC_RNG2CFGR_RNG2LPEN			BIT(2)
+
+/* RCC_PKACFGR register fields */
+#define RCC_PKACFGR_PKARST			BIT(0)
+#define RCC_PKACFGR_PKAEN			BIT(1)
+#define RCC_PKACFGR_PKALPEN			BIT(2)
+
+/* RCC_SAESCFGR register fields */
+#define RCC_SAESCFGR_SAESRST			BIT(0)
+#define RCC_SAESCFGR_SAESEN			BIT(1)
+#define RCC_SAESCFGR_SAESLPEN			BIT(2)
+
+/* RCC_HASH1CFGR register fields */
+#define RCC_HASH1CFGR_HASH1RST			BIT(0)
+#define RCC_HASH1CFGR_HASH1EN			BIT(1)
+#define RCC_HASH1CFGR_HASH1LPEN			BIT(2)
+
+/* RCC_HASH2CFGR register fields */
+#define RCC_HASH2CFGR_HASH2RST			BIT(0)
+#define RCC_HASH2CFGR_HASH2EN			BIT(1)
+#define RCC_HASH2CFGR_HASH2LPEN			BIT(2)
+
+/* RCC_CRYP1CFGR register fields */
+#define RCC_CRYP1CFGR_CRYP1RST			BIT(0)
+#define RCC_CRYP1CFGR_CRYP1EN			BIT(1)
+#define RCC_CRYP1CFGR_CRYP1LPEN			BIT(2)
+
+/* RCC_CRYP2CFGR register fields */
+#define RCC_CRYP2CFGR_CRYP2RST			BIT(0)
+#define RCC_CRYP2CFGR_CRYP2EN			BIT(1)
+#define RCC_CRYP2CFGR_CRYP2LPEN			BIT(2)
+
+/* RCC_CRYPxCFGR register fields */
+#define RCC_CRYPxCFGR_CRYPxRST			BIT(0)
+#define RCC_CRYPxCFGR_CRYPxEN			BIT(1)
+#define RCC_CRYPxCFGR_CRYPxLPEN			BIT(2)
+
+/* RCC_IWDG1CFGR register fields */
+#define RCC_IWDG1CFGR_IWDG1EN			BIT(1)
+#define RCC_IWDG1CFGR_IWDG1LPEN			BIT(2)
+
+/* RCC_IWDG2CFGR register fields */
+#define RCC_IWDG2CFGR_IWDG2EN			BIT(1)
+#define RCC_IWDG2CFGR_IWDG2LPEN			BIT(2)
+
+/* RCC_IWDG3CFGR register fields */
+#define RCC_IWDG3CFGR_IWDG3EN			BIT(1)
+#define RCC_IWDG3CFGR_IWDG3LPEN			BIT(2)
+
+/* RCC_IWDG4CFGR register fields */
+#define RCC_IWDG4CFGR_IWDG4EN			BIT(1)
+#define RCC_IWDG4CFGR_IWDG4LPEN			BIT(2)
+
+/* RCC_IWDGxCFGR register fields */
+#define RCC_IWDGxCFGR_IWDGxEN			BIT(1)
+#define RCC_IWDGxCFGR_IWDGxLPEN			BIT(2)
+
+/* RCC_WWDG1CFGR register fields */
+#define RCC_WWDG1CFGR_WWDG1RST			BIT(0)
+#define RCC_WWDG1CFGR_WWDG1EN			BIT(1)
+#define RCC_WWDG1CFGR_WWDG1LPEN			BIT(2)
+
+/* RCC_VREFCFGR register fields */
+#define RCC_VREFCFGR_VREFRST			BIT(0)
+#define RCC_VREFCFGR_VREFEN			BIT(1)
+#define RCC_VREFCFGR_VREFLPEN			BIT(2)
+
+/* RCC_DTSCFGR register fields */
+#define RCC_DTSCFGR_DTSRST			BIT(0)
+#define RCC_DTSCFGR_DTSEN			BIT(1)
+#define RCC_DTSCFGR_DTSLPEN			BIT(2)
+#define RCC_DTSCFGR_DTSKERSEL_MASK		GENMASK_32(13, 12)
+#define RCC_DTSCFGR_DTSKERSEL_SHIFT		12
+
+/* RCC_CRCCFGR register fields */
+#define RCC_CRCCFGR_CRCRST			BIT(0)
+#define RCC_CRCCFGR_CRCEN			BIT(1)
+#define RCC_CRCCFGR_CRCLPEN			BIT(2)
+
+/* RCC_SERCCFGR register fields */
+#define RCC_SERCCFGR_SERCRST			BIT(0)
+#define RCC_SERCCFGR_SERCEN			BIT(1)
+#define RCC_SERCCFGR_SERCLPEN			BIT(2)
+
+/* RCC_DDRPERFMCFGR register fields */
+#define RCC_DDRPERFMCFGR_DDRPERFMRST		BIT(0)
+#define RCC_DDRPERFMCFGR_DDRPERFMEN		BIT(1)
+#define RCC_DDRPERFMCFGR_DDRPERFMLPEN		BIT(2)
+
+/* RCC_I3C1CFGR register fields */
+#define RCC_I3C1CFGR_I3C1RST			BIT(0)
+#define RCC_I3C1CFGR_I3C1EN			BIT(1)
+#define RCC_I3C1CFGR_I3C1LPEN			BIT(2)
+
+/* RCC_I3C2CFGR register fields */
+#define RCC_I3C2CFGR_I3C2RST			BIT(0)
+#define RCC_I3C2CFGR_I3C2EN			BIT(1)
+#define RCC_I3C2CFGR_I3C2LPEN			BIT(2)
+
+/* RCC_I3C3CFGR register fields */
+#define RCC_I3C3CFGR_I3C3RST			BIT(0)
+#define RCC_I3C3CFGR_I3C3EN			BIT(1)
+#define RCC_I3C3CFGR_I3C3LPEN			BIT(2)
+
+/* RCC_I3CxCFGR register fields */
+#define RCC_I3CxCFGR_I3CxRST			BIT(0)
+#define RCC_I3CxCFGR_I3CxEN			BIT(1)
+#define RCC_I3CxCFGR_I3CxLPEN			BIT(2)
+#define RCC_I3CxCFGR_I3CxAMEN			BIT(3)
+
+/* RCC_MUXSELCFGR register fields */
+#define RCC_MUXSELCFGR_MUXSEL0_MASK		GENMASK_32(2, 0)
+#define RCC_MUXSELCFGR_MUXSEL0_SHIFT		0
+#define RCC_MUXSELCFGR_MUXSEL1_MASK		GENMASK_32(6, 4)
+#define RCC_MUXSELCFGR_MUXSEL1_SHIFT		4
+#define RCC_MUXSELCFGR_MUXSEL2_MASK		GENMASK_32(10, 8)
+#define RCC_MUXSELCFGR_MUXSEL2_SHIFT		8
+#define RCC_MUXSELCFGR_MUXSEL3_MASK		GENMASK_32(14, 12)
+#define RCC_MUXSELCFGR_MUXSEL3_SHIFT		12
+#define RCC_MUXSELCFGR_MUXSEL4_MASK		GENMASK_32(18, 16)
+#define RCC_MUXSELCFGR_MUXSEL4_SHIFT		16
+#define RCC_MUXSELCFGR_MUXSEL5_MASK		GENMASK_32(21, 20)
+#define RCC_MUXSELCFGR_MUXSEL5_SHIFT		20
+#define RCC_MUXSELCFGR_MUXSEL6_MASK		GENMASK_32(25, 24)
+#define RCC_MUXSELCFGR_MUXSEL6_SHIFT		24
+#define RCC_MUXSELCFGR_MUXSEL7_MASK		GENMASK_32(29, 28)
+#define RCC_MUXSELCFGR_MUXSEL7_SHIFT		28
+
+/* RCC_XBAR0CFGR register fields */
+#define RCC_XBAR0CFGR_XBAR0SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR0CFGR_XBAR0SEL_SHIFT		0
+#define RCC_XBAR0CFGR_XBAR0EN			BIT(6)
+#define RCC_XBAR0CFGR_XBAR0STS			BIT(7)
+
+/* RCC_XBAR1CFGR register fields */
+#define RCC_XBAR1CFGR_XBAR1SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR1CFGR_XBAR1SEL_SHIFT		0
+#define RCC_XBAR1CFGR_XBAR1EN			BIT(6)
+#define RCC_XBAR1CFGR_XBAR1STS			BIT(7)
+
+/* RCC_XBAR2CFGR register fields */
+#define RCC_XBAR2CFGR_XBAR2SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR2CFGR_XBAR2SEL_SHIFT		0
+#define RCC_XBAR2CFGR_XBAR2EN			BIT(6)
+#define RCC_XBAR2CFGR_XBAR2STS			BIT(7)
+
+/* RCC_XBAR3CFGR register fields */
+#define RCC_XBAR3CFGR_XBAR3SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR3CFGR_XBAR3SEL_SHIFT		0
+#define RCC_XBAR3CFGR_XBAR3EN			BIT(6)
+#define RCC_XBAR3CFGR_XBAR3STS			BIT(7)
+
+/* RCC_XBAR4CFGR register fields */
+#define RCC_XBAR4CFGR_XBAR4SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR4CFGR_XBAR4SEL_SHIFT		0
+#define RCC_XBAR4CFGR_XBAR4EN			BIT(6)
+#define RCC_XBAR4CFGR_XBAR4STS			BIT(7)
+
+/* RCC_XBAR5CFGR register fields */
+#define RCC_XBAR5CFGR_XBAR5SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR5CFGR_XBAR5SEL_SHIFT		0
+#define RCC_XBAR5CFGR_XBAR5EN			BIT(6)
+#define RCC_XBAR5CFGR_XBAR5STS			BIT(7)
+
+/* RCC_XBAR6CFGR register fields */
+#define RCC_XBAR6CFGR_XBAR6SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR6CFGR_XBAR6SEL_SHIFT		0
+#define RCC_XBAR6CFGR_XBAR6EN			BIT(6)
+#define RCC_XBAR6CFGR_XBAR6STS			BIT(7)
+
+/* RCC_XBAR7CFGR register fields */
+#define RCC_XBAR7CFGR_XBAR7SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR7CFGR_XBAR7SEL_SHIFT		0
+#define RCC_XBAR7CFGR_XBAR7EN			BIT(6)
+#define RCC_XBAR7CFGR_XBAR7STS			BIT(7)
+
+/* RCC_XBAR8CFGR register fields */
+#define RCC_XBAR8CFGR_XBAR8SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR8CFGR_XBAR8SEL_SHIFT		0
+#define RCC_XBAR8CFGR_XBAR8EN			BIT(6)
+#define RCC_XBAR8CFGR_XBAR8STS			BIT(7)
+
+/* RCC_XBAR9CFGR register fields */
+#define RCC_XBAR9CFGR_XBAR9SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR9CFGR_XBAR9SEL_SHIFT		0
+#define RCC_XBAR9CFGR_XBAR9EN			BIT(6)
+#define RCC_XBAR9CFGR_XBAR9STS			BIT(7)
+
+/* RCC_XBAR10CFGR register fields */
+#define RCC_XBAR10CFGR_XBAR10SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR10CFGR_XBAR10SEL_SHIFT		0
+#define RCC_XBAR10CFGR_XBAR10EN			BIT(6)
+#define RCC_XBAR10CFGR_XBAR10STS		BIT(7)
+
+/* RCC_XBAR11CFGR register fields */
+#define RCC_XBAR11CFGR_XBAR11SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR11CFGR_XBAR11SEL_SHIFT		0
+#define RCC_XBAR11CFGR_XBAR11EN			BIT(6)
+#define RCC_XBAR11CFGR_XBAR11STS		BIT(7)
+
+/* RCC_XBAR12CFGR register fields */
+#define RCC_XBAR12CFGR_XBAR12SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR12CFGR_XBAR12SEL_SHIFT		0
+#define RCC_XBAR12CFGR_XBAR12EN			BIT(6)
+#define RCC_XBAR12CFGR_XBAR12STS		BIT(7)
+
+/* RCC_XBAR13CFGR register fields */
+#define RCC_XBAR13CFGR_XBAR13SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR13CFGR_XBAR13SEL_SHIFT		0
+#define RCC_XBAR13CFGR_XBAR13EN			BIT(6)
+#define RCC_XBAR13CFGR_XBAR13STS		BIT(7)
+
+/* RCC_XBAR14CFGR register fields */
+#define RCC_XBAR14CFGR_XBAR14SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR14CFGR_XBAR14SEL_SHIFT		0
+#define RCC_XBAR14CFGR_XBAR14EN			BIT(6)
+#define RCC_XBAR14CFGR_XBAR14STS		BIT(7)
+
+/* RCC_XBAR15CFGR register fields */
+#define RCC_XBAR15CFGR_XBAR15SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR15CFGR_XBAR15SEL_SHIFT		0
+#define RCC_XBAR15CFGR_XBAR15EN			BIT(6)
+#define RCC_XBAR15CFGR_XBAR15STS		BIT(7)
+
+/* RCC_XBAR16CFGR register fields */
+#define RCC_XBAR16CFGR_XBAR16SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR16CFGR_XBAR16SEL_SHIFT		0
+#define RCC_XBAR16CFGR_XBAR16EN			BIT(6)
+#define RCC_XBAR16CFGR_XBAR16STS		BIT(7)
+
+/* RCC_XBAR17CFGR register fields */
+#define RCC_XBAR17CFGR_XBAR17SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR17CFGR_XBAR17SEL_SHIFT		0
+#define RCC_XBAR17CFGR_XBAR17EN			BIT(6)
+#define RCC_XBAR17CFGR_XBAR17STS		BIT(7)
+
+/* RCC_XBAR18CFGR register fields */
+#define RCC_XBAR18CFGR_XBAR18SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR18CFGR_XBAR18SEL_SHIFT		0
+#define RCC_XBAR18CFGR_XBAR18EN			BIT(6)
+#define RCC_XBAR18CFGR_XBAR18STS		BIT(7)
+
+/* RCC_XBAR19CFGR register fields */
+#define RCC_XBAR19CFGR_XBAR19SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR19CFGR_XBAR19SEL_SHIFT		0
+#define RCC_XBAR19CFGR_XBAR19EN			BIT(6)
+#define RCC_XBAR19CFGR_XBAR19STS		BIT(7)
+
+/* RCC_XBAR20CFGR register fields */
+#define RCC_XBAR20CFGR_XBAR20SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR20CFGR_XBAR20SEL_SHIFT		0
+#define RCC_XBAR20CFGR_XBAR20EN			BIT(6)
+#define RCC_XBAR20CFGR_XBAR20STS		BIT(7)
+
+/* RCC_XBAR21CFGR register fields */
+#define RCC_XBAR21CFGR_XBAR21SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR21CFGR_XBAR21SEL_SHIFT		0
+#define RCC_XBAR21CFGR_XBAR21EN			BIT(6)
+#define RCC_XBAR21CFGR_XBAR21STS		BIT(7)
+
+/* RCC_XBAR22CFGR register fields */
+#define RCC_XBAR22CFGR_XBAR22SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR22CFGR_XBAR22SEL_SHIFT		0
+#define RCC_XBAR22CFGR_XBAR22EN			BIT(6)
+#define RCC_XBAR22CFGR_XBAR22STS		BIT(7)
+
+/* RCC_XBAR23CFGR register fields */
+#define RCC_XBAR23CFGR_XBAR23SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR23CFGR_XBAR23SEL_SHIFT		0
+#define RCC_XBAR23CFGR_XBAR23EN			BIT(6)
+#define RCC_XBAR23CFGR_XBAR23STS		BIT(7)
+
+/* RCC_XBAR24CFGR register fields */
+#define RCC_XBAR24CFGR_XBAR24SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR24CFGR_XBAR24SEL_SHIFT		0
+#define RCC_XBAR24CFGR_XBAR24EN			BIT(6)
+#define RCC_XBAR24CFGR_XBAR24STS		BIT(7)
+
+/* RCC_XBAR25CFGR register fields */
+#define RCC_XBAR25CFGR_XBAR25SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR25CFGR_XBAR25SEL_SHIFT		0
+#define RCC_XBAR25CFGR_XBAR25EN			BIT(6)
+#define RCC_XBAR25CFGR_XBAR25STS		BIT(7)
+
+/* RCC_XBAR26CFGR register fields */
+#define RCC_XBAR26CFGR_XBAR26SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR26CFGR_XBAR26SEL_SHIFT		0
+#define RCC_XBAR26CFGR_XBAR26EN			BIT(6)
+#define RCC_XBAR26CFGR_XBAR26STS		BIT(7)
+
+/* RCC_XBAR27CFGR register fields */
+#define RCC_XBAR27CFGR_XBAR27SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR27CFGR_XBAR27SEL_SHIFT		0
+#define RCC_XBAR27CFGR_XBAR27EN			BIT(6)
+#define RCC_XBAR27CFGR_XBAR27STS		BIT(7)
+
+/* RCC_XBAR28CFGR register fields */
+#define RCC_XBAR28CFGR_XBAR28SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR28CFGR_XBAR28SEL_SHIFT		0
+#define RCC_XBAR28CFGR_XBAR28EN			BIT(6)
+#define RCC_XBAR28CFGR_XBAR28STS		BIT(7)
+
+/* RCC_XBAR29CFGR register fields */
+#define RCC_XBAR29CFGR_XBAR29SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR29CFGR_XBAR29SEL_SHIFT		0
+#define RCC_XBAR29CFGR_XBAR29EN			BIT(6)
+#define RCC_XBAR29CFGR_XBAR29STS		BIT(7)
+
+/* RCC_XBAR30CFGR register fields */
+#define RCC_XBAR30CFGR_XBAR30SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR30CFGR_XBAR30SEL_SHIFT		0
+#define RCC_XBAR30CFGR_XBAR30EN			BIT(6)
+#define RCC_XBAR30CFGR_XBAR30STS		BIT(7)
+
+/* RCC_XBAR31CFGR register fields */
+#define RCC_XBAR31CFGR_XBAR31SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR31CFGR_XBAR31SEL_SHIFT		0
+#define RCC_XBAR31CFGR_XBAR31EN			BIT(6)
+#define RCC_XBAR31CFGR_XBAR31STS		BIT(7)
+
+/* RCC_XBAR32CFGR register fields */
+#define RCC_XBAR32CFGR_XBAR32SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR32CFGR_XBAR32SEL_SHIFT		0
+#define RCC_XBAR32CFGR_XBAR32EN			BIT(6)
+#define RCC_XBAR32CFGR_XBAR32STS		BIT(7)
+
+/* RCC_XBAR33CFGR register fields */
+#define RCC_XBAR33CFGR_XBAR33SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR33CFGR_XBAR33SEL_SHIFT		0
+#define RCC_XBAR33CFGR_XBAR33EN			BIT(6)
+#define RCC_XBAR33CFGR_XBAR33STS		BIT(7)
+
+/* RCC_XBAR34CFGR register fields */
+#define RCC_XBAR34CFGR_XBAR34SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR34CFGR_XBAR34SEL_SHIFT		0
+#define RCC_XBAR34CFGR_XBAR34EN			BIT(6)
+#define RCC_XBAR34CFGR_XBAR34STS		BIT(7)
+
+/* RCC_XBAR35CFGR register fields */
+#define RCC_XBAR35CFGR_XBAR35SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR35CFGR_XBAR35SEL_SHIFT		0
+#define RCC_XBAR35CFGR_XBAR35EN			BIT(6)
+#define RCC_XBAR35CFGR_XBAR35STS		BIT(7)
+
+/* RCC_XBAR36CFGR register fields */
+#define RCC_XBAR36CFGR_XBAR36SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR36CFGR_XBAR36SEL_SHIFT		0
+#define RCC_XBAR36CFGR_XBAR36EN			BIT(6)
+#define RCC_XBAR36CFGR_XBAR36STS		BIT(7)
+
+/* RCC_XBAR37CFGR register fields */
+#define RCC_XBAR37CFGR_XBAR37SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR37CFGR_XBAR37SEL_SHIFT		0
+#define RCC_XBAR37CFGR_XBAR37EN			BIT(6)
+#define RCC_XBAR37CFGR_XBAR37STS		BIT(7)
+
+/* RCC_XBAR38CFGR register fields */
+#define RCC_XBAR38CFGR_XBAR38SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR38CFGR_XBAR38SEL_SHIFT		0
+#define RCC_XBAR38CFGR_XBAR38EN			BIT(6)
+#define RCC_XBAR38CFGR_XBAR38STS		BIT(7)
+
+/* RCC_XBAR39CFGR register fields */
+#define RCC_XBAR39CFGR_XBAR39SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR39CFGR_XBAR39SEL_SHIFT		0
+#define RCC_XBAR39CFGR_XBAR39EN			BIT(6)
+#define RCC_XBAR39CFGR_XBAR39STS		BIT(7)
+
+/* RCC_XBAR40CFGR register fields */
+#define RCC_XBAR40CFGR_XBAR40SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR40CFGR_XBAR40SEL_SHIFT		0
+#define RCC_XBAR40CFGR_XBAR40EN			BIT(6)
+#define RCC_XBAR40CFGR_XBAR40STS		BIT(7)
+
+/* RCC_XBAR41CFGR register fields */
+#define RCC_XBAR41CFGR_XBAR41SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR41CFGR_XBAR41SEL_SHIFT		0
+#define RCC_XBAR41CFGR_XBAR41EN			BIT(6)
+#define RCC_XBAR41CFGR_XBAR41STS		BIT(7)
+
+/* RCC_XBAR42CFGR register fields */
+#define RCC_XBAR42CFGR_XBAR42SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR42CFGR_XBAR42SEL_SHIFT		0
+#define RCC_XBAR42CFGR_XBAR42EN			BIT(6)
+#define RCC_XBAR42CFGR_XBAR42STS		BIT(7)
+
+/* RCC_XBAR43CFGR register fields */
+#define RCC_XBAR43CFGR_XBAR43SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR43CFGR_XBAR43SEL_SHIFT		0
+#define RCC_XBAR43CFGR_XBAR43EN			BIT(6)
+#define RCC_XBAR43CFGR_XBAR43STS		BIT(7)
+
+/* RCC_XBAR44CFGR register fields */
+#define RCC_XBAR44CFGR_XBAR44SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR44CFGR_XBAR44SEL_SHIFT		0
+#define RCC_XBAR44CFGR_XBAR44EN			BIT(6)
+#define RCC_XBAR44CFGR_XBAR44STS		BIT(7)
+
+/* RCC_XBAR45CFGR register fields */
+#define RCC_XBAR45CFGR_XBAR45SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR45CFGR_XBAR45SEL_SHIFT		0
+#define RCC_XBAR45CFGR_XBAR45EN			BIT(6)
+#define RCC_XBAR45CFGR_XBAR45STS		BIT(7)
+
+/* RCC_XBAR46CFGR register fields */
+#define RCC_XBAR46CFGR_XBAR46SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR46CFGR_XBAR46SEL_SHIFT		0
+#define RCC_XBAR46CFGR_XBAR46EN			BIT(6)
+#define RCC_XBAR46CFGR_XBAR46STS		BIT(7)
+
+/* RCC_XBAR47CFGR register fields */
+#define RCC_XBAR47CFGR_XBAR47SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR47CFGR_XBAR47SEL_SHIFT		0
+#define RCC_XBAR47CFGR_XBAR47EN			BIT(6)
+#define RCC_XBAR47CFGR_XBAR47STS		BIT(7)
+
+/* RCC_XBAR48CFGR register fields */
+#define RCC_XBAR48CFGR_XBAR48SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR48CFGR_XBAR48SEL_SHIFT		0
+#define RCC_XBAR48CFGR_XBAR48EN			BIT(6)
+#define RCC_XBAR48CFGR_XBAR48STS		BIT(7)
+
+/* RCC_XBAR49CFGR register fields */
+#define RCC_XBAR49CFGR_XBAR49SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR49CFGR_XBAR49SEL_SHIFT		0
+#define RCC_XBAR49CFGR_XBAR49EN			BIT(6)
+#define RCC_XBAR49CFGR_XBAR49STS		BIT(7)
+
+/* RCC_XBAR50CFGR register fields */
+#define RCC_XBAR50CFGR_XBAR50SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR50CFGR_XBAR50SEL_SHIFT		0
+#define RCC_XBAR50CFGR_XBAR50EN			BIT(6)
+#define RCC_XBAR50CFGR_XBAR50STS		BIT(7)
+
+/* RCC_XBAR51CFGR register fields */
+#define RCC_XBAR51CFGR_XBAR51SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR51CFGR_XBAR51SEL_SHIFT		0
+#define RCC_XBAR51CFGR_XBAR51EN			BIT(6)
+#define RCC_XBAR51CFGR_XBAR51STS		BIT(7)
+
+/* RCC_XBAR52CFGR register fields */
+#define RCC_XBAR52CFGR_XBAR52SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR52CFGR_XBAR52SEL_SHIFT		0
+#define RCC_XBAR52CFGR_XBAR52EN			BIT(6)
+#define RCC_XBAR52CFGR_XBAR52STS		BIT(7)
+
+/* RCC_XBAR53CFGR register fields */
+#define RCC_XBAR53CFGR_XBAR53SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR53CFGR_XBAR53SEL_SHIFT		0
+#define RCC_XBAR53CFGR_XBAR53EN			BIT(6)
+#define RCC_XBAR53CFGR_XBAR53STS		BIT(7)
+
+/* RCC_XBAR54CFGR register fields */
+#define RCC_XBAR54CFGR_XBAR54SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR54CFGR_XBAR54SEL_SHIFT		0
+#define RCC_XBAR54CFGR_XBAR54EN			BIT(6)
+#define RCC_XBAR54CFGR_XBAR54STS		BIT(7)
+
+/* RCC_XBAR55CFGR register fields */
+#define RCC_XBAR55CFGR_XBAR55SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR55CFGR_XBAR55SEL_SHIFT		0
+#define RCC_XBAR55CFGR_XBAR55EN			BIT(6)
+#define RCC_XBAR55CFGR_XBAR55STS		BIT(7)
+
+/* RCC_XBAR56CFGR register fields */
+#define RCC_XBAR56CFGR_XBAR56SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR56CFGR_XBAR56SEL_SHIFT		0
+#define RCC_XBAR56CFGR_XBAR56EN			BIT(6)
+#define RCC_XBAR56CFGR_XBAR56STS		BIT(7)
+
+/* RCC_XBAR57CFGR register fields */
+#define RCC_XBAR57CFGR_XBAR57SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR57CFGR_XBAR57SEL_SHIFT		0
+#define RCC_XBAR57CFGR_XBAR57EN			BIT(6)
+#define RCC_XBAR57CFGR_XBAR57STS		BIT(7)
+
+/* RCC_XBAR58CFGR register fields */
+#define RCC_XBAR58CFGR_XBAR58SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR58CFGR_XBAR58SEL_SHIFT		0
+#define RCC_XBAR58CFGR_XBAR58EN			BIT(6)
+#define RCC_XBAR58CFGR_XBAR58STS		BIT(7)
+
+/* RCC_XBAR59CFGR register fields */
+#define RCC_XBAR59CFGR_XBAR59SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR59CFGR_XBAR59SEL_SHIFT		0
+#define RCC_XBAR59CFGR_XBAR59EN			BIT(6)
+#define RCC_XBAR59CFGR_XBAR59STS		BIT(7)
+
+/* RCC_XBAR60CFGR register fields */
+#define RCC_XBAR60CFGR_XBAR60SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR60CFGR_XBAR60SEL_SHIFT		0
+#define RCC_XBAR60CFGR_XBAR60EN			BIT(6)
+#define RCC_XBAR60CFGR_XBAR60STS		BIT(7)
+
+/* RCC_XBAR61CFGR register fields */
+#define RCC_XBAR61CFGR_XBAR61SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR61CFGR_XBAR61SEL_SHIFT		0
+#define RCC_XBAR61CFGR_XBAR61EN			BIT(6)
+#define RCC_XBAR61CFGR_XBAR61STS		BIT(7)
+
+/* RCC_XBAR62CFGR register fields */
+#define RCC_XBAR62CFGR_XBAR62SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR62CFGR_XBAR62SEL_SHIFT		0
+#define RCC_XBAR62CFGR_XBAR62EN			BIT(6)
+#define RCC_XBAR62CFGR_XBAR62STS		BIT(7)
+
+/* RCC_XBAR63CFGR register fields */
+#define RCC_XBAR63CFGR_XBAR63SEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBAR63CFGR_XBAR63SEL_SHIFT		0
+#define RCC_XBAR63CFGR_XBAR63EN			BIT(6)
+#define RCC_XBAR63CFGR_XBAR63STS		BIT(7)
+
+/* RCC_XBARxCFGR register fields */
+#define RCC_XBARxCFGR_XBARxSEL_MASK		GENMASK_32(3, 0)
+#define RCC_XBARxCFGR_XBARxSEL_SHIFT		0
+#define RCC_XBARxCFGR_XBARxEN			BIT(6)
+#define RCC_XBARxCFGR_XBARxSTS			BIT(7)
+
+/* RCC_PREDIV0CFGR register fields */
+#define RCC_PREDIV0CFGR_PREDIV0_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV0CFGR_PREDIV0_SHIFT		0
+
+/* RCC_PREDIV1CFGR register fields */
+#define RCC_PREDIV1CFGR_PREDIV1_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV1CFGR_PREDIV1_SHIFT		0
+
+/* RCC_PREDIV2CFGR register fields */
+#define RCC_PREDIV2CFGR_PREDIV2_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV2CFGR_PREDIV2_SHIFT		0
+
+/* RCC_PREDIV3CFGR register fields */
+#define RCC_PREDIV3CFGR_PREDIV3_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV3CFGR_PREDIV3_SHIFT		0
+
+/* RCC_PREDIV4CFGR register fields */
+#define RCC_PREDIV4CFGR_PREDIV4_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV4CFGR_PREDIV4_SHIFT		0
+
+/* RCC_PREDIV5CFGR register fields */
+#define RCC_PREDIV5CFGR_PREDIV5_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV5CFGR_PREDIV5_SHIFT		0
+
+/* RCC_PREDIV6CFGR register fields */
+#define RCC_PREDIV6CFGR_PREDIV6_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV6CFGR_PREDIV6_SHIFT		0
+
+/* RCC_PREDIV7CFGR register fields */
+#define RCC_PREDIV7CFGR_PREDIV7_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV7CFGR_PREDIV7_SHIFT		0
+
+/* RCC_PREDIV8CFGR register fields */
+#define RCC_PREDIV8CFGR_PREDIV8_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV8CFGR_PREDIV8_SHIFT		0
+
+/* RCC_PREDIV9CFGR register fields */
+#define RCC_PREDIV9CFGR_PREDIV9_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV9CFGR_PREDIV9_SHIFT		0
+
+/* RCC_PREDIV10CFGR register fields */
+#define RCC_PREDIV10CFGR_PREDIV10_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV10CFGR_PREDIV10_SHIFT		0
+
+/* RCC_PREDIV11CFGR register fields */
+#define RCC_PREDIV11CFGR_PREDIV11_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV11CFGR_PREDIV11_SHIFT		0
+
+/* RCC_PREDIV12CFGR register fields */
+#define RCC_PREDIV12CFGR_PREDIV12_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV12CFGR_PREDIV12_SHIFT		0
+
+/* RCC_PREDIV13CFGR register fields */
+#define RCC_PREDIV13CFGR_PREDIV13_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV13CFGR_PREDIV13_SHIFT		0
+
+/* RCC_PREDIV14CFGR register fields */
+#define RCC_PREDIV14CFGR_PREDIV14_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV14CFGR_PREDIV14_SHIFT		0
+
+/* RCC_PREDIV15CFGR register fields */
+#define RCC_PREDIV15CFGR_PREDIV15_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV15CFGR_PREDIV15_SHIFT		0
+
+/* RCC_PREDIV16CFGR register fields */
+#define RCC_PREDIV16CFGR_PREDIV16_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV16CFGR_PREDIV16_SHIFT		0
+
+/* RCC_PREDIV17CFGR register fields */
+#define RCC_PREDIV17CFGR_PREDIV17_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV17CFGR_PREDIV17_SHIFT		0
+
+/* RCC_PREDIV18CFGR register fields */
+#define RCC_PREDIV18CFGR_PREDIV18_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV18CFGR_PREDIV18_SHIFT		0
+
+/* RCC_PREDIV19CFGR register fields */
+#define RCC_PREDIV19CFGR_PREDIV19_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV19CFGR_PREDIV19_SHIFT		0
+
+/* RCC_PREDIV20CFGR register fields */
+#define RCC_PREDIV20CFGR_PREDIV20_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV20CFGR_PREDIV20_SHIFT		0
+
+/* RCC_PREDIV21CFGR register fields */
+#define RCC_PREDIV21CFGR_PREDIV21_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV21CFGR_PREDIV21_SHIFT		0
+
+/* RCC_PREDIV22CFGR register fields */
+#define RCC_PREDIV22CFGR_PREDIV22_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV22CFGR_PREDIV22_SHIFT		0
+
+/* RCC_PREDIV23CFGR register fields */
+#define RCC_PREDIV23CFGR_PREDIV23_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV23CFGR_PREDIV23_SHIFT		0
+
+/* RCC_PREDIV24CFGR register fields */
+#define RCC_PREDIV24CFGR_PREDIV24_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV24CFGR_PREDIV24_SHIFT		0
+
+/* RCC_PREDIV25CFGR register fields */
+#define RCC_PREDIV25CFGR_PREDIV25_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV25CFGR_PREDIV25_SHIFT		0
+
+/* RCC_PREDIV26CFGR register fields */
+#define RCC_PREDIV26CFGR_PREDIV26_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV26CFGR_PREDIV26_SHIFT		0
+
+/* RCC_PREDIV27CFGR register fields */
+#define RCC_PREDIV27CFGR_PREDIV27_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV27CFGR_PREDIV27_SHIFT		0
+
+/* RCC_PREDIV28CFGR register fields */
+#define RCC_PREDIV28CFGR_PREDIV28_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV28CFGR_PREDIV28_SHIFT		0
+
+/* RCC_PREDIV29CFGR register fields */
+#define RCC_PREDIV29CFGR_PREDIV29_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV29CFGR_PREDIV29_SHIFT		0
+
+/* RCC_PREDIV30CFGR register fields */
+#define RCC_PREDIV30CFGR_PREDIV30_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV30CFGR_PREDIV30_SHIFT		0
+
+/* RCC_PREDIV31CFGR register fields */
+#define RCC_PREDIV31CFGR_PREDIV31_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV31CFGR_PREDIV31_SHIFT		0
+
+/* RCC_PREDIV32CFGR register fields */
+#define RCC_PREDIV32CFGR_PREDIV32_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV32CFGR_PREDIV32_SHIFT		0
+
+/* RCC_PREDIV33CFGR register fields */
+#define RCC_PREDIV33CFGR_PREDIV33_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV33CFGR_PREDIV33_SHIFT		0
+
+/* RCC_PREDIV34CFGR register fields */
+#define RCC_PREDIV34CFGR_PREDIV34_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV34CFGR_PREDIV34_SHIFT		0
+
+/* RCC_PREDIV35CFGR register fields */
+#define RCC_PREDIV35CFGR_PREDIV35_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV35CFGR_PREDIV35_SHIFT		0
+
+/* RCC_PREDIV36CFGR register fields */
+#define RCC_PREDIV36CFGR_PREDIV36_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV36CFGR_PREDIV36_SHIFT		0
+
+/* RCC_PREDIV37CFGR register fields */
+#define RCC_PREDIV37CFGR_PREDIV37_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV37CFGR_PREDIV37_SHIFT		0
+
+/* RCC_PREDIV38CFGR register fields */
+#define RCC_PREDIV38CFGR_PREDIV38_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV38CFGR_PREDIV38_SHIFT		0
+
+/* RCC_PREDIV39CFGR register fields */
+#define RCC_PREDIV39CFGR_PREDIV39_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV39CFGR_PREDIV39_SHIFT		0
+
+/* RCC_PREDIV40CFGR register fields */
+#define RCC_PREDIV40CFGR_PREDIV40_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV40CFGR_PREDIV40_SHIFT		0
+
+/* RCC_PREDIV41CFGR register fields */
+#define RCC_PREDIV41CFGR_PREDIV41_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV41CFGR_PREDIV41_SHIFT		0
+
+/* RCC_PREDIV42CFGR register fields */
+#define RCC_PREDIV42CFGR_PREDIV42_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV42CFGR_PREDIV42_SHIFT		0
+
+/* RCC_PREDIV43CFGR register fields */
+#define RCC_PREDIV43CFGR_PREDIV43_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV43CFGR_PREDIV43_SHIFT		0
+
+/* RCC_PREDIV44CFGR register fields */
+#define RCC_PREDIV44CFGR_PREDIV44_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV44CFGR_PREDIV44_SHIFT		0
+
+/* RCC_PREDIV45CFGR register fields */
+#define RCC_PREDIV45CFGR_PREDIV45_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV45CFGR_PREDIV45_SHIFT		0
+
+/* RCC_PREDIV46CFGR register fields */
+#define RCC_PREDIV46CFGR_PREDIV46_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV46CFGR_PREDIV46_SHIFT		0
+
+/* RCC_PREDIV47CFGR register fields */
+#define RCC_PREDIV47CFGR_PREDIV47_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV47CFGR_PREDIV47_SHIFT		0
+
+/* RCC_PREDIV48CFGR register fields */
+#define RCC_PREDIV48CFGR_PREDIV48_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV48CFGR_PREDIV48_SHIFT		0
+
+/* RCC_PREDIV49CFGR register fields */
+#define RCC_PREDIV49CFGR_PREDIV49_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV49CFGR_PREDIV49_SHIFT		0
+
+/* RCC_PREDIV50CFGR register fields */
+#define RCC_PREDIV50CFGR_PREDIV50_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV50CFGR_PREDIV50_SHIFT		0
+
+/* RCC_PREDIV51CFGR register fields */
+#define RCC_PREDIV51CFGR_PREDIV51_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV51CFGR_PREDIV51_SHIFT		0
+
+/* RCC_PREDIV52CFGR register fields */
+#define RCC_PREDIV52CFGR_PREDIV52_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV52CFGR_PREDIV52_SHIFT		0
+
+/* RCC_PREDIV53CFGR register fields */
+#define RCC_PREDIV53CFGR_PREDIV53_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV53CFGR_PREDIV53_SHIFT		0
+
+/* RCC_PREDIV54CFGR register fields */
+#define RCC_PREDIV54CFGR_PREDIV54_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV54CFGR_PREDIV54_SHIFT		0
+
+/* RCC_PREDIV55CFGR register fields */
+#define RCC_PREDIV55CFGR_PREDIV55_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV55CFGR_PREDIV55_SHIFT		0
+
+/* RCC_PREDIV56CFGR register fields */
+#define RCC_PREDIV56CFGR_PREDIV56_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV56CFGR_PREDIV56_SHIFT		0
+
+/* RCC_PREDIV57CFGR register fields */
+#define RCC_PREDIV57CFGR_PREDIV57_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV57CFGR_PREDIV57_SHIFT		0
+
+/* RCC_PREDIV58CFGR register fields */
+#define RCC_PREDIV58CFGR_PREDIV58_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV58CFGR_PREDIV58_SHIFT		0
+
+/* RCC_PREDIV59CFGR register fields */
+#define RCC_PREDIV59CFGR_PREDIV59_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV59CFGR_PREDIV59_SHIFT		0
+
+/* RCC_PREDIV60CFGR register fields */
+#define RCC_PREDIV60CFGR_PREDIV60_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV60CFGR_PREDIV60_SHIFT		0
+
+/* RCC_PREDIV61CFGR register fields */
+#define RCC_PREDIV61CFGR_PREDIV61_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV61CFGR_PREDIV61_SHIFT		0
+
+/* RCC_PREDIV62CFGR register fields */
+#define RCC_PREDIV62CFGR_PREDIV62_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV62CFGR_PREDIV62_SHIFT		0
+
+/* RCC_PREDIV63CFGR register fields */
+#define RCC_PREDIV63CFGR_PREDIV63_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIV63CFGR_PREDIV63_SHIFT		0
+
+/* RCC_PREDIVxCFGR register fields */
+#define RCC_PREDIVxCFGR_PREDIVx_MASK		GENMASK_32(9, 0)
+#define RCC_PREDIVxCFGR_PREDIVx_SHIFT		0
+
+/* RCC_FINDIV0CFGR register fields */
+#define RCC_FINDIV0CFGR_FINDIV0_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV0CFGR_FINDIV0_SHIFT		0
+#define RCC_FINDIV0CFGR_FINDIV0EN		BIT(6)
+
+/* RCC_FINDIV1CFGR register fields */
+#define RCC_FINDIV1CFGR_FINDIV1_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV1CFGR_FINDIV1_SHIFT		0
+#define RCC_FINDIV1CFGR_FINDIV1EN		BIT(6)
+
+/* RCC_FINDIV2CFGR register fields */
+#define RCC_FINDIV2CFGR_FINDIV2_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV2CFGR_FINDIV2_SHIFT		0
+#define RCC_FINDIV2CFGR_FINDIV2EN		BIT(6)
+
+/* RCC_FINDIV3CFGR register fields */
+#define RCC_FINDIV3CFGR_FINDIV3_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV3CFGR_FINDIV3_SHIFT		0
+#define RCC_FINDIV3CFGR_FINDIV3EN		BIT(6)
+
+/* RCC_FINDIV4CFGR register fields */
+#define RCC_FINDIV4CFGR_FINDIV4_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV4CFGR_FINDIV4_SHIFT		0
+#define RCC_FINDIV4CFGR_FINDIV4EN		BIT(6)
+
+/* RCC_FINDIV5CFGR register fields */
+#define RCC_FINDIV5CFGR_FINDIV5_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV5CFGR_FINDIV5_SHIFT		0
+#define RCC_FINDIV5CFGR_FINDIV5EN		BIT(6)
+
+/* RCC_FINDIV6CFGR register fields */
+#define RCC_FINDIV6CFGR_FINDIV6_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV6CFGR_FINDIV6_SHIFT		0
+#define RCC_FINDIV6CFGR_FINDIV6EN		BIT(6)
+
+/* RCC_FINDIV7CFGR register fields */
+#define RCC_FINDIV7CFGR_FINDIV7_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV7CFGR_FINDIV7_SHIFT		0
+#define RCC_FINDIV7CFGR_FINDIV7EN		BIT(6)
+
+/* RCC_FINDIV8CFGR register fields */
+#define RCC_FINDIV8CFGR_FINDIV8_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV8CFGR_FINDIV8_SHIFT		0
+#define RCC_FINDIV8CFGR_FINDIV8EN		BIT(6)
+
+/* RCC_FINDIV9CFGR register fields */
+#define RCC_FINDIV9CFGR_FINDIV9_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV9CFGR_FINDIV9_SHIFT		0
+#define RCC_FINDIV9CFGR_FINDIV9EN		BIT(6)
+
+/* RCC_FINDIV10CFGR register fields */
+#define RCC_FINDIV10CFGR_FINDIV10_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV10CFGR_FINDIV10_SHIFT		0
+#define RCC_FINDIV10CFGR_FINDIV10EN		BIT(6)
+
+/* RCC_FINDIV11CFGR register fields */
+#define RCC_FINDIV11CFGR_FINDIV11_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV11CFGR_FINDIV11_SHIFT		0
+#define RCC_FINDIV11CFGR_FINDIV11EN		BIT(6)
+
+/* RCC_FINDIV12CFGR register fields */
+#define RCC_FINDIV12CFGR_FINDIV12_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV12CFGR_FINDIV12_SHIFT		0
+#define RCC_FINDIV12CFGR_FINDIV12EN		BIT(6)
+
+/* RCC_FINDIV13CFGR register fields */
+#define RCC_FINDIV13CFGR_FINDIV13_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV13CFGR_FINDIV13_SHIFT		0
+#define RCC_FINDIV13CFGR_FINDIV13EN		BIT(6)
+
+/* RCC_FINDIV14CFGR register fields */
+#define RCC_FINDIV14CFGR_FINDIV14_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV14CFGR_FINDIV14_SHIFT		0
+#define RCC_FINDIV14CFGR_FINDIV14EN		BIT(6)
+
+/* RCC_FINDIV15CFGR register fields */
+#define RCC_FINDIV15CFGR_FINDIV15_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV15CFGR_FINDIV15_SHIFT		0
+#define RCC_FINDIV15CFGR_FINDIV15EN		BIT(6)
+
+/* RCC_FINDIV16CFGR register fields */
+#define RCC_FINDIV16CFGR_FINDIV16_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV16CFGR_FINDIV16_SHIFT		0
+#define RCC_FINDIV16CFGR_FINDIV16EN		BIT(6)
+
+/* RCC_FINDIV17CFGR register fields */
+#define RCC_FINDIV17CFGR_FINDIV17_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV17CFGR_FINDIV17_SHIFT		0
+#define RCC_FINDIV17CFGR_FINDIV17EN		BIT(6)
+
+/* RCC_FINDIV18CFGR register fields */
+#define RCC_FINDIV18CFGR_FINDIV18_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV18CFGR_FINDIV18_SHIFT		0
+#define RCC_FINDIV18CFGR_FINDIV18EN		BIT(6)
+
+/* RCC_FINDIV19CFGR register fields */
+#define RCC_FINDIV19CFGR_FINDIV19_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV19CFGR_FINDIV19_SHIFT		0
+#define RCC_FINDIV19CFGR_FINDIV19EN		BIT(6)
+
+/* RCC_FINDIV20CFGR register fields */
+#define RCC_FINDIV20CFGR_FINDIV20_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV20CFGR_FINDIV20_SHIFT		0
+#define RCC_FINDIV20CFGR_FINDIV20EN		BIT(6)
+
+/* RCC_FINDIV21CFGR register fields */
+#define RCC_FINDIV21CFGR_FINDIV21_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV21CFGR_FINDIV21_SHIFT		0
+#define RCC_FINDIV21CFGR_FINDIV21EN		BIT(6)
+
+/* RCC_FINDIV22CFGR register fields */
+#define RCC_FINDIV22CFGR_FINDIV22_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV22CFGR_FINDIV22_SHIFT		0
+#define RCC_FINDIV22CFGR_FINDIV22EN		BIT(6)
+
+/* RCC_FINDIV23CFGR register fields */
+#define RCC_FINDIV23CFGR_FINDIV23_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV23CFGR_FINDIV23_SHIFT		0
+#define RCC_FINDIV23CFGR_FINDIV23EN		BIT(6)
+
+/* RCC_FINDIV24CFGR register fields */
+#define RCC_FINDIV24CFGR_FINDIV24_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV24CFGR_FINDIV24_SHIFT		0
+#define RCC_FINDIV24CFGR_FINDIV24EN		BIT(6)
+
+/* RCC_FINDIV25CFGR register fields */
+#define RCC_FINDIV25CFGR_FINDIV25_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV25CFGR_FINDIV25_SHIFT		0
+#define RCC_FINDIV25CFGR_FINDIV25EN		BIT(6)
+
+/* RCC_FINDIV26CFGR register fields */
+#define RCC_FINDIV26CFGR_FINDIV26_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV26CFGR_FINDIV26_SHIFT		0
+#define RCC_FINDIV26CFGR_FINDIV26EN		BIT(6)
+
+/* RCC_FINDIV27CFGR register fields */
+#define RCC_FINDIV27CFGR_FINDIV27_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV27CFGR_FINDIV27_SHIFT		0
+#define RCC_FINDIV27CFGR_FINDIV27EN		BIT(6)
+
+/* RCC_FINDIV28CFGR register fields */
+#define RCC_FINDIV28CFGR_FINDIV28_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV28CFGR_FINDIV28_SHIFT		0
+#define RCC_FINDIV28CFGR_FINDIV28EN		BIT(6)
+
+/* RCC_FINDIV29CFGR register fields */
+#define RCC_FINDIV29CFGR_FINDIV29_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV29CFGR_FINDIV29_SHIFT		0
+#define RCC_FINDIV29CFGR_FINDIV29EN		BIT(6)
+
+/* RCC_FINDIV30CFGR register fields */
+#define RCC_FINDIV30CFGR_FINDIV30_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV30CFGR_FINDIV30_SHIFT		0
+#define RCC_FINDIV30CFGR_FINDIV30EN		BIT(6)
+
+/* RCC_FINDIV31CFGR register fields */
+#define RCC_FINDIV31CFGR_FINDIV31_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV31CFGR_FINDIV31_SHIFT		0
+#define RCC_FINDIV31CFGR_FINDIV31EN		BIT(6)
+
+/* RCC_FINDIV32CFGR register fields */
+#define RCC_FINDIV32CFGR_FINDIV32_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV32CFGR_FINDIV32_SHIFT		0
+#define RCC_FINDIV32CFGR_FINDIV32EN		BIT(6)
+
+/* RCC_FINDIV33CFGR register fields */
+#define RCC_FINDIV33CFGR_FINDIV33_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV33CFGR_FINDIV33_SHIFT		0
+#define RCC_FINDIV33CFGR_FINDIV33EN		BIT(6)
+
+/* RCC_FINDIV34CFGR register fields */
+#define RCC_FINDIV34CFGR_FINDIV34_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV34CFGR_FINDIV34_SHIFT		0
+#define RCC_FINDIV34CFGR_FINDIV34EN		BIT(6)
+
+/* RCC_FINDIV35CFGR register fields */
+#define RCC_FINDIV35CFGR_FINDIV35_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV35CFGR_FINDIV35_SHIFT		0
+#define RCC_FINDIV35CFGR_FINDIV35EN		BIT(6)
+
+/* RCC_FINDIV36CFGR register fields */
+#define RCC_FINDIV36CFGR_FINDIV36_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV36CFGR_FINDIV36_SHIFT		0
+#define RCC_FINDIV36CFGR_FINDIV36EN		BIT(6)
+
+/* RCC_FINDIV37CFGR register fields */
+#define RCC_FINDIV37CFGR_FINDIV37_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV37CFGR_FINDIV37_SHIFT		0
+#define RCC_FINDIV37CFGR_FINDIV37EN		BIT(6)
+
+/* RCC_FINDIV38CFGR register fields */
+#define RCC_FINDIV38CFGR_FINDIV38_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV38CFGR_FINDIV38_SHIFT		0
+#define RCC_FINDIV38CFGR_FINDIV38EN		BIT(6)
+
+/* RCC_FINDIV39CFGR register fields */
+#define RCC_FINDIV39CFGR_FINDIV39_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV39CFGR_FINDIV39_SHIFT		0
+#define RCC_FINDIV39CFGR_FINDIV39EN		BIT(6)
+
+/* RCC_FINDIV40CFGR register fields */
+#define RCC_FINDIV40CFGR_FINDIV40_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV40CFGR_FINDIV40_SHIFT		0
+#define RCC_FINDIV40CFGR_FINDIV40EN		BIT(6)
+
+/* RCC_FINDIV41CFGR register fields */
+#define RCC_FINDIV41CFGR_FINDIV41_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV41CFGR_FINDIV41_SHIFT		0
+#define RCC_FINDIV41CFGR_FINDIV41EN		BIT(6)
+
+/* RCC_FINDIV42CFGR register fields */
+#define RCC_FINDIV42CFGR_FINDIV42_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV42CFGR_FINDIV42_SHIFT		0
+#define RCC_FINDIV42CFGR_FINDIV42EN		BIT(6)
+
+/* RCC_FINDIV43CFGR register fields */
+#define RCC_FINDIV43CFGR_FINDIV43_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV43CFGR_FINDIV43_SHIFT		0
+#define RCC_FINDIV43CFGR_FINDIV43EN		BIT(6)
+
+/* RCC_FINDIV44CFGR register fields */
+#define RCC_FINDIV44CFGR_FINDIV44_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV44CFGR_FINDIV44_SHIFT		0
+#define RCC_FINDIV44CFGR_FINDIV44EN		BIT(6)
+
+/* RCC_FINDIV45CFGR register fields */
+#define RCC_FINDIV45CFGR_FINDIV45_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV45CFGR_FINDIV45_SHIFT		0
+#define RCC_FINDIV45CFGR_FINDIV45EN		BIT(6)
+
+/* RCC_FINDIV46CFGR register fields */
+#define RCC_FINDIV46CFGR_FINDIV46_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV46CFGR_FINDIV46_SHIFT		0
+#define RCC_FINDIV46CFGR_FINDIV46EN		BIT(6)
+
+/* RCC_FINDIV47CFGR register fields */
+#define RCC_FINDIV47CFGR_FINDIV47_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV47CFGR_FINDIV47_SHIFT		0
+#define RCC_FINDIV47CFGR_FINDIV47EN		BIT(6)
+
+/* RCC_FINDIV48CFGR register fields */
+#define RCC_FINDIV48CFGR_FINDIV48_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV48CFGR_FINDIV48_SHIFT		0
+#define RCC_FINDIV48CFGR_FINDIV48EN		BIT(6)
+
+/* RCC_FINDIV49CFGR register fields */
+#define RCC_FINDIV49CFGR_FINDIV49_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV49CFGR_FINDIV49_SHIFT		0
+#define RCC_FINDIV49CFGR_FINDIV49EN		BIT(6)
+
+/* RCC_FINDIV50CFGR register fields */
+#define RCC_FINDIV50CFGR_FINDIV50_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV50CFGR_FINDIV50_SHIFT		0
+#define RCC_FINDIV50CFGR_FINDIV50EN		BIT(6)
+
+/* RCC_FINDIV51CFGR register fields */
+#define RCC_FINDIV51CFGR_FINDIV51_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV51CFGR_FINDIV51_SHIFT		0
+#define RCC_FINDIV51CFGR_FINDIV51EN		BIT(6)
+
+/* RCC_FINDIV52CFGR register fields */
+#define RCC_FINDIV52CFGR_FINDIV52_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV52CFGR_FINDIV52_SHIFT		0
+#define RCC_FINDIV52CFGR_FINDIV52EN		BIT(6)
+
+/* RCC_FINDIV53CFGR register fields */
+#define RCC_FINDIV53CFGR_FINDIV53_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV53CFGR_FINDIV53_SHIFT		0
+#define RCC_FINDIV53CFGR_FINDIV53EN		BIT(6)
+
+/* RCC_FINDIV54CFGR register fields */
+#define RCC_FINDIV54CFGR_FINDIV54_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV54CFGR_FINDIV54_SHIFT		0
+#define RCC_FINDIV54CFGR_FINDIV54EN		BIT(6)
+
+/* RCC_FINDIV55CFGR register fields */
+#define RCC_FINDIV55CFGR_FINDIV55_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV55CFGR_FINDIV55_SHIFT		0
+#define RCC_FINDIV55CFGR_FINDIV55EN		BIT(6)
+
+/* RCC_FINDIV56CFGR register fields */
+#define RCC_FINDIV56CFGR_FINDIV56_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV56CFGR_FINDIV56_SHIFT		0
+#define RCC_FINDIV56CFGR_FINDIV56EN		BIT(6)
+
+/* RCC_FINDIV57CFGR register fields */
+#define RCC_FINDIV57CFGR_FINDIV57_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV57CFGR_FINDIV57_SHIFT		0
+#define RCC_FINDIV57CFGR_FINDIV57EN		BIT(6)
+
+/* RCC_FINDIV58CFGR register fields */
+#define RCC_FINDIV58CFGR_FINDIV58_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV58CFGR_FINDIV58_SHIFT		0
+#define RCC_FINDIV58CFGR_FINDIV58EN		BIT(6)
+
+/* RCC_FINDIV59CFGR register fields */
+#define RCC_FINDIV59CFGR_FINDIV59_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV59CFGR_FINDIV59_SHIFT		0
+#define RCC_FINDIV59CFGR_FINDIV59EN		BIT(6)
+
+/* RCC_FINDIV60CFGR register fields */
+#define RCC_FINDIV60CFGR_FINDIV60_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV60CFGR_FINDIV60_SHIFT		0
+#define RCC_FINDIV60CFGR_FINDIV60EN		BIT(6)
+
+/* RCC_FINDIV61CFGR register fields */
+#define RCC_FINDIV61CFGR_FINDIV61_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV61CFGR_FINDIV61_SHIFT		0
+#define RCC_FINDIV61CFGR_FINDIV61EN		BIT(6)
+
+/* RCC_FINDIV62CFGR register fields */
+#define RCC_FINDIV62CFGR_FINDIV62_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV62CFGR_FINDIV62_SHIFT		0
+#define RCC_FINDIV62CFGR_FINDIV62EN		BIT(6)
+
+/* RCC_FINDIV63CFGR register fields */
+#define RCC_FINDIV63CFGR_FINDIV63_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIV63CFGR_FINDIV63_SHIFT		0
+#define RCC_FINDIV63CFGR_FINDIV63EN		BIT(6)
+
+/* RCC_FINDIVxCFGR register fields */
+#define RCC_FINDIVxCFGR_FINDIVx_MASK		GENMASK_32(5, 0)
+#define RCC_FINDIVxCFGR_FINDIVx_SHIFT		0
+#define RCC_FINDIVxCFGR_FINDIVxEN		BIT(6)
+
+/* RCC_FCALCOBS0CFGR register fields */
+#define RCC_FCALCOBS0CFGR_CKINTSEL_MASK		GENMASK_32(7, 0)
+#define RCC_FCALCOBS0CFGR_CKINTSEL_SHIFT	0
+#define RCC_FCALCOBS0CFGR_CKEXTSEL_MASK		GENMASK_32(10, 8)
+#define RCC_FCALCOBS0CFGR_CKEXTSEL_SHIFT	8
+#define RCC_FCALCOBS0CFGR_FCALCCKEXTSEL		BIT(15)
+#define RCC_FCALCOBS0CFGR_CKOBSEXTSEL		BIT(16)
+#define RCC_FCALCOBS0CFGR_FCALCCKINV		BIT(17)
+#define RCC_FCALCOBS0CFGR_CKOBSINV		BIT(18)
+#define RCC_FCALCOBS0CFGR_CKOBSDIV_MASK		GENMASK_32(24, 22)
+#define RCC_FCALCOBS0CFGR_CKOBSDIV_SHIFT	22
+#define RCC_FCALCOBS0CFGR_FCALCCKEN		BIT(25)
+#define RCC_FCALCOBS0CFGR_CKOBSEN		BIT(26)
+
+/* RCC_FCALCOBS1CFGR register fields */
+#define RCC_FCALCOBS1CFGR_CKINTSEL_MASK		GENMASK_32(7, 0)
+#define RCC_FCALCOBS1CFGR_CKINTSEL_SHIFT	0
+#define RCC_FCALCOBS1CFGR_CKEXTSEL_MASK		GENMASK_32(10, 8)
+#define RCC_FCALCOBS1CFGR_CKEXTSEL_SHIFT	8
+#define RCC_FCALCOBS1CFGR_CKOBSEXTSEL		BIT(16)
+#define RCC_FCALCOBS1CFGR_CKOBSINV		BIT(18)
+#define RCC_FCALCOBS1CFGR_CKOBSDIV_MASK		GENMASK_32(24, 22)
+#define RCC_FCALCOBS1CFGR_CKOBSDIV_SHIFT	22
+#define RCC_FCALCOBS1CFGR_CKOBSEN		BIT(26)
+#define RCC_FCALCOBS1CFGR_FCALCRSTN		BIT(27)
+
+/* RCC_FCALCREFCFGR register fields */
+#define RCC_FCALCREFCFGR_FCALCREFCKSEL_MASK	GENMASK_32(2, 0)
+#define RCC_FCALCREFCFGR_FCALCREFCKSEL_SHIFT	0
+
+/* RCC_FCALCCR1 register fields */
+#define RCC_FCALCCR1_FCALCRUN			BIT(0)
+
+/* RCC_FCALCCR2 register fields */
+#define RCC_FCALCCR2_FCALCMD_MASK		GENMASK_32(4, 3)
+#define RCC_FCALCCR2_FCALCMD_SHIFT		3
+#define RCC_FCALCCR2_FCALCTWC_MASK		GENMASK_32(14, 11)
+#define RCC_FCALCCR2_FCALCTWC_SHIFT		11
+#define RCC_FCALCCR2_FCALCTYP_MASK		GENMASK_32(21, 17)
+#define RCC_FCALCCR2_FCALCTYP_SHIFT		17
+
+/* RCC_FCALCSR register fields */
+#define RCC_FCALCSR_FVAL_MASK			GENMASK_32(16, 0)
+#define RCC_FCALCSR_FVAL_SHIFT			0
+#define RCC_FCALCSR_FCALCSTS			BIT(19)
+
+/* RCC_PLL4CFGR1 register fields */
+#define RCC_PLL4CFGR1_SSMODRST			BIT(0)
+#define RCC_PLL4CFGR1_PLLEN			BIT(8)
+#define RCC_PLL4CFGR1_PLLRDY			BIT(24)
+#define RCC_PLL4CFGR1_CKREFST			BIT(28)
+
+/* RCC_PLL4CFGR2 register fields */
+#define RCC_PLL4CFGR2_FREFDIV_MASK		GENMASK_32(5, 0)
+#define RCC_PLL4CFGR2_FREFDIV_SHIFT		0
+#define RCC_PLL4CFGR2_FBDIV_MASK		GENMASK_32(27, 16)
+#define RCC_PLL4CFGR2_FBDIV_SHIFT		16
+
+/* RCC_PLL4CFGR3 register fields */
+#define RCC_PLL4CFGR3_FRACIN_MASK		GENMASK_32(23, 0)
+#define RCC_PLL4CFGR3_FRACIN_SHIFT		0
+#define RCC_PLL4CFGR3_DOWNSPREAD		BIT(24)
+#define RCC_PLL4CFGR3_DACEN			BIT(25)
+#define RCC_PLL4CFGR3_SSCGDIS			BIT(26)
+
+/* RCC_PLL4CFGR4 register fields */
+#define RCC_PLL4CFGR4_DSMEN			BIT(8)
+#define RCC_PLL4CFGR4_FOUTPOSTDIVEN		BIT(9)
+#define RCC_PLL4CFGR4_BYPASS			BIT(10)
+
+/* RCC_PLL4CFGR5 register fields */
+#define RCC_PLL4CFGR5_DIVVAL_MASK		GENMASK_32(3, 0)
+#define RCC_PLL4CFGR5_DIVVAL_SHIFT		0
+#define RCC_PLL4CFGR5_SPREAD_MASK		GENMASK_32(20, 16)
+#define RCC_PLL4CFGR5_SPREAD_SHIFT		16
+
+/* RCC_PLL4CFGR6 register fields */
+#define RCC_PLL4CFGR6_POSTDIV1_MASK		GENMASK_32(2, 0)
+#define RCC_PLL4CFGR6_POSTDIV1_SHIFT		0
+
+/* RCC_PLL4CFGR7 register fields */
+#define RCC_PLL4CFGR7_POSTDIV2_MASK		GENMASK_32(2, 0)
+#define RCC_PLL4CFGR7_POSTDIV2_SHIFT		0
+
+/* RCC_PLL5CFGR1 register fields */
+#define RCC_PLL5CFGR1_SSMODRST			BIT(0)
+#define RCC_PLL5CFGR1_PLLEN			BIT(8)
+#define RCC_PLL5CFGR1_PLLRDY			BIT(24)
+#define RCC_PLL5CFGR1_CKREFST			BIT(28)
+
+/* RCC_PLL5CFGR2 register fields */
+#define RCC_PLL5CFGR2_FREFDIV_MASK		GENMASK_32(5, 0)
+#define RCC_PLL5CFGR2_FREFDIV_SHIFT		0
+#define RCC_PLL5CFGR2_FBDIV_MASK		GENMASK_32(27, 16)
+#define RCC_PLL5CFGR2_FBDIV_SHIFT		16
+
+/* RCC_PLL5CFGR3 register fields */
+#define RCC_PLL5CFGR3_FRACIN_MASK		GENMASK_32(23, 0)
+#define RCC_PLL5CFGR3_FRACIN_SHIFT		0
+#define RCC_PLL5CFGR3_DOWNSPREAD		BIT(24)
+#define RCC_PLL5CFGR3_DACEN			BIT(25)
+#define RCC_PLL5CFGR3_SSCGDIS			BIT(26)
+
+/* RCC_PLL5CFGR4 register fields */
+#define RCC_PLL5CFGR4_DSMEN			BIT(8)
+#define RCC_PLL5CFGR4_FOUTPOSTDIVEN		BIT(9)
+#define RCC_PLL5CFGR4_BYPASS			BIT(10)
+
+/* RCC_PLL5CFGR5 register fields */
+#define RCC_PLL5CFGR5_DIVVAL_MASK		GENMASK_32(3, 0)
+#define RCC_PLL5CFGR5_DIVVAL_SHIFT		0
+#define RCC_PLL5CFGR5_SPREAD_MASK		GENMASK_32(20, 16)
+#define RCC_PLL5CFGR5_SPREAD_SHIFT		16
+
+/* RCC_PLL5CFGR6 register fields */
+#define RCC_PLL5CFGR6_POSTDIV1_MASK		GENMASK_32(2, 0)
+#define RCC_PLL5CFGR6_POSTDIV1_SHIFT		0
+
+/* RCC_PLL5CFGR7 register fields */
+#define RCC_PLL5CFGR7_POSTDIV2_MASK		GENMASK_32(2, 0)
+#define RCC_PLL5CFGR7_POSTDIV2_SHIFT		0
+
+/* RCC_PLL6CFGR1 register fields */
+#define RCC_PLL6CFGR1_SSMODRST			BIT(0)
+#define RCC_PLL6CFGR1_PLLEN			BIT(8)
+#define RCC_PLL6CFGR1_PLLRDY			BIT(24)
+#define RCC_PLL6CFGR1_CKREFST			BIT(28)
+
+/* RCC_PLL6CFGR2 register fields */
+#define RCC_PLL6CFGR2_FREFDIV_MASK		GENMASK_32(5, 0)
+#define RCC_PLL6CFGR2_FREFDIV_SHIFT		0
+#define RCC_PLL6CFGR2_FBDIV_MASK		GENMASK_32(27, 16)
+#define RCC_PLL6CFGR2_FBDIV_SHIFT		16
+
+/* RCC_PLL6CFGR3 register fields */
+#define RCC_PLL6CFGR3_FRACIN_MASK		GENMASK_32(23, 0)
+#define RCC_PLL6CFGR3_FRACIN_SHIFT		0
+#define RCC_PLL6CFGR3_DOWNSPREAD		BIT(24)
+#define RCC_PLL6CFGR3_DACEN			BIT(25)
+#define RCC_PLL6CFGR3_SSCGDIS			BIT(26)
+
+/* RCC_PLL6CFGR4 register fields */
+#define RCC_PLL6CFGR4_DSMEN			BIT(8)
+#define RCC_PLL6CFGR4_FOUTPOSTDIVEN		BIT(9)
+#define RCC_PLL6CFGR4_BYPASS			BIT(10)
+
+/* RCC_PLL6CFGR5 register fields */
+#define RCC_PLL6CFGR5_DIVVAL_MASK		GENMASK_32(3, 0)
+#define RCC_PLL6CFGR5_DIVVAL_SHIFT		0
+#define RCC_PLL6CFGR5_SPREAD_MASK		GENMASK_32(20, 16)
+#define RCC_PLL6CFGR5_SPREAD_SHIFT		16
+
+/* RCC_PLL6CFGR6 register fields */
+#define RCC_PLL6CFGR6_POSTDIV1_MASK		GENMASK_32(2, 0)
+#define RCC_PLL6CFGR6_POSTDIV1_SHIFT		0
+
+/* RCC_PLL6CFGR7 register fields */
+#define RCC_PLL6CFGR7_POSTDIV2_MASK		GENMASK_32(2, 0)
+#define RCC_PLL6CFGR7_POSTDIV2_SHIFT		0
+
+/* RCC_PLL7CFGR1 register fields */
+#define RCC_PLL7CFGR1_SSMODRST			BIT(0)
+#define RCC_PLL7CFGR1_PLLEN			BIT(8)
+#define RCC_PLL7CFGR1_PLLRDY			BIT(24)
+#define RCC_PLL7CFGR1_CKREFST			BIT(28)
+
+/* RCC_PLL7CFGR2 register fields */
+#define RCC_PLL7CFGR2_FREFDIV_MASK		GENMASK_32(5, 0)
+#define RCC_PLL7CFGR2_FREFDIV_SHIFT		0
+#define RCC_PLL7CFGR2_FBDIV_MASK		GENMASK_32(27, 16)
+#define RCC_PLL7CFGR2_FBDIV_SHIFT		16
+
+/* RCC_PLL7CFGR3 register fields */
+#define RCC_PLL7CFGR3_FRACIN_MASK		GENMASK_32(23, 0)
+#define RCC_PLL7CFGR3_FRACIN_SHIFT		0
+#define RCC_PLL7CFGR3_DOWNSPREAD		BIT(24)
+#define RCC_PLL7CFGR3_DACEN			BIT(25)
+#define RCC_PLL7CFGR3_SSCGDIS			BIT(26)
+
+/* RCC_PLL7CFGR4 register fields */
+#define RCC_PLL7CFGR4_DSMEN			BIT(8)
+#define RCC_PLL7CFGR4_FOUTPOSTDIVEN		BIT(9)
+#define RCC_PLL7CFGR4_BYPASS			BIT(10)
+
+/* RCC_PLL7CFGR5 register fields */
+#define RCC_PLL7CFGR5_DIVVAL_MASK		GENMASK_32(3, 0)
+#define RCC_PLL7CFGR5_DIVVAL_SHIFT		0
+#define RCC_PLL7CFGR5_SPREAD_MASK		GENMASK_32(20, 16)
+#define RCC_PLL7CFGR5_SPREAD_SHIFT		16
+
+/* RCC_PLL7CFGR6 register fields */
+#define RCC_PLL7CFGR6_POSTDIV1_MASK		GENMASK_32(2, 0)
+#define RCC_PLL7CFGR6_POSTDIV1_SHIFT		0
+
+/* RCC_PLL7CFGR7 register fields */
+#define RCC_PLL7CFGR7_POSTDIV2_MASK		GENMASK_32(2, 0)
+#define RCC_PLL7CFGR7_POSTDIV2_SHIFT		0
+
+/* RCC_PLL8CFGR1 register fields */
+#define RCC_PLL8CFGR1_SSMODRST			BIT(0)
+#define RCC_PLL8CFGR1_PLLEN			BIT(8)
+#define RCC_PLL8CFGR1_PLLRDY			BIT(24)
+#define RCC_PLL8CFGR1_CKREFST			BIT(28)
+
+/* RCC_PLL8CFGR2 register fields */
+#define RCC_PLL8CFGR2_FREFDIV_MASK		GENMASK_32(5, 0)
+#define RCC_PLL8CFGR2_FREFDIV_SHIFT		0
+#define RCC_PLL8CFGR2_FBDIV_MASK		GENMASK_32(27, 16)
+#define RCC_PLL8CFGR2_FBDIV_SHIFT		16
+
+/* RCC_PLL8CFGR3 register fields */
+#define RCC_PLL8CFGR3_FRACIN_MASK		GENMASK_32(23, 0)
+#define RCC_PLL8CFGR3_FRACIN_SHIFT		0
+#define RCC_PLL8CFGR3_DOWNSPREAD		BIT(24)
+#define RCC_PLL8CFGR3_DACEN			BIT(25)
+#define RCC_PLL8CFGR3_SSCGDIS			BIT(26)
+
+/* RCC_PLL8CFGR4 register fields */
+#define RCC_PLL8CFGR4_DSMEN			BIT(8)
+#define RCC_PLL8CFGR4_FOUTPOSTDIVEN		BIT(9)
+#define RCC_PLL8CFGR4_BYPASS			BIT(10)
+
+/* RCC_PLL8CFGR5 register fields */
+#define RCC_PLL8CFGR5_DIVVAL_MASK		GENMASK_32(3, 0)
+#define RCC_PLL8CFGR5_DIVVAL_SHIFT		0
+#define RCC_PLL8CFGR5_SPREAD_MASK		GENMASK_32(20, 16)
+#define RCC_PLL8CFGR5_SPREAD_SHIFT		16
+
+/* RCC_PLL8CFGR6 register fields */
+#define RCC_PLL8CFGR6_POSTDIV1_MASK		GENMASK_32(2, 0)
+#define RCC_PLL8CFGR6_POSTDIV1_SHIFT		0
+
+/* RCC_PLL8CFGR7 register fields */
+#define RCC_PLL8CFGR7_POSTDIV2_MASK		GENMASK_32(2, 0)
+#define RCC_PLL8CFGR7_POSTDIV2_SHIFT		0
+
+/* RCC_PLLxCFGR1 register fields */
+#define RCC_PLLxCFGR1_SSMODRST			BIT(0)
+#define RCC_PLLxCFGR1_PLLEN			BIT(8)
+#define RCC_PLLxCFGR1_PLLRDY			BIT(24)
+#define RCC_PLLxCFGR1_CKREFST			BIT(28)
+
+/* RCC_PLLxCFGR2 register fields */
+#define RCC_PLLxCFGR2_FREFDIV_MASK		GENMASK_32(5, 0)
+#define RCC_PLLxCFGR2_FREFDIV_SHIFT		0
+#define RCC_PLLxCFGR2_FBDIV_MASK		GENMASK_32(27, 16)
+#define RCC_PLLxCFGR2_FBDIV_SHIFT		16
+
+/* RCC_PLLxCFGR3 register fields */
+#define RCC_PLLxCFGR3_FRACIN_MASK		GENMASK_32(23, 0)
+#define RCC_PLLxCFGR3_FRACIN_SHIFT		0
+#define RCC_PLLxCFGR3_DOWNSPREAD		BIT(24)
+#define RCC_PLLxCFGR3_DACEN			BIT(25)
+#define RCC_PLLxCFGR3_SSCGDIS			BIT(26)
+
+/* RCC_PLLxCFGR4 register fields */
+#define RCC_PLLxCFGR4_DSMEN			BIT(8)
+#define RCC_PLLxCFGR4_FOUTPOSTDIVEN		BIT(9)
+#define RCC_PLLxCFGR4_BYPASS			BIT(10)
+
+/* RCC_PLLxCFGR5 register fields */
+#define RCC_PLLxCFGR5_DIVVAL_MASK		GENMASK_32(3, 0)
+#define RCC_PLLxCFGR5_DIVVAL_SHIFT		0
+#define RCC_PLLxCFGR5_SPREAD_MASK		GENMASK_32(20, 16)
+#define RCC_PLLxCFGR5_SPREAD_SHIFT		16
+
+/* RCC_PLLxCFGR6 register fields */
+#define RCC_PLLxCFGR6_POSTDIV1_MASK		GENMASK_32(2, 0)
+#define RCC_PLLxCFGR6_POSTDIV1_SHIFT		0
+
+/* RCC_PLLxCFGR7 register fields */
+#define RCC_PLLxCFGR7_POSTDIV2_MASK		GENMASK_32(2, 0)
+#define RCC_PLLxCFGR7_POSTDIV2_SHIFT		0
+
+/* RCC_VERR register fields */
+#define RCC_VERR_MINREV_MASK			GENMASK_32(3, 0)
+#define RCC_VERR_MINREV_SHIFT			0
+#define RCC_VERR_MAJREV_MASK			GENMASK_32(7, 4)
+#define RCC_VERR_MAJREV_SHIFT			4
+
+#endif /* STM32MP21_RCC_H */

diff --git a/include/drivers/st/stm32mp25_rcc.h b/include/drivers/st/stm32mp25_rcc.h
index d5d228c..752d3c3 100644
--- a/include/drivers/st/stm32mp25_rcc.h
+++ b/include/drivers/st/stm32mp25_rcc.h

@@ -2308,6 +2308,12 @@
 #define RCC_C1BOOTRSTSCLRR_D1STBYRSTF		BIT(22)
 #define RCC_C1BOOTRSTSCLRR_D2STBYRSTF		BIT(23)
 
+#define RCC_C1BOOTRSTSCLRR_IWDGXSYSRSTF (RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF | \
+					 RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF | \
+					 RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF | \
+					 RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF | \
+					 RCC_C1BOOTRSTSCLRR_IWDG5SYSRSTF)
+
 /* RCC_C2BOOTRSTSSETR register fields */
 #define RCC_C2BOOTRSTSSETR_PORRSTF		BIT(0)
 #define RCC_C2BOOTRSTSSETR_BORRSTF		BIT(1)

diff --git a/include/drivers/st/stm32mp2_ddr_helpers.h b/include/drivers/st/stm32mp2_ddr_helpers.h
index 9329fff..d9bf7ae 100644
--- a/include/drivers/st/stm32mp2_ddr_helpers.h
+++ b/include/drivers/st/stm32mp2_ddr_helpers.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2024-2025, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -22,7 +22,6 @@
 void ddr_activate_controller(struct stm32mp_ddrctl *ctl, bool sr_entry);
 void ddr_wait_lp3_mode(bool state);
 int ddr_sr_exit_loop(void);
-uint32_t ddr_get_io_calibration_val(void);
 int ddr_sr_entry(bool standby);
 int ddr_sr_exit(void);
 enum stm32mp2_ddr_sr_mode ddr_read_sr_mode(void);

diff --git a/include/drivers/st/stm32mp_ddr.h b/include/drivers/st/stm32mp_ddr.h
index 57b0668..970ff19 100644
--- a/include/drivers/st/stm32mp_ddr.h
+++ b/include/drivers/st/stm32mp_ddr.h

@@ -28,7 +28,7 @@
 struct stm32mp_ddr_reg_desc {
 	uint16_t offset;	/* Offset for base address */
 	uint8_t par_offset;	/* Offset for parameter array */
-#if !STM32MP13 && !STM32MP15
+#ifdef STM32MP2X
 	bool qd; /* quasi-dynamic register if true */
 #endif
 };

diff --git a/include/dt-bindings/clock/st,stm32mp21-rcc.h b/include/dt-bindings/clock/st,stm32mp21-rcc.h
new file mode 100644
index 0000000..f23c536
--- /dev/null
+++ b/include/dt-bindings/clock/st,stm32mp21-rcc.h

@@ -0,0 +1,429 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
+ * Author(s): Gabriel Fernandez <gabriel.fernandez@foss.st.com>
+ */
+
+#ifndef _DT_BINDINGS_STM32MP21_CLKS_H_
+#define _DT_BINDINGS_STM32MP21_CLKS_H_
+
+/* INTERNAL/EXTERNAL OSCILLATORS */
+#define HSI_CK			0
+#define HSE_CK			1
+#define MSI_CK			2
+#define LSI_CK			3
+#define LSE_CK			4
+#define I2S_CK			5
+#define RTC_CK			6
+#define SPDIF_CK_SYMB		7
+
+/* PLL CLOCKS */
+#define PLL1_CK			8
+#define PLL2_CK			9
+#define PLL4_CK			10
+#define PLL5_CK			11
+#define PLL6_CK			12
+#define PLL7_CK			13
+#define PLL8_CK			14
+
+#define CK_CPU1			15
+
+/* APB DIV CLOCKS */
+#define CK_ICN_APB1		16
+#define CK_ICN_APB2		17
+#define CK_ICN_APB3		18
+#define CK_ICN_APB4		19
+#define CK_ICN_APB5		20
+#define CK_ICN_APBDBG		21
+
+/* GLOBAL TIMER */
+#define TIMG1_CK		22
+#define TIMG2_CK		23
+
+/* FLEXGEN CLOCKS */
+#define CK_ICN_HS_MCU		24
+#define CK_ICN_SDMMC		25
+#define CK_ICN_DDR		26
+#define CK_ICN_DISPLAY		27
+#define CK_ICN_HSL		28
+#define CK_ICN_NIC		29
+#define CK_ICN_VID		30
+#define CK_FLEXGEN_07		31
+#define CK_FLEXGEN_08		32
+#define CK_FLEXGEN_09		33
+#define CK_FLEXGEN_10		34
+#define CK_FLEXGEN_11		35
+#define CK_FLEXGEN_12		36
+#define CK_FLEXGEN_13		37
+#define CK_FLEXGEN_14		38
+#define CK_FLEXGEN_15		39
+#define CK_FLEXGEN_16		40
+#define CK_FLEXGEN_17		41
+#define CK_FLEXGEN_18		42
+#define CK_FLEXGEN_19		43
+#define CK_FLEXGEN_20		44
+#define CK_FLEXGEN_21		45
+#define CK_FLEXGEN_22		46
+#define CK_FLEXGEN_23		47
+#define CK_FLEXGEN_24		48
+#define CK_FLEXGEN_25		49
+#define CK_FLEXGEN_26		50
+#define CK_FLEXGEN_27		51
+#define CK_FLEXGEN_28		52
+#define CK_FLEXGEN_29		53
+#define CK_FLEXGEN_30		54
+#define CK_FLEXGEN_31		55
+#define CK_FLEXGEN_32		56
+#define CK_FLEXGEN_33		57
+#define CK_FLEXGEN_34		58
+#define CK_FLEXGEN_35		59
+#define CK_FLEXGEN_36		60
+#define CK_FLEXGEN_37		61
+#define CK_FLEXGEN_38		62
+#define CK_FLEXGEN_39		63
+#define CK_FLEXGEN_40		64
+#define CK_FLEXGEN_41		65
+#define CK_FLEXGEN_42		66
+#define CK_FLEXGEN_43		67
+#define CK_FLEXGEN_44		68
+#define CK_FLEXGEN_45		69
+#define CK_FLEXGEN_46		70
+#define CK_FLEXGEN_47		71
+#define CK_FLEXGEN_48		72
+#define CK_FLEXGEN_49		73
+#define CK_FLEXGEN_50		74
+#define CK_FLEXGEN_51		75
+#define CK_FLEXGEN_52		76
+#define CK_FLEXGEN_53		77
+#define CK_FLEXGEN_54		78
+#define CK_FLEXGEN_55		79
+#define CK_FLEXGEN_56		80
+#define CK_FLEXGEN_57		81
+#define CK_FLEXGEN_58		82
+#define CK_FLEXGEN_59		83
+#define CK_FLEXGEN_60		84
+#define CK_FLEXGEN_61		85
+#define CK_FLEXGEN_62		86
+#define CK_FLEXGEN_63		87
+
+/* LOW SPEED MCU CLOCK */
+#define CK_ICN_LS_MCU		88
+
+#define CK_BUS_STM		89
+#define CK_BUS_FMC		90
+#define CK_BUS_ETH1		91
+#define CK_BUS_ETH2		92
+#define CK_BUS_DDRPHYC		93
+#define CK_BUS_SYSCPU1		94
+#define CK_BUS_HPDMA1		95
+#define CK_BUS_HPDMA2		96
+#define CK_BUS_HPDMA3		97
+#define CK_BUS_ADC1		98
+#define CK_BUS_ADC2		99
+#define CK_BUS_IPCC1		100
+#define CK_BUS_DCMIPSSI		101
+#define CK_BUS_CRC		102
+#define CK_BUS_MDF1		103
+#define CK_BUS_BKPSRAM		104
+#define CK_BUS_HASH1		105
+#define CK_BUS_HASH2		106
+#define CK_BUS_RNG1		107
+#define CK_BUS_RNG2		108
+#define CK_BUS_CRYP1		109
+#define CK_BUS_CRYP2		110
+#define CK_BUS_SAES		111
+#define CK_BUS_PKA		112
+#define CK_BUS_GPIOA		113
+#define CK_BUS_GPIOB		114
+#define CK_BUS_GPIOC		115
+#define CK_BUS_GPIOD		116
+#define CK_BUS_GPIOE		117
+#define CK_BUS_GPIOF		118
+#define CK_BUS_GPIOG		119
+#define CK_BUS_GPIOH		120
+#define CK_BUS_GPIOI		121
+#define CK_BUS_GPIOZ		122
+#define CK_BUS_RTC		124
+#define CK_BUS_LPUART1		125
+#define CK_BUS_LPTIM3		126
+#define CK_BUS_LPTIM4		127
+#define CK_BUS_LPTIM5		128
+#define CK_BUS_TIM2		129
+#define CK_BUS_TIM3		130
+#define CK_BUS_TIM4		131
+#define CK_BUS_TIM5		132
+#define CK_BUS_TIM6		133
+#define CK_BUS_TIM7		134
+#define CK_BUS_TIM10		135
+#define CK_BUS_TIM11		136
+#define CK_BUS_TIM12		137
+#define CK_BUS_TIM13		138
+#define CK_BUS_TIM14		139
+#define CK_BUS_LPTIM1		140
+#define CK_BUS_LPTIM2		141
+#define CK_BUS_SPI2		142
+#define CK_BUS_SPI3		143
+#define CK_BUS_SPDIFRX		144
+#define CK_BUS_USART2		145
+#define CK_BUS_USART3		146
+#define CK_BUS_UART4		147
+#define CK_BUS_UART5		148
+#define CK_BUS_I2C1		149
+#define CK_BUS_I2C2		150
+#define CK_BUS_I2C3		151
+#define CK_BUS_I3C1		152
+#define CK_BUS_I3C2		153
+#define CK_BUS_I3C3		154
+#define CK_BUS_TIM1		155
+#define CK_BUS_TIM8		156
+#define CK_BUS_TIM15		157
+#define CK_BUS_TIM16		158
+#define CK_BUS_TIM17		159
+#define CK_BUS_SAI1		160
+#define CK_BUS_SAI2		161
+#define CK_BUS_SAI3		162
+#define CK_BUS_SAI4		163
+#define CK_BUS_USART1		164
+#define CK_BUS_USART6		165
+#define CK_BUS_UART7		166
+#define CK_BUS_FDCAN		167
+#define CK_BUS_SPI1		168
+#define CK_BUS_SPI4		169
+#define CK_BUS_SPI5		170
+#define CK_BUS_SPI6		171
+#define CK_BUS_BSEC		172
+#define CK_BUS_IWDG1		173
+#define CK_BUS_IWDG2		174
+#define CK_BUS_IWDG3		175
+#define CK_BUS_IWDG4		176
+#define CK_BUS_WWDG1		177
+#define CK_BUS_VREF		178
+#define CK_BUS_DTS		179
+#define CK_BUS_SERC		180
+#define CK_BUS_HDP		181
+#define CK_BUS_DDRPERFM		182
+#define CK_BUS_OTG		183
+#define CK_BUS_LTDC		184
+#define CK_BUS_CSI		185
+#define CK_BUS_DCMIPP		186
+#define CK_BUS_DDRC		187
+#define CK_BUS_DDRCFG		188
+#define CK_BUS_STGEN		189
+#define CK_SYSDBG		190
+#define CK_KER_TIM2		191
+#define CK_KER_TIM3		192
+#define CK_KER_TIM4		193
+#define CK_KER_TIM5		194
+#define CK_KER_TIM6		195
+#define CK_KER_TIM7		196
+#define CK_KER_TIM10		197
+#define CK_KER_TIM11		198
+#define CK_KER_TIM12		199
+#define CK_KER_TIM13		200
+#define CK_KER_TIM14		201
+#define CK_KER_TIM1		202
+#define CK_KER_TIM8		203
+#define CK_KER_TIM15		204
+#define CK_KER_TIM16		205
+#define CK_KER_TIM17		206
+#define CK_BUS_SYSRAM		207
+#define CK_BUS_RETRAM		208
+#define CK_BUS_OSPI1		209
+#define CK_BUS_OTFD1		210
+#define CK_BUS_SRAM1		211
+#define CK_BUS_SDMMC1		212
+#define CK_BUS_SDMMC2		213
+#define CK_BUS_SDMMC3		214
+#define CK_BUS_DDR		215
+#define CK_BUS_RISAF4		216
+#define CK_BUS_USBHOHCI		217
+#define CK_BUS_USBHEHCI		218
+#define CK_KER_LPTIM1		219
+#define CK_KER_LPTIM2		220
+#define CK_KER_USART2		221
+#define CK_KER_UART4		222
+#define CK_KER_USART3		223
+#define CK_KER_UART5		224
+#define CK_KER_SPI2		225
+#define CK_KER_SPI3		226
+#define CK_KER_SPDIFRX		227
+#define CK_KER_I2C1		228
+#define CK_KER_I2C2		229
+#define CK_KER_I3C1		230
+#define CK_KER_I3C2		231
+#define CK_KER_I2C3		232
+#define CK_KER_I3C3		233
+#define CK_KER_SPI1		234
+#define CK_KER_SPI4		235
+#define CK_KER_SPI5		236
+#define CK_KER_SPI6		237
+#define CK_KER_USART1		238
+#define CK_KER_USART6		239
+#define CK_KER_UART7		240
+#define CK_KER_MDF1		241
+#define CK_KER_SAI1		242
+#define CK_KER_SAI2		243
+#define CK_KER_SAI3		244
+#define CK_KER_SAI4		245
+#define CK_KER_FDCAN		246
+#define CK_KER_CSI		247
+#define CK_KER_CSITXESC		248
+#define CK_KER_CSIPHY		249
+#define CK_KER_STGEN		250
+#define CK_KER_USB2PHY2EN	251
+#define CK_KER_LPUART1		252
+#define CK_KER_LPTIM3		253
+#define CK_KER_LPTIM4		254
+#define CK_KER_LPTIM5		255
+#define CK_KER_TSDBG		256
+#define CK_KER_TPIU		257
+#define CK_BUS_ETR		258
+#define CK_BUS_SYSATB		259
+#define CK_KER_ADC1		260
+#define CK_KER_ADC2		261
+#define CK_KER_OSPI1		262
+#define CK_KER_FMC		263
+#define CK_KER_SDMMC1		264
+#define CK_KER_SDMMC2		265
+#define CK_KER_SDMMC3		266
+#define CK_KER_ETH1		267
+#define CK_KER_ETH2		268
+#define CK_KER_ETH1PTP		269
+#define CK_KER_ETH2PTP		270
+#define CK_KER_USB2PHY1		271
+#define CK_KER_USB2PHY2		272
+#define CK_MCO1			273
+#define CK_MCO2			274
+#define CK_KER_DTS		275
+#define CK_ETH1_RX		276
+#define CK_ETH1_TX		277
+#define CK_ETH1_MAC		278
+#define CK_ETH2_RX		279
+#define CK_ETH2_TX		280
+#define CK_ETH2_MAC		281
+#define CK_ETH1_STP		282
+#define CK_ETH2_STP		283
+#define CK_KER_LTDC		284
+#define HSE_DIV2_CK		285
+#define CK_DBGMCU		286
+#define CK_DAP			287
+#define CK_KER_ETR		288
+#define CK_KER_STM		289
+
+#define STM32MP21_LAST_CLK	290
+
+#define CK_SCMI_ICN_HS_MCU	0
+#define CK_SCMI_ICN_SDMMC	1
+#define CK_SCMI_ICN_DDR		2
+#define CK_SCMI_ICN_DISPLAY	3
+#define CK_SCMI_ICN_HSL		4
+#define CK_SCMI_ICN_NIC		5
+#define CK_SCMI_ICN_VID		6
+#define CK_SCMI_FLEXGEN_07	7
+#define CK_SCMI_FLEXGEN_08	8
+#define CK_SCMI_FLEXGEN_09	9
+#define CK_SCMI_FLEXGEN_10	10
+#define CK_SCMI_FLEXGEN_11	11
+#define CK_SCMI_FLEXGEN_12	12
+#define CK_SCMI_FLEXGEN_13	13
+#define CK_SCMI_FLEXGEN_14	14
+#define CK_SCMI_FLEXGEN_15	15
+#define CK_SCMI_FLEXGEN_16	16
+#define CK_SCMI_FLEXGEN_17	17
+#define CK_SCMI_FLEXGEN_18	18
+#define CK_SCMI_FLEXGEN_19	19
+#define CK_SCMI_FLEXGEN_20	20
+#define CK_SCMI_FLEXGEN_21	21
+#define CK_SCMI_FLEXGEN_22	22
+#define CK_SCMI_FLEXGEN_23	23
+#define CK_SCMI_FLEXGEN_24	24
+#define CK_SCMI_FLEXGEN_25	25
+#define CK_SCMI_FLEXGEN_26	26
+#define CK_SCMI_FLEXGEN_27	27
+#define CK_SCMI_FLEXGEN_28	28
+#define CK_SCMI_FLEXGEN_29	29
+#define CK_SCMI_FLEXGEN_30	30
+#define CK_SCMI_FLEXGEN_31	31
+#define CK_SCMI_FLEXGEN_32	32
+#define CK_SCMI_FLEXGEN_33	33
+#define CK_SCMI_FLEXGEN_34	34
+#define CK_SCMI_FLEXGEN_35	35
+#define CK_SCMI_FLEXGEN_36	36
+#define CK_SCMI_FLEXGEN_37	37
+#define CK_SCMI_FLEXGEN_38	38
+#define CK_SCMI_FLEXGEN_39	39
+#define CK_SCMI_FLEXGEN_40	40
+#define CK_SCMI_FLEXGEN_41	41
+#define CK_SCMI_FLEXGEN_42	42
+#define CK_SCMI_FLEXGEN_43	43
+#define CK_SCMI_FLEXGEN_44	44
+#define CK_SCMI_FLEXGEN_45	45
+#define CK_SCMI_FLEXGEN_46	46
+#define CK_SCMI_FLEXGEN_47	47
+#define CK_SCMI_FLEXGEN_48	48
+#define CK_SCMI_FLEXGEN_49	49
+#define CK_SCMI_FLEXGEN_50	50
+#define CK_SCMI_FLEXGEN_51	51
+#define CK_SCMI_FLEXGEN_52	52
+#define CK_SCMI_FLEXGEN_53	53
+#define CK_SCMI_FLEXGEN_54	54
+#define CK_SCMI_FLEXGEN_55	55
+#define CK_SCMI_FLEXGEN_56	56
+#define CK_SCMI_FLEXGEN_57	57
+#define CK_SCMI_FLEXGEN_58	58
+#define CK_SCMI_FLEXGEN_59	59
+#define CK_SCMI_FLEXGEN_60	60
+#define CK_SCMI_FLEXGEN_61	61
+#define CK_SCMI_FLEXGEN_62	62
+#define CK_SCMI_FLEXGEN_63	63
+#define CK_SCMI_ICN_LS_MCU	64
+#define CK_SCMI_HSE		65
+#define CK_SCMI_LSE		66
+#define CK_SCMI_HSI		67
+#define CK_SCMI_LSI		68
+#define CK_SCMI_MSI		69
+#define CK_SCMI_HSE_DIV2	70
+#define CK_SCMI_CPU1		71
+#define CK_SCMI_SYSCPU1		72
+#define CK_SCMI_PLL2		73
+#define CK_SCMI_RTC		74
+#define CK_SCMI_RTCCK		75
+#define CK_SCMI_ICN_APB1	76
+#define CK_SCMI_ICN_APB2	77
+#define CK_SCMI_ICN_APB3	78
+#define CK_SCMI_ICN_APB4	79
+#define CK_SCMI_ICN_APB5	80
+#define CK_SCMI_ICN_APBDBG	81
+#define CK_SCMI_TIMG1		82
+#define CK_SCMI_TIMG2		83
+#define CK_SCMI_BKPSRAM		84
+#define CK_SCMI_BSEC		85
+#define CK_SCMI_BUS_ETR		86
+#define CK_SCMI_FMC		87
+#define CK_SCMI_GPIOA		88
+#define CK_SCMI_GPIOB		89
+#define CK_SCMI_GPIOC		90
+#define CK_SCMI_GPIOD		91
+#define CK_SCMI_GPIOE		92
+#define CK_SCMI_GPIOF		93
+#define CK_SCMI_GPIOG		94
+#define CK_SCMI_GPIOH		95
+#define CK_SCMI_GPIOI		96
+#define CK_SCMI_GPIOZ		97
+#define CK_SCMI_HPDMA1		98
+#define CK_SCMI_HPDMA2		99
+#define CK_SCMI_HPDMA3		100
+#define CK_SCMI_IPCC1		101
+#define CK_SCMI_RETRAM		102
+#define CK_SCMI_SRAM1		103
+#define CK_SCMI_SYSRAM		104
+#define CK_SCMI_OSPI1		105
+#define CK_SCMI_TPIU		106
+#define CK_SCMI_SYSDBG		107
+#define CK_SCMI_SYSATB		108
+#define CK_SCMI_TSDBG		109
+#define CK_SCMI_BUS_STM		110
+#define CK_SCMI_KER_STM		111
+#define CK_SCMI_KER_ETR		112
+
+#endif /* _DT_BINDINGS_STM32MP21_CLKS_H_ */

diff --git a/include/dt-bindings/clock/stm32mp21-clksrc.h b/include/dt-bindings/clock/stm32mp21-clksrc.h
new file mode 100644
index 0000000..560ca0a
--- /dev/null
+++ b/include/dt-bindings/clock/stm32mp21-clksrc.h

@@ -0,0 +1,206 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
+/*
+ * Copyright (C) 2025, STMicroelectronics - All Rights Reserved
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_STM32MP21_CLKSRC_H_
+#define _DT_BINDINGS_CLOCK_STM32MP21_CLKSRC_H_
+
+#define CMD_DIV		0
+#define CMD_MUX		1
+#define CMD_CLK		2
+#define CMD_FLEXGEN	3
+
+#define CMD_ADDR_BIT	0x80000000
+
+#define CMD_SHIFT	26
+#define CMD_MASK	0xFC000000
+#define CMD_DATA_MASK	0x03FFFFFF
+
+#define DIV_ID_SHIFT	8
+#define DIV_ID_MASK	0x0000FF00
+
+#define DIV_DIVN_SHIFT	0
+#define DIV_DIVN_MASK	0x000000FF
+
+#define MUX_ID_SHIFT	4
+#define MUX_ID_MASK	0x00000FF0
+
+#define MUX_SEL_SHIFT	0
+#define MUX_SEL_MASK	0x0000000F
+
+/* CLK define */
+#define CLK_ON_MASK	BIT(21)
+#define CLK_ON_SHIFT	21
+
+#define CLK_ID_MASK	GENMASK_32(20, 12)
+#define CLK_ID_SHIFT	12
+
+#define CLK_NO_DIV_MASK	0x0000080
+#define CLK_DIV_MASK	GENMASK_32(10, 5)
+#define CLK_DIV_SHIFT	5
+
+#define CLK_NO_SEL_MASK	0x00000010
+#define CLK_SEL_MASK	GENMASK_32(3, 0)
+#define CLK_SEL_SHIFT	0
+
+#define CLK_CFG(clk_id, sel, div, state)	((CMD_CLK << CMD_SHIFT) |\
+						 ((state) << CLK_ON_SHIFT) |\
+						 ((clk_id) << CLK_ID_SHIFT) |\
+						 ((div) << CLK_DIV_SHIFT) |\
+						 ((sel) << CLK_SEL_SHIFT))
+
+#define CLK_OFF		0
+#define CLK_ON		1
+#define CLK_NODIV	0x00000040
+#define CLK_NOMUX	0x00000010
+
+/* Flexgen define */
+#define FLEX_ID_SHIFT	20
+#define FLEX_SEL_SHIFT	16
+#define FLEX_PDIV_SHIFT	6
+#define FLEX_FDIV_SHIFT	0
+
+#define FLEX_ID_MASK	GENMASK_32(25, 20)
+#define FLEX_SEL_MASK	GENMASK_32(19, 16)
+#define FLEX_PDIV_MASK	GENMASK_32(15, 6)
+#define FLEX_FDIV_MASK	GENMASK_32(5, 0)
+
+#define DIV_CFG(div_id, div)	((CMD_DIV << CMD_SHIFT) |\
+				 ((div_id) << DIV_ID_SHIFT |\
+				 (div)))
+
+#define MUX_CFG(mux_id, sel)	((CMD_MUX << CMD_SHIFT) |\
+				 ((mux_id) << MUX_ID_SHIFT |\
+				 (sel)))
+
+#define CLK_ADDR_SHIFT		16
+#define CLK_ADDR_MASK		0x7FFF0000
+#define CLK_ADDR_VAL_MASK	0xFFFF
+
+#define DIV_LSMCU	0
+#define DIV_APB1	1
+#define DIV_APB2	2
+#define DIV_APB3	3
+#define DIV_APB4	4
+#define DIV_APB5	5
+#define DIV_APBDBG	6
+#define DIV_RTC		7
+#define DIV_NB		8
+
+#define MUX_MUXSEL0	0
+#define MUX_MUXSEL1	1
+#define MUX_MUXSEL2	2
+#define MUX_MUXSEL3	3
+#define MUX_MUXSEL4	4
+#define MUX_MUXSEL5	5
+#define MUX_MUXSEL6	6
+#define MUX_MUXSEL7	7
+#define MUX_XBARSEL	8
+#define MUX_RTC		9
+#define MUX_MCO1	10
+#define MUX_MCO2	11
+#define MUX_ADC1	12
+#define MUX_ADC2	13
+#define MUX_USB2PHY1	14
+#define MUX_USB2PHY2	15
+#define MUX_DTS		16
+#define MUX_CPU1	17
+#define MUX_NB		18
+
+#define MUXSEL_HSI		0
+#define MUXSEL_HSE		1
+#define MUXSEL_MSI		2
+
+/* KERNEL source clocks */
+#define MUX_RTC_DISABLED	0x0
+#define MUX_RTC_LSE		0x1
+#define MUX_RTC_LSI		0x2
+#define MUX_RTC_HSE		0x3
+
+#define MUX_MCO1_FLEX61		0x0
+#define MUX_MCO1_OBSER0		0x1
+
+#define MUX_MCO2_FLEX62		0x0
+#define MUX_MCO2_OBSER1		0x1
+
+#define MUX_ADC1_FLEX46		0x0
+#define MUX_ADC1_LSMCU		0x1
+
+#define MUX_ADC2_FLEX47		0x0
+#define MUX_ADC2_LSMCU		0x1
+#define MUX_ADC2_FLEX46		0x2
+
+#define MUX_USB2PHY1_FLEX57	0x0
+#define MUX_USB2PHY1_HSE	0x1
+
+#define MUX_USB2PHY2_FLEX58	0x0
+#define MUX_USB2PHY2_HSE	0x1
+
+#define MUX_DTS_HSI		0x0
+#define MUX_DTS_HSE		0x1
+#define MUX_DTS_MSI		0x2
+
+/* PLLs source clocks */
+#define PLL_SRC_HSI		0x0
+#define PLL_SRC_HSE		0x1
+#define PLL_SRC_MSI		0x2
+#define PLL_SRC_DISABLED	0x3
+
+/* XBAR source clocks */
+#define XBAR_SRC_PLL4		0x0
+#define XBAR_SRC_PLL5		0x1
+#define XBAR_SRC_PLL6		0x2
+#define XBAR_SRC_PLL7		0x3
+#define XBAR_SRC_PLL8		0x4
+#define XBAR_SRC_HSI		0x5
+#define XBAR_SRC_HSE		0x6
+#define XBAR_SRC_MSI		0x7
+#define XBAR_SRC_HSI_KER	0x8
+#define XBAR_SRC_HSE_KER	0x9
+#define XBAR_SRC_MSI_KER	0xA
+#define XBAR_SRC_SPDIF_SYMB	0xB
+#define XBAR_SRC_I2S		0xC
+#define XBAR_SRC_LSI		0xD
+#define XBAR_SRC_LSE		0xE
+
+/*
+ * Configure a XBAR channel with its clock source
+ * channel_nb: XBAR channel number from 0 to 63
+ * channel_src: one of the 15 previous XBAR source clocks defines
+ * channel_prediv: value of the PREDIV in channel RCC_PREDIVxCFGR register
+ *		   can be either 1, 2, 4 or 1024
+ * channel_findiv: value of the FINDIV in channel RCC_FINDIVxCFGR register
+ *		   from 1 to 64
+ */
+
+#define FLEXGEN_CFG(ch, sel, pdiv, fdiv)	((CMD_FLEXGEN << CMD_SHIFT) |\
+						((ch) << FLEX_ID_SHIFT) |\
+						((sel) << FLEX_SEL_SHIFT) |\
+						((pdiv) << FLEX_PDIV_SHIFT) |\
+						((fdiv) << FLEX_FDIV_SHIFT))
+
+/* Register addresses of MCO1 & MCO2 */
+#define MCO1			0x488
+#define MCO2			0x48C
+
+#define MCO_OFF			0
+#define MCO_ON			1
+#define MCO_STATUS_SHIFT	8
+
+#define MCO_CFG(addr, sel, status)	(CMD_ADDR_BIT |\
+					((addr) << CLK_ADDR_SHIFT) |\
+					((status) << MCO_STATUS_SHIFT) |\
+					(sel))
+
+/* define for st,pll /csg */
+#define SSCG_MODE_CENTER_SPREAD	0
+#define SSCG_MODE_DOWN_SPREAD	1
+
+/* define for st,drive */
+#define LSEDRV_LOWEST		0
+#define LSEDRV_MEDIUM_LOW	2
+#define LSEDRV_MEDIUM_HIGH	1
+#define LSEDRV_HIGHEST		3
+
+#endif /* _DT_BINDINGS_CLOCK_STM32MP21_CLKSRC_H_ */

diff --git a/include/dt-bindings/reset/st,stm32mp21-rcc.h b/include/dt-bindings/reset/st,stm32mp21-rcc.h
new file mode 100644
index 0000000..377a170
--- /dev/null
+++ b/include/dt-bindings/reset/st,stm32mp21-rcc.h

@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
+ * Author(s): Gabriel Fernandez <gabriel.fernandez@foss.st.com>
+ */
+
+#ifndef _DT_BINDINGS_STM32MP21_RESET_H_
+#define _DT_BINDINGS_STM32MP21_RESET_H_
+
+/* TF-A use a binding required by driver, not aligned with Linux*/
+
+#define SYS_R		8192
+#define C1_R		8224
+#define C2_R		8288
+#define C2_HOLDBOOT_R	8608
+#define C1_HOLDBOOT_R	8609
+#define VSW_R		8672
+#define C1MS_R		8840
+#define IWDG2_KER_R	9106
+#define IWDG4_KER_R	9234
+#define DDRCP_R		9888
+#define DDRCAPB_R	9920
+#define DDRPHYCAPB_R	9952
+#define DDRCFG_R	10016
+#define DDR_R		10048
+#define OSPI1_R		10400
+#define OSPI1DLL_R	10416
+#define FMC_R		10464
+#define DBG_R		10508
+#define GPIOA_R		10592
+#define GPIOB_R		10624
+#define GPIOC_R		10656
+#define GPIOD_R		10688
+#define GPIOE_R		10720
+#define GPIOF_R		10752
+#define GPIOG_R		10784
+#define GPIOH_R		10816
+#define GPIOI_R		10848
+#define GPIOZ_R		10944
+#define HPDMA1_R	10976
+#define HPDMA2_R	11008
+#define HPDMA3_R	11040
+#define IPCC1_R		11136
+#define SSMOD_R		11392
+#define TIM1_R		14336
+#define TIM2_R		14368
+#define TIM3_R		14400
+#define TIM4_R		14432
+#define TIM5_R		14464
+#define TIM6_R		14496
+#define TIM7_R		14528
+#define TIM8_R		14560
+#define TIM10_R		14592
+#define TIM11_R		14624
+#define TIM12_R		14656
+#define TIM13_R		14688
+#define TIM14_R		14720
+#define TIM15_R		14752
+#define TIM16_R		14784
+#define TIM17_R		14816
+#define LPTIM1_R	14880
+#define LPTIM2_R	14912
+#define LPTIM3_R	14944
+#define LPTIM4_R	14976
+#define LPTIM5_R	15008
+#define SPI1_R		15040
+#define SPI2_R		15072
+#define SPI3_R		15104
+#define SPI4_R		15136
+#define SPI5_R		15168
+#define SPI6_R		15200
+#define SPDIFRX_R	15296
+#define USART1_R	15328
+#define USART2_R	15360
+#define USART3_R	15392
+#define UART4_R		15424
+#define UART5_R		15456
+#define USART6_R	15488
+#define UART7_R		15520
+#define LPUART1_R	15616
+#define I2C1_R		15648
+#define I2C2_R		15680
+#define I2C3_R		15712
+#define SAI1_R		15904
+#define SAI2_R		15936
+#define SAI3_R		15968
+#define SAI4_R		16000
+#define MDF1_R		16064
+#define ADF1_R		16096
+#define FDCAN_R		16128
+#define HDP_R		16160
+#define ADC1_R		16192
+#define ADC2_R		16224
+#define ETH1_R		16256
+#define ETH2_R		16288
+#define USBH_R		16352
+#define USB2PHY1_R	16384
+#define OTG_R		16448
+#define USB2PHY2_R	16480
+#define SDMMC1_R	16768
+#define SDMMC1DLL_R	16784
+#define SDMMC2_R	16800
+#define SDMMC2DLL_R	16816
+#define SDMMC3_R	16832
+#define SDMMC3DLL_R	16848
+#define LTDC_R		16896
+#define CSI_R		17088
+#define DCMIPP_R	17120
+#define DCMIPSSI_R	17152
+#define RNG1_R		17280
+#define RNG2_R		17312
+#define PKA_R		17344
+#define SAES_R		17376
+#define HASH1_R		17408
+#define HASH2_R		17440
+#define CRYP1_R		17472
+#define CRYP2_R		17504
+#define WWDG1_R		17696
+#define VREF_R		17760
+#define DTS_R		17792
+#define CRC_R		17824
+#define SERC_R		17856
+#define I3C1_R		17984
+#define I3C2_R		18016
+#define I3C3_R		18048
+
+#define RST_SCMI_C1_R		0
+#define RST_SCMI_C2_R		1
+#define RST_SCMI_C1_HOLDBOOT_R	2
+#define RST_SCMI_C2_HOLDBOOT_R	3
+#define RST_SCMI_FMC		4
+#define RST_SCMI_OSPI1		5
+#define RST_SCMI_OSPI1DLL	6
+
+#endif /* _DT_BINDINGS_STM32MP21_RESET_H_ */

diff --git a/include/lib/cpus/aarch64/cortex_a710.h b/include/lib/cpus/aarch64/cortex_a710.h
index a47a47e..ccd35f9 100644
--- a/include/lib/cpus/aarch64/cortex_a710.h
+++ b/include/lib/cpus/aarch64/cortex_a710.h

@@ -44,6 +44,11 @@
 #define CORTEX_A710_CPUACTLR3_EL1				S3_0_C15_C1_2
 
 /*******************************************************************************
+ * CPU Auxiliary Control register 4 specific definitions.
+ ******************************************************************************/
+#define CORTEX_A710_CPUACTLR4_EL1                               S3_0_C15_C1_3
+
+/*******************************************************************************
  * CPU Auxiliary Control register 5 specific definitions.
  ******************************************************************************/
 #define CORTEX_A710_CPUACTLR5_EL1				S3_0_C15_C8_0

diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S
index 402e07f..84107a4 100644
--- a/include/lib/cpus/aarch64/cpu_macros.S
+++ b/include/lib/cpus/aarch64/cpu_macros.S

@@ -152,14 +152,14 @@
 	 * If the field equals 1, branch targets trained in one context cannot
 	 * affect speculative execution in a different context.
 	 *
-	 * If the field equals 2, it means that the system is also aware of
+	 * If the field equals 2 or 3, it means that the system is also aware of
 	 * SCXTNUM_ELx register contexts. We aren't using them in the TF, so we
 	 * expect users of the registers to do the right thing.
 	 *
 	 * Only apply mitigations if the value of this field is 0.
 	 */
 #if ENABLE_ASSERTIONS
-	cmp	\_reg, #3 /* Only values 0 to 2 are expected */
+	cmp	\_reg, #4 /* Only values 0 to 3 are expected */
 	ASM_ASSERT(lo)
 #endif
 

diff --git a/include/lib/cpus/aarch64/dsu_def.h b/include/lib/cpus/aarch64/dsu_def.h
index 78b3e7f..3f6dbfe 100644
--- a/include/lib/cpus/aarch64/dsu_def.h
+++ b/include/lib/cpus/aarch64/dsu_def.h

@@ -26,14 +26,18 @@
 #define CLUSTERIDR_VAR_SHIFT	U(4)
 #define CLUSTERIDR_VAR_BITS	U(4)
 
+#define CLUSTERREVIDR_EL1	S3_0_C15_C3_2
+
 /********************************************************************
  * DSU Cluster Auxiliary Control registers definitions
  ********************************************************************/
 #define CLUSTERACTLR_EL1	S3_0_C15_C3_3
 #define CLUSTERPWRCTLR_EL1	S3_0_C15_C3_5
 
-#define CLUSTERACTLR_EL1_DISABLE_CLOCK_GATING	(ULL(1) << 15)
-#define CLUSTERACTLR_EL1_DISABLE_SCLK_GATING	(ULL(3) << 15)
+#define CLUSTERACTLR_EL1_ASSERT_CBUSY			(ULL(1) << 8)
+#define CLUSTERACTLR_EL1_DISABLE_CLOCK_GATING		(ULL(1) << 15)
+#define CLUSTERACTLR_EL1_DISABLE_SCLK_GATING		(ULL(3) << 15)
+#define CLUSTERACTLR_EL1_IGNORE_INTERCONNECT_CBUSY	(ULL(3) << 20)
 
 /********************************************************************
  * Masks applied for DSU errata workarounds

diff --git a/include/lib/cpus/aarch64/dsu_macros.S b/include/lib/cpus/aarch64/dsu_macros.S
index 6c8cb69..fd23f66 100644
--- a/include/lib/cpus/aarch64/dsu_macros.S
+++ b/include/lib/cpus/aarch64/dsu_macros.S

@@ -94,4 +94,44 @@
 	orr	x0, x0, #CLUSTERACTLR_EL1_DISABLE_SCLK_GATING
 	msr	CLUSTERACTLR_EL1, x0
 .endm
+
+/*
+ * Check if erratum is fixed via CLUSTERREVIDR_EL1 bit (\bitpos).
+ * If not fixed (bit is clear), set x0 = ERRATA_APPLIES (from x3).
+ * If fixed (bit is set), keep x0 = ERRATA_NOT_APPLIES.
+ */
+.macro check_revidr_bit bitpos:req
+	mrs	x4, CLUSTERREVIDR_EL1
+	mov	x1, #1
+	lsl	x1, x1, #\bitpos
+	tst	x1, x4
+	csel	x0, x0, x3, NE
+.endm
+
+.macro check_errata_dsu_2900952_applies
+	mov	x0, #ERRATA_NOT_APPLIES
+	mov	x3, #ERRATA_APPLIES
+
+	/* Check if DSU revision is equal to r2p0 */
+	mrs	x1, CLUSTERIDR_EL1
+
+	/* DSU variant and revision bitfields in CLUSTERIDR are adjacent */
+	ubfx	x2, x1, #CLUSTERIDR_REV_SHIFT,\
+			#(CLUSTERIDR_REV_BITS + CLUSTERIDR_VAR_BITS)
+	cmp x2, #(0x2 << CLUSTERIDR_VAR_SHIFT)
+	b.ne	1f
+	check_revidr_bit 1
+1:
+.endm
+
+.macro errata_dsu_2900952_wa_apply
+
+	ldr	x1, =((CLUSTERACTLR_EL1_IGNORE_INTERCONNECT_CBUSY | \
+				CLUSTERACTLR_EL1_ASSERT_CBUSY))
+
+	mrs	x0, CLUSTERACTLR_EL1
+	orr	x0, x0, x1
+	msr	CLUSTERACTLR_EL1, x0
+.endm
+
 #endif /* DSU_MACROS_S */

diff --git a/include/lib/cpus/errata.h b/include/lib/cpus/errata.h
index 235e2b9..bb755e0 100644
--- a/include/lib/cpus/errata.h
+++ b/include/lib/cpus/errata.h

@@ -93,8 +93,9 @@
  * NOTE an erratum and CVE id could clash. However, both numbers are very large
  * and the probablity is minuscule. Working around this makes code very
  * complicated and extremely difficult to read so it is not considered. In the
- * unlikely event that this does happen, prepending the CVE id with a 0 should
- * resolve the conflict
+ * unlikely event that this does happen, the build will fail, and unless the
+ * framework is updated to account for this one of the IDs will need to be
+ * altered to prevent the conflict.
  */
 #define NO_ISB			1
 #define NO_ASSERT		0

diff --git a/include/lib/el3_runtime/cpu_data.h b/include/lib/el3_runtime/cpu_data.h
index 3dc156a..20a6c39 100644
--- a/include/lib/el3_runtime/cpu_data.h
+++ b/include/lib/el3_runtime/cpu_data.h

@@ -138,7 +138,7 @@
 	void *cpu_context[CPU_DATA_CONTEXT_NUM];
 #endif /* __aarch64__ */
 	entry_point_info_t *warmboot_ep_info;
-	uintptr_t cpu_ops_ptr;
+	struct cpu_ops *cpu_ops_ptr;
 	struct psci_cpu_data psci_svc_cpu_data;
 #if ENABLE_PAUTH
 	uint64_t apiakey[2];
@@ -196,16 +196,19 @@
 		assert_cpu_data_pmf_ts0_offset_mismatch);
 #endif
 
-struct cpu_data *_cpu_data_by_index(uint32_t cpu_index);
+static inline cpu_data_t *_cpu_data_by_index(unsigned int cpu_index)
+{
+	return &percpu_data[cpu_index];
+}
 
 #ifdef __aarch64__
 /* Return the cpu_data structure for the current CPU. */
-static inline struct cpu_data *_cpu_data(void)
+static inline cpu_data_t *_cpu_data(void)
 {
 	return (cpu_data_t *)read_tpidr_el3();
 }
 #else
-struct cpu_data *_cpu_data(void);
+cpu_data_t *_cpu_data(void);
 #endif
 
 /*

diff --git a/include/lib/libc/string_private.h b/include/lib/libc/string_private.h
index da85fae..ab7647a 100644
--- a/include/lib/libc/string_private.h
+++ b/include/lib/libc/string_private.h

@@ -11,6 +11,7 @@
 
 #include <stddef.h>
 
+void *memcpy(void *dst, const void *src, size_t len);
 int memcmp(const void *s1, const void *s2, size_t len);
 int strcmp(const char *s1, const char *s2);
 int strncmp(const char *s1, const char *s2, size_t n);

diff --git a/include/lib/psci/psci_lib.h b/include/lib/psci/psci_lib.h
index 8c9296b..1e1d5fc 100644
--- a/include/lib/psci/psci_lib.h
+++ b/include/lib/psci/psci_lib.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -98,6 +98,7 @@
 void __dead2 psci_pwrdown_cpu_end_terminal(void);
 void psci_pwrdown_cpu_end_wakeup(unsigned int power_level);
 void psci_do_manage_extensions(void);
+unsigned int psci_num_cpus_running_on_safe(unsigned int this_core);
 
 #endif /* __ASSEMBLER__ */
 

diff --git a/include/lib/xlat_tables/xlat_tables_defs.h b/include/lib/xlat_tables/xlat_tables_defs.h
index f540fa5..a0bc1f3 100644
--- a/include/lib/xlat_tables/xlat_tables_defs.h
+++ b/include/lib/xlat_tables/xlat_tables_defs.h

@@ -148,8 +148,8 @@
 
 /* Normal Memory, Outer Write-Through non-transient, Inner Non-cacheable */
 #define ATTR_NON_CACHEABLE		MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_NC, MAIR_NORM_NC)
-/* Device-nGnRE */
-#define ATTR_DEVICE			MAIR_DEV_nGnRE
+/* Device-nGnRnE */
+#define ATTR_DEVICE			MAIR_DEV_nGnRnE
 /* Normal Memory, Outer Write-Back non-transient, Inner Write-Back non-transient */
 #define ATTR_IWBWA_OWBWA_NTR		MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_WB_NTR_RWA, MAIR_NORM_WB_NTR_RWA)
 #define MAIR_ATTR_SET(attr, index)	((attr) << ((index) << 3))

diff --git a/include/plat/arm/common/plat_acs_smc_handler.h b/include/plat/arm/common/plat_acs_smc_handler.h
new file mode 100644
index 0000000..4d337cb
--- /dev/null
+++ b/include/plat/arm/common/plat_acs_smc_handler.h

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef ACS_SMC_HANDLER_H
+#define ACS_SMC_HANDLER_H
+
+#include <common/runtime_svc.h>
+#include <lib/utils_def.h>
+
+/* ARM ACS SMC service call */
+#define ARM_VEN_EL3_ACS_SMC_HANDLER     U(0xC7000030)
+#define is_acs_fid(smc_fid)             (smc_fid == ARM_VEN_EL3_ACS_SMC_HANDLER)
+
+uintptr_t plat_arm_acs_smc_handler(unsigned int smc_fid,
+				   uint64_t services,
+				   uint64_t arg0,
+				   uint64_t arg1,
+				   uint64_t arg2,
+				   void *handle);
+#endif /* ACS_SMC_HANDLER_H */

diff --git a/include/services/drtm_svc.h b/include/services/drtm_svc.h
index 56ae129..8e27b18 100644
--- a/include/services/drtm_svc.h
+++ b/include/services/drtm_svc.h

@@ -102,7 +102,7 @@
 #define ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK	ULL(0xFFFFFFFF)
 
 #define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT	U(8)
-#define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK	ULL(0xF)
+#define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK	ULL(0xFFFF)
 
 #define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT	U(0)
 #define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK	ULL(0xFF)

diff --git a/include/services/ven_el3_svc.h b/include/services/ven_el3_svc.h
index e030b68..0336059 100644
--- a/include/services/ven_el3_svc.h
+++ b/include/services/ven_el3_svc.h

@@ -21,7 +21,7 @@
 #define VEN_EL3_SVC_VERSION	0x8700ff03
 
 #define VEN_EL3_SVC_VERSION_MAJOR	1
-#define VEN_EL3_SVC_VERSION_MINOR	0
+#define VEN_EL3_SVC_VERSION_MINOR	1
 
 /* DEBUGFS_SMC_32		0x87000010U */
 /* DEBUGFS_SMC_64		0xC7000010U */
@@ -29,4 +29,7 @@
 /* PMF_SMC_GET_TIMESTAMP_32	0x87000020U */
 /* PMF_SMC_GET_TIMESTAMP_64	0xC7000020U */
 
+/* ACS_SMC_HANDLER_32           0x87000030U */
+/* ACS_SMC_HANDLER_64           0xC7000030U */
+
 #endif /* VEN_EL3_SVC_H */

diff --git a/lib/cpus/aarch64/cortex_a520.S b/lib/cpus/aarch64/cortex_a520.S
index ac8019e..5e0b711 100644
--- a/lib/cpus/aarch64/cortex_a520.S
+++ b/lib/cpus/aarch64/cortex_a520.S

@@ -9,6 +9,7 @@
 #include <common/bl_common.h>
 #include <cortex_a520.h>
 #include <cpu_macros.S>
+#include <dsu_macros.S>
 #include <plat_macros.S>
 
 .global check_erratum_cortex_a520_2938996
@@ -37,6 +38,15 @@
 
 check_erratum_ls cortex_a520, ERRATUM(2858100), CPU_REV(0, 1)
 
+workaround_reset_start cortex_a520, ERRATUM(2900952), ERRATA_DSU_2900952
+	errata_dsu_2900952_wa_apply
+workaround_reset_end cortex_a520, ERRATUM(2900952)
+
+check_erratum_custom_start cortex_a520, ERRATUM(2900952)
+	check_errata_dsu_2900952_applies
+	ret
+check_erratum_custom_end cortex_a520, ERRATUM(2900952)
+
 add_erratum_entry cortex_a520, ERRATUM(2938996), ERRATA_A520_2938996
 
 check_erratum_ls cortex_a520, ERRATUM(2938996), CPU_REV(0, 1)

diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S
index 54bb453..728c51f 100644
--- a/lib/cpus/aarch64/cortex_a710.S
+++ b/lib/cpus/aarch64/cortex_a710.S

@@ -31,6 +31,24 @@
 
 cpu_reset_prologue cortex_a710
 
+workaround_reset_start cortex_a710, ERRATUM(1901946), ERRATA_A710_1901946
+	sysreg_bit_set	CORTEX_A710_CPUACTLR4_EL1, BIT(15)
+workaround_reset_end cortex_a710, ERRATUM(1901946)
+
+check_erratum_range cortex_a710, ERRATUM(1901946), CPU_REV(1, 0), CPU_REV(1, 0)
+
+workaround_reset_start cortex_a710, ERRATUM(1916945), ERRATA_A710_1916945
+	sysreg_bit_set	CORTEX_A710_CPUECTLR_EL1, BIT(8)
+workaround_reset_end cortex_a710, ERRATUM(1916945)
+
+check_erratum_ls cortex_a710, ERRATUM(1916945), CPU_REV(1, 0)
+
+workaround_reset_start cortex_a710, ERRATUM(1917258), ERRATA_A710_1917258
+	sysreg_bit_set	CORTEX_A710_CPUACTLR4_EL1, BIT(43)
+workaround_reset_end cortex_a710, ERRATUM(1917258)
+
+check_erratum_ls cortex_a710, ERRATUM(1917258), CPU_REV(1, 0)
+
 workaround_reset_start cortex_a710, ERRATUM(1987031), ERRATA_A710_1987031
 	ldr x0,=0x6
 	msr S3_6_c15_c8_0,x0

diff --git a/lib/cpus/aarch64/cortex_a720.S b/lib/cpus/aarch64/cortex_a720.S
index e639996..0c713c3 100644
--- a/lib/cpus/aarch64/cortex_a720.S
+++ b/lib/cpus/aarch64/cortex_a720.S

@@ -9,6 +9,7 @@
 #include <common/bl_common.h>
 #include <cortex_a720.h>
 #include <cpu_macros.S>
+#include <dsu_macros.S>
 #include <plat_macros.S>
 #include "wa_cve_2022_23960_bhb_vector.S"
 
@@ -42,6 +43,15 @@
 
 check_erratum_ls cortex_a720, ERRATUM(2844092), CPU_REV(0, 1)
 
+workaround_reset_start cortex_a720, ERRATUM(2900952), ERRATA_DSU_2900952
+	errata_dsu_2900952_wa_apply
+workaround_reset_end cortex_a720, ERRATUM(2900952)
+
+check_erratum_custom_start cortex_a720, ERRATUM(2900952)
+	check_errata_dsu_2900952_applies
+	ret
+check_erratum_custom_end cortex_a720, ERRATUM(2900952)
+
 workaround_reset_start cortex_a720, ERRATUM(2926083), ERRATA_A720_2926083
 /* Erratum 2926083 workaround is required only if SPE is enabled */
 #if ENABLE_SPE_FOR_NS != 0

diff --git a/lib/cpus/aarch64/cortex_a725.S b/lib/cpus/aarch64/cortex_a725.S
index 682ca45..e940bde 100644
--- a/lib/cpus/aarch64/cortex_a725.S
+++ b/lib/cpus/aarch64/cortex_a725.S

@@ -9,6 +9,7 @@
 #include <common/bl_common.h>
 #include <cortex_a725.h>
 #include <cpu_macros.S>
+#include <dsu_macros.S>
 #include <plat_macros.S>
 
 /* Hardware handled coherency */
@@ -25,6 +26,15 @@
 
 .global check_erratum_cortex_a725_3699564
 
+workaround_reset_start cortex_a725, ERRATUM(2900952), ERRATA_DSU_2900952
+	errata_dsu_2900952_wa_apply
+workaround_reset_end cortex_a725, ERRATUM(2900952)
+
+check_erratum_custom_start cortex_a725, ERRATUM(2900952)
+	check_errata_dsu_2900952_applies
+	ret
+check_erratum_custom_end cortex_a725, ERRATUM(2900952)
+
 add_erratum_entry cortex_a725, ERRATUM(3699564), ERRATA_A725_3699564
 
 check_erratum_ls cortex_a725, ERRATUM(3699564), CPU_REV(0, 1)

diff --git a/lib/cpus/aarch64/cortex_x4.S b/lib/cpus/aarch64/cortex_x4.S
index 1d0c377..b1dc52c 100644
--- a/lib/cpus/aarch64/cortex_x4.S
+++ b/lib/cpus/aarch64/cortex_x4.S

@@ -9,6 +9,7 @@
 #include <common/bl_common.h>
 #include <cortex_x4.h>
 #include <cpu_macros.S>
+#include <dsu_macros.S>
 #include <plat_macros.S>
 #include "wa_cve_2022_23960_bhb_vector.S"
 
@@ -64,6 +65,15 @@
 
 check_erratum_ls cortex_x4, ERRATUM(2897503), CPU_REV(0, 1)
 
+workaround_reset_start cortex_x4, ERRATUM(2900952), ERRATA_DSU_2900952
+	errata_dsu_2900952_wa_apply
+workaround_reset_end cortex_x4, ERRATUM(2900952)
+
+check_erratum_custom_start cortex_x4, ERRATUM(2900952)
+	check_errata_dsu_2900952_applies
+	ret
+check_erratum_custom_end cortex_x4, ERRATUM(2900952)
+
 workaround_reset_start cortex_x4, ERRATUM(2923985), ERRATA_X4_2923985
 	sysreg_bit_set CORTEX_X4_CPUACTLR4_EL1, (BIT(11) | BIT(10))
 workaround_reset_end cortex_x4, ERRATUM(2923985)

diff --git a/lib/cpus/aarch64/cortex_x925.S b/lib/cpus/aarch64/cortex_x925.S
index 0663b21..003dc97 100644
--- a/lib/cpus/aarch64/cortex_x925.S
+++ b/lib/cpus/aarch64/cortex_x925.S

@@ -9,6 +9,7 @@
 #include <common/bl_common.h>
 #include <cortex_x925.h>
 #include <cpu_macros.S>
+#include <dsu_macros.S>
 #include <plat_macros.S>
 
 /* Hardware handled coherency */
@@ -23,6 +24,15 @@
 
 cpu_reset_prologue cortex_x925
 
+workaround_reset_start cortex_x925, ERRATUM(2900952), ERRATA_DSU_2900952
+	errata_dsu_2900952_wa_apply
+workaround_reset_end cortex_x925, ERRATUM(2900952)
+
+check_erratum_custom_start cortex_x925, ERRATUM(2900952)
+	check_errata_dsu_2900952_applies
+	ret
+check_erratum_custom_end cortex_x925, ERRATUM(2900952)
+
 add_erratum_entry cortex_x925, ERRATUM(3701747), ERRATA_X925_3701747
 
 check_erratum_ls cortex_x925, ERRATUM(3701747), CPU_REV(0, 1)

diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 4b8de00..a0cb872 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk

@@ -561,6 +561,18 @@
 # the Neoverse V3 cpu and is still open.
 CPU_FLAG_LIST += ERRATA_V3_3701767
 
+# Flag to apply erratum 1901946 workaround during reset. This erratum applies
+# to revision r1p0 and is fixed in r2p0.
+CPU_FLAG_LIST += ERRATA_A710_1901946
+
+# Flag to apply erratum 1916945 workaround during reset. This erratum applies
+# to revisions r0p0 and r1p0 of the Cortex-A710 CPU and is fixed in r2p0.
+CPU_FLAG_LIST += ERRATA_A710_1916945
+
+# Flag to apply erratum 1917258 workaround during reset. This erratum applies
+# to revisions r0p0 and r1p0 of the Cortex-A710 CPU and is fixed in r2p0.
+CPU_FLAG_LIST += ERRATA_A710_1917258
+
 # Flag to apply erratum 1987031 workaround during reset. This erratum applies
 # to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
 CPU_FLAG_LIST += ERRATA_A710_1987031
@@ -1063,6 +1075,13 @@
 # results in higher DSU power consumption on idle.
 CPU_FLAG_LIST += ERRATA_DSU_2313941
 
+# Flag to apply DSU erratum 2900952 during reset. This erratum applies
+# to some implementations of DSU-120 revision r2p0. Erratum might be fixed
+# in some implementations of r2p0. This can be determined by reading
+# the IMP_CLUSTERREVIDR_EL1 register where a set bit indicates that
+# the erratum is fixed in this part. It is fixed in r2p1.
+CPU_FLAG_LIST += ERRATA_DSU_2900952
+
 ifneq (${DYNAMIC_WORKAROUND_CVE_2018_3639},0)
 	ifeq (${WORKAROUND_CVE_2018_3639},0)
 		$(error "Error: WORKAROUND_CVE_2018_3639 must be 1 if DYNAMIC_WORKAROUND_CVE_2018_3639 is 1")

diff --git a/lib/cpus/errata_report.c b/lib/cpus/errata_report.c
index ab68467..47e8699 100644
--- a/lib/cpus/errata_report.c
+++ b/lib/cpus/errata_report.c

@@ -31,7 +31,7 @@
 /* Errata format: BL stage, CPU, errata ID, message */
 #define ERRATA_FORMAT	"%s: %s: CPU workaround for %s was %s\n"
 
-#define CVE_FORMAT	"%s: %s: CPU workaround for CVE %u_%u was %s\n"
+#define CVE_FORMAT	"%s: %s: CPU workaround for CVE %u_%04u was %s\n"
 #define ERRATUM_FORMAT	"%s: %s: CPU workaround for erratum %u was %s\n"
 
 

diff --git a/lib/el3_runtime/aarch32/cpu_data.S b/lib/el3_runtime/aarch32/cpu_data.S
deleted file mode 100644
index e59b7fd..0000000
--- a/lib/el3_runtime/aarch32/cpu_data.S
+++ /dev/null

@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2016, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <asm_macros.S>
-#include <lib/el3_runtime/cpu_data.h>
-
-	.globl	_cpu_data
-	.globl	_cpu_data_by_index
-
-/* -----------------------------------------------------------------
- * cpu_data_t *_cpu_data(void)
- *
- * Return the cpu_data structure for the current CPU.
- * -----------------------------------------------------------------
- */
-func _cpu_data
-	/* r12 is pushed to meet the 8 byte stack alignment requirement */
-	push	{r12, lr}
-	bl	plat_my_core_pos
-	pop	{r12, lr}
-	b	_cpu_data_by_index
-endfunc _cpu_data
-
-/* -----------------------------------------------------------------
- * cpu_data_t *_cpu_data_by_index(uint32_t cpu_index)
- *
- * Return the cpu_data structure for the CPU with given linear index
- *
- * This can be called without a valid stack.
- * clobbers: r0, r1
- * -----------------------------------------------------------------
- */
-func _cpu_data_by_index
-	mov_imm	r1, CPU_DATA_SIZE
-	mul	r0, r0, r1
-	ldr	r1, =percpu_data
-	add	r0, r0, r1
-	bx	lr
-endfunc _cpu_data_by_index

diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index d04e02f..7795fcf 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c

@@ -191,6 +191,15 @@
 		scr_el3 |= SCR_SCTLR2En_BIT;
 	}
 
+	if (is_feat_d128_supported()) {
+		/*
+		 * Set the D128En bit in SCR_EL3 to enable access to 128-bit
+		 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1,
+		 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers.
+		 */
+		scr_el3 |= SCR_D128En_BIT;
+	}
+
 	write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
 
 	if (is_feat_fgt2_supported()) {

diff --git a/lib/el3_runtime/aarch64/cpu_data.S b/lib/el3_runtime/aarch64/cpu_data.S
deleted file mode 100644
index 02d9415..0000000
--- a/lib/el3_runtime/aarch64/cpu_data.S
+++ /dev/null

@@ -1,28 +0,0 @@
-/*
- * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <asm_macros.S>
-#include <lib/el3_runtime/cpu_data.h>
-
-.globl	_cpu_data_by_index
-
-/* -----------------------------------------------------------------
- * cpu_data_t *_cpu_data_by_index(uint32_t cpu_index)
- *
- * Return the cpu_data structure for the CPU with given linear index
- *
- * This can be called without a valid stack.
- * clobbers: x0, x1
- * -----------------------------------------------------------------
- */
-func _cpu_data_by_index
-	mov_imm	x1, CPU_DATA_SIZE
-	mul	x0, x0, x1
-	adrp	x1, percpu_data
-	add	x1, x1, :lo12:percpu_data
-	add	x0, x0, x1
-	ret
-endfunc _cpu_data_by_index

diff --git a/lib/el3_runtime/cpu_data_array.c b/lib/el3_runtime/cpu_data_array.c
index 2056182..f2e97f0 100644
--- a/lib/el3_runtime/cpu_data_array.c
+++ b/lib/el3_runtime/cpu_data_array.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2016, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,6 +8,14 @@
 
 #include <lib/cassert.h>
 #include <lib/el3_runtime/cpu_data.h>
+#include <plat/common/platform.h>
 
 /* The per_cpu_ptr_cache_t space allocation */
 cpu_data_t percpu_data[PLATFORM_CORE_COUNT];
+
+#ifndef __aarch64__
+cpu_data_t *_cpu_data(void)
+{
+	return _cpu_data_by_index(plat_my_core_pos());
+}
+#endif

diff --git a/lib/libc/memcpy.c b/lib/libc/memcpy.c
index ca31de5..e8be154 100644
--- a/lib/libc/memcpy.c
+++ b/lib/libc/memcpy.c

@@ -12,8 +12,9 @@
 	const char *s = src;
 	char *d = dst;
 
-	while (len--)
+	while (len--) {
 		*d++ = *s++;
+	}
 
 	return dst;
 }

diff --git a/lib/libc/memmove.c b/lib/libc/memmove.c
index 6451e4e..7aee83f 100644
--- a/lib/libc/memmove.c
+++ b/lib/libc/memmove.c

@@ -24,8 +24,9 @@
 		const char *end = dst;
 		const char *s = (const char *)src + len;
 		char *d = (char *)dst + len;
-		while (d != end)
+		while (d != end) {
 			*--d = *--s;
+		}
 	}
 	return dst;
 }

diff --git a/lib/libc/printf.c b/lib/libc/printf.c
index c9e8a04..65c5238 100644
--- a/lib/libc/printf.c
+++ b/lib/libc/printf.c

@@ -131,8 +131,9 @@
 					(void)putchar((int32_t)'-');
 					unum = (unsigned long long int)-num;
 					padn--;
-				} else
+				} else {
 					unum = (unsigned long long int)num;
+				}
 
 				count += unsigned_num_print(unum, 10,
 							    padc, padn, uppercase);
@@ -164,8 +165,9 @@
 							    padc, padn, uppercase);
 				break;
 			case 'z':
-				if (sizeof(size_t) == 8U)
+				if (sizeof(size_t) == 8U) {
 					l_count = 2;
+				}
 
 				fmt++;
 				goto loop;

diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index 1c634e3..1021ef6 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c

@@ -215,7 +215,7 @@
  ******************************************************************************/
 bool psci_is_last_on_cpu(unsigned int my_idx)
 {
-	for (unsigned int cpu_idx = 0; cpu_idx < psci_plat_core_count; cpu_idx++) {
+	for (unsigned int cpu_idx = 0U; cpu_idx < psci_plat_core_count; cpu_idx++) {
 		if (cpu_idx == my_idx) {
 			assert(psci_get_aff_info_state() == AFF_STATE_ON);
 			continue;
@@ -239,7 +239,7 @@
 {
 	unsigned int cpu_idx;
 
-	for (cpu_idx = 0; cpu_idx < psci_plat_core_count; cpu_idx++) {
+	for (cpu_idx = 0U; cpu_idx < psci_plat_core_count; cpu_idx++) {
 		if (psci_get_aff_info_state_by_idx(cpu_idx) == AFF_STATE_OFF) {
 			return false;
 		}
@@ -249,6 +249,33 @@
 }
 
 /*******************************************************************************
+ * Counts the number of CPUs in the system that are currently in the ON or
+ * ON_PENDING state.
+ *
+ * @note This function does not acquire any power domain locks. It must only be
+ *       called in contexts where it is guaranteed that PSCI state transitions
+ *       are not concurrently happening, or where locks are already held.
+ *
+ * @return The number of CPUs currently in AFF_STATE_ON or AFF_STATE_ON_PENDING.
+ ******************************************************************************/
+static unsigned int psci_num_cpus_running(void)
+{
+	unsigned int cpu_idx;
+	unsigned int no_of_cpus = 0U;
+	aff_info_state_t aff_state;
+
+	for (cpu_idx = 0U; cpu_idx < psci_plat_core_count; cpu_idx++) {
+		aff_state = psci_get_aff_info_state_by_idx(cpu_idx);
+		if (aff_state == AFF_STATE_ON ||
+		    aff_state == AFF_STATE_ON_PENDING) {
+			no_of_cpus++;
+		}
+	}
+
+	return no_of_cpus;
+}
+
+/*******************************************************************************
  * Routine to return the maximum power level to traverse to after a cpu has
  * been physically powered up. It is expected to be called immediately after
  * reset from assembler code.
@@ -1371,3 +1398,30 @@
 
 	return true;
 }
+
+/*******************************************************************************
+ * Safely counts the number of CPUs in the system that are currently in the ON
+ * or ON_PENDING state.
+ *
+ * This function acquires and releases the necessary power domain locks to
+ * ensure consistency of the CPU state information.
+ *
+ * @param this_core The index of the current core making the query.
+ *
+ * @return The number of CPUs currently in AFF_STATE_ON or AFF_STATE_ON_PENDING.
+ ******************************************************************************/
+unsigned int psci_num_cpus_running_on_safe(unsigned int this_core)
+{
+	unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0};
+	unsigned int no_of_cpus;
+
+	psci_get_parent_pwr_domain_nodes(this_core, PLAT_MAX_PWR_LVL, parent_nodes);
+
+	psci_acquire_pwr_domain_locks(PLAT_MAX_PWR_LVL, parent_nodes);
+
+	no_of_cpus = psci_num_cpus_running();
+
+	psci_release_pwr_domain_locks(PLAT_MAX_PWR_LVL, parent_nodes);
+
+	return no_of_cpus;
+}

diff --git a/lib/psci/psci_lib.mk b/lib/psci/psci_lib.mk
index 527ad3a..e1dbec2 100644
--- a/lib/psci/psci_lib.mk
+++ b/lib/psci/psci_lib.mk

@@ -1,11 +1,10 @@
 #
-# Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
 PSCI_LIB_SOURCES	:=	lib/el3_runtime/cpu_data_array.c	\
-				lib/el3_runtime/${ARCH}/cpu_data.S	\
 				lib/el3_runtime/${ARCH}/context_mgmt.c	\
 				lib/cpus/${ARCH}/cpu_helpers.S		\
 				lib/cpus/errata_report.c		\

diff --git a/lib/psci/psci_setup.c b/lib/psci/psci_setup.c
index 0863a82..44c9bdb 100644
--- a/lib/psci/psci_setup.c
+++ b/lib/psci/psci_setup.c

@@ -63,8 +63,7 @@
 		/* Initialize with an invalid mpidr */
 		psci_cpu_pd_nodes[node_idx].mpidr = PSCI_INVALID_MPIDR;
 
-		svc_cpu_data =
-			&(_cpu_data_by_index(node_idx)->psci_svc_cpu_data);
+		svc_cpu_data = &get_cpu_data_by_index(node_idx, psci_svc_cpu_data);
 
 		/* Set the Affinity Info for the cores as OFF */
 		svc_cpu_data->aff_info_state = AFF_STATE_OFF;

diff --git a/make_helpers/arch_features.mk b/make_helpers/arch_features.mk
index 1561a59..a6fd6be 100644
--- a/make_helpers/arch_features.mk
+++ b/make_helpers/arch_features.mk

@@ -58,11 +58,6 @@
 armv8-5-a-feats         += ${armv8-4-a-feats}
 
 FEAT_LIST               := ${armv8-5-a-feats}
-# Enable Memory tagging, Branch Target Identification for aarch64 only.
-ifeq ($(ARCH), aarch64)
-	mem_tag_arch_support		?= 	yes
-endif #(ARCH=aarch64)
-
 endif
 
 # Enable the features which are mandatory from ARCH version 8.6 and upwards.
@@ -433,6 +428,9 @@
 # Flag to enable access to Arm v9.3 FEAT_D128 extension
 ENABLE_FEAT_D128			?=	0
 
+# Flag to enable access to GICv5 CPU interface extension (FEAT_GCIE)
+ENABLE_FEAT_GCIE			?=	0
+
 #----
 #9.4
 #----

diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index f438a9d..4ccca9f 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk

@@ -346,11 +346,6 @@
 # CTX_INCLUDE_EL2_REGS.
 CTX_INCLUDE_EL2_REGS		:= 0
 
-# Enable Memory tag extension which is supported for architecture greater
-# than Armv8.5-A
-# By default it is set to "no"
-SUPPORT_STACK_MEMTAG		:= no
-
 # Select workaround for AT speculative behaviour.
 ERRATA_SPECULATIVE_AT		:= 0
 

diff --git a/package-lock.json b/package-lock.json
index 57b44de..92921f9 100644
--- a/package-lock.json
+++ b/package-lock.json

@@ -1,12 +1,12 @@
 {
   "name": "trusted-firmware-a",
-  "version": "2.12.0",
+  "version": "2.13.0",
   "lockfileVersion": 3,
   "requires": true,
   "packages": {
     "": {
       "name": "trusted-firmware-a",
-      "version": "2.12.0",
+      "version": "2.13.0",
       "license": "BSD-3-Clause",
       "devDependencies": {
         "@commitlint/cli": "^19.0.0",

diff --git a/package.json b/package.json
index 0908528..6061bf8 100644
--- a/package.json
+++ b/package.json

@@ -1,6 +1,6 @@
 {
   "name": "trusted-firmware-a",
-  "version": "2.12.0",
+  "version": "2.13.0",
   "license": "BSD-3-Clause",
   "type": "module",
   "private": true,

diff --git a/plat/amd/common/plat_fdt.c b/plat/amd/common/plat_fdt.c
index e72c0dd..194d538 100644
--- a/plat/amd/common/plat_fdt.c
+++ b/plat/amd/common/plat_fdt.c

@@ -10,7 +10,9 @@
 #include <platform_def.h>
 
 #include <plat_fdt.h>
+#ifdef TRANSFER_LIST
 #include <plat_xfer_list.h>
+#endif
 
 #define FIT_CONFS_PATH	"/configurations"
 

diff --git a/plat/amd/versal2/aarch64/common.c b/plat/amd/versal2/aarch64/common.c
index 8d9e05c..9e52f9d 100644
--- a/plat/amd/versal2/aarch64/common.c
+++ b/plat/amd/versal2/aarch64/common.c

@@ -8,12 +8,12 @@
 
 #include <common/debug.h>
 #include <common/runtime_svc.h>
+#include <def.h>
 #include <drivers/generic_delay_timer.h>
 #include <lib/mmio.h>
 #include <lib/xlat_tables/xlat_tables_v2.h>
 #include <plat/common/platform.h>
-
-#include <def.h>
+#include <plat_clkfunc.h>
 #include <plat_common.h>
 #include <plat_ipi.h>
 #include <plat_private.h>
@@ -123,7 +123,7 @@
 	uintptr_t crl_base, iou_scntrs_base, psx_base;
 
 	crl_base = CRL;
-	iou_scntrs_base = IOU_SCNTRS;
+	iou_scntrs_base = IOU_SCNTRS_BASE;
 	psx_base = PSX_CRF;
 
 	/* Reset for system timestamp generator in FPX */
@@ -143,13 +143,11 @@
 	mmio_write_32(iou_scntrs_base + IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET,
 		      IOU_SCNTRS_CONTROL_EN);
 
+	/* set cntfrq_el0 value so that software can discover the frequency of the system counter */
+	set_cnt_freq();
+
 	generic_delay_timer_init();
 
 	/* Configure IPI data */
 	soc_ipi_config_table_init();
 }
-
-uint32_t plat_get_syscnt_freq2(void)
-{
-	return cpu_clock;
-}

diff --git a/plat/amd/versal2/bl31_setup.c b/plat/amd/versal2/bl31_setup.c
index 94ace7d..28bcaa1 100644
--- a/plat/amd/versal2/bl31_setup.c
+++ b/plat/amd/versal2/bl31_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved.
  * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
  * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
@@ -27,7 +27,9 @@
 #include <plat_fdt.h>
 #include <plat_private.h>
 #include <plat_startup.h>
+#if TRANSFER_LIST
 #include <plat_xfer_list.h>
+#endif
 #include <pm_api_sys.h>
 #include <pm_client.h>
 

diff --git a/plat/amd/versal2/include/def.h b/plat/amd/versal2/include/def.h
index 9bef9d0..3b42b15 100644
--- a/plat/amd/versal2/include/def.h
+++ b/plat/amd/versal2/include/def.h

@@ -126,8 +126,14 @@
 
 #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT	(1U << 25U)
 
-/* IOU SCNTRS */
-#define IOU_SCNTRS					U(0xEC920000)
+#define FPD_SYSTMR_CTRL_BASE				U(0xEC920000)
+
+/*
+ * Note: There is no IOU_SCNTRS in Versal Gen 2, the equivalent
+ * functionality is provided through FPD_SYSTMR_CTRL. For compatibility
+ * with existing code, maintain the same macro names.
+ */
+#define IOU_SCNTRS_BASE					FPD_SYSTMR_CTRL_BASE
 #define IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET	U(0)
 #define IOU_SCNTRS_BASE_FREQ_OFFSET			U(0x20)
 

diff --git a/plat/amd/versal2/plat_psci.c b/plat/amd/versal2/plat_psci.c
index d53d751..cded1f3 100644
--- a/plat/amd/versal2/plat_psci.c
+++ b/plat/amd/versal2/plat_psci.c

@@ -19,7 +19,6 @@
 #include <plat_private.h>
 #include <pm_defs.h>
 
-#define PM_RET_ERROR_NOFEATURE U(19)
 #define ALWAYSTRUE true
 #define LINEAR_MODE BIT(1)
 
@@ -192,7 +191,7 @@
 	case IOCTL_USB_SET_STATE:
 		break;
 	default:
-		ret = PM_RET_ERROR_NOFEATURE;
+		ret = PM_RET_ERROR_IOCTL_NOT_SUPPORTED;
 		break;
 	}
 

diff --git a/plat/amd/versal2/platform.mk b/plat/amd/versal2/platform.mk
index 283ad42..475e8ff 100644
--- a/plat/amd/versal2/platform.mk
+++ b/plat/amd/versal2/platform.mk

@@ -116,6 +116,7 @@
 				drivers/delay_timer/generic_delay_timer.c	\
 				${GICV3_SOURCES}				\
 				drivers/arm/pl011/aarch64/pl011_console.S	\
+				plat/xilinx/common/plat_clkfunc.c		\
 				plat/common/aarch64/crash_console_helpers.S	\
 				plat/arm/common/arm_common.c			\
 				plat/common/plat_gicv3.c			\

diff --git a/plat/amd/versal2/pm_service/pm_client.c b/plat/amd/versal2/pm_service/pm_client.c
index 8d6b9b1..67099a6 100644
--- a/plat/amd/versal2/pm_service/pm_client.c
+++ b/plat/amd/versal2/pm_service/pm_client.c

@@ -336,6 +336,23 @@
 	uintptr_t val;
 
 	if (cpuid != (uint32_t) UNDEFINED_CPUID) {
+		/*
+		 * Get the core index and use it to calculate offset for
+		 * disabling power down and wakeup interrupts.
+		 * i.e., Convert cpu-id to core_index with the following mapping:
+		 *  cpu-id -> core_index
+		 *       0 -> 0
+		 *       1 -> 1
+		 *       2 -> 4
+		 *       3 -> 5
+		 *       4 -> 8
+		 *       5 -> 9
+		 *       6 -> 12
+		 *       7 -> 13
+		 * to match with register database.
+		 */
+		uint32_t core_index = cpuid + ((cpuid / 2U) * 2U);
+
 		pm_client_lock_get();
 
 		/* Clear powerdown request */
@@ -346,10 +363,10 @@
 		isb();
 
 		/* Disabled power down interrupt */
-		mmio_write_32(APU_PCIL_CORE_X_IDS_POWER_REG(cpuid),
+		mmio_write_32(APU_PCIL_CORE_X_IDS_POWER_REG(core_index),
 			      APU_PCIL_CORE_X_IDS_POWER_MASK);
 		/* Disable wake interrupt */
-		mmio_write_32(APU_PCIL_CORE_X_IDS_WAKE_REG(cpuid),
+		mmio_write_32(APU_PCIL_CORE_X_IDS_WAKE_REG(core_index),
 			      APU_PCIL_CORE_X_IDS_WAKE_MASK);
 
 		pm_client_lock_release();

diff --git a/plat/amd/versal2/pm_service/pm_svc_main.c b/plat/amd/versal2/pm_service/pm_svc_main.c
index 10d2ed2..55fd963 100644
--- a/plat/amd/versal2/pm_service/pm_svc_main.c
+++ b/plat/amd/versal2/pm_service/pm_svc_main.c

@@ -163,7 +163,8 @@
 		break;
 	case PM_NOTIFY_CB:
 		if (sgi != INVALID_SGI) {
-			if (payload[2] == EVENT_CPU_PWRDWN) {
+			if ((payload[2] == EVENT_CPU_PWRDWN) &&
+			    (NODECLASS(payload[1]) == (uint32_t)XPM_NODECLASS_DEVICE)) {
 				if (pwrdwn_req_received) {
 					pwrdwn_req_received = false;
 					request_cpu_pwrdwn();
@@ -182,7 +183,8 @@
 				 */
 			}
 			notify_os();
-		} else if (payload[2] == EVENT_CPU_PWRDWN) {
+		} else if ((payload[2] == EVENT_CPU_PWRDWN) &&
+			  (NODECLASS(payload[1]) == (uint32_t)XPM_NODECLASS_DEVICE)) {
 			request_cpu_pwrdwn();
 			(void)psci_cpu_off();
 		} else {

diff --git a/plat/arm/board/fvp/fconf/fconf_gicv3_config_getter.c b/plat/arm/board/fvp/fconf/fconf_gicv3_config_getter.c
new file mode 100644
index 0000000..7cb88ed
--- /dev/null
+++ b/plat/arm/board/fvp/fconf/fconf_gicv3_config_getter.c

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <common/fdt_wrappers.h>
+#include <drivers/arm/gicv3.h>
+
+#include <fconf_hw_config_getter.h>
+
+struct gicv3_config_t gicv3_config;
+
+int fconf_populate_gicv3_config(uintptr_t config)
+{
+	int err;
+	int node;
+	uintptr_t addr;
+
+	/* Necessary to work with libfdt APIs */
+	const void *hw_config_dtb = (const void *)config;
+
+	/*
+	 * Find the offset of the node containing "arm,gic-v3" compatible property.
+	 * Populating fconf strucutures dynamically is not supported for legacy
+	 * systems which use GICv2 IP. Simply skip extracting GIC properties.
+	 */
+	node = fdt_node_offset_by_compatible(hw_config_dtb, -1, "arm,gic-v3");
+	if (node < 0) {
+		WARN("FCONF: Unable to locate node with arm,gic-v3 compatible property\n");
+		return 0;
+	}
+	/* The GICv3 DT binding holds at least two address/size pairs,
+	 * the first describing the distributor, the second the redistributors.
+	 * See: bindings/interrupt-controller/arm,gic-v3.yaml
+	 */
+	err = fdt_get_reg_props_by_index(hw_config_dtb, node, 0, &addr, NULL);
+	if (err < 0) {
+		ERROR("FCONF: Failed to read GICD reg property of GIC node\n");
+		return err;
+	}
+	gicv3_config.gicd_base = addr;
+
+	err = fdt_get_reg_props_by_index(hw_config_dtb, node, 1, &addr, NULL);
+	if (err < 0) {
+		ERROR("FCONF: Failed to read GICR reg property of GIC node\n");
+	} else {
+		gicv3_config.gicr_base = addr;
+	}
+
+	return err;
+}
+FCONF_REGISTER_POPULATOR(HW_CONFIG, gicv3_config, fconf_populate_gicv3_config);

diff --git a/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c b/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
index fb7f48e..abc78ce 100644
--- a/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
+++ b/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c

@@ -14,7 +14,6 @@
 #include <libfdt.h>
 #include <plat/common/platform.h>
 
-struct gicv3_config_t gicv3_config;
 struct hw_topology_t soc_topology;
 struct uart_serial_config_t uart_serial_config;
 struct cpu_timer_t cpu_timer;
@@ -32,45 +31,6 @@
 
 #define ILLEGAL_ADDR	ULL(~0)
 
-int fconf_populate_gicv3_config(uintptr_t config)
-{
-	int err;
-	int node;
-	uintptr_t addr;
-
-	/* Necessary to work with libfdt APIs */
-	const void *hw_config_dtb = (const void *)config;
-
-	/*
-	 * Find the offset of the node containing "arm,gic-v3" compatible property.
-	 * Populating fconf strucutures dynamically is not supported for legacy
-	 * systems which use GICv2 IP. Simply skip extracting GIC properties.
-	 */
-	node = fdt_node_offset_by_compatible(hw_config_dtb, -1, "arm,gic-v3");
-	if (node < 0) {
-		WARN("FCONF: Unable to locate node with arm,gic-v3 compatible property\n");
-		return 0;
-	}
-	/* The GICv3 DT binding holds at least two address/size pairs,
-	 * the first describing the distributor, the second the redistributors.
-	 * See: bindings/interrupt-controller/arm,gic-v3.yaml
-	 */
-	err = fdt_get_reg_props_by_index(hw_config_dtb, node, 0, &addr, NULL);
-	if (err < 0) {
-		ERROR("FCONF: Failed to read GICD reg property of GIC node\n");
-		return err;
-	}
-	gicv3_config.gicd_base = addr;
-
-	err = fdt_get_reg_props_by_index(hw_config_dtb, node, 1, &addr, NULL);
-	if (err < 0) {
-		ERROR("FCONF: Failed to read GICR reg property of GIC node\n");
-	} else {
-		gicv3_config.gicr_base = addr;
-	}
-
-	return err;
-}
 
 int fconf_populate_topology(uintptr_t config)
 {
@@ -447,7 +407,6 @@
 	return 0;
 }
 
-FCONF_REGISTER_POPULATOR(HW_CONFIG, gicv3_config, fconf_populate_gicv3_config);
 FCONF_REGISTER_POPULATOR(HW_CONFIG, topology, fconf_populate_topology);
 FCONF_REGISTER_POPULATOR(HW_CONFIG, uart_config, fconf_populate_uart_config);
 FCONF_REGISTER_POPULATOR(HW_CONFIG, cpu_timer, fconf_populate_cpu_timer);

diff --git a/plat/arm/board/fvp/fdts/fvp_fw_config.dts b/plat/arm/board/fvp/fdts/fvp_fw_config.dts
index a11c1de..fd6cf78 100644
--- a/plat/arm/board/fvp/fdts/fvp_fw_config.dts
+++ b/plat/arm/board/fvp/fdts/fvp_fw_config.dts

@@ -27,7 +27,7 @@
 			load-address = <0x0 0x07f00000>;
 			max-size = <PLAT_ARM_HW_CONFIG_SIZE>;
 			id = <HW_CONFIG_ID>;
-			secondary-load-address = <0x0 0x82000000>;
+			secondary-load-address = <0x0 FVP_HW_CONFIG_ADDR>;
 		};
 
 		/*

diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index 9d0463d..9c80283 100644
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c

@@ -68,6 +68,10 @@
 
 #define MAP_DEVICE1	MAP_REGION_FLAT(DEVICE1_BASE,			\
 					DEVICE1_SIZE,			\
+					MT_DEVICE | MT_RW | EL3_PAS)
+
+#define MAP_CCN		MAP_REGION_FLAT(CCN_BASE,			\
+					CCN_SIZE,			\
 					MT_DEVICE | MT_RW | MT_SECURE)
 
 #if FVP_GICR_REGION_PROTECTION
@@ -115,7 +119,7 @@
 	V2M_MAP_IOFPGA,
 	MAP_DEVICE0,
 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
-	MAP_DEVICE1,
+	MAP_CCN,
 #endif
 #if TRUSTED_BOARD_BOOT
 	/* To access the Root of Trust Public Key registers. */
@@ -133,7 +137,7 @@
 	V2M_MAP_IOFPGA,
 	MAP_DEVICE0,
 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
-	MAP_DEVICE1,
+	MAP_CCN,
 #endif
 	ARM_MAP_NS_DRAM1,
 #ifdef __aarch64__
@@ -208,6 +212,9 @@
 	MAP_GICD_MEM,
 	MAP_GICR_MEM,
 #else
+#if FVP_INTERCONNECT_DRIVER == FVP_CCN
+	MAP_CCN,
+#endif
 	MAP_DEVICE1,
 #endif /* FVP_GICR_REGION_PROTECTION */
 	ARM_V2M_MAP_MEM_PROTECT,
@@ -254,6 +261,9 @@
 #endif
 	V2M_MAP_IOFPGA,
 	MAP_DEVICE0,
+#if FVP_INTERCONNECT_DRIVER == FVP_CCN
+	MAP_CCN,
+#endif
 	MAP_DEVICE1,
 	{0}
 };
@@ -773,8 +783,8 @@
 	/* Set number of consoles */
 	num_consoles = FVP_RMM_CONSOLE_COUNT;
 
-	/* Set number of device non-coherent address ranges based on DT */
-	num_ncoh_regions = FCONF_GET_PROPERTY(hw_config, pci_props, num_ncoh_regions);
+	/* Set number of device non-coherent address ranges for FVP RevC */
+	num_ncoh_regions = 2;
 
 	/* Set number of SMMUs */
 	num_smmus = FVP_RMM_SMMU_COUNT;
@@ -907,6 +917,11 @@
 	(void)memset((void *)ncoh_region_ptr, 0,
 			sizeof(struct memory_bank) * num_ncoh_regions);
 
+	/* Set number of device non-coherent address ranges based on DT */
+	num_ncoh_regions = FCONF_GET_PROPERTY(hw_config, pci_props, num_ncoh_regions);
+	/* At least 1 PCIe region need to be described in DT */
+	assert((num_ncoh_regions > 0) && (num_ncoh_regions <= 2));
+
 	for (unsigned long i = 0UL; i < num_ncoh_regions; i++) {
 		ncoh_region_ptr[i].base =
 			FCONF_GET_PROPERTY(hw_config, pci_props, ncoh_regions[i].base);
@@ -914,6 +929,17 @@
 			FCONF_GET_PROPERTY(hw_config, pci_props, ncoh_regions[i].size);
 	}
 
+	/*
+	 * Workaround if the DT does not specify the 2nd PCIe region. This code can be
+	 * removed when upstream DT is updated to have 2nd PCIe region.
+	 */
+	if (num_ncoh_regions == 1) {
+		num_ncoh_regions++;
+		/* Add 3GB of 2nd PCIe region */
+		ncoh_region_ptr[1].base = 0x4000000000;
+		ncoh_region_ptr[1].size = 0xc0000000;
+	}
+
 	/* Update checksum */
 	checksum += checksum_calc((uint64_t *)ncoh_region_ptr,
 			sizeof(struct memory_bank) * num_ncoh_regions);

diff --git a/plat/arm/board/fvp/fvp_cpu_pwr.c b/plat/arm/board/fvp/fvp_cpu_pwr.c
index f2771c2..a294534 100644
--- a/plat/arm/board/fvp/fvp_cpu_pwr.c
+++ b/plat/arm/board/fvp/fvp_cpu_pwr.c

@@ -20,8 +20,8 @@
 
 bool check_cpupwrctrl_el1_is_available(void)
 {
-	/* Poupulate list of CPU midr that doesn't support CPUPWRCTL_EL1 */
-	const unsigned int midr_no_cpupwrctl[] = {
+	/* Populate list of CPU midr that doesn't support CPUPWRCTL_EL1 */
+	static const unsigned int midr_no_cpupwrctl[] = {
 		BASE_AEM_MIDR,
 		CORTEX_A35_MIDR,
 		CORTEX_A53_MIDR,

diff --git a/plat/arm/board/fvp/fvp_def.h b/plat/arm/board/fvp/fvp_def.h
index 831eb35..d87be31 100644
--- a/plat/arm/board/fvp/fvp_def.h
+++ b/plat/arm/board/fvp/fvp_def.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -53,12 +53,12 @@
  *  In case of FVP models with CCN, the CCN register space overlaps into
  *  the NSRAM area.
  */
-#if FVP_INTERCONNECT_DRIVER == FVP_CCN
-#define DEVICE1_BASE			UL(0x2e000000)
-#define DEVICE1_SIZE			UL(0x1A00000)
-#else
-#define DEVICE1_BASE			BASE_GICD_BASE
+#define CCN_BASE			UL(0x2e000000)
+#define CCN_SIZE			UL(0x1000000)
 
+/* TODO: this covers gicv5, but macros should be adjusted */
+#if USE_GIC_DRIVER != 5
+#define DEVICE1_BASE			BASE_GICD_BASE
 #if GIC_ENABLE_V4_EXTN
 /* GICv4 mapping: GICD + CORE_COUNT * 256KB */
 #define DEVICE1_SIZE			((BASE_GICR_BASE - BASE_GICD_BASE) + \
@@ -68,10 +68,11 @@
 #define DEVICE1_SIZE			((BASE_GICR_BASE - BASE_GICD_BASE) + \
 					 (PLATFORM_CORE_COUNT * 0x20000))
 #endif /* GIC_ENABLE_V4_EXTN */
-
-#define NSRAM_BASE			UL(0x2e000000)
-#define NSRAM_SIZE			UL(0x10000)
+#else
+#define DEVICE1_BASE			BASE_IWB_BASE
+#define DEVICE1_SIZE			((BASE_IRS_BASE - BASE_IWB_BASE) + SZ_64K)
 #endif
+
 /* Devices in the second GB */
 #define DEVICE2_BASE			UL(0x7fe00000)
 #define DEVICE2_SIZE			UL(0x00200000)
@@ -124,6 +125,15 @@
 #define FVP_SP810_CTRL_TIM2_OV		BIT_32(20)
 #define FVP_SP810_CTRL_TIM3_OV		BIT_32(22)
 
+
+#define NSRAM_BASE			UL(0x2e000000)
+#define NSRAM_SIZE			UL(0x10000)
+/*
+ *  In case of FVP models with CCN, the CCN register space overlaps into
+ *  the NSRAM area.
+ */
+#define CCN_BASE			UL(0x2e000000)
+#define CCN_SIZE			UL(0x1000000)
 /*******************************************************************************
  * GIC & interrupt handling related constants
  ******************************************************************************/
@@ -138,6 +148,9 @@
 #define BASE_GICD_SIZE			UL(0x10000)
 #define BASE_GICR_BASE			UL(0x2f100000)
 
+#define BASE_IWB_BASE			UL(0x2f000000)
+#define BASE_IRS_BASE			UL(0x2f1c0000)
+
 #if GIC_ENABLE_V4_EXTN
 /* GICv4 redistributor size: 256KB */
 #define BASE_GICR_SIZE			UL(0x40000)

diff --git a/plat/arm/board/fvp/fvp_gicv5.c b/plat/arm/board/fvp/fvp_gicv5.c
new file mode 100644
index 0000000..73bd9c5
--- /dev/null
+++ b/plat/arm/board/fvp/fvp_gicv5.c

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/arm/gicv5.h>
+#include <platform_def.h>
+
+/* wire 26 is the timer interrupt. Will be assigned NS by default */
+struct gicv5_wire_props irs0_spis[] = {
+};
+
+struct gicv5_wire_props iwb0_wires[] = {
+};
+
+struct gicv5_irs irss[] = {{
+	.el3_config_frame = BASE_IRS_BASE,
+	.spis = irs0_spis,
+	.num_spis = ARRAY_SIZE(irs0_spis),
+}};
+
+struct gicv5_iwb iwbs[] = {{
+	.config_frame = BASE_IWB_BASE,
+	.wires = iwb0_wires,
+	.num_wires = ARRAY_SIZE(iwb0_wires)
+}};
+
+const struct gicv5_driver_data plat_gicv5_driver_data = {
+	.irss = irss,
+	.iwbs = iwbs,
+	.num_irss = ARRAY_SIZE(irss),
+	.num_iwbs = ARRAY_SIZE(iwbs)
+};
+
+void fvp_gic_driver_pre_init(void)
+{
+}
+
+void fvp_pcpu_init(void)
+{
+}

diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index b90ba37..002674c 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h

@@ -93,15 +93,6 @@
 #define FVP_DRAM6_SIZE	ULL(0x7800000000000) /* 1920 TB */
 #define FVP_DRAM6_END	(FVP_DRAM6_BASE + FVP_DRAM6_SIZE - 1U)
 
-/* Range of kernel DTB load address */
-#define FVP_DTB_DRAM_MAP_START		ULL(0x82000000)
-#define FVP_DTB_DRAM_MAP_SIZE		ULL(0x02000000)	/* 32 MB */
-
-#define ARM_DTB_DRAM_NS			MAP_REGION_FLAT(		\
-					FVP_DTB_DRAM_MAP_START,		\
-					FVP_DTB_DRAM_MAP_SIZE,		\
-					MT_MEMORY | MT_RO | MT_NS)
-
 /*
  * On the FVP platform when using the EL3 SPMC implementation allocate the
  * datastore for tracking shared memory descriptors in the TZC DRAM section
@@ -509,16 +500,19 @@
 
 /*
  * Maximum size of Event Log buffer used in Measured Boot Event Log driver
+ * TODO: calculate maximum EventLog size using the calculation:
+ * Maximum size of Event Log * Number of images
  */
-#if ENABLE_RME && (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd))
-/* Account for additional measurements of secure partitions and SPM. */
-#define	PLAT_ARM_EVENT_LOG_MAX_SIZE		UL(0x800)
-#else
-#if defined(IMAGE_BL1) && TRANSFER_LIST
+#if (defined(SPD_spmd)) || (ENABLE_RME && (defined(SPD_tspd) || defined(SPD_opteed)))
+/*
+ * Account for additional measurements of secure partitions and SPM.
+ * Also, account for OP-TEE running with maximum number of SPs.
+ */
+#define PLAT_ARM_EVENT_LOG_MAX_SIZE		UL(0x800)
+#elif defined(IMAGE_BL1) && TRANSFER_LIST
 #define PLAT_ARM_EVENT_LOG_MAX_SIZE		UL(0x200)
 #else
-#define	PLAT_ARM_EVENT_LOG_MAX_SIZE		UL(0x400)
-#endif
+#define PLAT_ARM_EVENT_LOG_MAX_SIZE		UL(0x400)
 #endif
 
 /*

diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 8e8870c..ea1b7e7 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk

@@ -22,13 +22,6 @@
 # only; enable redistributor frames of all CPU cores by default.
 FVP_GICR_REGION_PROTECTION	:= 0
 
-ifeq (${HW_ASSISTED_COHERENCY}, 0)
-FVP_DT_PREFIX			:= fvp-base-gicv3-psci
-else
-FVP_DT_PREFIX			:= fvp-base-gicv3-psci-dynamiq
-endif
-# fdts is wrong otherwise
-
 # Size (in kilobytes) of the Trusted SRAM region to utilize when building for
 # the FVP platform.
 ifeq (${ENABLE_RME},1)
@@ -137,7 +130,26 @@
 GICV3_OVERRIDE_DISTIF_PWR_OPS	:=	1
 
 FVP_SECURITY_SOURCES += plat/arm/board/fvp/fvp_gicv3.c
+ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),)
+BL31_SOURCES		+=	plat/arm/board/fvp/fconf/fconf_gicv3_config_getter.c
+endif
 
+ifeq (${HW_ASSISTED_COHERENCY}, 0)
+FVP_DT_PREFIX			:= fvp-base-gicv3-psci
+else
+FVP_DT_PREFIX			:= fvp-base-gicv3-psci-dynamiq
+endif
+else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV5)
+USE_GIC_DRIVER		:=	5
+ENABLE_FEAT_GCIE	:=	1
+BL31_SOURCES		+=	plat/arm/board/fvp/fvp_gicv5.c
+FVP_DT_PREFIX		:=	"FVP does not provide a GICv5 dts yet"
+ifneq ($(SPD),none)
+        $(error Error: GICv5 is not compatible with SPDs)
+endif
+ifeq ($(ENABLE_RME),1)
+       $(error Error: GICv5 is not compatible with RME)
+endif
 else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2)
 USE_GIC_DRIVER		:=	2
 
@@ -359,6 +371,10 @@
 $(eval FVP_HW_CONFIG	:=	${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS)))
 HW_CONFIG		:=	${FVP_HW_CONFIG}
 
+# Allow hw_config's secondary-load-address in the DT to be changed
+FVP_HW_CONFIG_ADDR	?=	0x82000000
+DTC_CPPFLAGS		+=	-DFVP_HW_CONFIG_ADDR=$(FVP_HW_CONFIG_ADDR)
+
 # Set default initrd base 128MiB offset of the default kernel address in FVP
 INITRD_BASE		?=	0x90000000
 

diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index c94761a..53fe806 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk

@@ -79,6 +79,15 @@
 $(eval $(call assert_boolean,ARM_BL31_IN_DRAM))
 $(eval $(call add_define,ARM_BL31_IN_DRAM))
 
+# Macro to enable ACS SMC handler
+PLAT_ARM_ACS_SMC_HANDLER	:=	0
+ifeq (${ENABLE_ACS_SMC}, 1)
+PLAT_ARM_ACS_SMC_HANDLER	:=	1
+endif
+
+# Build macro necessary for branching to ACS tests
+$(eval $(call add_define,PLAT_ARM_ACS_SMC_HANDLER))
+
 # As per CCA security model, all root firmware must execute from on-chip secure
 # memory. This means we must not run BL31 from TZC-protected DRAM.
 ifeq (${ARM_BL31_IN_DRAM},1)
@@ -305,6 +314,11 @@
 				plat/arm/common/arm_topology.c			\
 				plat/common/plat_psci_common.c
 
+ifeq (${PLAT_ARM_ACS_SMC_HANDLER},1)
+BL31_SOURCES		+=	plat/arm/common/plat_acs_smc_handler.c		\
+				${VENDOR_EL3_SRCS}
+endif
+
 ifeq (${TRANSFER_LIST}, 1)
 	include lib/transfer_list/transfer_list.mk
 	TRANSFER_LIST_SOURCES += plat/arm/common/arm_transfer_list.c

diff --git a/plat/arm/common/plat_acs_smc_handler.c b/plat/arm/common/plat_acs_smc_handler.c
new file mode 100644
index 0000000..6f96874
--- /dev/null
+++ b/plat/arm/common/plat_acs_smc_handler.c

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2025, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <stdint.h>
+#include <plat/arm/common/plat_acs_smc_handler.h>
+
+/*
+ * Placeholder function for handling ACS SMC calls.
+ * return 0  till the handling is done.
+ */
+uintptr_t plat_arm_acs_smc_handler(unsigned int smc_fid, uint64_t services,
+		 uint64_t arg0, uint64_t arg1, uint64_t arg2, void *handle)
+{
+	WARN("Unimplemented ACS Call: 0x%x\n", smc_fid);
+	SMC_RET1(handle, SMC_UNK);
+}

diff --git a/plat/common/plat_gicv5.c b/plat/common/plat_gicv5.c
new file mode 100644
index 0000000..e445886
--- /dev/null
+++ b/plat/common/plat_gicv5.c

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2025, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <bl31/interrupt_mgmt.h>
+#include <drivers/arm/gicv5.h>
+
+uint32_t plat_ic_get_pending_interrupt_type(void)
+{
+	return gicv5_get_pending_interrupt_type();
+}
+
+bool plat_ic_has_interrupt_type(unsigned int type)
+{
+	return gicv5_has_interrupt_type(type);
+}

diff --git a/plat/intel/soc/agilex/bl31_plat_setup.c b/plat/intel/soc/agilex/bl31_plat_setup.c
index a3c3545..dabe865 100644
--- a/plat/intel/soc/agilex/bl31_plat_setup.c
+++ b/plat/intel/soc/agilex/bl31_plat_setup.c

@@ -67,6 +67,11 @@
 	mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY);
 	console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK,
 		PLAT_BAUDRATE, &console);
+
+	/* Enable TF-A BL31 logs when running from non-secure world also. */
+	console_set_scope(&console,
+		(CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH));
+
 	/*
 	 * Check params passed from BL31 should not be NULL,
 	 */

diff --git a/plat/intel/soc/agilex5/bl31_plat_setup.c b/plat/intel/soc/agilex5/bl31_plat_setup.c
index 9cf1e11..66e0ea5 100644
--- a/plat/intel/soc/agilex5/bl31_plat_setup.c
+++ b/plat/intel/soc/agilex5/bl31_plat_setup.c

@@ -217,9 +217,11 @@
 	NOTICE("SOCFPGA: CPU ID = %x\n", cpuid);
 	INFO("SOCFPGA: Invalidate Data cache\n");
 	invalidate_dcache_all();
-
 	/* Invalidate for NS EL2 and EL1 */
 	invalidate_cache_low_el();
+
+	NOTICE("SOCFPGA: Setting CLUSTERECTRL_EL1\n");
+	setup_clusterectlr_el1();
 }
 
 /* Get non-secure image entrypoint for BL33. Zephyr and Linux */
@@ -303,6 +305,22 @@
 	mmio_write_32(AGX5_PWRMGR(MPU_PCHCTLR), pch_cpu);
 }
 
+void setup_clusterectlr_el1(void)
+{
+	uint64_t value = 0;
+
+	/* Read CLUSTERECTLR_EL1 */
+	asm volatile("mrs %0, S3_0_C15_C3_4" : "=r"(value));
+
+	/* Disable broadcasting atomics */
+	value |= 0x80; /* set bit 7 */
+	/* Disable sending data with clean evicts */
+	value &= 0xFFFFBFFF; /* Mask out bit 14 */
+
+	/* Write CLUSTERECTLR_EL1 */
+	asm volatile("msr S3_0_C15_C3_4, %0" :: "r"(value));
+}
+
 void bl31_plat_runtime_setup(void)
 {
 	/* Dummy override function. */

diff --git a/plat/intel/soc/agilex5/include/agilex5_system_manager.h b/plat/intel/soc/agilex5/include/agilex5_system_manager.h
index 8c86ab1..f4b53e8 100644
--- a/plat/intel/soc/agilex5/include/agilex5_system_manager.h
+++ b/plat/intel/soc/agilex5/include/agilex5_system_manager.h

@@ -160,6 +160,11 @@
 #define SOCFPGA_ECC_QSPI_ECC_STARTACC					0x7C
 #define SOCFPGA_ECC_QSPI_ECC_WDCTRL					0x80
 
+/* IOSSM mailbox address */
+#define IOSSM_CMD_PARAM							0x18400438
+#define IOSSM_CMD_TRIG_OP						0x1840043C
+#define IOSSM_CMD_RESP_STATUS						0x1840045C
+
 #define DMA0_STREAM_CTRL_REG						0x10D1217C
 #define DMA1_STREAM_CTRL_REG						0x10D12180
 #define SDM_STREAM_CTRL_REG						0x10D12184

diff --git a/plat/intel/soc/agilex5/soc/agilex5_ddr.c b/plat/intel/soc/agilex5/soc/agilex5_ddr.c
index 0d60324..acf7528 100644
--- a/plat/intel/soc/agilex5/soc/agilex5_ddr.c
+++ b/plat/intel/soc/agilex5/soc/agilex5_ddr.c

@@ -297,7 +297,7 @@
 	bool full_mem_init = false;
 	phys_size_t hw_ddr_size;
 	phys_size_t config_ddr_size;
-	struct io96b_info io96b_ctrl;
+	struct io96b_info io96b_ctrl = {0};
 	enum reset_type reset_t = get_reset_type(mmio_read_32(SOCFPGA_SYSMGR(
 						BOOT_SCRATCH_COLD_3)));
 	bool is_dualport = hoff_ptr->ddr_config & BIT(0);

diff --git a/plat/intel/soc/common/include/socfpga_fcs.h b/plat/intel/soc/common/include/socfpga_fcs.h
index f92678f..21d9b66 100644
--- a/plat/intel/soc/common/include/socfpga_fcs.h
+++ b/plat/intel/soc/common/include/socfpga_fcs.h

@@ -76,6 +76,10 @@
 #define FCS_MAX_DATA_SIZE					0x20000000	/* 512 MB */
 #define FCS_MIN_DATA_SIZE					0x8	/* 8 Bytes */
 
+#define FCS_AES_DATA_SIZE_CHECK(x)				(((x >= FCS_AES_MIN_DATA_SIZE) && \
+								  (x <= FCS_AES_MAX_DATA_SIZE)) ? \
+								  true : false)
+
 #define FCS_GET_DIGEST_CMD_MAX_WORD_SIZE			7U
 #define FCS_GET_DIGEST_RESP_MAX_WORD_SIZE			19U
 #define FCS_MAC_VERIFY_CMD_MAX_WORD_SIZE			23U
@@ -362,7 +366,7 @@
 				uint32_t session_id, uint32_t context_id,
 				uint64_t src_addr, uint32_t src_size,
 				uint64_t dst_addr, uint32_t dst_size,
-				uint32_t aad_size, uint8_t is_finalised,
+				uint32_t padding_size, uint8_t is_finalised,
 				uint32_t *send_id, uint64_t smmu_src_addr,
 				uint64_t smmu_dst_addr);
 

diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h
index f965b7d..4da318b 100644
--- a/plat/intel/soc/common/include/socfpga_mailbox.h
+++ b/plat/intel/soc/common/include/socfpga_mailbox.h

@@ -309,7 +309,7 @@
 				((client_id << MBOX_CLIENT_ID_SHIFT) |	 \
 				(job_id << MBOX_JOB_ID_SHIFT) |		 \
 				(args_len << MBOX_CMD_LEN_SHIFT) |	 \
-				(indirect << MBOX_CMD_LEN_SHIFT) |	 \
+				(indirect << MBOX_INDIRECT_SHIFT) |	 \
 				cmd)
 
 #define FLAG_SDM_RESPONSE_IS_VALID			BIT(0)
@@ -362,7 +362,7 @@
 
 /* SDM client callback template */
 typedef uint8_t (*sdm_command_callback)(void *resp, void *cmd,
-					uint32_t *ret_args);
+					uint64_t *ret_args);
 
 /* SDM command data structure */
 typedef struct sdm_command {
@@ -394,7 +394,7 @@
 			      sdm_command_callback cb, uint32_t *cb_args,
 			      uint32_t cb_args_len);
 
-int mailbox_response_poll_v3(uint8_t client_id, uint8_t job_id, uint32_t *ret_args,
+int mailbox_response_poll_v3(uint8_t client_id, uint8_t job_id, uint64_t *ret_args,
 			     uint32_t *ret_args_size);
 
 int mailbox_response_poll_on_intr_v3(uint8_t *client_id, uint8_t *job_id,

diff --git a/plat/intel/soc/common/include/socfpga_private.h b/plat/intel/soc/common/include/socfpga_private.h
index fbe18c3..782b2b5 100644
--- a/plat/intel/soc/common/include/socfpga_private.h
+++ b/plat/intel/soc/common/include/socfpga_private.h

@@ -65,4 +65,6 @@
 
 void plat_secondary_cpus_bl31_entry(void);
 
+void setup_clusterectlr_el1(void);
+
 #endif /* SOCFPGA_PRIVATE_H */

diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h
index 7f96adb..9e06397 100644
--- a/plat/intel/soc/common/include/socfpga_sip_svc.h
+++ b/plat/intel/soc/common/include/socfpga_sip_svc.h

@@ -153,6 +153,9 @@
 /* ATF build version */
 #define INTEL_SIP_SMC_ATF_BUILD_VER					0xC200009B
 
+/* IO96B ECC Error Injection */
+#define INTEL_SIP_SMC_INJECT_IO96B_ECC_ERR				0xC200009C
+
 #define INTEL_SIP_SMC_FCS_SHA_MODE_MASK					0xF
 #define INTEL_SIP_SMC_FCS_DIGEST_SIZE_MASK				0xF
 #define INTEL_SIP_SMC_FCS_DIGEST_SIZE_OFFSET				4U
@@ -163,6 +166,8 @@
 #define SYSMGR_ECC_DBE_COLD_RST_MASK					(SYSMGR_ECC_OCRAM_MASK |\
 									SYSMGR_ECC_DDR0_MASK |\
 									SYSMGR_ECC_DDR1_MASK)
+#define IOSSM_ECC_ERR_INJ_DELAY_USECS					(40U)
+#define IOSSM_CMD_STATUS_RESP_READY					BIT(0)
 
 /* Non-mailbox SMC Call */
 #define INTEL_SIP_SMC_SVC_VERSION					0xC2000200
@@ -255,6 +260,12 @@
 #define SMC_RET_ARGS_FOUR							(4)
 #define SMC_RET_ARGS_FIVE							(5)
 #define SMC_RET_ARGS_SIX							(6)
+#define SMC_RET_ARGS_SEVEN							(7)
+#define SMC_RET_ARGS_EIGHT							(8)
+#define SMC_RET_ARGS_NINE							(9)
+#define SMC_RET_ARGS_TEN							(10)
+
+#define MBOX_GEN_CMD_MAX_WORDS							(0x1000)
 
 /*
  * SiP SVC Version3 SMC Functions IDs
@@ -278,6 +289,14 @@
 #define ALTERA_SIP_SMC_ASYNC_HWMON_READTEMP					(0x420000E8)
 #define ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT					(0x420000E9)
 
+/* RSU related commands */
+#define ALTERA_SIP_SMC_ASYNC_RSU_GET_SPT					(0x420000EA)
+#define ALTERA_SIP_SMC_ASYNC_RSU_GET_STATUS					(0x420000EB)
+#define ALTERA_SIP_SMC_ASYNC_RSU_NOTIFY						(0x420000EC)
+
+/* V3 Generic mailbox command. */
+#define ALTERA_SIP_SMC_ASYNC_GEN_MBOX_CMD					(0x420000EE)
+
 /* FCS crypto service VAB/SDOS commands */
 #define ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER					(0x4200012C)
 #define ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT				(0x4200012D)
@@ -344,6 +363,8 @@
 
 #define GET_CLIENT_ID(x)							(((x) & 0xF0) >> 4)
 #define GET_JOB_ID(x)								((x) & 0x0F)
+#define GET_ADDR64(high, low)							(((uint64_t)(high) \
+										   << 32) | (low))
 #endif	/* SIP_SVC_V3 */
 
 #endif /* SOCFPGA_SIP_SVC_H */

diff --git a/plat/intel/soc/common/sip/socfpga_sip_fcs.c b/plat/intel/soc/common/sip/socfpga_sip_fcs.c
index b9c7b59..507a9e9 100644
--- a/plat/intel/soc/common/sip/socfpga_sip_fcs.c
+++ b/plat/intel/soc/common/sip/socfpga_sip_fcs.c

@@ -25,7 +25,7 @@
 static fcs_crypto_service_data fcs_ecdsa_get_pubkey_param;
 static fcs_crypto_service_data fcs_ecdh_request_param;
 
-uint8_t fcs_send_cert_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_send_cert_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
 {
 	uint8_t ret_args_len = 0U;
 	sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -42,7 +42,7 @@
 	return ret_args_len;
 }
 
-uint8_t fcs_cntr_set_preauth_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cntr_set_preauth_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
 {
 	uint8_t ret_args_len = 0U;
 	sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -57,7 +57,7 @@
 	return ret_args_len;
 }
 
-uint8_t fcs_get_attest_cert_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_get_attest_cert_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
 {
 	uint8_t ret_args_len = 0U;
 	sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -74,7 +74,7 @@
 	return ret_args_len;
 }
 
-uint8_t fcs_hkdf_request_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_hkdf_request_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
 {
 	uint8_t ret_args_len = 0U;
 	sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -92,7 +92,7 @@
 	return ret_args_len;
 }
 
-uint8_t fcs_create_cert_reload_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_create_cert_reload_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
 {
 	uint8_t ret_args_len = 0U;
 	sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -107,7 +107,7 @@
 	return ret_args_len;
 }
 
-uint8_t fcs_cs_get_digest_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_get_digest_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
 {
 	uint8_t ret_args_len = 0U;
 	sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -124,7 +124,7 @@
 	return ret_args_len;
 }
 
-uint8_t fcs_cs_mac_verify_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_mac_verify_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
 {
 	uint8_t ret_args_len = 0U;
 	sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -144,7 +144,7 @@
 	return ret_args_len;
 }
 
-uint8_t fcs_cs_hash_sign_req_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_hash_sign_req_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
 {
 	uint8_t ret_args_len = 0U;
 	sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -162,7 +162,7 @@
 	return ret_args_len;
 }
 
-uint8_t fcs_cs_hash_sig_verify_req_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_hash_sig_verify_req_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
 {
 	uint8_t ret_args_len = 0U;
 	sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -180,7 +180,7 @@
 	return ret_args_len;
 }
 
-uint8_t fcs_cs_aes_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_aes_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
 {
 	uint8_t ret_args_len = 0U;
 	sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -198,7 +198,7 @@
 	return ret_args_len;
 }
 
-uint8_t fcs_cs_data_sign_req_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_data_sign_req_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
 {
 	uint8_t ret_args_len = 0U;
 	sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -215,7 +215,7 @@
 	return ret_args_len;
 }
 
-uint8_t fcs_sdos_crypto_request_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_sdos_crypto_request_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
 {
 	uint8_t ret_args_len = 0U;
 	sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -233,7 +233,7 @@
 	return ret_args_len;
 }
 
-uint8_t fcs_cs_get_public_key_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_get_public_key_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
 {
 	uint8_t ret_args_len = 0U;
 	sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -251,7 +251,7 @@
 	return ret_args_len;
 }
 
-uint8_t fcs_cs_data_sig_verify_req_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_data_sig_verify_req_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
 {
 	uint8_t ret_args_len = 0U;
 	sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -268,7 +268,7 @@
 	return ret_args_len;
 }
 
-uint8_t fcs_cs_ecdh_request_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t fcs_cs_ecdh_request_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
 {
 	uint8_t ret_args_len = 0U;
 	sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -304,6 +304,17 @@
 	}
 }
 
+/* As of now used on only Agilex5 platform. */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+static bool is_16_bytes_aligned(uint32_t data)
+{
+	if ((data % (MBOX_WORD_BYTE * 4U)) != 0U)
+		return false;
+	else
+		return true;
+}
+#endif
+
 static bool is_32_bytes_aligned(uint32_t data)
 {
 	if ((data % (8U * MBOX_WORD_BYTE)) != 0U) {
@@ -2708,7 +2719,7 @@
 				uint32_t session_id, uint32_t context_id,
 				uint64_t src_addr, uint32_t src_size,
 				uint64_t dst_addr, uint32_t dst_size,
-				uint32_t aad_size, uint8_t is_finalised,
+				uint32_t padding_size, uint8_t is_finalised,
 				uint32_t *send_id, uint64_t smmu_src_addr,
 				uint64_t smmu_dst_addr)
 {
@@ -2719,30 +2730,55 @@
 	uint32_t fcs_aes_crypt_payload[FCS_AES_CMD_MAX_WORD_SIZE];
 	uint32_t src_addr_sdm = (uint32_t)src_addr;
 	uint32_t dst_addr_sdm = (uint32_t)dst_addr;
+	bool is_src_size_aligned;
+	bool is_dst_size_aligned;
+	bool is_src_size_valid;
+	bool is_dst_size_valid;
 
 	if (fcs_aes_init_payload.session_id != session_id ||
 		fcs_aes_init_payload.context_id != context_id) {
 		return INTEL_SIP_SMC_STATUS_REJECTED;
 	}
+
+	/* Default source and destination size align check, 32 bytes alignment. */
+	is_src_size_aligned = is_32_bytes_aligned(src_size);
+	is_dst_size_aligned = is_32_bytes_aligned(dst_size);
+	is_src_size_valid = FCS_AES_DATA_SIZE_CHECK(src_size);
+	is_dst_size_valid = FCS_AES_DATA_SIZE_CHECK(dst_size);
+
+	/*
+	 * Get the requested block mode.
+	 * On the Agilex5 platform with GCM and GCM-GHASH modes, the source and destination size
+	 * should be in multiples of 16 bytes. For other platforms and other modes, it should be
+	 * in multiples of 32 bytes.
+	 */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+	uint32_t block_mode = fcs_aes_init_payload.crypto_param[0] & FCS_CRYPTO_BLOCK_MODE_MASK;
+
+	if ((block_mode == FCS_CRYPTO_GCM_MODE) ||
+	    (block_mode == FCS_CRYPTO_GCM_GHASH_MODE)) {
+		is_src_size_aligned = is_16_bytes_aligned(src_size);
+		is_dst_size_aligned = is_16_bytes_aligned(dst_size);
+		/* The size validity here is, should be 0 or multiples of 16 bytes. */
+		is_src_size_valid = is_16_bytes_aligned(src_size);
+		is_dst_size_valid = is_16_bytes_aligned(dst_size);
+	}
+#endif
 
 	if ((!is_8_bytes_aligned(src_addr)) ||
-		(!is_32_bytes_aligned(src_size)) ||
+		(!is_src_size_aligned) ||
 		(!is_address_in_ddr_range(src_addr, src_size))) {
 		return INTEL_SIP_SMC_STATUS_REJECTED;
 	}
 
 	if ((!is_8_bytes_aligned(dst_addr)) ||
-		(!is_32_bytes_aligned(dst_size)) ||
+		(!is_dst_size_aligned) ||
 		(!is_address_in_ddr_range(dst_addr, dst_size))) {
 		return INTEL_SIP_SMC_STATUS_REJECTED;
 	}
 
-	if ((dst_size > FCS_AES_MAX_DATA_SIZE ||
-		dst_size < FCS_AES_MIN_DATA_SIZE) ||
-		(src_size > FCS_AES_MAX_DATA_SIZE ||
-		src_size < FCS_AES_MIN_DATA_SIZE)) {
+	if (!is_src_size_valid || !is_dst_size_valid)
 		return INTEL_SIP_SMC_STATUS_REJECTED;
-	}
 
 	/* Prepare crypto header*/
 	flag = 0;
@@ -2802,11 +2838,14 @@
 	fcs_aes_crypt_payload[i] = dst_size;
 	i++;
 
-	/* Additional Authenticated Data size */
-	if (aad_size > 0) {
-		fcs_aes_crypt_payload[i] = aad_size;
+	/* Padding data size, only on Agilex5 with GCM and GCM-GHASH modes. */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+	if ((block_mode == FCS_CRYPTO_GCM_MODE) ||
+	    (block_mode == FCS_CRYPTO_GCM_GHASH_MODE)) {
+		fcs_aes_crypt_payload[i] = padding_size;
 		i++;
 	}
+#endif
 
 	status = ((smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_UPDATE) ||
 		  (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE)) ?
@@ -2828,7 +2867,7 @@
 			sizeof(fcs_aes_init_payload));
 	}
 
-	if (status < 0U) {
+	if (status < 0) {
 		return INTEL_SIP_SMC_STATUS_ERROR;
 	}
 

diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c
index 3b3b479..bf1b7fb 100644
--- a/plat/intel/soc/common/soc/socfpga_mailbox.c
+++ b/plat/intel/soc/common/soc/socfpga_mailbox.c

@@ -1442,7 +1442,7 @@
 }
 
 int mailbox_response_poll_v3(uint8_t client_id, uint8_t job_id,
-			     uint32_t *ret_args, uint32_t *ret_args_len)
+			     uint64_t *ret_args, uint32_t *ret_args_len)
 {
 	sdm_command_t *cmd_desc = NULL;
 	sdm_response_t *resp_desc = NULL;

diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index f4a3ea0..ff19e23 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c

@@ -9,6 +9,7 @@
 #include <assert.h>
 #include <common/debug.h>
 #include <common/runtime_svc.h>
+#include <drivers/delay_timer.h>
 #include <lib/mmio.h>
 #include <tools_share/uuid.h>
 
@@ -799,10 +800,26 @@
 	}
 	return INTEL_SIP_SMC_STATUS_OK;
 }
+
+static void intel_inject_io96b_ecc_err(const uint32_t *syndrome, const uint32_t command)
+{
+	volatile uint64_t atf_ddr_buffer;
+	volatile uint64_t val;
+
+	mmio_write_32(IOSSM_CMD_PARAM, *syndrome);
+	mmio_write_32(IOSSM_CMD_TRIG_OP, command);
+	udelay(IOSSM_ECC_ERR_INJ_DELAY_USECS);
+	atf_ddr_buffer = 0xCAFEBABEFEEDFACE;	/* Write data */
+	memcpy_s((void *)&val, sizeof(val),
+		 (void *)&atf_ddr_buffer, sizeof(atf_ddr_buffer));
+
+	/* Clear response_ready BIT0 of status_register before sending next command. */
+	mmio_clrbits_32(IOSSM_CMD_RESP_STATUS, IOSSM_CMD_STATUS_RESP_READY);
+}
 #endif
 
 #if SIP_SVC_V3
-uint8_t sip_smc_cmd_cb_ret2(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t sip_smc_cmd_cb_ret2(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
 {
 	uint8_t ret_args_len = 0U;
 	sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -816,7 +833,7 @@
 	return ret_args_len;
 }
 
-uint8_t sip_smc_cmd_cb_ret3(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t sip_smc_cmd_cb_ret3(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
 {
 	uint8_t ret_args_len = 0U;
 	sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -831,7 +848,7 @@
 	return ret_args_len;
 }
 
-uint8_t sip_smc_ret_nbytes_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t sip_smc_ret_nbytes_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
 {
 	uint8_t ret_args_len = 0U;
 	sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -848,7 +865,7 @@
 	return ret_args_len;
 }
 
-uint8_t sip_smc_get_chipid_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+uint8_t sip_smc_get_chipid_cb(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
 {
 	uint8_t ret_args_len = 0U;
 	sdm_response_t *resp = (sdm_response_t *)resp_desc;
@@ -866,35 +883,201 @@
 	return ret_args_len;
 }
 
+uint8_t sip_smc_cmd_cb_rsu_status(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
+{
+	uint8_t ret_args_len = 0U;
+	uint32_t retry_counter = ~0U;
+	uint32_t failure_source = 0U;
+	sdm_response_t *resp = (sdm_response_t *)resp_desc;
+	sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+	(void)cmd;
+	/* Get the failure source and current image retry counter value from the response. */
+	failure_source = resp->resp_data[5] & RSU_VERSION_ACMF_MASK;
+	retry_counter = resp->resp_data[8];
+
+	if ((retry_counter != ~0U) && (failure_source == 0U))
+		resp->resp_data[5] |= RSU_VERSION_ACMF;
+
+	ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+	ret_args[ret_args_len++] = resp->err_code;
+	/* Current CMF */
+	ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[1], resp->resp_data[0]);
+	/* Last Failing CMF Address */
+	ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[3], resp->resp_data[2]);
+	/* Config State */
+	ret_args[ret_args_len++] = resp->resp_data[4];
+	/* Version */
+	ret_args[ret_args_len++] = (GENMASK(16, 0) & resp->resp_data[5]);
+	/* Failure Source */
+	ret_args[ret_args_len++] = ((GENMASK(32, 17) & resp->resp_data[5]) >> 16);
+	/* Error location */
+	ret_args[ret_args_len++] = resp->resp_data[6];
+	/* Error details */
+	ret_args[ret_args_len++] = resp->resp_data[7];
+	/* Current image retry counter */
+	ret_args[ret_args_len++] = resp->resp_data[8];
+
+	return ret_args_len;
+}
+
-static uintptr_t smc_ret(void *handle, uint32_t *ret_args, uint32_t ret_args_len)
+uint8_t sip_smc_cmd_cb_rsu_spt(void *resp_desc, void *cmd_desc, uint64_t *ret_args)
 {
+	uint8_t ret_args_len = 0U;
+	sdm_response_t *resp = (sdm_response_t *)resp_desc;
+	sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+	(void)cmd;
+
+	ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+	ret_args[ret_args_len++] = resp->err_code;
+	/* Sub Partition Table (SPT) 0 address */
+	ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[0], resp->resp_data[1]);
+	/* Sub Partition Table (SPT) 1 address */
+	ret_args[ret_args_len++] = GET_ADDR64(resp->resp_data[2], resp->resp_data[3]);
+
+	return ret_args_len;
+}
+
+static uintptr_t smc_ret(void *handle, uint64_t *ret_args, uint32_t ret_args_len)
+{
+
 	switch (ret_args_len) {
 	case SMC_RET_ARGS_ONE:
+		VERBOSE("SVC V3: %s: x0 0x%lx\n", __func__, ret_args[0]);
 		SMC_RET1(handle, ret_args[0]);
 		break;
 
 	case SMC_RET_ARGS_TWO:
+		VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx\n", __func__, ret_args[0], ret_args[1]);
 		SMC_RET2(handle, ret_args[0], ret_args[1]);
 		break;
 
 	case SMC_RET_ARGS_THREE:
+		VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx\n",
+			__func__, ret_args[0],	ret_args[1], ret_args[2]);
 		SMC_RET3(handle, ret_args[0], ret_args[1], ret_args[2]);
 		break;
 
 	case SMC_RET_ARGS_FOUR:
+		VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx\n",
+			__func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3]);
 		SMC_RET4(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3]);
 		break;
 
 	case SMC_RET_ARGS_FIVE:
+		VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx\n",
+			__func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]);
 		SMC_RET5(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]);
 		break;
 
+	case SMC_RET_ARGS_SIX:
+		VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx x3 0x%lx, x4 0x%lx x5 0x%lx\n",
+			__func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+			ret_args[5]);
+		SMC_RET6(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+			 ret_args[5]);
+		break;
+
+	case SMC_RET_ARGS_SEVEN:
+		VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\t"
+			"x6 0x%lx\n",
+			__func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+			ret_args[5], ret_args[6]);
+		SMC_RET7(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+			 ret_args[5], ret_args[6]);
+		break;
+
+	case SMC_RET_ARGS_EIGHT:
+		VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx x5 0x%lx\t"
+			"x6 0x%lx, x7 0x%lx\n",
+			__func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+			ret_args[5], ret_args[6], ret_args[7]);
+		SMC_RET8(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+			 ret_args[5], ret_args[6], ret_args[7]);
+		break;
+
+	case SMC_RET_ARGS_NINE:
+		VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\t"
+			"x6 0x%lx, x7 0x%lx, x8 0x%lx\n",
+			__func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+			ret_args[5], ret_args[6], ret_args[7], ret_args[8]);
+		SMC_RET18(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+			 ret_args[5], ret_args[6], ret_args[7], ret_args[8],
+			 0, 0, 0, 0, 0, 0, 0, 0, 0);
+		break;
+
+	case SMC_RET_ARGS_TEN:
+		VERBOSE("SVC V3: %s: x0 0x%lx, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx x5 0x%lx\t"
+			"x6 0x%lx, x7 0x%lx x8 0x%lx, x9 0x%lx, x10 0x%lx\n",
+			__func__, ret_args[0], ret_args[1], ret_args[2], ret_args[3],
+			ret_args[4], ret_args[5], ret_args[6], ret_args[7], ret_args[8],
+			ret_args[9], ret_args[10]);
+		SMC_RET18(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4],
+			  ret_args[5], ret_args[6], ret_args[7], ret_args[8], ret_args[9],
+			  0, 0, 0, 0, 0, 0, 0, 0);
+		break;
+
 	default:
+		VERBOSE("SVC V3: %s ret_args_len is wrong, please check %d\n ",
+			__func__, ret_args_len);
 		SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR);
 		break;
 	}
 }
 
+static inline bool is_gen_mbox_cmd_allowed(uint32_t cmd)
+{
+	/* Check if the command is allowed to be executed in generic mbox format */
+	bool is_cmd_allowed = false;
+
+	switch (cmd) {
+	case ALTERA_SIP_SMC_ASYNC_FCS_OPEN_CS_SESSION:
+	case ALTERA_SIP_SMC_ASYNC_FCS_CLOSE_CS_SESSION:
+	case ALTERA_SIP_SMC_ASYNC_FCS_IMPORT_CS_KEY:
+	case ALTERA_SIP_SMC_ASYNC_FCS_EXPORT_CS_KEY:
+	case ALTERA_SIP_SMC_ASYNC_FCS_REMOVE_CS_KEY:
+	case ALTERA_SIP_SMC_ASYNC_FCS_GET_CS_KEY_INFO:
+	case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CS_KEY:
+	case ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT:
+	case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_INIT:
+	case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_UPDATE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_INIT:
+	case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_UPDATE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_INIT:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_FINALIZE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_INIT:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_INIT:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_INIT:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_FINALIZE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_INIT:
+	case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_FINALIZE:
+	case ALTERA_SIP_SMC_ASYNC_FCS_HKDF_REQUEST:
+	case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION_EXT:
+	case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION:
+		/* These commands are not supported in the generic mailbox format. */
+		break;
+
+	default:
+		is_cmd_allowed = true;
+		break;
+	} /* switch */
+
+	return is_cmd_allowed;
+}
+
 /*
  * This function is responsible for handling all SiP SVC V3 calls from the
  * non-secure world.
@@ -929,8 +1112,8 @@
 	switch (smc_fid) {
 	case ALTERA_SIP_SMC_ASYNC_RESP_POLL:
 	{
-		uint32_t ret_args[8] = {0};
-		uint32_t ret_args_len;
+		uint64_t ret_args[16] = {0};
+		uint32_t ret_args_len = 0;
 
 		status = mailbox_response_poll_v3(GET_CLIENT_ID(x1),
 						  GET_JOB_ID(x1),
@@ -1177,6 +1360,111 @@
 		SMC_RET1(handle, status);
 	}
 
+	case ALTERA_SIP_SMC_ASYNC_RSU_GET_SPT:
+	{
+		status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+						   GET_JOB_ID(x1),
+						   MBOX_GET_SUBPARTITION_TABLE,
+						   NULL,
+						   0,
+						   MBOX_CMD_FLAG_CASUAL,
+						   sip_smc_cmd_cb_rsu_spt,
+						   NULL,
+						   0);
+
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_RSU_GET_STATUS:
+	{
+		status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+						   GET_JOB_ID(x1),
+						   MBOX_RSU_STATUS,
+						   NULL,
+						   0,
+						   MBOX_CMD_FLAG_CASUAL,
+						   sip_smc_cmd_cb_rsu_status,
+						   NULL,
+						   0);
+
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_RSU_NOTIFY:
+	{
+		uint32_t notify_code = (uint32_t)x2;
+
+		status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+						   GET_JOB_ID(x1),
+						   MBOX_HPS_STAGE_NOTIFY,
+						   &notify_code,
+						   1U,
+						   MBOX_CMD_FLAG_CASUAL,
+						   sip_smc_cmd_cb_ret2,
+						   NULL,
+						   0);
+
+		SMC_RET1(handle, status);
+	}
+
+	case ALTERA_SIP_SMC_ASYNC_GEN_MBOX_CMD:
+	{
+		/* Filter the required commands here. */
+		if (!is_gen_mbox_cmd_allowed(smc_fid)) {
+			status = INTEL_SIP_SMC_STATUS_REJECTED;
+			SMC_RET1(handle, status);
+		}
+
+		/* Collect all the args passed in, and send the mailbox command. */
+		uint32_t mbox_cmd = (uint32_t)x2;
+		uint32_t *cmd_payload_addr = NULL;
+		uint32_t cmd_payload_len = (uint32_t)x4 / MBOX_WORD_BYTE;
+		uint32_t *resp_payload_addr = NULL;
+		uint32_t resp_payload_len = (uint32_t)x6 / MBOX_WORD_BYTE;
+
+		if ((cmd_payload_len > MBOX_GEN_CMD_MAX_WORDS) ||
+		    (resp_payload_len > MBOX_GEN_CMD_MAX_WORDS)) {
+			ERROR("MBOX: 0x%x: Command/Response payload length exceeds max limit\n",
+				smc_fid);
+			status = INTEL_SIP_SMC_STATUS_REJECTED;
+			SMC_RET1(handle, status);
+		}
+
+		/* Make sure we have valid command payload length and buffer */
+		if (cmd_payload_len != 0U) {
+			cmd_payload_addr = (uint32_t *)x3;
+			if (cmd_payload_addr == NULL) {
+				ERROR("MBOX: 0x%x: Command payload address is NULL\n",
+					smc_fid);
+				status = INTEL_SIP_SMC_STATUS_REJECTED;
+				SMC_RET1(handle, status);
+			}
+		}
+
+		/* Make sure we have valid response payload length and buffer */
+		if (resp_payload_len != 0U) {
+			resp_payload_addr = (uint32_t *)x5;
+			if (resp_payload_addr == NULL) {
+				ERROR("MBOX: 0x%x: Response payload address is NULL\n",
+					smc_fid);
+				status = INTEL_SIP_SMC_STATUS_REJECTED;
+				SMC_RET1(handle, status);
+			}
+		}
+
+		status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+						   GET_JOB_ID(x1),
+						   mbox_cmd,
+						   (uint32_t *)cmd_payload_addr,
+						   cmd_payload_len,
+						   MBOX_CMD_FLAG_CASUAL,
+						   sip_smc_ret_nbytes_cb,
+						   (uint32_t *)resp_payload_addr,
+						   resp_payload_len);
+
+		SMC_RET1(handle, status);
+	}
+
 	case ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT:
 	{
 		uint32_t session_id = (uint32_t)x2;
@@ -2194,6 +2482,12 @@
 		SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, VERSION_MAJOR,
 			 VERSION_MINOR, VERSION_PATCH);
 
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+	case INTEL_SIP_SMC_INJECT_IO96B_ECC_ERR:
+		intel_inject_io96b_ecc_err((uint32_t *)&x1, (uint32_t)x2);
+		SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK);
+#endif
+
 	default:
 		return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
 			cookie, handle, flags);

diff --git a/plat/mediatek/build_helpers/options.mk b/plat/mediatek/build_helpers/options.mk
index 080e735..d2a8fd3 100644
--- a/plat/mediatek/build_helpers/options.mk
+++ b/plat/mediatek/build_helpers/options.mk

@@ -14,6 +14,7 @@
 	CONFIG_MTK_MTCMOS \
 	CONFIG_MTK_PM_ARCH \
 	CONFIG_MTK_PM_SUPPORT \
+	CONFIG_MTK_SMMU_SID \
 	CONFIG_MTK_SMP_EN \
 	CONFIG_MTK_SUPPORT_SYSTEM_SUSPEND \
 	MTK_ADAPTED \

diff --git a/plat/mediatek/common/mtk_bl31_lib.c b/plat/mediatek/common/mtk_bl31_lib.c
new file mode 100644
index 0000000..3428471
--- /dev/null
+++ b/plat/mediatek/common/mtk_bl31_lib.c

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
+
+#include <mtk_bl31_interface.h>
+#include <mtk_sip_svc.h>
+
+int mtk_bl31_map_to_sip_error(enum mtk_bl31_status status)
+{
+	switch (status) {
+	case MTK_BL31_STATUS_SUCCESS:
+		return MTK_SIP_E_SUCCESS;
+	case MTK_BL31_STATUS_INVALID_PARAM:
+		return MTK_SIP_E_INVALID_PARAM;
+	case MTK_BL31_STATUS_NOT_SUPPORTED:
+		return MTK_SIP_E_NOT_SUPPORTED;
+	case MTK_BL31_STATUS_INVALID_RANGE:
+		return MTK_SIP_E_INVALID_RANGE;
+	case MTK_BL31_STATUS_PERMISSION_DENY:
+		return MTK_SIP_E_PERMISSION_DENY;
+	case MTK_BL31_STATUS_LOCK_FAIL:
+		return MTK_SIP_E_LOCK_FAIL;
+	default:
+		ERROR("%s: unknown status: %d\n", __func__, status);
+	}
+
+	return MTK_SIP_E_NOT_SUPPORTED;
+}
+
+int mtk_bl31_mmap_add_dynamic_region(unsigned long long base_pa, size_t size,
+				     enum mtk_bl31_memory_type type)
+{
+	unsigned int attr;
+
+	switch (type) {
+	case MTK_BL31_DEV_RW_SEC:
+		attr = MT_DEVICE | MT_RW | MT_SECURE;
+		break;
+	default:
+		attr = 0;
+		ERROR("%s: unknown memory type %d\n", __func__, type);
+		break;
+	}
+
+	return mmap_add_dynamic_region(base_pa, base_pa, size, attr);
+}
+
+int mtk_bl31_mmap_remove_dynamic_region(uintptr_t base_va, size_t size)
+{
+	return mmap_remove_dynamic_region(base_va, size);
+}

diff --git a/plat/mediatek/common/rules.mk b/plat/mediatek/common/rules.mk
index 6acc731..66ea8b7 100644
--- a/plat/mediatek/common/rules.mk
+++ b/plat/mediatek/common/rules.mk

@@ -8,7 +8,8 @@
 
 MODULE := mtk_common
 
-LOCAL_SRCS-y := ${LOCAL_DIR}/mtk_bl31_setup.c
+LOCAL_SRCS-y := ${LOCAL_DIR}/mtk_bl31_lib.c
+LOCAL_SRCS-y += ${LOCAL_DIR}/mtk_bl31_setup.c
 LOCAL_SRCS-y += ${LOCAL_DIR}/mtk_smc_handlers.c
 LOCAL_SRCS-$(MTK_SIP_KERNEL_BOOT_ENABLE) += ${LOCAL_DIR}/cold_boot.c
 

diff --git a/plat/mediatek/drivers/apusys/mt8196/apusys_security_ctrl_plat.c b/plat/mediatek/drivers/apusys/mt8196/apusys_security_ctrl_plat.c
index a0d21c6..6edf9c6 100644
--- a/plat/mediatek/drivers/apusys/mt8196/apusys_security_ctrl_plat.c
+++ b/plat/mediatek/drivers/apusys/mt8196/apusys_security_ctrl_plat.c

@@ -6,14 +6,11 @@
 
 #define ENABLE_SMPU_PROTECT	(1)
 
-#if ENABLE_SMPU_PROTECT
-#include "emi.h"
-#endif
-
 #include <common/debug.h>
 #include <lib/mmio.h>
 
 #include <apusys_security_ctrl_plat.h>
+#include <mtk_bl31_interface.h>
 
 #define APUSYS_SEC_FW_EMI_REGION	(23)
 
@@ -71,9 +68,10 @@
 int apusys_plat_setup_sec_mem(void)
 {
 #if ENABLE_SMPU_PROTECT
-	return sip_emi_mpu_set_protection(APU_RESERVE_MEMORY >> EMI_MPU_ALIGN_BITS,
-		(APU_RESERVE_MEMORY + APU_RESERVE_SIZE) >> EMI_MPU_ALIGN_BITS,
-		APUSYS_SEC_FW_EMI_REGION);
+	return emi_mpu_set_protection(APU_RESERVE_MEMORY >> EMI_MPU_ALIGN_BITS,
+				      (APU_RESERVE_MEMORY + APU_RESERVE_SIZE) >>
+				      EMI_MPU_ALIGN_BITS,
+				      APUSYS_SEC_FW_EMI_REGION);
 #else
 	INFO("%s: Bypass SMPU protection setup.\n", __func__);
 	return 0;

diff --git a/plat/mediatek/drivers/apusys/mt8196/rules.mk b/plat/mediatek/drivers/apusys/mt8196/rules.mk
index aeb6d3d..67243da 100644
--- a/plat/mediatek/drivers/apusys/mt8196/rules.mk
+++ b/plat/mediatek/drivers/apusys/mt8196/rules.mk

@@ -8,10 +8,6 @@
 
 MODULE := apusys_${MTK_SOC}
 
-ifeq (${CONFIG_MTK_APUSYS_EMI_SUPPORT}, y)
-PLAT_INCLUDES += -I${MTK_PLAT}/drivers/emi/common
-endif
-
 LOCAL_SRCS-y := ${LOCAL_DIR}/apusys_ammu.c
 LOCAL_SRCS-y += ${LOCAL_DIR}/apusys_devapc.c
 LOCAL_SRCS-y += ${LOCAL_DIR}/apusys_power.c

diff --git a/plat/mediatek/drivers/apusys/rules.mk b/plat/mediatek/drivers/apusys/rules.mk
index 24cc79c..f487c11 100644
--- a/plat/mediatek/drivers/apusys/rules.mk
+++ b/plat/mediatek/drivers/apusys/rules.mk

@@ -13,7 +13,6 @@
 PLAT_INCLUDES += -I${LOCAL_DIR} -I${LOCAL_DIR}/${MTK_SOC} -I${LOCAL_DIR}/apusys_rv/2.0
 
 $(eval $(call add_defined_option,CONFIG_MTK_APUSYS_CE_SUPPORT))
-$(eval $(call add_defined_option,CONFIG_MTK_APUSYS_EMI_SUPPORT))
 $(eval $(call add_defined_option,CONFIG_MTK_APUSYS_LOGTOP_SUPPORT))
 $(eval $(call add_defined_option,CONFIG_MTK_APUSYS_RV_APUMMU_SUPPORT))
 $(eval $(call add_defined_option,CONFIG_MTK_APUSYS_RV_COREDUMP_WA_SUPPORT))

diff --git a/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.h b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.h
index 4d99df1..e1ead97 100644
--- a/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.h
+++ b/plat/mediatek/drivers/cpu_pm/cpcv3_2/mt_cpu_pm.h

@@ -71,6 +71,7 @@
 		PER_CPU_PWR_DATA(ctrl, 0, 7); \
 		break; \
 	default: \
+		PER_CPU_PWR_DATA(ctrl, 0, 0); \
 		assert(0); \
 		break; \
 	} })

diff --git a/plat/mediatek/drivers/cpu_qos/mt8196/mtk_cpuqos.c b/plat/mediatek/drivers/cpu_qos/mt8196/mtk_cpuqos.c
new file mode 100644
index 0000000..eb4436c
--- /dev/null
+++ b/plat/mediatek/drivers/cpu_qos/mt8196/mtk_cpuqos.c

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/pm/mtk_pm.h>
+#include <mtk_bl31_interface.h>
+
+static void *cpu_qos_handle_cluster_on_event_cb(const void *arg)
+{
+	return cpu_qos_handle_cluster_on_event(arg);
+}
+
+MT_CPUPM_SUBCRIBE_CLUSTER_PWR_ON(cpu_qos_handle_cluster_on_event_cb);

diff --git a/plat/mediatek/drivers/cpu_qos/mt8196/mtk_cpuqos_stub.c b/plat/mediatek/drivers/cpu_qos/mt8196/mtk_cpuqos_stub.c
new file mode 100644
index 0000000..f3540bd
--- /dev/null
+++ b/plat/mediatek/drivers/cpu_qos/mt8196/mtk_cpuqos_stub.c

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mtk_bl31_interface.h>
+
+void cpu_qos_change_dcc(uint32_t on, uint32_t is_auto)
+{
+}
+
+void *cpu_qos_handle_cluster_on_event(const void *arg)
+{
+	return (void *)arg;
+}

diff --git a/plat/mediatek/drivers/cpu_qos/mt8196/rules.mk b/plat/mediatek/drivers/cpu_qos/mt8196/rules.mk
new file mode 100644
index 0000000..fa12496
--- /dev/null
+++ b/plat/mediatek/drivers/cpu_qos/mt8196/rules.mk

@@ -0,0 +1,16 @@
+#
+# Copyright (c) 2025, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := cpu_qos_$(MTK_SOC)
+
+LOCAL_SRCS-y := $(LOCAL_DIR)/mtk_cpuqos.c
+ifeq ($(MTKLIB_PATH),)
+LOCAL_SRCS-y += $(LOCAL_DIR)/mtk_cpuqos_stub.c
+endif
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))

diff --git a/plat/mediatek/drivers/cpu_qos/rules.mk b/plat/mediatek/drivers/cpu_qos/rules.mk
new file mode 100644
index 0000000..c67a136
--- /dev/null
+++ b/plat/mediatek/drivers/cpu_qos/rules.mk

@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2025, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+SUB_RULES := $(LOCAL_DIR)/$(MTK_SOC)
+
+$(eval $(call INCLUDE_MAKEFILE,$(SUB_RULES)))

diff --git a/plat/mediatek/drivers/emi/common/emi.h b/plat/mediatek/drivers/emi/common/emi.h
deleted file mode 100644
index eb2a0d3..0000000
--- a/plat/mediatek/drivers/emi/common/emi.h
+++ /dev/null

@@ -1,16 +0,0 @@
-/*
- * Copyright (c) 2025, Mediatek Inc. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef EMI_H
-#define EMI_H
-
-#include <stdint.h>
-
-#define EMI_MPU_ALIGN_BITS	12
-
-uint64_t sip_emi_mpu_set_protection(u_register_t start, u_register_t end, u_register_t region);
-
-#endif /* EMI_H */

diff --git a/plat/mediatek/drivers/emi/emi_ctrl.c b/plat/mediatek/drivers/emi/emi_ctrl.c
new file mode 100644
index 0000000..00ac7df
--- /dev/null
+++ b/plat/mediatek/drivers/emi/emi_ctrl.c

@@ -0,0 +1,189 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+
+#include <lib/mtk_init/mtk_init.h>
+#include <mtk_bl31_interface.h>
+#include <mtk_sip_svc.h>
+
+#define NO_PROTECTION	0
+#define SEC_RW		1
+#define SEC_RW_NSEC_R	2
+#define SEC_RW_NSEC_W	3
+#define SEC_R_NSEC_R	4
+#define FORBIDDEN	5
+#define SEC_R_NSEC_RW	6
+
+#define EMIMPU_SET	0
+#define EMIMPU_CLEAR	1
+#define EMIMPU_READ	2
+#define EMIMPU_SLVERR	3
+#define EMIDBG_DUMP	4
+#define EMIDBG_MSG	5
+#define AID_TABLE_SET	6
+#define EMIMPU_CLEAR_MD	7
+#define KP_SET		8
+#define KP_CLEAR	9
+
+#define EMIMPU_READ_SA			0
+#define EMIMPU_READ_EA			1
+#define EMIMPU_READ_APC			2
+#define EMIMPU_READ_ENABLE		3
+#define EMIMPU_READ_AID			4
+#define EMIMPU_CHECK_NS_CPU		5
+#define EMIMPU_CHECK_REGION_INFO	6
+#define EMIMPU_PAGE_BASE_REGION		7
+#define SLBMPU_CLEAR			8
+#define EMIMPU_CHECK_HP_MOD		9
+#define EMI_CLE				10
+#define SLC_PARITY_SELECT		11
+#define SLC_PARITY_CLEAR		12
+
+static uint64_t emi_mpu_read_by_type(unsigned int reg_type, unsigned int region,
+				     unsigned int aid_shift, struct smccc_res *smccc_ret)
+{
+	switch (reg_type) {
+	case EMIMPU_READ_SA:
+		return emi_mpu_read_addr(region, 0x0);
+	case EMIMPU_READ_EA:
+		return emi_mpu_read_addr(region, 0x8);
+	case EMIMPU_READ_ENABLE:
+		return emi_mpu_read_enable(region);
+	case EMIMPU_READ_AID:
+		return emi_mpu_read_aid(region, aid_shift);
+	case EMIMPU_CHECK_REGION_INFO:
+		return emi_mpu_check_region_info(region, &smccc_ret->a1, &smccc_ret->a2);
+	case EMIMPU_CHECK_NS_CPU:
+		return emi_mpu_check_ns_cpu();
+	case EMIMPU_PAGE_BASE_REGION:
+		return emi_mpu_page_base_region();
+	case EMIMPU_CHECK_HP_MOD:
+		return emi_mpu_smc_hp_mod_check();
+	default:
+		return 0;
+	}
+}
+
+static u_register_t sip_emidbg_control(u_register_t op_id,
+				       u_register_t x2,
+				       u_register_t x3,
+				       u_register_t x4,
+				       void *handle,
+				       struct smccc_res *smccc_ret)
+{
+	enum mtk_bl31_status ret;
+
+	switch (op_id) {
+	case EMIDBG_DUMP:
+		return MTK_SIP_E_SUCCESS;
+	case EMIDBG_MSG:
+		return MTK_SIP_E_SUCCESS;
+#ifdef MTK_EMI_MPU_DEBUG
+	case EMIMPU_READ:
+		ret = emi_mpu_read_by_type((unsigned int)x2, (unsigned int)x3,
+					   (unsigned int)x4, smccc_ret);
+		break;
+#endif
+	case EMIMPU_CLEAR_MD:
+		ret = emi_clear_md_violation();
+		break;
+	case KP_CLEAR:
+		ret = emi_kp_clear_violation((unsigned int)x2);
+		break;
+#ifdef CONFIG_MTK_SLB_MPU_CLEAR
+	case SLBMPU_CLEAR:
+		ret = slb_clear_violation((unsigned int)x2);
+		break;
+#endif
+#ifdef CONFIG_MTK_EMI_CLEAR
+	case EMI_CLEAR:
+		ret = emi_clear_violation((unsigned int)x2, (unsigned int)x3);
+		break;
+#endif
+#ifdef CONFIG_MTK_SLC_PARITY
+	case SLC_PARITY_SELECT:
+		ret = slc_parity_select((unsigned int)x2, (unsigned int)x3);
+		break;
+	case SLC_PARITY_CLEAR:
+		ret = slc_parity_clear((unsigned int)x2);
+		break;
+#endif
+	default:
+		return MTK_SIP_E_NOT_SUPPORTED;
+	}
+
+	return mtk_bl31_map_to_sip_error(ret);
+}
+DECLARE_SMC_HANDLER(MTK_SIP_EMIDBG_CONTROL, sip_emidbg_control);
+
+static u_register_t sip_emimpu_control(u_register_t op_id,
+				       u_register_t x2,
+				       u_register_t x3,
+				       u_register_t x4,
+				       void *handle,
+				       struct smccc_res *smccc_ret)
+{
+	enum mtk_bl31_status ret;
+
+	switch (op_id) {
+	case EMIMPU_SET:
+		ret = emi_mpu_set_protection((uint32_t)x2, (uint32_t)x3, (unsigned int)x4);
+		break;
+	case AID_TABLE_SET:
+		ret = emi_mpu_set_aid((unsigned int)x2, (unsigned int)x3);
+		break;
+	case EMIMPU_READ:
+		ret = emi_mpu_read_by_type((unsigned int)x2, (unsigned int)x3,
+					   (unsigned int)x4, smccc_ret);
+		break;
+	case KP_SET:
+		ret = emi_kp_set_protection((size_t)x2, (size_t)x3, (unsigned int)x4);
+		break;
+	case KP_CLEAR:
+		ret = emi_kp_clear_violation((unsigned int)x2);
+		break;
+	default:
+		return MTK_SIP_E_NOT_SUPPORTED;
+	}
+
+	return mtk_bl31_map_to_sip_error(ret);
+}
+DECLARE_SMC_HANDLER(MTK_SIP_BL_EMIMPU_CONTROL, sip_emimpu_control);
+
+static u_register_t sip_tee_emimpu_control(u_register_t op_id,
+					   u_register_t x2,
+					   u_register_t x3,
+					   u_register_t x4,
+					   void *handle,
+					   struct smccc_res *smccc_ret)
+{
+	enum mtk_bl31_status ret;
+
+	switch (op_id) {
+	case EMIMPU_SET:
+		ret = emi_mpu_set_protection((uint32_t)x2, (uint32_t)x3, (unsigned int)x4);
+		break;
+	case EMIMPU_CLEAR:
+		ret = emi_clear_protection((unsigned int)x2);
+		break;
+	default:
+		return MTK_SIP_E_NOT_SUPPORTED;
+	}
+
+	return mtk_bl31_map_to_sip_error(ret);
+}
+DECLARE_SMC_HANDLER(MTK_SIP_TEE_EMI_MPU_CONTROL, sip_tee_emimpu_control);
+
+int emi_mpu_init(void)
+{
+	INFO("[%s] emi mpu initialization\n", __func__);
+
+	emi_protection_init();
+
+	return 0;
+}
+MTK_PLAT_SETUP_0_INIT(emi_mpu_init);

diff --git a/plat/mediatek/drivers/emi/emi_stub.c b/plat/mediatek/drivers/emi/emi_stub.c
index 3682bf7..abe559a 100644
--- a/plat/mediatek/drivers/emi/emi_stub.c
+++ b/plat/mediatek/drivers/emi/emi_stub.c

@@ -3,13 +3,95 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#include <common/debug.h>
 
-#include "common/emi.h"
-#include <mtk_sip_svc.h>
+#include <mtk_bl31_interface.h>
 
-uint64_t sip_emi_mpu_set_protection(u_register_t start, u_register_t end,
-				    u_register_t region)
+uint64_t emi_mpu_read_addr(unsigned int region, unsigned int offset)
+{
+	return 0;
+}
+
+uint64_t emi_mpu_read_enable(unsigned int region)
+{
+	return 0;
+}
+
+uint64_t emi_mpu_read_aid(unsigned int region, unsigned int aid_shift)
+{
+	return 0;
+}
+
+uint64_t emi_mpu_check_ns_cpu(void)
+{
+	return MTK_BL31_STATUS_NOT_SUPPORTED;
+}
+
+enum mtk_bl31_status emi_kp_set_protection(size_t start, size_t end, unsigned int region)
+{
+	return MTK_BL31_STATUS_NOT_SUPPORTED;
+}
+
+enum mtk_bl31_status emi_kp_clear_violation(unsigned int emiid)
+{
+	return MTK_BL31_STATUS_NOT_SUPPORTED;
+}
+
+enum mtk_bl31_status emi_clear_protection(unsigned int region)
+{
+	return MTK_BL31_STATUS_NOT_SUPPORTED;
+}
+
+enum mtk_bl31_status emi_clear_md_violation(void)
+{
+	return MTK_BL31_STATUS_NOT_SUPPORTED;
+}
+
+uint64_t emi_mpu_check_region_info(unsigned int region, uint64_t *sa, uint64_t *ea)
+{
+	return 0;
+}
+
+uint64_t emi_mpu_page_base_region(void)
+{
+	return 0;
+}
+
+uint64_t emi_mpu_smc_hp_mod_check(void)
+{
+	return 0;
+}
+
+enum mtk_bl31_status slb_clear_violation(unsigned int id)
+{
+	return MTK_BL31_STATUS_NOT_SUPPORTED;
+}
+
+enum mtk_bl31_status emi_clear_violation(unsigned int id, unsigned int type)
+{
+	return MTK_BL31_STATUS_NOT_SUPPORTED;
+}
+
+enum mtk_bl31_status slc_parity_select(unsigned int id, unsigned int port)
+{
+	return MTK_BL31_STATUS_NOT_SUPPORTED;
+}
+
+enum mtk_bl31_status slc_parity_clear(unsigned int id)
+{
+	return MTK_BL31_STATUS_NOT_SUPPORTED;
+}
+
+enum mtk_bl31_status emi_mpu_set_aid(unsigned int region, unsigned int num)
+{
+	return MTK_BL31_STATUS_NOT_SUPPORTED;
+}
+
+void emi_protection_init(void)
+{
+}
+
+enum mtk_bl31_status emi_mpu_set_protection(uint32_t start, uint32_t end,
+					    unsigned int region)
 {
-	return MTK_SIP_E_NOT_SUPPORTED;
+	return MTK_BL31_STATUS_NOT_SUPPORTED;
 }

diff --git a/plat/mediatek/drivers/emi/rules.mk b/plat/mediatek/drivers/emi/rules.mk
index 9f462bb..ffe1817 100644
--- a/plat/mediatek/drivers/emi/rules.mk
+++ b/plat/mediatek/drivers/emi/rules.mk

@@ -8,8 +8,9 @@
 
 MODULE := emi
 
+LOCAL_SRCS-y := $(LOCAL_DIR)/emi_ctrl.c
 ifeq ($(MTKLIB_PATH),)
-LOCAL_SRCS-y := $(LOCAL_DIR)/emi_stub.c
+LOCAL_SRCS-y += $(LOCAL_DIR)/emi_stub.c
 endif
 
 $(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))

diff --git a/plat/mediatek/drivers/iommu/mt8189/mtk_iommu_plat.c b/plat/mediatek/drivers/iommu/mt8189/mtk_iommu_plat.c
new file mode 100644
index 0000000..50fd2e7
--- /dev/null
+++ b/plat/mediatek/drivers/iommu/mt8189/mtk_iommu_plat.c

@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mtk_iommu_priv.h>
+#include <mtk_mmap_pool.h>
+#include <platform_def.h>
+
+/* mm iommu */
+#define SMI_L0_ID		(0)
+#define SMI_L1_ID		(1)
+#define SMI_L2_ID		(2)
+#define SMI_L4_ID		(3)
+#define SMI_L7_ID		(4)
+#define SMI_L9_ID		(5)
+#define SMI_L11_ID		(6)
+#define SMI_L13_ID		(7)
+#define SMI_L14_ID		(8)
+#define SMI_L16_ID		(9)
+#define SMI_L17_ID		(10)
+#define SMI_L19_ID		(11)
+#define SMI_L20_ID		(12)
+
+/* infra iommu */
+#define PERICFG_AO_IOMMU_0	(0x90)
+#define PERICFG_AO_IOMMU_1	(0x94)
+#define MMU_DEV_PCIE_0		(0)
+#define IFR_CFG_GROUP_NUM	(1)
+
+static struct mtk_smi_larb_config mt8189_larb_cfg[] = {
+	[SMI_L0_ID] = LARB_CFG_ENTRY(SMI_LARB_0_BASE, 8, 0),
+	[SMI_L1_ID] = LARB_CFG_ENTRY(SMI_LARB_1_BASE, 8, 0),
+	[SMI_L2_ID] = LARB_CFG_ENTRY(SMI_LARB_2_BASE, 11, 0),
+	[SMI_L4_ID] = LARB_CFG_ENTRY(SMI_LARB_4_BASE, 12, 0),
+	[SMI_L7_ID] = LARB_CFG_ENTRY(SMI_LARB_7_BASE, 18, 0),
+	[SMI_L9_ID] = LARB_CFG_ENTRY(SMI_LARB_9_BASE, 29, 0),
+	[SMI_L11_ID] = LARB_CFG_ENTRY(SMI_LARB_11_BASE, 29, 0),
+	[SMI_L13_ID] = LARB_CFG_ENTRY(SMI_LARB_13_BASE, 15, 0),
+	[SMI_L14_ID] = LARB_CFG_ENTRY(SMI_LARB_14_BASE, 10, 0),
+	[SMI_L16_ID] = LARB_CFG_ENTRY(SMI_LARB_16_BASE, 17, 0),
+	[SMI_L17_ID] = LARB_CFG_ENTRY(SMI_LARB_17_BASE, 17, 0),
+	[SMI_L19_ID] = LARB_CFG_ENTRY(SMI_LARB_19_BASE, 4, 0),
+	[SMI_L20_ID] = LARB_CFG_ENTRY(SMI_LARB_20_BASE, 6, 0),
+};
+
+static uint32_t mt8189_ifr_mst_cfg_base[IFR_CFG_GROUP_NUM] = {
+	PERICFG_AO_BASE,
+};
+static uint32_t mt8189_ifr_mst_cfg_offs[IFR_CFG_GROUP_NUM] = {
+	PERICFG_AO_IOMMU_1,
+};
+static struct mtk_ifr_mst_config mt8189_ifr_mst_cfg[] = {
+	[MMU_DEV_PCIE_0] = IFR_MST_CFG_ENTRY(0, 0),
+};
+
+struct mtk_smi_larb_config *g_larb_cfg = &mt8189_larb_cfg[0];
+const unsigned int g_larb_num = ARRAY_SIZE(mt8189_larb_cfg);
+
+static struct mtk_secure_iommu_config mt8189_secure_iommu_config[] = {
+	SEC_IOMMU_CFG_ENTRY(MM_IOMMU_BASE),
+};
+
+struct mtk_secure_iommu_config *g_sec_iommu_cfg = &mt8189_secure_iommu_config[0];
+const unsigned int g_sec_iommu_num = ARRAY_SIZE(mt8189_secure_iommu_config);
+
+struct mtk_ifr_mst_config *g_ifr_mst_cfg = &mt8189_ifr_mst_cfg[0];
+const unsigned int g_ifr_mst_num = ARRAY_SIZE(mt8189_ifr_mst_cfg);
+
+uint32_t *g_ifr_mst_cfg_base = &mt8189_ifr_mst_cfg_base[0];
+uint32_t *g_ifr_mst_cfg_offs = &mt8189_ifr_mst_cfg_offs[0];
+
+/**
+ * Protect infra iommu enable setting registers as secure access.
+ * This is removed in MT8189, just return here.
+ */
+void mtk_infra_iommu_enable_protect(void)
+{
+}

diff --git a/plat/mediatek/drivers/iommu/mt8189/mtk_iommu_plat.h b/plat/mediatek/drivers/iommu/mt8189/mtk_iommu_plat.h
new file mode 100644
index 0000000..935036f
--- /dev/null
+++ b/plat/mediatek/drivers/iommu/mt8189/mtk_iommu_plat.h

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IOMMU_PLAT_H
+#define IOMMU_PLAT_H
+
+/* mm iommu */
+#define ATF_MTK_SMI_LARB_CFG_SUPPORT
+
+/* mm iommu, sec bank dump */
+#define ATF_MTK_IOMMU_CFG_SUPPORT
+
+/* infra iommu */
+#define ATF_MTK_INFRA_MASTER_CFG_SUPPORT
+
+#endif /* IOMMU_PLAT_H */

diff --git a/plat/mediatek/drivers/mminfra/mminfra_common.h b/plat/mediatek/drivers/mminfra/mminfra_common.h
new file mode 100644
index 0000000..93820c7
--- /dev/null
+++ b/plat/mediatek/drivers/mminfra/mminfra_common.h

@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MMINFRA_COMMON_H
+#define MMINFRA_COMMON_H
+
+#define mminfra_info(fmt, args...)	INFO("[mminfra] %s: "fmt"\n", __func__, ##args)
+#define mminfra_err(fmt, args...)	ERROR("[mminfra] %s: "fmt"\n", __func__, ##args)
+
+#endif

diff --git a/plat/mediatek/drivers/mminfra/mminfra_stub.c b/plat/mediatek/drivers/mminfra/mminfra_stub.c
deleted file mode 100644
index dc37280..0000000
--- a/plat/mediatek/drivers/mminfra/mminfra_stub.c
+++ /dev/null

@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2025, MediaTek Inc. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <drivers/mminfra_public.h>
-
-int mminfra_get_if_in_use(void)
-{
-	return 0;
-}
-
-int mminfra_put(void)
-{
-	return 0;
-}

diff --git a/plat/mediatek/drivers/mminfra/mt8196/mminfra.c b/plat/mediatek/drivers/mminfra/mt8196/mminfra.c
new file mode 100644
index 0000000..1086c75
--- /dev/null
+++ b/plat/mediatek/drivers/mminfra/mt8196/mminfra.c

@@ -0,0 +1,228 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+
+#include <drivers/mminfra_public.h>
+#include <mminfra.h>
+#include <mtk_mmap_pool.h>
+
+static const mmap_region_t mminfra_plat_mmap[] MTK_MMAP_SECTION = {
+	MAP_REGION_FLAT(MMINFRA_HW_VOTER_BASE, PAGE_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
+	{0}
+};
+DECLARE_MTK_MMAP_REGIONS(mminfra_plat_mmap);
+
+static struct mtk_mminfra_pwr_ctrl mminfra_pwr_ctrl = {
+	.hw_voter = {
+		.base = MMINFRA_HW_VOTER_BASE,
+		.set_ofs = 0x104,
+		.clr_ofs = 0x108,
+		.en_ofs = 0x100,
+		.en_shift = 0x1,
+		.done_bits = VLP_AO_RSVD6,
+	},
+	.hw_sema = {
+		.base = SPM_BASE,
+		.offset = SPM_SEMAPHORE_M1,
+		.offset_all = {
+			SPM_SEMAPHORE_M0,
+			SPM_SEMAPHORE_M1,
+			SPM_SEMAPHORE_M2,
+			SPM_SEMAPHORE_M3,
+			SPM_SEMAPHORE_M4,
+			SPM_SEMAPHORE_M5,
+			SPM_SEMAPHORE_M6,
+			SPM_SEMAPHORE_M7,
+		},
+		.set_val = SPM_SEMA_MMINFRA,
+	},
+	.active = true,
+	.ref_cnt = 0,
+};
+
+static int spm_semaphore_get(uint32_t base, uint32_t set_val)
+{
+	int  cnt = SEMA_RETRY_CNT;
+	uint32_t val;
+
+	val = mmio_read_32(base);
+	if ((val & set_val) == set_val) {
+		mminfra_err("hw_sem was already got, base:0x%x=0x%x, set_val:0x%x\n",
+			    base, val, set_val);
+		return -1;
+	}
+
+	while (cnt > 0) {
+		mmio_write_32(base, set_val);
+		udelay(10);
+		if ((mmio_read_32(base) & set_val) == set_val)
+			return 0;
+		cnt--;
+	}
+
+	mminfra_err("timeout! base:0x%x, set_val:0x%x\n", base, set_val);
+	return -1;
+}
+
+static int spm_semaphore_release(uint32_t base, uint32_t set_val)
+{
+	int cnt = SEMA_RETRY_CNT;
+	uint32_t val;
+
+	val = mmio_read_32(base);
+	if ((val & set_val) != set_val) {
+		mminfra_err("hw_sem was already released, base:0x%x=0x%x, set_val:0x%x\n",
+			    base, val, set_val);
+		return -1;
+	}
+	do {
+		mmio_write_32(base, set_val);
+		udelay(10);
+		if (cnt-- < 0) {
+			if ((mmio_read_32(base) & set_val) != set_val)
+				return 0;
+			mminfra_err("timeout! base:0x%x, set_val:0x%x\n", base, set_val);
+			return -1;
+		}
+	} while ((mmio_read_32(base) & set_val) == set_val);
+
+	return 0;
+}
+
+static int mminfra_hw_sema_ctrl(struct mminfra_hw_sema *hw_sema, bool is_get)
+{
+	int i, ret;
+
+	if (!hw_sema)
+		return 0;
+
+	if (is_get)
+		ret = spm_semaphore_get(hw_sema->base + hw_sema->offset, hw_sema->set_val);
+	else
+		ret = spm_semaphore_release(hw_sema->base + hw_sema->offset, hw_sema->set_val);
+
+	if (ret)
+		for (i = 0; i < SPM_SEMA_MMINFRA_NR; i++)
+			mminfra_err("0x%x=0x%x\n", hw_sema->base + hw_sema->offset_all[i],
+				    mmio_read_32(hw_sema->base + hw_sema->offset_all[i]));
+
+	return ret;
+}
+
+static bool is_mminfra_ready(struct mminfra_hw_voter *hw_voter)
+{
+	if (!hw_voter)
+		return false;
+
+	return !!(mmio_read_32(hw_voter->done_bits) & MMINFRA_DONE);
+}
+
+static int mminfra_hwv_power_ctrl(struct mminfra_hw_voter *hw_voter, bool is_on)
+{
+	uint32_t vote_ofs, vote_mask, vote_ack;
+	uint32_t val = 0, cnt;
+
+	vote_mask = BIT(hw_voter->en_shift);
+	vote_ofs = is_on ? hw_voter->set_ofs : hw_voter->clr_ofs;
+	vote_ack = is_on ? vote_mask : 0x0;
+
+	/* Vote on off */
+	cnt = 0;
+	do {
+		mmio_write_32(hw_voter->base + vote_ofs, vote_mask);
+		udelay(MTK_POLL_HWV_VOTE_US);
+		val = mmio_read_32(hw_voter->base + hw_voter->en_ofs);
+		if ((val & vote_mask) == vote_ack)
+			break;
+
+		if (cnt > MTK_POLL_HWV_VOTE_CNT) {
+			mminfra_err("vote mminfra timeout, is_on:%d, 0x%x=0x%x\n",
+				    is_on, hw_voter->base + hw_voter->en_ofs, val);
+			return -1;
+		}
+		cnt++;
+	} while (1);
+
+	if (!is_on)
+		return 0;
+
+	/* Confirm done bits */
+	cnt = 0;
+	while (cnt < MTK_POLL_DONE_RETRY) {
+		if (is_mminfra_ready(hw_voter))
+			return 0;
+		udelay(MTK_POLL_DONE_DELAY_US);
+		cnt++;
+	}
+
+	mminfra_err("polling mminfra done timeout, 0x%x=0x%x\n",
+		    hw_voter->done_bits, val);
+	return -1;
+}
+
+int mminfra_get_if_in_use(void)
+{
+	int ret, is_on = MMINFRA_RET_POWER_OFF;
+
+	if (!mminfra_pwr_ctrl.active) {
+		mminfra_err("not ready\n");
+		return MMINFRA_RET_POWER_OFF;
+	}
+
+	spin_lock(&mminfra_pwr_ctrl.lock);
+	if (mminfra_pwr_ctrl.ref_cnt > 0) {
+		mminfra_pwr_ctrl.ref_cnt++;
+		is_on = MMINFRA_RET_POWER_ON;
+		spin_unlock(&mminfra_pwr_ctrl.lock);
+		return is_on;
+	}
+
+	ret = mminfra_hw_sema_ctrl(&mminfra_pwr_ctrl.hw_sema, true);
+	if (ret)
+		goto err;
+
+	/* Check if mminfra is in use */
+	if (is_mminfra_ready(&mminfra_pwr_ctrl.hw_voter)) {
+		ret = mminfra_hwv_power_ctrl(&mminfra_pwr_ctrl.hw_voter, true);
+		if (ret) {
+			mminfra_err("vote for mminfra fail, ret=%d\n", ret);
+			goto err;
+		}
+		mminfra_pwr_ctrl.ref_cnt++;
+		is_on = MMINFRA_RET_POWER_ON;
+	} else {
+		is_on = MMINFRA_RET_POWER_OFF;
+	}
+
+	ret = mminfra_hw_sema_ctrl(&mminfra_pwr_ctrl.hw_sema, false);
+	if (ret)
+		goto err;
+	ret = is_on; /* Return power is on or off. */
+err:
+	spin_unlock(&mminfra_pwr_ctrl.lock);
+	return ret;
+}
+
+int mminfra_put(void)
+{
+	if (!mminfra_pwr_ctrl.active) {
+		mminfra_err("not ready\n");
+		return 0;
+	}
+
+	spin_lock(&mminfra_pwr_ctrl.lock);
+	mminfra_pwr_ctrl.ref_cnt--;
+	if (mminfra_pwr_ctrl.ref_cnt > 0)
+		goto out;
+
+	mminfra_hwv_power_ctrl(&mminfra_pwr_ctrl.hw_voter, false);
+out:
+	spin_unlock(&mminfra_pwr_ctrl.lock);
+	return 0;
+}

diff --git a/plat/mediatek/drivers/mminfra/mt8196/mminfra.h b/plat/mediatek/drivers/mminfra/mt8196/mminfra.h
new file mode 100644
index 0000000..fcee08c
--- /dev/null
+++ b/plat/mediatek/drivers/mminfra/mt8196/mminfra.h

@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MMINFRA_H
+#define MMINFRA_H
+
+#include <lib/spinlock.h>
+
+#include "../mminfra_common.h"
+#include <platform_def.h>
+
+#define VLP_AO_RSVD6			(MTK_VLP_TRACER_MON_BASE + 0x918)
+#define MMINFRA_DONE			(1U << 0)
+
+#define SPM_SEMA_MMINFRA                (1U << 5)
+#define SPM_SEMA_MMINFRA_NR             (8)
+
+#define SEMA_RETRY_CNT			(500)
+
+#define SPM_SEMAPHORE_M0		(0x69C)
+#define SPM_SEMAPHORE_M1		(0x6A0)
+#define SPM_SEMAPHORE_M2		(0x6A4)
+#define SPM_SEMAPHORE_M3		(0x6A8)
+#define SPM_SEMAPHORE_M4		(0x6AC)
+#define SPM_SEMAPHORE_M5		(0x6B0)
+#define SPM_SEMAPHORE_M6		(0x6B4)
+#define SPM_SEMAPHORE_M7		(0x6B8)
+
+#define MMINFRA_HW_VOTER_BASE		(0x31A80000)
+#define MTK_POLL_HWV_VOTE_US		(2)
+#define MTK_POLL_HWV_VOTE_CNT		(2500)
+#define MTK_POLL_DONE_DELAY_US		(1)
+#define MTK_POLL_DONE_RETRY		(3000)
+
+struct mminfra_hw_sema {
+	uint32_t base;
+	uint32_t offset;
+	uint32_t offset_all[SPM_SEMA_MMINFRA_NR];
+	uint32_t set_val;
+};
+
+struct mminfra_hw_voter {
+	uint32_t base;
+	uint32_t set_ofs;
+	uint32_t clr_ofs;
+	uint32_t en_ofs;
+	uint32_t en_shift;
+	uint32_t done_bits;
+};
+
+struct mtk_mminfra_pwr_ctrl {
+	spinlock_t lock;
+	struct mminfra_hw_voter hw_voter;
+	struct mminfra_hw_sema hw_sema;
+	uint32_t ref_cnt;
+	bool active;
+};
+
+#endif

diff --git a/plat/mediatek/drivers/mminfra/rules.mk b/plat/mediatek/drivers/mminfra/rules.mk
index f3a6822..cd5d607 100644
--- a/plat/mediatek/drivers/mminfra/rules.mk
+++ b/plat/mediatek/drivers/mminfra/rules.mk

@@ -8,10 +8,9 @@
 
 MODULE := mminfra
 
-PLAT_INCLUDES += -I${MTK_PLAT}/include/drivers/
+PLAT_INCLUDES += -I$(MTK_PLAT)/include/drivers/
+PLAT_INCLUDES += -I$(MTK_PLAT)/drivers/mminfra/$(MTK_SOC)
 
-ifeq ($(MTKLIB_PATH),)
-LOCAL_SRCS-y := ${LOCAL_DIR}/mminfra_stub.c
-endif
+LOCAL_SRCS-y := $(LOCAL_DIR)/$(MTK_SOC)/mminfra.c
 
 $(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))

diff --git a/plat/mediatek/drivers/pmic/mt6359p/mt6359p_psc.c b/plat/mediatek/drivers/pmic/mt6359p/mt6359p_psc.c
new file mode 100644
index 0000000..6c0eb9c
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/mt6359p/mt6359p_psc.c

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+
+#include <common/debug.h>
+#include <drivers/pmic/pmic_psc.h>
+#include <lib/mtk_init/mtk_init.h>
+#include <pmic_wrap_init_common.h>
+
+#include "registers.h"
+
+static const struct pmic_psc_reg mt6359p_psc_regs[] = {
+	PMIC_PSC_REG(RG_PWRHOLD, MT6359P_PPCCTL0, 0),
+	PMIC_PSC_REG(RG_CRST, MT6359P_PPCCTL1, 0),
+	PMIC_PSC_REG(RG_SMART_RST_SDN_EN, MT6359P_STRUP_CON12, 9),
+	PMIC_PSC_REG(RG_SMART_RST_MODE, MT6359P_STRUP_CON12, 10),
+};
+
+static const struct pmic_psc_config mt6359p_psc_config = {
+	.read_field = pwrap_read_field,
+	.write_field = pwrap_write_field,
+	.regs = mt6359p_psc_regs,
+	.reg_size = ARRAY_SIZE(mt6359p_psc_regs),
+};
+
+static int mt6359p_psc_init(void)
+{
+	return pmic_psc_register(&mt6359p_psc_config);
+}
+
+MTK_PLAT_SETUP_0_INIT(mt6359p_psc_init);

diff --git a/plat/mediatek/drivers/pmic/mt6359p/registers.h b/plat/mediatek/drivers/pmic/mt6359p/registers.h
new file mode 100644
index 0000000..f1b2a6d
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/mt6359p/registers.h

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef REGISTER_H
+#define REGISTER_H
+
+/* PMIC Registers for PSC */
+#define MT6359P_PPCCTL0		0xa08
+#define MT6359P_PPCCTL1		0xa0a
+#define MT6359P_STRUP_CON12	0xa12
+
+#endif /* REGISTER_H */

diff --git a/plat/mediatek/drivers/pmic/mt6359p/rules.mk b/plat/mediatek/drivers/pmic/mt6359p/rules.mk
new file mode 100644
index 0000000..39908f8
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/mt6359p/rules.mk

@@ -0,0 +1,13 @@
+#
+# Copyright (c) 2025, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := mt6359p
+
+LOCAL_SRCS-y := $(LOCAL_DIR)/${PMIC_CHIP}_psc.c
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))

diff --git a/plat/mediatek/drivers/pmic/mt8189/pmic_lowpower_init.c b/plat/mediatek/drivers/pmic/mt8189/pmic_lowpower_init.c
new file mode 100644
index 0000000..aa90b86
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/mt8189/pmic_lowpower_init.c

@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+
+#include <common/debug.h>
+
+#include <drivers/pmic/mt6319_lowpower_reg.h>
+#include <drivers/pmic/mt6359p_set_lowpower.h>
+#include <drivers/pmic/pmic_swap_api.h>
+#include <lib/mtk_init/mtk_init.h>
+#include <pmic_wrap_init_common.h>
+
+#define PMIC_SLVID_BUCK_SET_LP(_chip, _slvid, _name, _user, _en, _mode, _cfg) \
+{ \
+	struct spmi_device *sdev = lowpower_sdev[_slvid]; \
+	if (sdev) {\
+		pmic_spmi_update_bits(sdev, \
+				      _chip##_RG_BUCK_##_name##_##_user##_OP_CFG_ADDR, \
+				      1 << _user, \
+				      _cfg ? 1 << _user : 0); \
+		pmic_spmi_update_bits(sdev, \
+				      _chip##_RG_BUCK_##_name##_##_user##_OP_MODE_ADDR, \
+				      1 << _user, \
+				      _mode ? 1 << _user : 0); \
+		pmic_spmi_update_bits(sdev, \
+				      _chip##_RG_BUCK_##_name##_##_user##_OP_EN_ADDR, \
+				      1 << _user, \
+				      _en ? 1 << _user : 0); \
+	} \
+}
+
+struct spmi_device *lowpower_sdev[SPMI_MAX_SLAVE_ID];
+
+static const uint8_t lowpower_slvid_arr[] = {
+	SPMI_SLAVE_7,
+};
+
+static int pmic_spmi_update_bits(struct spmi_device *sdev, uint16_t reg,
+				 uint8_t mask, uint8_t val)
+{
+	uint8_t orig = 0;
+	int ret = 0;
+
+	ret = spmi_ext_register_readl(sdev, reg, &orig, 1);
+	if (ret < 0)
+		return ret;
+	orig &= ~mask;
+	orig |= val & mask;
+	ret = spmi_ext_register_writel(sdev, reg, &orig, 1);
+	return ret;
+}
+
+static int pmic_lowpower_init(void)
+{
+	uint8_t i, slvid;
+
+	for (i = 0; i < ARRAY_SIZE(lowpower_slvid_arr); i++) {
+		slvid = lowpower_slvid_arr[i];
+		lowpower_sdev[slvid] = get_spmi_device(SPMI_MASTER_P_1, slvid);
+		if (!lowpower_sdev[slvid])
+			return -ENODEV;
+	}
+
+	PMIC_SLVID_BUCK_SET_LP(MT6319, SPMI_SLAVE_7, VBUCK3, HW0, true, OP_MODE_LP, HW_LP);
+
+	PMIC_BUCK_SET_LP(MT6359P, VPROC2, HW0, true, OP_MODE_LP, HW_OFF);
+	PMIC_BUCK_SET_LP(MT6359P, VPROC2, HW2, true, OP_MODE_LP, HW_LP);
+	PMIC_BUCK_SET_LP(MT6359P, VGPU11, HW0, true, OP_MODE_LP, HW_LP);
+	PMIC_BUCK_SET_LP(MT6359P, VGPU11, HW2, true, OP_MODE_LP, HW_LP);
+	PMIC_BUCK_SET_LP(MT6359P, VS1, HW0, true, OP_MODE_LP, HW_LP);
+	PMIC_BUCK_SET_LP(MT6359P, VS1, HW2, true, OP_MODE_LP, HW_LP);
+	PMIC_BUCK_SET_LP(MT6359P, VS2, HW0, true, OP_MODE_LP, HW_LP);
+	PMIC_BUCK_SET_LP(MT6359P, VS2, HW2, true, OP_MODE_LP, HW_LP);
+	PMIC_LDO_SET_LP(MT6359P, VRF12, HW0, true, OP_MODE_LP, HW_LP);
+	PMIC_LDO_SET_LP(MT6359P, VRF12, HW2, true, OP_MODE_LP, HW_LP);
+	PMIC_LDO_SET_LP(MT6359P, VA12, HW0, true, OP_MODE_LP, HW_LP);
+	PMIC_LDO_SET_LP(MT6359P, VA12, HW2, true, OP_MODE_LP, HW_LP);
+	PMIC_LDO_SET_LP(MT6359P, VA09, HW0, true, OP_MODE_LP, HW_LP);
+	PMIC_LDO_SET_LP(MT6359P, VA09, HW2, true, OP_MODE_LP, HW_LP);
+	PMIC_LDO_SET_LP(MT6359P, VAUX18, HW0, true, OP_MODE_LP, HW_LP);
+	PMIC_LDO_SET_LP(MT6359P, VAUX18, HW2, true, OP_MODE_LP, HW_LP);
+	PMIC_LDO_SET_LP(MT6359P, VXO22, HW0, true, OP_MODE_LP, HW_LP);
+	PMIC_LDO_SET_LP(MT6359P, VXO22, HW2, true, OP_MODE_LP, HW_LP);
+	PMIC_LDO_SET_LP(MT6359P, VUSB, HW0, true, OP_MODE_LP, HW_LP);
+	PMIC_LDO_SET_LP(MT6359P, VUSB, HW2, true, OP_MODE_LP, HW_LP);
+	PMIC_LDO_SET_LP(MT6359P, VUFS, HW0, true, OP_MODE_LP, HW_LP);
+
+	return 0;
+}
+
+MTK_PLAT_SETUP_0_INIT(pmic_lowpower_init);

diff --git a/plat/mediatek/drivers/pmic/mt8189/pmic_shutdown_cfg.c b/plat/mediatek/drivers/pmic/mt8189/pmic_shutdown_cfg.c
new file mode 100644
index 0000000..dbb5852
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/mt8189/pmic_shutdown_cfg.c

@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include "../mt6359p/registers.h"
+#include <drivers/pmic/pmic_shutdown_cfg.h>
+#include <drivers/spmi/spmi_common.h>
+#include <drivers/spmi_api.h>
+#include <lib/mtk_init/mtk_init.h>
+#include <pmic_wrap_init_common.h>
+
+#define MT6319_RG_SEQ_OFF		0x2d
+#define MT6319_TOP_RST_MISC_CLR		0x128
+#define MT6319_TOP_DIG_WPK_H		0x3a9
+#define MT6319_TOP_DIG_WPK_H_MASK	0xFF
+#define MT6319_TOP_DIG_WPK_H_SHIFT	0
+#define MT6319_TOP_DIG_WPK		0x3a8
+#define MT6319_TOP_DIG_WPK_MASK		0xFF
+#define MT6319_TOP_DIG_WPK_SHIFT	0
+
+
+int pmic_shutdown_cfg(void)
+{
+/*
+ * In mt8189, the pmic_shutdown_cfg() api does not need to read and write the
+ * pmic register to determine the return value and in order not to modify the
+ * common code to affect other ICs, the pmic_shutdown_cfg() will directly
+ * return 1.
+ */
+	return 1;
+}
+
+static void shutdown_slave_dev(struct spmi_device *dev)
+{
+	spmi_ext_register_writel_field(dev, MT6319_TOP_DIG_WPK_H, 0x63,
+				       MT6319_TOP_DIG_WPK_H_MASK,
+				       MT6319_TOP_DIG_WPK_H_SHIFT);
+	spmi_ext_register_writel_field(dev, MT6319_TOP_DIG_WPK, 0x15,
+				       MT6319_TOP_DIG_WPK_MASK,
+				       MT6319_TOP_DIG_WPK_SHIFT);
+
+	/* Disable WDTRSTB_EN */
+	spmi_ext_register_writel_field(dev, MT6319_TOP_RST_MISC_CLR, 1, 0x1, 0);
+	/* Normal sequence power off when PAD_EN falling */
+	spmi_ext_register_writel_field(dev, MT6319_RG_SEQ_OFF, 1, 0x1, 0);
+
+	spmi_ext_register_writel_field(dev, MT6319_TOP_DIG_WPK_H, 0,
+				       MT6319_TOP_DIG_WPK_H_MASK,
+				       MT6319_TOP_DIG_WPK_H_SHIFT);
+	spmi_ext_register_writel_field(dev, MT6319_TOP_DIG_WPK, 0,
+				       MT6319_TOP_DIG_WPK_MASK,
+				       MT6319_TOP_DIG_WPK_SHIFT);
+
+}
+
+int spmi_shutdown(void)
+{
+	struct spmi_device *mt6319_sdev;
+
+	mt6319_sdev = get_spmi_device(SPMI_MASTER_P_1, SPMI_SLAVE_7);
+	if (!mt6319_sdev)
+		return -ENODEV;
+	shutdown_slave_dev(mt6319_sdev);
+
+	if (mmio_read_32((uintptr_t)CHIP_ID_REG) == MTK_CPU_ID_MT8189 &&
+	    mmio_read_32((uintptr_t)CPU_SEG_ID_REG) == MTK_CPU_SEG_ID_MT8189H) {
+		mt6319_sdev = get_spmi_device(SPMI_MASTER_P_1, SPMI_SLAVE_8);
+		if (!mt6319_sdev)
+			return -ENODEV;
+		shutdown_slave_dev(mt6319_sdev);
+	}
+
+	/* clear main pmic power hold */
+	pwrap_write_field(MT6359P_PPCCTL0, 0, 0x1, 0);
+
+	return 0;
+}

diff --git a/plat/mediatek/drivers/pmic/mt8189/pmic_swap_api.c b/plat/mediatek/drivers/pmic/mt8189/pmic_swap_api.c
new file mode 100644
index 0000000..0310389
--- /dev/null
+++ b/plat/mediatek/drivers/pmic/mt8189/pmic_swap_api.c

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdbool.h>
+
+#include <drivers/pmic/pmic_swap_api.h>
+
+/* No need to check second pmic mt6369 */
+bool is_second_pmic_pp_swap(void)
+{
+	return false;
+}

diff --git a/plat/mediatek/drivers/pmic/rules.mk b/plat/mediatek/drivers/pmic/rules.mk
index 0280df8..13ce658 100644
--- a/plat/mediatek/drivers/pmic/rules.mk
+++ b/plat/mediatek/drivers/pmic/rules.mk

@@ -8,15 +8,15 @@
 
 MODULE := pmic
 
-ifneq (${PMIC_CHIP}, mt6363)
-LOCAL_SRCS-y += ${LOCAL_DIR}/pmic.c
-PLAT_INCLUDES += -I${LOCAL_DIR}/
-else
-LOCAL_SRCS-y := ${LOCAL_DIR}/pmic_psc.c
-LOCAL_SRCS-y += ${LOCAL_DIR}/pmic_common_swap_api.c
+ifeq (${CONFIG_MTK_PMIC_SHUTDOWN_V2}, y)
+LOCAL_SRCS-y := ${LOCAL_DIR}/pmic_common_swap_api.c
+LOCAL_SRCS-y += ${LOCAL_DIR}/pmic_psc.c
 LOCAL_SRCS-${CONFIG_MTK_PMIC_LOWPOWER} += ${LOCAL_DIR}/${MTK_SOC}/pmic_lowpower_init.c
 LOCAL_SRCS-${CONFIG_MTK_PMIC_LOWPOWER} += ${LOCAL_DIR}/${MTK_SOC}/pmic_swap_api.c
 LOCAL_SRCS-${CONFIG_MTK_PMIC_SHUTDOWN_CFG} += ${LOCAL_DIR}/${MTK_SOC}/pmic_shutdown_cfg.c
+else
+LOCAL_SRCS-y += ${LOCAL_DIR}/pmic.c
+PLAT_INCLUDES += -I${LOCAL_DIR}/
 endif
 
 $(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))

diff --git a/plat/mediatek/drivers/pmic_wrap/mt8189/pmic_wrap_init.h b/plat/mediatek/drivers/pmic_wrap/mt8189/pmic_wrap_init.h
new file mode 100644
index 0000000..9647326
--- /dev/null
+++ b/plat/mediatek/drivers/pmic_wrap/mt8189/pmic_wrap_init.h

@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PMIC_WRAP_INIT_H
+#define PMIC_WRAP_INIT_H
+
+#include <platform_def.h>
+#include <pmic_wrap_init_common.h>
+
+#define PWRAP_DEBUG				0
+
+/* PMIC_WRAP registers */
+struct mt8189_pmic_wrap_regs {
+	uint32_t init_done;
+	uint32_t reserved[511];
+	struct {
+		uint32_t cmd;
+		uint32_t wdata;
+		uint32_t reserved1[3];
+		uint32_t rdata;
+		uint32_t reserved2[3];
+		uint32_t vldclr;
+		uint32_t sta;
+		uint32_t reserved3[5];
+	} wacs[4];
+};
+
+static struct mt8189_pmic_wrap_regs *const mtk_pwrap = (void *)PMIC_WRAP_BASE;
+
+#define PMIF_SPI_SWINF_NO			2
+
+#endif /* PMIC_WRAP_INIT_H */

diff --git a/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h
index 4ba1f5c..3a30435 100644
--- a/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h
+++ b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_common.h

@@ -12,10 +12,14 @@
 #include "platform_def.h"
 
 /* external API */
+int32_t pmic_wrap_test(void);
 int32_t pwrap_read(uint32_t adr, uint32_t *rdata);
+int32_t pwrap_read_field(uint32_t reg, uint32_t *val, uint32_t mask, uint32_t shift);
 int32_t pwrap_write(uint32_t adr, uint32_t wdata);
+int32_t pwrap_write_field(uint32_t reg, uint32_t val, uint32_t mask, uint32_t shift);
 
-#define GET_WACS_FSM(x)	((x >> 1) & 0x7)
+#define GET_SWINF_INIT_DONE(x)	((x>>15) & 0x00000001)
+#define GET_WACS_FSM(x)		((x >> 1) & 0x7)
 
 /* macro for SWINF_FSM */
 #define SWINF_FSM_IDLE		(0x00)
@@ -43,6 +47,11 @@
 	E_PWR_INIT_SIDLY_FAIL		= 11,
 	E_PWR_RESET_TIMEOUT		= 12,
 	E_PWR_TIMEOUT			= 13,
+	E_PWR_INVALID_SWINF		= 14,
+	E_PWR_INVALID_CMD		= 15,
+	E_PWR_INVALID_PMIFID		= 16,
+	E_PWR_INVALID_SLVID		= 17,
+	E_PWR_INVALID_BYTECNT		= 18,
 	E_PWR_INIT_RESET_SPI		= 20,
 	E_PWR_INIT_SIDLY		= 21,
 	E_PWR_INIT_REG_CLOCK		= 22,

diff --git a/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_v3.c b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_v3.c
new file mode 100644
index 0000000..4e9c321
--- /dev/null
+++ b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_init_v3.c

@@ -0,0 +1,259 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <lib/spinlock.h>
+
+#include <mtk_mmap_pool.h>
+#include "pmic_wrap_init.h"
+#include "pmic_wrap_v3.h"
+
+static spinlock_t wrp_lock;
+
+static uint32_t pwrap_check_idle(uintptr_t wacs_register, uintptr_t wacs_vldclr_register,
+				 uint32_t timeout_us)
+{
+	uint32_t reg_rdata = 0U, retry;
+
+	retry = (timeout_us + PWRAP_POLL_STEP_US) / PWRAP_POLL_STEP_US;
+	while (retry != 0) {
+		udelay(PWRAP_POLL_STEP_US);
+		reg_rdata = mmio_read_32(wacs_register);
+		/* if last read command timeout,clear vldclr bit
+		 * read command state machine:FSM_REQ-->wfdle-->WFVLDCLR;
+		 * write:FSM_REQ-->idle
+		 */
+		switch (GET_WACS_FSM(reg_rdata)) {
+		case SWINF_FSM_WFVLDCLR:
+			mmio_write_32(wacs_vldclr_register, 0x1);
+			INFO("WACS_FSM = SWINF_FSM_WFVLDCLR\n");
+			break;
+		case SWINF_FSM_WFDLE:
+			INFO("WACS_FSM = SWINF_FSM_WFDLE\n");
+			break;
+		case SWINF_FSM_REQ:
+			INFO("WACS_FSM = SWINF_FSM_REQ\n");
+			break;
+		case SWINF_FSM_IDLE:
+			goto done;
+		default:
+			break;
+		}
+		retry--;
+	}
+
+done:
+	if (retry == 0) {
+		/* timeout */
+		return E_PWR_WAIT_IDLE_TIMEOUT;
+	}
+
+	return 0U;
+}
+
+static uint32_t pwrap_check_vldclr(uintptr_t wacs_register, uint32_t timeout_us)
+{
+	uint32_t reg_rdata = 0U, retry;
+
+	retry = (timeout_us + PWRAP_POLL_STEP_US) / PWRAP_POLL_STEP_US;
+	while (retry != 0) {
+		udelay(PWRAP_POLL_STEP_US);
+		reg_rdata = mmio_read_32(wacs_register);
+		if (GET_WACS_FSM(reg_rdata) == SWINF_FSM_WFVLDCLR) {
+			break;
+		}
+		retry--;
+	}
+
+	if (retry == 0) {
+		/* timeout */
+		return E_PWR_WAIT_IDLE_TIMEOUT;
+	}
+
+	return 0U;
+}
+
+static int32_t pwrap_swinf_acc(uint32_t swinf_no, uint32_t cmd, uint32_t write,
+			       uint32_t pmifid, uint32_t slvid, uint32_t addr,
+			       uint32_t bytecnt, uint32_t wdata, uint32_t *rdata)
+{
+	uint32_t reg_rdata = 0x0;
+	int32_t ret = 0x0;
+
+	/* Check argument validation */
+	if ((swinf_no & ~(0x3)) != 0)
+		return -E_PWR_INVALID_SWINF;
+	if ((cmd & ~(0x3)) != 0)
+		return -E_PWR_INVALID_CMD;
+	if ((write & ~(0x1)) != 0)
+		return -E_PWR_INVALID_RW;
+	if ((pmifid & ~(0x1)) != 0)
+		return -E_PWR_INVALID_PMIFID;
+	if ((slvid & ~(0xf)) != 0)
+		return -E_PWR_INVALID_SLVID;
+	if ((addr & ~(0xffff)) != 0)
+		return -E_PWR_INVALID_ADDR;
+	if ((bytecnt & ~(0x1)) != 0)
+		return -E_PWR_INVALID_BYTECNT;
+	if ((wdata & ~(0xffff)) != 0)
+		return -E_PWR_INVALID_WDAT;
+
+	spin_lock(&wrp_lock);
+	/* Check whether INIT_DONE is set */
+	if (pmifid == 0)
+		reg_rdata = mmio_read_32((uintptr_t)(&mtk_pwrap->wacs[swinf_no].sta));
+
+	if (GET_SWINF_INIT_DONE(reg_rdata) != 0x1) {
+		ERROR("[PWRAP] init not finish\n");
+		ret = -E_PWR_NOT_INIT_DONE;
+		goto end;
+	}
+
+	/* Wait for Software Interface FSM state to be IDLE */
+	ret = pwrap_check_idle((uintptr_t)(&mtk_pwrap->wacs[swinf_no].sta),
+			(uintptr_t)(&mtk_pwrap->wacs[swinf_no].vldclr), TIMEOUT_WAIT_IDLE);
+	if (ret != 0) {
+		ERROR("[PWRAP] fsm_idle fail\n");
+		goto end;
+	}
+
+	/* Set the write data */
+	if (write == 1) {
+		if (pmifid == 0)
+			mmio_write_32((uintptr_t)(&mtk_pwrap->wacs[swinf_no].wdata), wdata);
+	}
+
+	/* Send the command */
+	if (pmifid == 0)
+		mmio_write_32((uintptr_t)(&mtk_pwrap->wacs[swinf_no].cmd),
+			  (cmd << 30) | (write << 29) | (slvid << 24) | (bytecnt << 16) | addr);
+
+	if (write == 0) {
+		if (rdata == NULL) {
+			ERROR("[PWRAP] rdata null\n");
+			ret = -E_PWR_INVALID_ARG;
+			goto end;
+		}
+
+		/* Wait for Software Interface FSM to be WFVLDCLR */
+		/* read the data and clear the valid flag         */
+		ret = pwrap_check_vldclr((uintptr_t)(&mtk_pwrap->wacs[swinf_no].sta), TIMEOUT_READ);
+		if (ret != 0) {
+			ERROR("[PWRAP] fsm_vldclr fail\n");
+			goto end;
+		}
+
+		if (pmifid == 0) {
+			*rdata = mmio_read_32((uintptr_t)(&mtk_pwrap->wacs[swinf_no].rdata));
+			mmio_write_32((uintptr_t)(&mtk_pwrap->wacs[swinf_no].vldclr), 0x1);
+		}
+	}
+
+end:
+	spin_unlock(&wrp_lock);
+	if (ret < 0)
+		ERROR("%s fail, ret=%d\n", __func__, ret);
+	return ret;
+}
+
+/* external API for pmic_wrap user */
+
+int32_t pwrap_read(uint32_t adr, uint32_t *rdata)
+{
+	return pwrap_swinf_acc(PMIF_SPI_SWINF_NO, DEFAULT_CMD, 0, PMIF_SPI_PMIFID,
+		DEFAULT_SLVID, adr, DEFAULT_BYTECNT, 0x0, rdata);
+}
+
+int32_t pwrap_write(uint32_t adr, uint32_t wdata)
+{
+	return pwrap_swinf_acc(PMIF_SPI_SWINF_NO, DEFAULT_CMD, 1, PMIF_SPI_PMIFID,
+		DEFAULT_SLVID, adr, DEFAULT_BYTECNT, wdata, 0x0);
+}
+
+int32_t pwrap_read_field(uint32_t reg, uint32_t *val, uint32_t mask, uint32_t shift)
+{
+	uint32_t rdata;
+	int32_t ret;
+
+	if (!val)
+		return -E_PWR_INVALID_ARG;
+	ret = pwrap_read(reg, &rdata);
+	if (ret == 0x0)
+		*val = (rdata >> shift) & mask;
+
+	return ret;
+}
+
+int32_t pwrap_write_field(uint32_t reg, uint32_t val, uint32_t mask, uint32_t shift)
+{
+	uint32_t data;
+	int32_t ret;
+
+	ret = pwrap_read(reg, &data);
+	if (ret != 0)
+		return ret;
+
+	data = data & ~(mask << shift);
+	data |= (val << shift);
+	ret = pwrap_write(reg, data);
+
+	return ret;
+}
+
+#if PWRAP_DEBUG
+static int32_t pwrap_read_test(void)
+{
+	uint32_t rdata = 0;
+	int32_t ret;
+
+	ret = pwrap_read(DEW_READ_TEST, &rdata);
+	if (rdata != DEFAULT_VALUE_READ_TEST) {
+		ERROR("[PWRAP] Read fail,rdata=0x%x,exp=0x5aa5,ret=0x%x\n", rdata, ret);
+		return -E_PWR_READ_TEST_FAIL;
+	}
+	INFO("[PWRAP] Read Test pass,ret=%x\n", ret);
+	return 0;
+}
+
+static int32_t pwrap_write_test(void)
+{
+	uint32_t rdata = 0;
+	int32_t ret;
+	int32_t ret1;
+
+	ret = pwrap_write(DEW_WRITE_TEST, PWRAP_WRITE_TEST_VALUE);
+	ret1 = pwrap_read(DEW_WRITE_TEST, &rdata);
+	if ((rdata != PWRAP_WRITE_TEST_VALUE) || (ret != 0) || (ret1 != 0)) {
+		ERROR("[PWRAP] Write fail,rdata=0x%x,exp=0xa55a,ret=0x%x,ret1=0x%x\n",
+			rdata, ret, ret1);
+		return -E_PWR_WRITE_TEST_FAIL;
+	}
+	INFO("[PWRAP] Write Test pass\n");
+	return 0;
+}
+
+int32_t pmic_wrap_test(void)
+{
+	int32_t ret;
+
+	INFO("[PWRAP] Read/Write Test start\n");
+
+	ret = pwrap_read_test();
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = pwrap_write_test();
+	if (ret != 0) {
+		return ret;
+	}
+	INFO("[PWRAP] Read/Write Test done\n");
+
+	return 0;
+}
+#endif

diff --git a/plat/mediatek/drivers/pmic_wrap/pmic_wrap_v3.h b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_v3.h
new file mode 100644
index 0000000..075c2d5
--- /dev/null
+++ b/plat/mediatek/drivers/pmic_wrap/pmic_wrap_v3.h

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PMIC_WRAP_V3_H
+#define PMIC_WRAP_V3_H
+
+#include <stdint.h>
+
+#include <common/debug.h>
+#include <drivers/console.h>
+
+#define PMIF_REG_RANGE			(0x774)
+#define PMICSPI_MST_REG_RANGE		(0x80)
+#define DEFAULT_CMD			0
+#define DEFAULT_SLVID			0
+#define DEFAULT_BYTECNT			0
+#define PMIF_SPI_PMIFID			0
+/* #define PWRAP_DEBUG 1 */
+
+#if PWRAP_DEBUG
+#define PWRAP_LOG(fmts, args...) do {\
+		console_init(gteearg.atf_log_port, UART_CLOCK, UART_BAUDRATE);\
+		INFO("[%s:%d] -" fmts, __func__, __LINE__, ##args);\
+		console_uninit();\
+	} while (0)
+#endif
+
+/**********************************************************/
+#define DEFAULT_VALUE_READ_TEST		(0x5aa5)
+#define PWRAP_WRITE_TEST_VALUE		(0xa55a)
+#define PWRAP_POLL_STEP_US		(10)
+
+/* timeout setting */
+enum {
+	TIMEOUT_RESET		= 50,	/* us */
+	TIMEOUT_READ		= 50,	/* us */
+	TIMEOUT_WAIT_IDLE	= 50	/* us */
+};
+
+#endif /* PMIC_WRAP_V3_H */

diff --git a/plat/mediatek/drivers/pmic_wrap/rules.mk b/plat/mediatek/drivers/pmic_wrap/rules.mk
index 9ba44a6..662c7e4 100644
--- a/plat/mediatek/drivers/pmic_wrap/rules.mk
+++ b/plat/mediatek/drivers/pmic_wrap/rules.mk

@@ -10,6 +10,8 @@
 
 ifeq (${USE_PMIC_WRAP_INIT_V2}, 1)
 LOCAL_SRCS-y += ${LOCAL_DIR}/pmic_wrap_init_v2.c
+else ifeq (${USE_PMIC_WRAP_INIT_V3}, 1)
+LOCAL_SRCS-y += ${LOCAL_DIR}/pmic_wrap_init_v3.c
 else
 LOCAL_SRCS-y += ${LOCAL_DIR}/pmic_wrap_init.c
 endif

diff --git a/plat/mediatek/drivers/slbc/mt8196/rules.mk b/plat/mediatek/drivers/slbc/mt8196/rules.mk
new file mode 100644
index 0000000..eabddfa
--- /dev/null
+++ b/plat/mediatek/drivers/slbc/mt8196/rules.mk

@@ -0,0 +1,13 @@
+#
+# Copyright (c) 2025, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := slbc_$(MTK_SOC)
+
+LOCAL_SRCS-y := $(LOCAL_DIR)/slbc.c
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))

diff --git a/plat/mediatek/drivers/slbc/mt8196/slbc.c b/plat/mediatek/drivers/slbc/mt8196/slbc.c
new file mode 100644
index 0000000..5f7b1e1
--- /dev/null
+++ b/plat/mediatek/drivers/slbc/mt8196/slbc.c

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+
+#include <common/debug.h>
+
+#include <mtk_bl31_interface.h>
+#include <mtk_sip_svc.h>
+
+#define MODULE_TAG "[SLBC]"
+
+enum {
+	MTK_SLBC_KERNEL_OP_CPU_DCC = 0,
+};
+
+static u_register_t slbc_kernel_handler(u_register_t x1, u_register_t x2,
+					u_register_t x3, u_register_t x4,
+					void *handle,
+					struct smccc_res *smccc_ret)
+{
+	uint32_t request_ops = (uint32_t)x1;
+	u_register_t ret = 0;
+
+	switch (request_ops) {
+	case MTK_SLBC_KERNEL_OP_CPU_DCC:
+		cpu_qos_change_dcc(x2, x3);
+		break;
+	default:
+		ERROR("%s: %s, unknown request_ops = %x\n", MODULE_TAG, __func__, request_ops);
+		ret = EIO;
+		break;
+	}
+
+	VERBOSE("%s: %s, request_ops = %x, ret = %lu\n", MODULE_TAG, __func__, request_ops, ret);
+	return ret;
+}
+
+/* Register SiP SMC service */
+DECLARE_SMC_HANDLER(MTK_SIP_KERNEL_SLBC_CONTROL, slbc_kernel_handler);

diff --git a/plat/mediatek/drivers/slbc/rules.mk b/plat/mediatek/drivers/slbc/rules.mk
new file mode 100644
index 0000000..93fd1b8
--- /dev/null
+++ b/plat/mediatek/drivers/slbc/rules.mk

@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2025, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := slbc
+
+LOCAL_SOC_DIR := $(LOCAL_DIR)/$(MTK_SOC)
+PLATFORM_DIR_EXIST := $(shell test -f $(LOCAL_SOC_DIR)/rules.mk && echo yes)
+
+ifeq ($(PLATFORM_DIR_EXIST), yes)
+SUB_RULES-y := $(LOCAL_SOC_DIR)
+$(eval $(call INCLUDE_MAKEFILE,$(SUB_RULES-y)))
+endif

diff --git a/plat/mediatek/drivers/smmu_sid/rules.mk b/plat/mediatek/drivers/smmu_sid/rules.mk
new file mode 100644
index 0000000..9c6dfc8
--- /dev/null
+++ b/plat/mediatek/drivers/smmu_sid/rules.mk

@@ -0,0 +1,16 @@
+#
+# Copyright (c) 2025, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := smmu_sid
+
+LOCAL_SRCS-y := $(LOCAL_DIR)/smmu_sid.c
+ifeq ($(MTKLIB_PATH),)
+LOCAL_SRCS-y += $(LOCAL_DIR)/smmu_sid_stub.c
+endif
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))

diff --git a/plat/mediatek/drivers/smmu_sid/smmu_sid.c b/plat/mediatek/drivers/smmu_sid/smmu_sid.c
new file mode 100644
index 0000000..2d852b6
--- /dev/null
+++ b/plat/mediatek/drivers/smmu_sid/smmu_sid.c

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/mtk_init/mtk_init.h>
+#include <mtk_bl31_interface.h>
+
+static int mtk_smmu_sid_init(void)
+{
+	return smmu_sid_init();
+}
+
+MTK_PLAT_SETUP_0_INIT(mtk_smmu_sid_init);

diff --git a/plat/mediatek/drivers/smmu_sid/smmu_sid_stub.c b/plat/mediatek/drivers/smmu_sid/smmu_sid_stub.c
new file mode 100644
index 0000000..2ed162c
--- /dev/null
+++ b/plat/mediatek/drivers/smmu_sid/smmu_sid_stub.c

@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mtk_bl31_interface.h>
+
+int smmu_sid_init(void)
+{
+	return 0;
+}

diff --git a/plat/mediatek/drivers/spmi/mt8189/platform_pmif_spmi.c b/plat/mediatek/drivers/spmi/mt8189/platform_pmif_spmi.c
new file mode 100644
index 0000000..417f779
--- /dev/null
+++ b/plat/mediatek/drivers/spmi/mt8189/platform_pmif_spmi.c

@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+
+#include <drivers/spmi/pmif_common.h>
+#include <drivers/spmi/pmif_v1/pmif.h>
+#include <drivers/spmi/spmi_common.h>
+#include <drivers/spmi/spmi_sw.h>
+#include <drivers/spmi_api.h>
+#include <lib/mtk_init/mtk_init.h>
+#include <mtk_mmap_pool.h>
+
+#define SPMI_GROUP_ID	0xB
+#define SPMI_DEBUG	0
+
+static uint16_t mt6xxx_regs[] = {
+	[PMIF_INIT_DONE] =			0x0000,
+	[PMIF_INF_EN] =				0x0024,
+	[PMIF_ARB_EN] =				0x0150,
+	[PMIF_IRQ_EVENT_EN_0] =			0x0420,
+	[PMIF_IRQ_FLAG_0] =			0x0428,
+	[PMIF_IRQ_CLR_0] =			0x042C,
+	[PMIF_IRQ_EVENT_EN_2] =			0x0440,
+	[PMIF_IRQ_FLAG_2] =			0x0448,
+	[PMIF_IRQ_CLR_2] =			0x044C,
+	[PMIF_WDT_CTRL] =			0x0470,
+	[PMIF_WDT_EVENT_EN_1] =			0x047C,
+	[PMIF_WDT_FLAG_1] =			0x0480,
+	[PMIF_SWINF_2_ACC] =			0x0880,
+	[PMIF_SWINF_2_WDATA_31_0] =		0x0884,
+	[PMIF_SWINF_2_WDATA_63_32] =		0x0888,
+	[PMIF_SWINF_2_RDATA_31_0] =		0x0894,
+	[PMIF_SWINF_2_RDATA_63_32] =		0x0898,
+	[PMIF_SWINF_2_VLD_CLR] =		0x08A4,
+	[PMIF_SWINF_2_STA] =			0x08A8,
+	[PMIF_SWINF_3_ACC] =			0x08C0,
+	[PMIF_SWINF_3_WDATA_31_0] =		0x08C4,
+	[PMIF_SWINF_3_WDATA_63_32] =		0x08C8,
+	[PMIF_SWINF_3_RDATA_31_0] =		0x08D4,
+	[PMIF_SWINF_3_RDATA_63_32] =		0x08D8,
+	[PMIF_SWINF_3_VLD_CLR] =		0x08E4,
+	[PMIF_SWINF_3_STA] =			0x08E8,
+	/* hw mpu */
+	[PMIF_PMIC_ALL_RGN_EN_1] =		0x09B0,
+	[PMIF_PMIC_ALL_RGN_EN_2] =		0x0D30,
+	[PMIF_PMIC_ALL_RGN_0_START] =		0x09B4,
+	[PMIF_PMIC_ALL_RGN_0_END] =		0x09B8,
+	[PMIF_PMIC_ALL_RGN_1_START] =		0x09BC,
+	[PMIF_PMIC_ALL_RGN_1_END] =		0x09C0,
+	[PMIF_PMIC_ALL_RGN_2_START] =		0x09C4,
+	[PMIF_PMIC_ALL_RGN_2_END] =		0x09C8,
+	[PMIF_PMIC_ALL_RGN_3_START] =		0x09CC,
+	[PMIF_PMIC_ALL_RGN_3_END] =		0x09D0,
+	[PMIF_PMIC_ALL_RGN_31_START] =		0x0D34,
+	[PMIF_PMIC_ALL_RGN_31_END] =		0x0D38,
+	[PMIF_PMIC_ALL_INVLD_SLVID] =		0x0AAC,
+	[PMIF_PMIC_ALL_RGN_0_PER0] =		0x0AB0,
+	[PMIF_PMIC_ALL_RGN_0_PER1] =		0x0AB4,
+	[PMIF_PMIC_ALL_RGN_1_PER0] =		0x0AB8,
+	[PMIF_PMIC_ALL_RGN_2_PER0] =		0x0AC0,
+	[PMIF_PMIC_ALL_RGN_3_PER0] =		0x0AC8,
+	[PMIF_PMIC_ALL_RGN_31_PER0] =		0x0E34,
+	[PMIF_PMIC_ALL_RGN_31_PER1] =		0x0E38,
+	[PMIF_PMIC_ALL_RGN_OTHERS_PER0] =	0x0BA8,
+	[PMIF_PMIC_ALL_RGN_OTHERS_PER1] =	0x0BAC,
+};
+
+static uint16_t mt6xxx_spmi_regs[] = {
+	[SPMI_OP_ST_CTRL] =		0x0000,
+	[SPMI_GRP_ID_EN] =		0x0004,
+	[SPMI_OP_ST_STA] =		0x0008,
+	[SPMI_MST_SAMPL] =		0x000c,
+	[SPMI_MST_REQ_EN] =		0x0010,
+	[SPMI_RCS_CTRL] =		0x0014,
+	[SPMI_SLV_3_0_EINT] =		0x0020,
+	[SPMI_SLV_7_4_EINT] =		0x0024,
+	[SPMI_SLV_B_8_EINT] =		0x0028,
+	[SPMI_SLV_F_C_EINT] =		0x002c,
+	[SPMI_REC_CTRL] =		0x0040,
+	[SPMI_REC0] =			0x0044,
+	[SPMI_REC1] =			0x0048,
+	[SPMI_REC2] =			0x004c,
+	[SPMI_REC3] =			0x0050,
+	[SPMI_REC4] =			0x0054,
+	[SPMI_REC_CMD_DEC] =		0x005c,
+	[SPMI_DEC_DBG] =		0x00f8,
+	[SPMI_MST_DBG] =		0x00fc,
+};
+
+struct pmif pmif_spmi_arb[] = {
+	{
+		.regs = mt6xxx_regs,
+		.spmimst_regs = mt6xxx_spmi_regs,
+		.mstid = SPMI_MASTER_0,
+		.read_cmd = pmif_spmi_read_cmd,
+		.write_cmd = pmif_spmi_write_cmd,
+	},
+	{
+		.regs = mt6xxx_regs,
+		.spmimst_regs = mt6xxx_spmi_regs,
+		.mstid = SPMI_MASTER_1,
+		.read_cmd = pmif_spmi_read_cmd,
+		.write_cmd = pmif_spmi_write_cmd,
+	},
+	{
+		.base = (unsigned int *)PMIF_SPMI_P_BASE,
+		.regs = mt6xxx_regs,
+		.spmimst_base = (unsigned int *)SPMI_MST_P_BASE,
+		.spmimst_regs = mt6xxx_spmi_regs,
+		.mstid = SPMI_MASTER_P_1,
+		.read_cmd = pmif_spmi_read_cmd,
+		.write_cmd = pmif_spmi_write_cmd,
+	},
+};
+
+static struct spmi_device spmi_dev[] = {
+	{
+		.slvid = SPMI_SLAVE_7, /* MT6319 */
+		.grpiden = 0x800,
+		.type = BUCK_CPU,
+		.type_id = BUCK_CPU_ID,
+		.mstid = SPMI_MASTER_P_1,/* spmi-p */
+		.hwcid_addr = 0x09,
+		.hwcid_val = 0x15,
+		.swcid_addr = 0x0B,
+		.swcid_val = 0x15,
+		.wpk_key_addr = 0x3A8,
+		.wpk_key_val = 0x6315,
+		.tma_key_addr = 0x39F,
+		.tma_key_val = 0x9CEA,
+		.pmif_arb = &pmif_spmi_arb[SPMI_MASTER_P_1],
+	},
+	{
+		.slvid = SPMI_SLAVE_8, /* MT6319 */
+		.grpiden = 0x800,
+		.type = BUCK_CPU,
+		.type_id = BUCK_CPU_ID,
+		.mstid = SPMI_MASTER_P_1,/* spmi-p */
+		.hwcid_addr = 0x09,
+		.hwcid_val = 0x15,
+		.swcid_addr = 0x0B,
+		.swcid_val = 0x15,
+		.wpk_key_addr = 0x3A8,
+		.wpk_key_val = 0x6315,
+		.tma_key_addr = 0x39F,
+		.tma_key_val = 0x9CEA,
+		.pmif_arb = &pmif_spmi_arb[SPMI_MASTER_P_1],
+	},
+};
+
+int platform_pmif_spmi_init(void)
+{
+/*
+ * The MT8189 chipset comes in two variants: MT8189G and MT8189H. The
+ * MT8189G variant uses a single PMIC IC (MT6319), whereas the MT8189H
+ * variant uses two PMIC ICs. To ensure driver compatibility, we utilize
+ * the CPU ID and segment ID to accurately determine the required number
+ * of SPMIF instances.
+ */
+	if (mmio_read_32((uintptr_t)CHIP_ID_REG) == MTK_CPU_ID_MT8189 &&
+	    mmio_read_32((uintptr_t)CPU_SEG_ID_REG) == MTK_CPU_SEG_ID_MT8189G)
+		spmi_device_register(spmi_dev, 1);
+	else
+		spmi_device_register(spmi_dev, ARRAY_SIZE(spmi_dev));
+
+	return 0;
+}
+MTK_ARCH_INIT(platform_pmif_spmi_init);

diff --git a/plat/mediatek/drivers/ufs/mt8196/ufs_ctrl_soc.c b/plat/mediatek/drivers/ufs/mt8196/ufs_ctrl_soc.c
new file mode 100644
index 0000000..2db07bf
--- /dev/null
+++ b/plat/mediatek/drivers/ufs/mt8196/ufs_ctrl_soc.c

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2025, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/pmic/pmic_set_lowpower.h>
+#if defined(CONFIG_MTK_MTCMOS)
+#include <mtcmos.h>
+#endif
+#include <mtk_bl31_interface.h>
+
+static void ufs_vsx_lpm(bool lpm, uint64_t ufs_version)
+{
+	if (lpm) {
+		/* MT6363 VS2 voter LOW byte BIT6 vote reduce VS2 voltage */
+		PMIC_BUCK_VOTER_EN(MT6363, VS2, VOTER_EN_LO_BIT6, VOTER_EN_CLR);
+
+		/* VS2 buck can enter LPM */
+		PMIC_BUCK_SET_LP(MT6363, VS2, HW2, true, OP_MODE_LP, HW_LP);
+	} else {
+		/* MT6363 VS2 voter LOW byte BIT6 vote raise VS2 voltage */
+		PMIC_BUCK_VOTER_EN(MT6363, VS2, VOTER_EN_LO_BIT6, VOTER_EN_SET);
+
+		/* VS2 buck can not enter LPM */
+		PMIC_BUCK_SET_LP(MT6363, VS2, HW2, true, OP_MODE_LP, HW_ONLV);
+	}
+}
+
+void ufs_device_pwr_ctrl_soc(bool vcc_on, uint64_t ufs_version)
+{
+	if (vcc_on)
+		ufs_vsx_lpm(false, ufs_version);
+	else
+		ufs_vsx_lpm(true, ufs_version);
+}
+
+int ufs_spm_mtcmos_power(bool on)
+{
+#if defined(CONFIG_MTK_MTCMOS)
+	return spm_mtcmos_ctrl_ufs0(on ? STA_POWER_ON : STA_POWER_DOWN);
+#else
+	return 0;
+#endif
+}
+
+int ufs_phy_spm_mtcmos_power(bool on)
+{
+#if defined(CONFIG_MTK_MTCMOS)
+	return spm_mtcmos_ctrl_ufs0_phy(on ? STA_POWER_ON : STA_POWER_DOWN);
+#else
+	return 0;
+#endif
+}

diff --git a/plat/mediatek/drivers/ufs/rules.mk b/plat/mediatek/drivers/ufs/rules.mk
index 877cbc7..13d3f53 100644
--- a/plat/mediatek/drivers/ufs/rules.mk
+++ b/plat/mediatek/drivers/ufs/rules.mk

@@ -12,6 +12,7 @@
 PLAT_INCLUDES += -I$(MTK_PLAT)/include/drivers/
 
 LOCAL_SRCS-y := $(LOCAL_DIR)/ufs_ctrl.c
+LOCAL_SRCS-y += $(LOCAL_DIR)/$(MTK_SOC)/ufs_ctrl_soc.c
 ifeq ($(MTKLIB_PATH),)
 LOCAL_SRCS-y += $(LOCAL_DIR)/ufs_stub.c
 endif

diff --git a/plat/mediatek/drivers/ufs/ufs_ctrl.c b/plat/mediatek/drivers/ufs/ufs_ctrl.c
index af27e67..14d0616 100644
--- a/plat/mediatek/drivers/ufs/ufs_ctrl.c
+++ b/plat/mediatek/drivers/ufs/ufs_ctrl.c

@@ -8,6 +8,8 @@
 
 /* MTK header */
 #include <drivers/pmic/pmic_swap_api.h>
+#include <lpm_v2/mt_lp_api.h>
+#include <lpm_v2/mt_lp_rq.h>
 #include <mtk_bl31_interface.h>
 #include <mtk_sip_svc.h>
 
@@ -39,6 +41,63 @@
 		smccc_ret->a1 = VCC_1;
 }
 
+/* SPM resource control */
+#define RSC_MEM			(MT_LP_RQ_DRAM | MT_LP_RQ_EMI)
+#define RSC_PMIC		MT_LP_RQ_PMIC
+
+static int ufs_rsc_ctrl(unsigned int rsc, bool hold)
+{
+	static struct mt_lp_resource_user ufs_res_user;
+	int ret = -1;
+
+	if (!ufs_res_user.uid) {
+		ret = mt_lp_resource_user_register("UFS", &ufs_res_user);
+
+		if (ret) {
+			WARN("%s: register lp resource failed\n", __func__);
+			return ret;
+		}
+	}
+
+	if (hold)
+		ret = ufs_res_user.request(&ufs_res_user, rsc);
+	else
+		ret = ufs_res_user.release(&ufs_res_user);
+
+	VERBOSE("%s: rsc=%d, hold=%d\n", __func__, rsc, hold);
+
+	if (ret)
+		WARN("%s: RSC_%d %s failed\n", __func__, rsc, hold ? "request" : "release");
+
+	return ret;
+}
+
+int ufs_rsc_ctrl_mem(bool hold)
+{
+	return ufs_rsc_ctrl(RSC_MEM, hold);
+}
+
+int ufs_rcs_ctrl_pmic(bool hold)
+{
+	return ufs_rsc_ctrl(RSC_PMIC, hold);
+}
+
+/* UFS clock status */
+static uint32_t ufs_clk_sta = UFS_REF_CLK_ON;
+
+bool ufs_is_clk_status_off(void)
+{
+	return ufs_clk_sta == UFS_REF_CLK_OFF;
+}
+
+void ufs_set_clk_status(bool on)
+{
+	if (on)
+		ufs_clk_sta = UFS_REF_CLK_ON;
+	else
+		ufs_clk_sta = UFS_REF_CLK_OFF;
+}
+
 static u_register_t ufs_knl_ctrl(u_register_t x1,
 				 u_register_t x2,
 				 u_register_t x3,
@@ -50,10 +109,10 @@
 
 	switch (x1) {
 	case UFS_MTK_SIP_VA09_PWR_CTRL:
-		ufs_mphy_va09_cg_ctrl((bool)!!x2);
+		ufs_mphy_va09_cg_ctrl(!!x2);
 		break;
 	case UFS_MTK_SIP_DEVICE_RESET:
-		ufs_device_reset_ctrl((bool)!!x2);
+		ufs_device_reset_ctrl(!!x2);
 		break;
 	case UFS_MTK_SIP_CRYPTO_CTRL:
 		ufs_crypto_hie_init();
@@ -74,7 +133,9 @@
 		ufs_mphy_ctrl(x2);
 		break;
 	case UFS_MTK_SIP_MTCMOS_CTRL:
-		ufs_mtcmos_ctrl(x2);
+#if defined(CONFIG_MTK_MTCMOS)
+		ufs_mtcmos_ctrl(!!x2);
+#endif
 		break;
 	default:
 		ret = -1;

diff --git a/plat/mediatek/include/drivers/pmic/mt6319_lowpower_reg.h b/plat/mediatek/include/drivers/pmic/mt6319_lowpower_reg.h
new file mode 100644
index 0000000..71a2d2b
--- /dev/null
+++ b/plat/mediatek/include/drivers/pmic/mt6319_lowpower_reg.h

@@ -0,0 +1,185 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT6319_LOWPOWER_REG_H
+#define MT6319_LOWPOWER_REG_H
+
+#define MT6319_RG_LDO_VDIG18_SW_OP_EN_ADDR		0x0196
+#define MT6319_RG_LDO_VDIG18_HW_OP_EN_ADDR		0x0196
+#define MT6319_RG_VDIG18_PWROFF_OP_EN_ADDR		0x0197
+#define MT6319_RG_BUCK_VBUCK1_HW0_OP_EN_ADDR		0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW1_OP_EN_ADDR		0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW2_OP_EN_ADDR		0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW3_OP_EN_ADDR		0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW4_OP_EN_ADDR		0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW5_OP_EN_ADDR		0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW6_OP_EN_ADDR		0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW7_OP_EN_ADDR		0x148d
+#define MT6319_RG_BUCK_VBUCK1_HW8_OP_EN_ADDR		0x1708
+#define MT6319_RG_BUCK_VBUCK1_HW9_OP_EN_ADDR		0x1708
+#define MT6319_RG_BUCK_VBUCK1_HW10_OP_EN_ADDR		0x1708
+#define MT6319_RG_BUCK_VBUCK1_HW11_OP_EN_ADDR		0x1708
+#define MT6319_RG_BUCK_VBUCK1_HW12_OP_EN_ADDR		0x1708
+#define MT6319_RG_BUCK_VBUCK1_HW13_OP_EN_ADDR		0x1708
+#define MT6319_RG_BUCK_VBUCK1_SW_OP_EN_ADDR		0x1490
+#define MT6319_RG_BUCK_VBUCK1_HW0_OP_CFG_ADDR		0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW1_OP_CFG_ADDR		0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW2_OP_CFG_ADDR		0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW3_OP_CFG_ADDR		0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW4_OP_CFG_ADDR		0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW5_OP_CFG_ADDR		0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW6_OP_CFG_ADDR		0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW7_OP_CFG_ADDR		0x1493
+#define MT6319_RG_BUCK_VBUCK1_HW8_OP_CFG_ADDR		0x170b
+#define MT6319_RG_BUCK_VBUCK1_HW9_OP_CFG_ADDR		0x170b
+#define MT6319_RG_BUCK_VBUCK1_HW10_OP_CFG_ADDR		0x170b
+#define MT6319_RG_BUCK_VBUCK1_HW11_OP_CFG_ADDR		0x170b
+#define MT6319_RG_BUCK_VBUCK1_HW12_OP_CFG_ADDR		0x170b
+#define MT6319_RG_BUCK_VBUCK1_HW13_OP_CFG_ADDR		0x170b
+#define MT6319_RG_BUCK_VBUCK1_HW0_OP_MODE_ADDR		0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW1_OP_MODE_ADDR		0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW2_OP_MODE_ADDR		0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW3_OP_MODE_ADDR		0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW4_OP_MODE_ADDR		0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW5_OP_MODE_ADDR		0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW6_OP_MODE_ADDR		0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW7_OP_MODE_ADDR		0x1496
+#define MT6319_RG_BUCK_VBUCK1_HW8_OP_MODE_ADDR		0x170e
+#define MT6319_RG_BUCK_VBUCK1_HW9_OP_MODE_ADDR		0x170e
+#define MT6319_RG_BUCK_VBUCK1_HW10_OP_MODE_ADDR		0x170e
+#define MT6319_RG_BUCK_VBUCK1_HW11_OP_MODE_ADDR		0x170e
+#define MT6319_RG_BUCK_VBUCK1_HW12_OP_MODE_ADDR		0x170e
+#define MT6319_RG_BUCK_VBUCK1_HW13_OP_MODE_ADDR		0x170e
+#define MT6319_RG_BUCK_VBUCK2_HW0_OP_EN_ADDR		0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW1_OP_EN_ADDR		0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW2_OP_EN_ADDR		0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW3_OP_EN_ADDR		0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW4_OP_EN_ADDR		0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW5_OP_EN_ADDR		0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW6_OP_EN_ADDR		0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW7_OP_EN_ADDR		0x150d
+#define MT6319_RG_BUCK_VBUCK2_HW8_OP_EN_ADDR		0x1711
+#define MT6319_RG_BUCK_VBUCK2_HW9_OP_EN_ADDR		0x1711
+#define MT6319_RG_BUCK_VBUCK2_HW10_OP_EN_ADDR		0x1711
+#define MT6319_RG_BUCK_VBUCK2_HW11_OP_EN_ADDR		0x1711
+#define MT6319_RG_BUCK_VBUCK2_HW12_OP_EN_ADDR		0x1711
+#define MT6319_RG_BUCK_VBUCK2_HW13_OP_EN_ADDR		0x1711
+#define MT6319_RG_BUCK_VBUCK2_SW_OP_EN_ADDR		0x1510
+#define MT6319_RG_BUCK_VBUCK2_HW0_OP_CFG_ADDR		0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW1_OP_CFG_ADDR		0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW2_OP_CFG_ADDR		0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW3_OP_CFG_ADDR		0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW4_OP_CFG_ADDR		0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW5_OP_CFG_ADDR		0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW6_OP_CFG_ADDR		0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW7_OP_CFG_ADDR		0x1513
+#define MT6319_RG_BUCK_VBUCK2_HW8_OP_CFG_ADDR		0x1714
+#define MT6319_RG_BUCK_VBUCK2_HW9_OP_CFG_ADDR		0x1714
+#define MT6319_RG_BUCK_VBUCK2_HW10_OP_CFG_ADDR		0x1714
+#define MT6319_RG_BUCK_VBUCK2_HW11_OP_CFG_ADDR		0x1714
+#define MT6319_RG_BUCK_VBUCK2_HW12_OP_CFG_ADDR		0x1714
+#define MT6319_RG_BUCK_VBUCK2_HW13_OP_CFG_ADDR		0x1714
+#define MT6319_RG_BUCK_VBUCK2_HW0_OP_MODE_ADDR		0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW1_OP_MODE_ADDR		0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW2_OP_MODE_ADDR		0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW3_OP_MODE_ADDR		0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW4_OP_MODE_ADDR		0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW5_OP_MODE_ADDR		0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW6_OP_MODE_ADDR		0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW7_OP_MODE_ADDR		0x1516
+#define MT6319_RG_BUCK_VBUCK2_HW8_OP_MODE_ADD		0x1717
+#define MT6319_RG_BUCK_VBUCK2_HW9_OP_MODE_ADDR		0x1717
+#define MT6319_RG_BUCK_VBUCK2_HW10_OP_MODE_ADDR		0x1717
+#define MT6319_RG_BUCK_VBUCK2_HW11_OP_MODE_ADDR		0x1717
+#define MT6319_RG_BUCK_VBUCK2_HW12_OP_MODE_ADDR		0x1717
+#define MT6319_RG_BUCK_VBUCK2_HW13_OP_MODE_ADDR		0x1717
+#define MT6319_RG_BUCK_VBUCK3_HW0_OP_EN_ADDR		0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW1_OP_EN_ADDR		0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW2_OP_EN_ADDR		0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW3_OP_EN_ADDR		0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW4_OP_EN_ADDR		0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW5_OP_EN_ADDR		0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW6_OP_EN_ADDR		0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW7_OP_EN_ADDR		0x158d
+#define MT6319_RG_BUCK_VBUCK3_HW8_OP_EN_ADDR		0x171a
+#define MT6319_RG_BUCK_VBUCK3_HW9_OP_EN_ADDR		0x171a
+#define MT6319_RG_BUCK_VBUCK3_HW10_OP_EN_ADDR		0x171a
+#define MT6319_RG_BUCK_VBUCK3_HW11_OP_EN_ADDR		0x171a
+#define MT6319_RG_BUCK_VBUCK3_HW12_OP_EN_ADDR		0x171a
+#define MT6319_RG_BUCK_VBUCK3_HW13_OP_EN_ADDR		0x171a
+#define MT6319_RG_BUCK_VBUCK3_SW_OP_EN_ADDR		0x1590
+#define MT6319_RG_BUCK_VBUCK3_HW0_OP_CFG_ADDR		0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW1_OP_CFG_ADDR		0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW2_OP_CFG_ADDR		0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW3_OP_CFG_ADDR		0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW4_OP_CFG_ADDR		0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW5_OP_CFG_ADDR		0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW6_OP_CFG_ADDR		0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW7_OP_CFG_ADDR		0x1593
+#define MT6319_RG_BUCK_VBUCK3_HW8_OP_CFG_ADDR		0x171d
+#define MT6319_RG_BUCK_VBUCK3_HW9_OP_CFG_ADDR		0x171d
+#define MT6319_RG_BUCK_VBUCK3_HW10_OP_CFG_ADDR		0x171d
+#define MT6319_RG_BUCK_VBUCK3_HW11_OP_CFG_ADDR		0x171d
+#define MT6319_RG_BUCK_VBUCK3_HW12_OP_CFG_ADDR		0x171d
+#define MT6319_RG_BUCK_VBUCK3_HW13_OP_CFG_ADDR		0x171d
+#define MT6319_RG_BUCK_VBUCK3_HW0_OP_MODE_ADDR		0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW1_OP_MODE_ADDR		0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW2_OP_MODE_ADDR		0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW3_OP_MODE_ADDR		0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW4_OP_MODE_ADDR		0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW5_OP_MODE_ADDR		0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW6_OP_MODE_ADDR		0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW7_OP_MODE_ADDR		0x1596
+#define MT6319_RG_BUCK_VBUCK3_HW8_OP_MODE_ADDR		0x1720
+#define MT6319_RG_BUCK_VBUCK3_HW9_OP_MODE_ADDR		0x1720
+#define MT6319_RG_BUCK_VBUCK3_HW10_OP_MODE_ADDR		0x1720
+#define MT6319_RG_BUCK_VBUCK3_HW11_OP_MODE_ADDR		0x1720
+#define MT6319_RG_BUCK_VBUCK3_HW12_OP_MODE_ADDR		0x1720
+#define MT6319_RG_BUCK_VBUCK3_HW13_OP_MODE_ADDR		0x1720
+#define MT6319_RG_BUCK_VBUCK4_HW0_OP_EN_ADDR		0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW1_OP_EN_ADDR		0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW2_OP_EN_ADDR		0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW3_OP_EN_ADDR		0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW4_OP_EN_ADDR		0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW5_OP_EN_ADDR		0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW6_OP_EN_ADDR		0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW7_OP_EN_ADDR		0x160d
+#define MT6319_RG_BUCK_VBUCK4_HW8_OP_EN_ADDR		0x1723
+#define MT6319_RG_BUCK_VBUCK4_HW9_OP_EN_ADDR		0x1723
+#define MT6319_RG_BUCK_VBUCK4_HW10_OP_EN_ADDR		0x1723
+#define MT6319_RG_BUCK_VBUCK4_HW11_OP_EN_ADDR		0x1723
+#define MT6319_RG_BUCK_VBUCK4_HW12_OP_EN_ADDR		0x1723
+#define MT6319_RG_BUCK_VBUCK4_HW13_OP_EN_ADDR		0x1723
+#define MT6319_RG_BUCK_VBUCK4_SW_OP_EN_ADDR		0x1610
+#define MT6319_RG_BUCK_VBUCK4_HW0_OP_CFG_ADDR		0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW1_OP_CFG_ADDR		0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW2_OP_CFG_ADDR		0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW3_OP_CFG_ADDR		0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW4_OP_CFG_ADDR		0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW5_OP_CFG_ADDR		0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW6_OP_CFG_ADDR		0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW7_OP_CFG_ADDR		0x1613
+#define MT6319_RG_BUCK_VBUCK4_HW8_OP_CFG_ADDR		0x1726
+#define MT6319_RG_BUCK_VBUCK4_HW9_OP_CFG_ADDR		0x1726
+#define MT6319_RG_BUCK_VBUCK4_HW10_OP_CFG_ADDR		0x1726
+#define MT6319_RG_BUCK_VBUCK4_HW11_OP_CFG_ADDR		0x1726
+#define MT6319_RG_BUCK_VBUCK4_HW12_OP_CFG_ADDR		0x1726
+#define MT6319_RG_BUCK_VBUCK4_HW13_OP_CFG_ADDR		0x1726
+#define MT6319_RG_BUCK_VBUCK4_HW0_OP_MODE_ADDR		0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW1_OP_MODE_ADDR		0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW2_OP_MODE_ADDR		0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW3_OP_MODE_ADDR		0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW4_OP_MODE_ADDR		0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW5_OP_MODE_ADDR		0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW6_OP_MODE_ADDR		0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW7_OP_MODE_ADDR		0x1616
+#define MT6319_RG_BUCK_VBUCK4_HW8_OP_MODE_ADDR		0x1729
+#define MT6319_RG_BUCK_VBUCK4_HW9_OP_MODE_ADDR		0x1729
+#define MT6319_RG_BUCK_VBUCK4_HW10_OP_MODE_ADDR		0x1729
+#define MT6319_RG_BUCK_VBUCK4_HW11_OP_MODE_ADDR		0x1729
+#define MT6319_RG_BUCK_VBUCK4_HW12_OP_MODE_ADDR		0x1729
+#define MT6319_RG_BUCK_VBUCK4_HW13_OP_MODE_ADDR		0x1729
+
+#endif /* MT6319_LOWPOWER_REG_H */

diff --git a/plat/mediatek/include/drivers/pmic/mt6359p_lowpower_reg.h b/plat/mediatek/include/drivers/pmic/mt6359p_lowpower_reg.h
new file mode 100644
index 0000000..7e14f00
--- /dev/null
+++ b/plat/mediatek/include/drivers/pmic/mt6359p_lowpower_reg.h

@@ -0,0 +1,1593 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT6359P_LOWPOWER_REG_H
+#define MT6359P_LOWPOWER_REG_H
+
+#define MT6359P_RG_BUCK_VPU_VOSEL_SLEEP_ADDR			0x148e
+#define MT6359P_RG_BUCK_VPU_HW0_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_HW1_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_HW2_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_HW3_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_HW4_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_HW5_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_HW6_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_HW7_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_HW8_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_HW9_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_HW10_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_HW11_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_HW12_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_HW13_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_HW14_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_SW_OP_EN_ADDR			0x1494
+#define MT6359P_RG_BUCK_VPU_HW0_OP_CFG_ADDR			0x149a
+#define MT6359P_RG_BUCK_VPU_HW1_OP_CFG_ADDR			0x149a
+#define MT6359P_RG_BUCK_VPU_HW2_OP_CFG_ADDR			0x149a
+#define MT6359P_RG_BUCK_VPU_HW3_OP_CFG_ADDR			0x149a
+#define MT6359P_RG_BUCK_VPU_HW4_OP_CFG_ADDR			0x149a
+#define MT6359P_RG_BUCK_VPU_HW5_OP_CFG_ADDR			0x149a
+#define MT6359P_RG_BUCK_VPU_HW6_OP_CFG_ADDR			0x149a
+#define MT6359P_RG_BUCK_VPU_HW7_OP_CFG_ADDR			0x149a
+#define MT6359P_RG_BUCK_VPU_HW8_OP_CFG_ADDR			0x149a
+#define MT6359P_RG_BUCK_VPU_HW9_OP_CFG_ADDR			0x149a
+#define MT6359P_RG_BUCK_VPU_HW10_OP_CFG_ADDR			0x149a
+#define MT6359P_RG_BUCK_VPU_HW11_OP_CFG_ADDR			0x149a
+#define MT6359P_RG_BUCK_VPU_HW12_OP_CFG_ADDR			0x149a
+#define MT6359P_RG_BUCK_VPU_HW13_OP_CFG_ADDR			0x149a
+#define MT6359P_RG_BUCK_VPU_HW14_OP_CFG_ADDR			0x149a
+#define MT6359P_RG_BUCK_VPU_HW0_OP_MODE_ADDR			0x14a0
+#define MT6359P_RG_BUCK_VPU_HW0_OP_MODE_SHIFT			0
+#define MT6359P_RG_BUCK_VPU_HW1_OP_MODE_ADDR			0x14a0
+#define MT6359P_RG_BUCK_VPU_HW1_OP_MODE_SHIFT			1
+#define MT6359P_RG_BUCK_VPU_HW2_OP_MODE_ADDR			0x14a0
+#define MT6359P_RG_BUCK_VPU_HW2_OP_MODE_SHIFT			2
+#define MT6359P_RG_BUCK_VPU_HW3_OP_MODE_ADDR			0x14a0
+#define MT6359P_RG_BUCK_VPU_HW3_OP_MODE_SHIFT			3
+#define MT6359P_RG_BUCK_VPU_HW4_OP_MODE_ADDR			0x14a0
+#define MT6359P_RG_BUCK_VPU_HW4_OP_MODE_SHIFT			4
+#define MT6359P_RG_BUCK_VPU_HW5_OP_MODE_ADDR			0x14a0
+#define MT6359P_RG_BUCK_VPU_HW5_OP_MODE_SHIFT			5
+#define MT6359P_RG_BUCK_VPU_HW6_OP_MODE_ADDR			0x14a0
+#define MT6359P_RG_BUCK_VPU_HW6_OP_MODE_SHIFT			6
+#define MT6359P_RG_BUCK_VPU_HW7_OP_MODE_ADDR			0x14a0
+#define MT6359P_RG_BUCK_VPU_HW7_OP_MODE_SHIFT			7
+#define MT6359P_RG_BUCK_VPU_HW8_OP_MODE_ADDR			0x14a0
+#define MT6359P_RG_BUCK_VPU_HW8_OP_MODE_SHIFT			8
+#define MT6359P_RG_BUCK_VPU_HW9_OP_MODE_ADDR			0x14a0
+#define MT6359P_RG_BUCK_VPU_HW9_OP_MODE_SHIFT			9
+#define MT6359P_RG_BUCK_VPU_HW10_OP_MODE_ADDR			0x14a0
+#define MT6359P_RG_BUCK_VPU_HW10_OP_MODE_SHIFT			10
+#define MT6359P_RG_BUCK_VPU_HW11_OP_MODE_ADDR			0x14a0
+#define MT6359P_RG_BUCK_VPU_HW11_OP_MODE_SHIFT			11
+#define MT6359P_RG_BUCK_VPU_HW12_OP_MODE_ADDR			0x14a0
+#define MT6359P_RG_BUCK_VPU_HW12_OP_MODE_SHIFT			12
+#define MT6359P_RG_BUCK_VPU_HW13_OP_MODE_ADDR			0x14a0
+#define MT6359P_RG_BUCK_VPU_HW13_OP_MODE_SHIFT			13
+#define MT6359P_RG_BUCK_VPU_HW14_OP_MODE_ADDR			0x14a0
+#define MT6359P_RG_BUCK_VPU_HW14_OP_MODE_SHIFT			14
+#define MT6359P_RG_BUCK_VCORE_VOSEL_SLEEP_ADDR			0x150e
+#define MT6359P_RG_BUCK_VCORE_HW0_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_HW1_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_HW2_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_HW3_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_HW4_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_HW5_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_HW6_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_HW7_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_HW8_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_HW9_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_HW10_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_HW11_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_HW12_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_HW13_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_HW14_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_SW_OP_EN_ADDR			0x1514
+#define MT6359P_RG_BUCK_VCORE_HW0_OP_CFG_ADDR			0x151a
+#define MT6359P_RG_BUCK_VCORE_HW1_OP_CFG_ADDR			0x151a
+#define MT6359P_RG_BUCK_VCORE_HW2_OP_CFG_ADDR			0x151a
+#define MT6359P_RG_BUCK_VCORE_HW3_OP_CFG_ADDR			0x151a
+#define MT6359P_RG_BUCK_VCORE_HW4_OP_CFG_ADDR			0x151a
+#define MT6359P_RG_BUCK_VCORE_HW5_OP_CFG_ADDR			0x151a
+#define MT6359P_RG_BUCK_VCORE_HW6_OP_CFG_ADDR			0x151a
+#define MT6359P_RG_BUCK_VCORE_HW7_OP_CFG_ADDR			0x151a
+#define MT6359P_RG_BUCK_VCORE_HW8_OP_CFG_ADDR			0x151a
+#define MT6359P_RG_BUCK_VCORE_HW9_OP_CFG_ADDR			0x151a
+#define MT6359P_RG_BUCK_VCORE_HW10_OP_CFG_ADDR			0x151a
+#define MT6359P_RG_BUCK_VCORE_HW11_OP_CFG_ADDR			0x151a
+#define MT6359P_RG_BUCK_VCORE_HW12_OP_CFG_ADDR			0x151a
+#define MT6359P_RG_BUCK_VCORE_HW13_OP_CFG_ADDR			0x151a
+#define MT6359P_RG_BUCK_VCORE_HW14_OP_CFG_ADDR			0x151a
+#define MT6359P_RG_BUCK_VCORE_HW0_OP_MODE_ADDR			0x1520
+#define MT6359P_RG_BUCK_VCORE_HW0_OP_MODE_SHIFT			0
+#define MT6359P_RG_BUCK_VCORE_HW1_OP_MODE_ADDR			0x1520
+#define MT6359P_RG_BUCK_VCORE_HW1_OP_MODE_SHIFT			1
+#define MT6359P_RG_BUCK_VCORE_HW2_OP_MODE_ADDR			0x1520
+#define MT6359P_RG_BUCK_VCORE_HW2_OP_MODE_SHIFT			2
+#define MT6359P_RG_BUCK_VCORE_HW3_OP_MODE_ADDR			0x1520
+#define MT6359P_RG_BUCK_VCORE_HW3_OP_MODE_SHIFT			3
+#define MT6359P_RG_BUCK_VCORE_HW4_OP_MODE_ADDR			0x1520
+#define MT6359P_RG_BUCK_VCORE_HW4_OP_MODE_SHIFT			4
+#define MT6359P_RG_BUCK_VCORE_HW5_OP_MODE_ADDR			0x1520
+#define MT6359P_RG_BUCK_VCORE_HW5_OP_MODE_SHIFT			5
+#define MT6359P_RG_BUCK_VCORE_HW6_OP_MODE_ADDR			0x1520
+#define MT6359P_RG_BUCK_VCORE_HW6_OP_MODE_SHIFT			6
+#define MT6359P_RG_BUCK_VCORE_HW7_OP_MODE_ADDR			0x1520
+#define MT6359P_RG_BUCK_VCORE_HW7_OP_MODE_SHIFT			7
+#define MT6359P_RG_BUCK_VCORE_HW8_OP_MODE_ADDR			0x1520
+#define MT6359P_RG_BUCK_VCORE_HW8_OP_MODE_SHIFT			8
+#define MT6359P_RG_BUCK_VCORE_HW9_OP_MODE_ADDR			0x1520
+#define MT6359P_RG_BUCK_VCORE_HW9_OP_MODE_SHIFT			9
+#define MT6359P_RG_BUCK_VCORE_HW10_OP_MODE_ADDR			0x1520
+#define MT6359P_RG_BUCK_VCORE_HW10_OP_MODE_SHIFT		10
+#define MT6359P_RG_BUCK_VCORE_HW11_OP_MODE_ADDR			0x1520
+#define MT6359P_RG_BUCK_VCORE_HW11_OP_MODE_SHIFT		11
+#define MT6359P_RG_BUCK_VCORE_HW12_OP_MODE_ADDR			0x1520
+#define MT6359P_RG_BUCK_VCORE_HW12_OP_MODE_SHIFT		12
+#define MT6359P_RG_BUCK_VCORE_HW13_OP_MODE_ADDR			0x1520
+#define MT6359P_RG_BUCK_VCORE_HW13_OP_MODE_SHIFT		13
+#define MT6359P_RG_BUCK_VCORE_HW14_OP_MODE_ADDR			0x1520
+#define MT6359P_RG_BUCK_VCORE_HW14_OP_MODE_SHIFT		14
+#define MT6359P_RG_BUCK_VGPU11_VOSEL_SLEEP_ADDR			0x158e
+#define MT6359P_RG_BUCK_VGPU11_HW0_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW1_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW2_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW3_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW4_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW5_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW6_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW7_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW8_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW9_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW10_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW11_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW12_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW13_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW14_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_SW_OP_EN_ADDR			0x1594
+#define MT6359P_RG_BUCK_VGPU11_HW0_OP_CFG_ADDR			0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW1_OP_CFG_ADDR			0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW2_OP_CFG_ADDR			0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW3_OP_CFG_ADDR			0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW4_OP_CFG_ADDR			0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW5_OP_CFG_ADDR			0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW6_OP_CFG_ADDR			0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW7_OP_CFG_ADDR			0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW8_OP_CFG_ADDR			0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW9_OP_CFG_ADDR			0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW10_OP_CFG_ADDR			0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW11_OP_CFG_ADDR			0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW12_OP_CFG_ADDR			0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW13_OP_CFG_ADDR			0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW14_OP_CFG_ADDR			0x159a
+#define MT6359P_RG_BUCK_VGPU11_HW0_OP_MODE_ADDR			0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW0_OP_MODE_SHIFT		0
+#define MT6359P_RG_BUCK_VGPU11_HW1_OP_MODE_ADDR			0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW1_OP_MODE_SHIFT		1
+#define MT6359P_RG_BUCK_VGPU11_HW2_OP_MODE_ADDR			0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW2_OP_MODE_SHIFT		2
+#define MT6359P_RG_BUCK_VGPU11_HW3_OP_MODE_ADDR			0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW3_OP_MODE_SHIFT		3
+#define MT6359P_RG_BUCK_VGPU11_HW4_OP_MODE_ADDR			0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW4_OP_MODE_SHIFT		4
+#define MT6359P_RG_BUCK_VGPU11_HW5_OP_MODE_ADDR			0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW5_OP_MODE_SHIFT		5
+#define MT6359P_RG_BUCK_VGPU11_HW6_OP_MODE_ADDR			0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW6_OP_MODE_SHIFT		6
+#define MT6359P_RG_BUCK_VGPU11_HW7_OP_MODE_ADDR			0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW7_OP_MODE_SHIFT		7
+#define MT6359P_RG_BUCK_VGPU11_HW8_OP_MODE_ADDR			0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW8_OP_MODE_SHIFT		8
+#define MT6359P_RG_BUCK_VGPU11_HW9_OP_MODE_ADDR			0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW9_OP_MODE_SHIFT		9
+#define MT6359P_RG_BUCK_VGPU11_HW10_OP_MODE_ADDR		0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW10_OP_MODE_SHIFT		10
+#define MT6359P_RG_BUCK_VGPU11_HW11_OP_MODE_ADDR		0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW11_OP_MODE_SHIFT		11
+#define MT6359P_RG_BUCK_VGPU11_HW12_OP_MODE_ADDR		0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW12_OP_MODE_SHIFT		12
+#define MT6359P_RG_BUCK_VGPU11_HW13_OP_MODE_ADDR		0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW13_OP_MODE_SHIFT		13
+#define MT6359P_RG_BUCK_VGPU11_HW14_OP_MODE_ADDR		0x15a0
+#define MT6359P_RG_BUCK_VGPU11_HW14_OP_MODE_SHIFT		14
+#define MT6359P_RG_BUCK_VGPU12_VOSEL_SLEEP_ADDR			0x160e
+#define MT6359P_RG_BUCK_VGPU12_HW0_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW1_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW2_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW3_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW4_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW5_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW6_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW7_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW8_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW9_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW10_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW11_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW12_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW13_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW14_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_SW_OP_EN_ADDR			0x1614
+#define MT6359P_RG_BUCK_VGPU12_HW0_OP_CFG_ADDR			0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW1_OP_CFG_ADDR			0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW2_OP_CFG_ADDR			0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW3_OP_CFG_ADDR			0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW4_OP_CFG_ADDR			0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW5_OP_CFG_ADDR			0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW6_OP_CFG_ADDR			0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW7_OP_CFG_ADDR			0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW8_OP_CFG_ADDR			0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW9_OP_CFG_ADDR			0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW10_OP_CFG_ADDR			0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW11_OP_CFG_ADDR			0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW12_OP_CFG_ADDR			0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW13_OP_CFG_ADDR			0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW14_OP_CFG_ADDR			0x161a
+#define MT6359P_RG_BUCK_VGPU12_HW0_OP_MODE_ADDR			0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW0_OP_MODE_SHIFT		0
+#define MT6359P_RG_BUCK_VGPU12_HW1_OP_MODE_ADDR			0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW1_OP_MODE_SHIFT		1
+#define MT6359P_RG_BUCK_VGPU12_HW2_OP_MODE_ADDR			0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW2_OP_MODE_SHIFT		2
+#define MT6359P_RG_BUCK_VGPU12_HW3_OP_MODE_ADDR			0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW3_OP_MODE_SHIFT		3
+#define MT6359P_RG_BUCK_VGPU12_HW4_OP_MODE_ADDR			0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW4_OP_MODE_SHIFT		4
+#define MT6359P_RG_BUCK_VGPU12_HW5_OP_MODE_ADDR			0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW5_OP_MODE_SHIFT		5
+#define MT6359P_RG_BUCK_VGPU12_HW6_OP_MODE_ADDR			0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW6_OP_MODE_SHIFT		6
+#define MT6359P_RG_BUCK_VGPU12_HW7_OP_MODE_ADDR			0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW7_OP_MODE_SHIFT		7
+#define MT6359P_RG_BUCK_VGPU12_HW8_OP_MODE_ADDR			0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW8_OP_MODE_SHIFT		8
+#define MT6359P_RG_BUCK_VGPU12_HW9_OP_MODE_ADDR			0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW9_OP_MODE_SHIFT		9
+#define MT6359P_RG_BUCK_VGPU12_HW10_OP_MODE_ADDR		0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW10_OP_MODE_SHIFT		10
+#define MT6359P_RG_BUCK_VGPU12_HW11_OP_MODE_ADDR		0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW11_OP_MODE_SHIFT		11
+#define MT6359P_RG_BUCK_VGPU12_HW12_OP_MODE_ADDR		0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW12_OP_MODE_SHIFT		12
+#define MT6359P_RG_BUCK_VGPU12_HW13_OP_MODE_ADDR		0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW13_OP_MODE_SHIFT		13
+#define MT6359P_RG_BUCK_VGPU12_HW14_OP_MODE_ADDR		0x1620
+#define MT6359P_RG_BUCK_VGPU12_HW14_OP_MODE_SHIFT		14
+#define MT6359P_RG_BUCK_VMODEM_VOSEL_SLEEP_ADDR			0x168e
+#define MT6359P_RG_BUCK_VMODEM_HW0_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW1_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW2_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW3_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW4_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW5_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW6_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW7_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW8_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW9_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW10_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW11_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW12_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW13_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW14_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_SW_OP_EN_ADDR			0x1694
+#define MT6359P_RG_BUCK_VMODEM_HW0_OP_CFG_ADDR			0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW1_OP_CFG_ADDR			0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW2_OP_CFG_ADDR			0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW3_OP_CFG_ADDR			0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW4_OP_CFG_ADDR			0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW5_OP_CFG_ADDR			0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW6_OP_CFG_ADDR			0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW7_OP_CFG_ADDR			0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW8_OP_CFG_ADDR			0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW9_OP_CFG_ADDR			0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW10_OP_CFG_ADDR			0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW11_OP_CFG_ADDR			0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW12_OP_CFG_ADDR			0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW13_OP_CFG_ADDR			0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW14_OP_CFG_ADDR			0x169a
+#define MT6359P_RG_BUCK_VMODEM_HW0_OP_MODE_ADDR			0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW0_OP_MODE_SHIFT		0
+#define MT6359P_RG_BUCK_VMODEM_HW1_OP_MODE_ADDR			0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW1_OP_MODE_SHIFT		1
+#define MT6359P_RG_BUCK_VMODEM_HW2_OP_MODE_ADDR			0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW2_OP_MODE_SHIFT		2
+#define MT6359P_RG_BUCK_VMODEM_HW3_OP_MODE_ADDR			0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW3_OP_MODE_SHIFT		3
+#define MT6359P_RG_BUCK_VMODEM_HW4_OP_MODE_ADDR			0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW4_OP_MODE_SHIFT		4
+#define MT6359P_RG_BUCK_VMODEM_HW5_OP_MODE_ADDR			0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW5_OP_MODE_SHIFT		5
+#define MT6359P_RG_BUCK_VMODEM_HW6_OP_MODE_ADDR			0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW6_OP_MODE_SHIFT		6
+#define MT6359P_RG_BUCK_VMODEM_HW7_OP_MODE_ADDR			0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW7_OP_MODE_SHIFT		7
+#define MT6359P_RG_BUCK_VMODEM_HW8_OP_MODE_ADDR			0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW8_OP_MODE_SHIFT		8
+#define MT6359P_RG_BUCK_VMODEM_HW9_OP_MODE_ADDR			0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW9_OP_MODE_SHIFT		9
+#define MT6359P_RG_BUCK_VMODEM_HW10_OP_MODE_ADDR		0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW10_OP_MODE_SHIFT		10
+#define MT6359P_RG_BUCK_VMODEM_HW11_OP_MODE_ADDR		0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW11_OP_MODE_SHIFT		11
+#define MT6359P_RG_BUCK_VMODEM_HW12_OP_MODE_ADDR		0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW12_OP_MODE_SHIFT		12
+#define MT6359P_RG_BUCK_VMODEM_HW13_OP_MODE_ADDR		0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW13_OP_MODE_SHIFT		13
+#define MT6359P_RG_BUCK_VMODEM_HW14_OP_MODE_ADDR		0x16a0
+#define MT6359P_RG_BUCK_VMODEM_HW14_OP_MODE_SHIFT		14
+#define MT6359P_RG_BUCK_VPROC1_VOSEL_SLEEP_ADDR			0x170e
+#define MT6359P_RG_BUCK_VPROC1_HW0_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW1_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW2_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW3_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW4_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW5_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW6_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW7_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW8_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW9_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW10_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW11_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW12_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW13_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW14_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_SW_OP_EN_ADDR			0x1714
+#define MT6359P_RG_BUCK_VPROC1_HW0_OP_CFG_ADDR			0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW1_OP_CFG_ADDR			0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW2_OP_CFG_ADDR			0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW3_OP_CFG_ADDR			0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW4_OP_CFG_ADDR			0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW5_OP_CFG_ADDR			0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW6_OP_CFG_ADDR			0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW7_OP_CFG_ADDR			0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW8_OP_CFG_ADDR			0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW9_OP_CFG_ADDR			0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW10_OP_CFG_ADDR			0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW11_OP_CFG_ADDR			0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW12_OP_CFG_ADDR			0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW13_OP_CFG_ADDR			0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW14_OP_CFG_ADDR			0x171a
+#define MT6359P_RG_BUCK_VPROC1_HW0_OP_MODE_ADDR			0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW0_OP_MODE_SHIFT		0
+#define MT6359P_RG_BUCK_VPROC1_HW1_OP_MODE_ADDR			0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW1_OP_MODE_SHIFT		1
+#define MT6359P_RG_BUCK_VPROC1_HW2_OP_MODE_ADDR			0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW2_OP_MODE_SHIFT		2
+#define MT6359P_RG_BUCK_VPROC1_HW3_OP_MODE_ADDR			0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW3_OP_MODE_SHIFT		3
+#define MT6359P_RG_BUCK_VPROC1_HW4_OP_MODE_ADDR			0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW4_OP_MODE_SHIFT		4
+#define MT6359P_RG_BUCK_VPROC1_HW5_OP_MODE_ADDR			0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW5_OP_MODE_SHIFT		5
+#define MT6359P_RG_BUCK_VPROC1_HW6_OP_MODE_ADDR			0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW6_OP_MODE_SHIFT		6
+#define MT6359P_RG_BUCK_VPROC1_HW7_OP_MODE_ADDR			0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW7_OP_MODE_SHIFT		7
+#define MT6359P_RG_BUCK_VPROC1_HW8_OP_MODE_ADDR			0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW8_OP_MODE_SHIFT		8
+#define MT6359P_RG_BUCK_VPROC1_HW9_OP_MODE_ADDR			0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW9_OP_MODE_SHIFT		9
+#define MT6359P_RG_BUCK_VPROC1_HW10_OP_MODE_ADDR		0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW10_OP_MODE_SHIFT		10
+#define MT6359P_RG_BUCK_VPROC1_HW11_OP_MODE_ADDR		0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW11_OP_MODE_SHIFT		11
+#define MT6359P_RG_BUCK_VPROC1_HW12_OP_MODE_ADDR		0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW12_OP_MODE_SHIFT		12
+#define MT6359P_RG_BUCK_VPROC1_HW13_OP_MODE_ADDR		0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW13_OP_MODE_SHIFT		13
+#define MT6359P_RG_BUCK_VPROC1_HW14_OP_MODE_ADDR		0x1720
+#define MT6359P_RG_BUCK_VPROC1_HW14_OP_MODE_SHIFT		14
+#define MT6359P_RG_BUCK_VPROC2_VOSEL_SLEEP_ADDR			0x178e
+#define MT6359P_RG_BUCK_VPROC2_HW0_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW1_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW2_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW3_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW4_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW5_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW6_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW7_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW8_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW9_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW10_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW11_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW12_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW13_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW14_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_SW_OP_EN_ADDR			0x1794
+#define MT6359P_RG_BUCK_VPROC2_HW0_OP_CFG_ADDR			0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW1_OP_CFG_ADDR			0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW2_OP_CFG_ADDR			0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW3_OP_CFG_ADDR			0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW4_OP_CFG_ADDR			0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW5_OP_CFG_ADDR			0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW6_OP_CFG_ADDR			0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW7_OP_CFG_ADDR			0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW8_OP_CFG_ADDR			0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW9_OP_CFG_ADDR			0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW10_OP_CFG_ADDR			0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW11_OP_CFG_ADDR			0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW12_OP_CFG_ADDR			0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW13_OP_CFG_ADDR			0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW14_OP_CFG_ADDR			0x179a
+#define MT6359P_RG_BUCK_VPROC2_HW0_OP_MODE_ADDR			0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW0_OP_MODE_SHIFT		0
+#define MT6359P_RG_BUCK_VPROC2_HW1_OP_MODE_ADDR			0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW1_OP_MODE_SHIFT		1
+#define MT6359P_RG_BUCK_VPROC2_HW2_OP_MODE_ADDR			0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW2_OP_MODE_SHIFT		2
+#define MT6359P_RG_BUCK_VPROC2_HW3_OP_MODE_ADDR			0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW3_OP_MODE_SHIFT		3
+#define MT6359P_RG_BUCK_VPROC2_HW4_OP_MODE_ADDR			0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW4_OP_MODE_SHIFT		4
+#define MT6359P_RG_BUCK_VPROC2_HW5_OP_MODE_ADDR			0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW5_OP_MODE_SHIFT		5
+#define MT6359P_RG_BUCK_VPROC2_HW6_OP_MODE_ADDR			0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW6_OP_MODE_SHIFT		6
+#define MT6359P_RG_BUCK_VPROC2_HW7_OP_MODE_ADDR			0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW7_OP_MODE_SHIFT		7
+#define MT6359P_RG_BUCK_VPROC2_HW8_OP_MODE_ADDR			0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW8_OP_MODE_SHIFT		8
+#define MT6359P_RG_BUCK_VPROC2_HW9_OP_MODE_ADDR			0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW9_OP_MODE_SHIFT		9
+#define MT6359P_RG_BUCK_VPROC2_HW10_OP_MODE_ADDR		0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW10_OP_MODE_SHIFT		10
+#define MT6359P_RG_BUCK_VPROC2_HW11_OP_MODE_ADDR		0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW11_OP_MODE_SHIFT		11
+#define MT6359P_RG_BUCK_VPROC2_HW12_OP_MODE_ADDR		0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW12_OP_MODE_SHIFT		12
+#define MT6359P_RG_BUCK_VPROC2_HW13_OP_MODE_ADDR		0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW13_OP_MODE_SHIFT		13
+#define MT6359P_RG_BUCK_VPROC2_HW14_OP_MODE_ADDR		0x17a0
+#define MT6359P_RG_BUCK_VPROC2_HW14_OP_MODE_SHIFT		14
+#define MT6359P_RG_BUCK_VS1_VOSEL_SLEEP_ADDR			0x180e
+#define MT6359P_RG_BUCK_VS1_HW0_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_HW1_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_HW2_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_HW3_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_HW4_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_HW5_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_HW6_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_HW7_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_HW8_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_HW9_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_HW10_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_HW11_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_HW12_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_HW13_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_HW14_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_SW_OP_EN_ADDR			0x1814
+#define MT6359P_RG_BUCK_VS1_HW0_OP_CFG_ADDR			0x181a
+#define MT6359P_RG_BUCK_VS1_HW1_OP_CFG_ADDR			0x181a
+#define MT6359P_RG_BUCK_VS1_HW2_OP_CFG_ADDR			0x181a
+#define MT6359P_RG_BUCK_VS1_HW3_OP_CFG_ADDR			0x181a
+#define MT6359P_RG_BUCK_VS1_HW4_OP_CFG_ADDR			0x181a
+#define MT6359P_RG_BUCK_VS1_HW5_OP_CFG_ADDR			0x181a
+#define MT6359P_RG_BUCK_VS1_HW6_OP_CFG_ADDR			0x181a
+#define MT6359P_RG_BUCK_VS1_HW7_OP_CFG_ADDR			0x181a
+#define MT6359P_RG_BUCK_VS1_HW8_OP_CFG_ADDR			0x181a
+#define MT6359P_RG_BUCK_VS1_HW9_OP_CFG_ADDR			0x181a
+#define MT6359P_RG_BUCK_VS1_HW10_OP_CFG_ADDR			0x181a
+#define MT6359P_RG_BUCK_VS1_HW11_OP_CFG_ADDR			0x181a
+#define MT6359P_RG_BUCK_VS1_HW12_OP_CFG_ADDR			0x181a
+#define MT6359P_RG_BUCK_VS1_HW13_OP_CFG_ADDR			0x181a
+#define MT6359P_RG_BUCK_VS1_HW14_OP_CFG_ADDR			0x181a
+#define MT6359P_RG_BUCK_VS1_HW0_OP_MODE_ADDR			0x1820
+#define MT6359P_RG_BUCK_VS1_HW0_OP_MODE_SHIFT			0
+#define MT6359P_RG_BUCK_VS1_HW1_OP_MODE_ADDR			0x1820
+#define MT6359P_RG_BUCK_VS1_HW1_OP_MODE_SHIFT			1
+#define MT6359P_RG_BUCK_VS1_HW2_OP_MODE_ADDR			0x1820
+#define MT6359P_RG_BUCK_VS1_HW2_OP_MODE_SHIFT			2
+#define MT6359P_RG_BUCK_VS1_HW3_OP_MODE_ADDR			0x1820
+#define MT6359P_RG_BUCK_VS1_HW3_OP_MODE_SHIFT			3
+#define MT6359P_RG_BUCK_VS1_HW4_OP_MODE_ADDR			0x1820
+#define MT6359P_RG_BUCK_VS1_HW4_OP_MODE_SHIFT			4
+#define MT6359P_RG_BUCK_VS1_HW5_OP_MODE_ADDR			0x1820
+#define MT6359P_RG_BUCK_VS1_HW5_OP_MODE_SHIFT			5
+#define MT6359P_RG_BUCK_VS1_HW6_OP_MODE_ADDR			0x1820
+#define MT6359P_RG_BUCK_VS1_HW6_OP_MODE_SHIFT			6
+#define MT6359P_RG_BUCK_VS1_HW7_OP_MODE_ADDR			0x1820
+#define MT6359P_RG_BUCK_VS1_HW7_OP_MODE_SHIFT			7
+#define MT6359P_RG_BUCK_VS1_HW8_OP_MODE_ADDR			0x1820
+#define MT6359P_RG_BUCK_VS1_HW8_OP_MODE_SHIFT			8
+#define MT6359P_RG_BUCK_VS1_HW9_OP_MODE_ADDR			0x1820
+#define MT6359P_RG_BUCK_VS1_HW9_OP_MODE_SHIFT			9
+#define MT6359P_RG_BUCK_VS1_HW10_OP_MODE_ADDR			0x1820
+#define MT6359P_RG_BUCK_VS1_HW10_OP_MODE_SHIFT			10
+#define MT6359P_RG_BUCK_VS1_HW11_OP_MODE_ADDR			0x1820
+#define MT6359P_RG_BUCK_VS1_HW11_OP_MODE_SHIFT			11
+#define MT6359P_RG_BUCK_VS1_HW12_OP_MODE_ADDR			0x1820
+#define MT6359P_RG_BUCK_VS1_HW12_OP_MODE_SHIFT			12
+#define MT6359P_RG_BUCK_VS1_HW13_OP_MODE_ADDR			0x1820
+#define MT6359P_RG_BUCK_VS1_HW13_OP_MODE_SHIFT			13
+#define MT6359P_RG_BUCK_VS1_HW14_OP_MODE_ADDR			0x1820
+#define MT6359P_RG_BUCK_VS1_HW14_OP_MODE_SHIFT			14
+#define MT6359P_RG_BUCK_VS2_VOSEL_SLEEP_ADDR			0x188e
+#define MT6359P_RG_BUCK_VS2_HW0_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_HW1_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_HW2_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_HW3_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_HW4_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_HW5_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_HW6_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_HW7_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_HW8_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_HW9_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_HW10_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_HW11_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_HW12_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_HW13_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_HW14_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_SW_OP_EN_ADDR			0x1894
+#define MT6359P_RG_BUCK_VS2_HW0_OP_CFG_ADDR			0x189a
+#define MT6359P_RG_BUCK_VS2_HW1_OP_CFG_ADDR			0x189a
+#define MT6359P_RG_BUCK_VS2_HW2_OP_CFG_ADDR			0x189a
+#define MT6359P_RG_BUCK_VS2_HW3_OP_CFG_ADDR			0x189a
+#define MT6359P_RG_BUCK_VS2_HW4_OP_CFG_ADDR			0x189a
+#define MT6359P_RG_BUCK_VS2_HW5_OP_CFG_ADDR			0x189a
+#define MT6359P_RG_BUCK_VS2_HW6_OP_CFG_ADDR			0x189a
+#define MT6359P_RG_BUCK_VS2_HW7_OP_CFG_ADDR			0x189a
+#define MT6359P_RG_BUCK_VS2_HW8_OP_CFG_ADDR			0x189a
+#define MT6359P_RG_BUCK_VS2_HW9_OP_CFG_ADDR			0x189a
+#define MT6359P_RG_BUCK_VS2_HW10_OP_CFG_ADDR			0x189a
+#define MT6359P_RG_BUCK_VS2_HW11_OP_CFG_ADDR			0x189a
+#define MT6359P_RG_BUCK_VS2_HW12_OP_CFG_ADDR			0x189a
+#define MT6359P_RG_BUCK_VS2_HW13_OP_CFG_ADDR			0x189a
+#define MT6359P_RG_BUCK_VS2_HW14_OP_CFG_ADDR			0x189a
+#define MT6359P_RG_BUCK_VS2_HW0_OP_MODE_ADDR			0x18a0
+#define MT6359P_RG_BUCK_VS2_HW0_OP_MODE_SHIFT			0
+#define MT6359P_RG_BUCK_VS2_HW1_OP_MODE_ADDR			0x18a0
+#define MT6359P_RG_BUCK_VS2_HW1_OP_MODE_SHIFT			1
+#define MT6359P_RG_BUCK_VS2_HW2_OP_MODE_ADDR			0x18a0
+#define MT6359P_RG_BUCK_VS2_HW2_OP_MODE_SHIFT			2
+#define MT6359P_RG_BUCK_VS2_HW3_OP_MODE_ADDR			0x18a0
+#define MT6359P_RG_BUCK_VS2_HW3_OP_MODE_SHIFT			3
+#define MT6359P_RG_BUCK_VS2_HW4_OP_MODE_ADDR			0x18a0
+#define MT6359P_RG_BUCK_VS2_HW4_OP_MODE_SHIFT			4
+#define MT6359P_RG_BUCK_VS2_HW5_OP_MODE_ADDR			0x18a0
+#define MT6359P_RG_BUCK_VS2_HW5_OP_MODE_SHIFT			5
+#define MT6359P_RG_BUCK_VS2_HW6_OP_MODE_ADDR			0x18a0
+#define MT6359P_RG_BUCK_VS2_HW6_OP_MODE_SHIFT			6
+#define MT6359P_RG_BUCK_VS2_HW7_OP_MODE_ADDR			0x18a0
+#define MT6359P_RG_BUCK_VS2_HW7_OP_MODE_SHIFT			7
+#define MT6359P_RG_BUCK_VS2_HW8_OP_MODE_ADDR			0x18a0
+#define MT6359P_RG_BUCK_VS2_HW8_OP_MODE_SHIFT			8
+#define MT6359P_RG_BUCK_VS2_HW9_OP_MODE_ADDR			0x18a0
+#define MT6359P_RG_BUCK_VS2_HW9_OP_MODE_SHIFT			9
+#define MT6359P_RG_BUCK_VS2_HW10_OP_MODE_ADDR			0x18a0
+#define MT6359P_RG_BUCK_VS2_HW10_OP_MODE_SHIFT			10
+#define MT6359P_RG_BUCK_VS2_HW11_OP_MODE_ADDR			0x18a0
+#define MT6359P_RG_BUCK_VS2_HW11_OP_MODE_SHIFT			11
+#define MT6359P_RG_BUCK_VS2_HW12_OP_MODE_ADDR			0x18a0
+#define MT6359P_RG_BUCK_VS2_HW12_OP_MODE_SHIFT			12
+#define MT6359P_RG_BUCK_VS2_HW13_OP_MODE_ADDR			0x18a0
+#define MT6359P_RG_BUCK_VS2_HW13_OP_MODE_SHIFT			13
+#define MT6359P_RG_BUCK_VS2_HW14_OP_MODE_ADDR			0x18a0
+#define MT6359P_RG_BUCK_VS2_HW14_OP_MODE_SHIFT			14
+#define MT6359P_RG_LDO_VFE28_OP_MODE_ADDR			0x1b8a
+#define MT6359P_RG_LDO_VFE28_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VFE28_HW0_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW1_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW2_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW3_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW4_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW5_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW6_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW7_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW8_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW9_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW10_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW11_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW12_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW13_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW14_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_SW_OP_EN_ADDR			0x1b8e
+#define MT6359P_RG_LDO_VFE28_HW0_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VFE28_HW1_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VFE28_HW2_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VFE28_HW3_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VFE28_HW4_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VFE28_HW5_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VFE28_HW6_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VFE28_HW7_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VFE28_HW8_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VFE28_HW9_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VFE28_HW10_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VFE28_HW11_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VFE28_HW12_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VFE28_HW13_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VFE28_HW14_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VFE28_SW_OP_CFG_ADDR			0x1b94
+#define MT6359P_RG_LDO_VXO22_OP_MODE_ADDR			0x1b9c
+#define MT6359P_RG_LDO_VXO22_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VXO22_HW0_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW1_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW2_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW3_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW4_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW5_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW6_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW7_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW8_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW9_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW10_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW11_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW12_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW13_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW14_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_SW_OP_EN_ADDR			0x1ba0
+#define MT6359P_RG_LDO_VXO22_HW0_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW1_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW2_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW3_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW4_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW5_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW6_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW7_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW8_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW9_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW10_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW11_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW12_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW13_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VXO22_HW14_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VXO22_SW_OP_CFG_ADDR			0x1ba6
+#define MT6359P_RG_LDO_VRF18_OP_MODE_ADDR			0x1bae
+#define MT6359P_RG_LDO_VRF18_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VRF18_HW0_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW1_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW2_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW3_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW4_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW5_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW6_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW7_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW8_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW9_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW10_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW11_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW12_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW13_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW14_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_SW_OP_EN_ADDR			0x1bb2
+#define MT6359P_RG_LDO_VRF18_HW0_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW1_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW2_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW3_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW4_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW5_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW6_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW7_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW8_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW9_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW10_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW11_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW12_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW13_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF18_HW14_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF18_SW_OP_CFG_ADDR			0x1bb8
+#define MT6359P_RG_LDO_VRF12_OP_MODE_ADDR			0x1bc0
+#define MT6359P_RG_LDO_VRF12_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VRF12_HW0_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW1_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW2_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW3_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW4_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW5_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW6_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW7_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW8_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW9_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW10_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW11_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW12_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW13_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW14_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_SW_OP_EN_ADDR			0x1bc4
+#define MT6359P_RG_LDO_VRF12_HW0_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VRF12_HW1_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VRF12_HW2_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VRF12_HW3_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VRF12_HW4_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VRF12_HW5_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VRF12_HW6_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VRF12_HW7_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VRF12_HW8_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VRF12_HW9_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VRF12_HW10_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VRF12_HW11_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VRF12_HW12_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VRF12_HW13_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VRF12_HW14_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VRF12_SW_OP_CFG_ADDR			0x1bca
+#define MT6359P_RG_LDO_VEFUSE_OP_MODE_ADDR			0x1bd2
+#define MT6359P_RG_LDO_VEFUSE_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VEFUSE_HW0_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW1_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW2_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW3_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW4_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW5_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW6_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW7_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW8_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW9_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW10_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW11_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW12_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW13_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW14_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_SW_OP_EN_ADDR			0x1bd6
+#define MT6359P_RG_LDO_VEFUSE_HW0_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW1_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW2_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW3_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW4_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW5_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW6_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW7_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW8_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW9_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW10_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW11_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW12_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW13_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_HW14_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VEFUSE_SW_OP_CFG_ADDR			0x1bdc
+#define MT6359P_RG_LDO_VCN33_1_OP_MODE_ADDR			0x1be4
+#define MT6359P_RG_LDO_VCN33_1_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VCN33_1_HW0_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW1_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW2_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW3_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW4_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW5_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW6_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW7_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW8_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW9_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW10_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW11_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW12_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW13_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW14_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_SW_OP_EN_ADDR			0x1be8
+#define MT6359P_RG_LDO_VCN33_1_HW0_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW1_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW2_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW3_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW4_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW5_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW6_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW7_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW8_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW9_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW10_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW11_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW12_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW13_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_1_HW14_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_1_SW_OP_CFG_ADDR			0x1bee
+#define MT6359P_RG_LDO_VCN33_2_OP_MODE_ADDR			0x1c0a
+#define MT6359P_RG_LDO_VCN33_2_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VCN33_2_HW0_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW1_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW2_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW3_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW4_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW5_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW6_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW7_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW8_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW9_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW10_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW11_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW12_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW13_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW14_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_SW_OP_EN_ADDR			0x1c0e
+#define MT6359P_RG_LDO_VCN33_2_HW0_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW1_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW2_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW3_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW4_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW5_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW6_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW7_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW8_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW9_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW10_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW11_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW12_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW13_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN33_2_HW14_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN33_2_SW_OP_CFG_ADDR			0x1c14
+#define MT6359P_RG_LDO_VCN13_OP_MODE_ADDR			0x1c1e
+#define MT6359P_RG_LDO_VCN13_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VCN13_HW0_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_HW1_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_HW2_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_HW3_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_HW4_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_HW5_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_HW6_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_HW7_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_HW8_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_HW9_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_HW10_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_HW11_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_HW12_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_HW13_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_HW14_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_SW_OP_EN_ADDR			0x1c22
+#define MT6359P_RG_LDO_VCN13_HW0_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN13_HW1_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN13_HW2_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN13_HW3_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN13_HW4_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN13_HW5_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN13_HW6_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN13_HW7_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN13_HW8_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN13_HW9_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN13_HW10_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN13_HW11_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN13_HW12_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN13_HW13_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN13_HW14_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN13_SW_OP_CFG_ADDR			0x1c28
+#define MT6359P_RG_LDO_VCN18_OP_MODE_ADDR			0x1c30
+#define MT6359P_RG_LDO_VCN18_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VCN18_HW0_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_HW1_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_HW2_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_HW3_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_HW4_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_HW5_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_HW6_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_HW7_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_HW8_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_HW9_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_HW10_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_HW11_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_HW12_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_HW13_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_HW14_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_SW_OP_EN_ADDR			0x1c34
+#define MT6359P_RG_LDO_VCN18_HW0_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW1_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW2_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW3_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW4_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW5_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW6_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW7_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW8_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW9_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW10_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW11_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW12_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW13_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VCN18_HW14_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VCN18_SW_OP_CFG_ADDR			0x1c3a
+#define MT6359P_RG_LDO_VA09_OP_MODE_ADDR			0x1c42
+#define MT6359P_RG_LDO_VA09_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VA09_HW0_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_HW1_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_HW2_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_HW3_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_HW4_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_HW5_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_HW6_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_HW7_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_HW8_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_HW9_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_HW10_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_HW11_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_HW12_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_HW13_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_HW14_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_SW_OP_EN_ADDR			0x1c46
+#define MT6359P_RG_LDO_VA09_HW0_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VA09_HW1_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VA09_HW2_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VA09_HW3_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VA09_HW4_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VA09_HW5_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VA09_HW6_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VA09_HW7_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VA09_HW8_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VA09_HW9_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VA09_HW10_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VA09_HW11_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VA09_HW12_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VA09_HW13_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VA09_HW14_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VA09_SW_OP_CFG_ADDR			0x1c4c
+#define MT6359P_RG_LDO_VCAMIO_OP_MODE_ADDR			0x1c54
+#define MT6359P_RG_LDO_VCAMIO_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VCAMIO_HW0_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW1_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW2_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW3_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW4_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW5_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW6_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW7_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW8_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW9_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW10_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW11_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW12_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW13_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW14_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_SW_OP_EN_ADDR			0x1c58
+#define MT6359P_RG_LDO_VCAMIO_HW0_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW1_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW2_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW3_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW4_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW5_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW6_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW7_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW8_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW9_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW10_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW11_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW12_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW13_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_HW14_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VCAMIO_SW_OP_CFG_ADDR			0x1c5e
+#define MT6359P_RG_LDO_VA12_OP_MODE_ADDR			0x1c66
+#define MT6359P_RG_LDO_VA12_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VA12_HW0_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_HW1_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_HW2_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_HW3_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_HW4_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_HW5_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_HW6_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_HW7_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_HW8_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_HW9_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_HW10_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_HW11_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_HW12_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_HW13_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_HW14_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_SW_OP_EN_ADDR			0x1c6a
+#define MT6359P_RG_LDO_VA12_HW0_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VA12_HW1_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VA12_HW2_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VA12_HW3_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VA12_HW4_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VA12_HW5_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VA12_HW6_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VA12_HW7_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VA12_HW8_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VA12_HW9_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VA12_HW10_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VA12_HW11_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VA12_HW12_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VA12_HW13_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VA12_HW14_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VA12_SW_OP_CFG_ADDR			0x1c70
+#define MT6359P_RG_LDO_VAUX18_OP_MODE_ADDR			0x1c8a
+#define MT6359P_RG_LDO_VAUX18_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VAUX18_HW0_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW1_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW2_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW3_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW4_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW5_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW6_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW7_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW8_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW9_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW10_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW11_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW12_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW13_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW14_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_SW_OP_EN_ADDR			0x1c8e
+#define MT6359P_RG_LDO_VAUX18_HW0_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW1_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW2_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW3_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW4_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW5_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW6_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW7_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW8_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW9_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW10_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW11_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW12_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW13_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUX18_HW14_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUX18_SW_OP_CFG_ADDR			0x1c94
+#define MT6359P_RG_LDO_VAUD18_OP_MODE_ADDR			0x1c9c
+#define MT6359P_RG_LDO_VAUD18_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VAUD18_HW0_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW1_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW2_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW3_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW4_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW5_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW6_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW7_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW8_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW9_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW10_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW11_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW12_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW13_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW14_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_SW_OP_EN_ADDR			0x1ca0
+#define MT6359P_RG_LDO_VAUD18_HW0_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW1_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW2_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW3_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW4_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW5_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW6_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW7_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW8_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW9_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW10_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW11_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW12_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW13_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VAUD18_HW14_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VAUD18_SW_OP_CFG_ADDR			0x1ca6
+#define MT6359P_RG_LDO_VIO18_OP_MODE_ADDR			0x1cae
+#define MT6359P_RG_LDO_VIO18_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VIO18_HW0_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW1_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW2_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW3_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW4_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW5_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW6_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW7_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW8_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW9_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW10_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW11_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW12_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW13_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW14_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_SW_OP_EN_ADDR			0x1cb2
+#define MT6359P_RG_LDO_VIO18_HW0_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW1_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW2_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW3_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW4_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW5_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW6_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW7_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW8_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW9_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW10_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW11_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW12_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW13_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VIO18_HW14_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VIO18_SW_OP_CFG_ADDR			0x1cb8
+#define MT6359P_RG_LDO_VEMC_OP_MODE_ADDR			0x1cc0
+#define MT6359P_RG_LDO_VEMC_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VEMC_HW0_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW1_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW2_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW3_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW4_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW5_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW6_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW7_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW8_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW9_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW10_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW11_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW12_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW13_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW14_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_SW_OP_EN_ADDR			0x1cc4
+#define MT6359P_RG_LDO_VEMC_HW0_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VEMC_HW1_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VEMC_HW2_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VEMC_HW3_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VEMC_HW4_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VEMC_HW5_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VEMC_HW6_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VEMC_HW7_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VEMC_HW8_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VEMC_HW9_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VEMC_HW10_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VEMC_HW11_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VEMC_HW12_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VEMC_HW13_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VEMC_HW14_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VEMC_SW_OP_CFG_ADDR			0x1cca
+#define MT6359P_RG_LDO_VSIM1_OP_MODE_ADDR			0x1cd2
+#define MT6359P_RG_LDO_VSIM1_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VSIM1_HW0_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW1_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW2_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW3_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW4_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW5_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW6_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW7_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW8_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW9_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW10_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW11_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW12_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW13_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW14_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_SW_OP_EN_ADDR			0x1cd6
+#define MT6359P_RG_LDO_VSIM1_HW0_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW1_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW2_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW3_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW4_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW5_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW6_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW7_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW8_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW9_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW10_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW11_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW12_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW13_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM1_HW14_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM1_SW_OP_CFG_ADDR			0x1cdc
+#define MT6359P_RG_LDO_VSIM2_OP_MODE_ADDR			0x1ce4
+#define MT6359P_RG_LDO_VSIM2_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VSIM2_HW0_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW1_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW2_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW3_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW4_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW5_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW6_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW7_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW8_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW9_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW10_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW11_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW12_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW13_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW14_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_SW_OP_EN_ADDR			0x1ce8
+#define MT6359P_RG_LDO_VSIM2_HW0_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW1_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW2_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW3_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW4_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW5_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW6_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW7_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW8_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW9_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW10_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW11_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW12_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW13_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VSIM2_HW14_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VSIM2_SW_OP_CFG_ADDR			0x1cee
+#define MT6359P_RG_LDO_VUSB_OP_MODE_ADDR			0x1d0a
+#define MT6359P_RG_LDO_VUSB_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VUSB_HW0_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW1_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW2_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW3_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW4_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW5_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW6_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW7_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW8_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW9_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW10_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW11_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW12_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW13_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW14_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_SW_OP_EN_ADDR			0x1d0e
+#define MT6359P_RG_LDO_VUSB_HW0_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VUSB_HW1_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VUSB_HW2_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VUSB_HW3_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VUSB_HW4_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VUSB_HW5_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VUSB_HW6_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VUSB_HW7_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VUSB_HW8_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VUSB_HW9_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VUSB_HW10_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VUSB_HW11_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VUSB_HW12_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VUSB_HW13_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VUSB_HW14_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VUSB_SW_OP_CFG_ADDR			0x1d14
+#define MT6359P_RG_LDO_VRFCK_OP_MODE_ADDR			0x1d1e
+#define MT6359P_RG_LDO_VRFCK_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VRFCK_HW0_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW1_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW2_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW3_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW4_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW5_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW6_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW7_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW8_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW9_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW10_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW11_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW12_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW13_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW14_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_SW_OP_EN_ADDR			0x1d22
+#define MT6359P_RG_LDO_VRFCK_HW0_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW1_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW2_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW3_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW4_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW5_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW6_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW7_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW8_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW9_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW10_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW11_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW12_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW13_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VRFCK_HW14_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VRFCK_SW_OP_CFG_ADDR			0x1d28
+#define MT6359P_RG_LDO_VBBCK_OP_MODE_ADDR			0x1d30
+#define MT6359P_RG_LDO_VBBCK_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VBBCK_HW0_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW1_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW2_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW3_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW4_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW5_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW6_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW7_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW8_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW9_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW10_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW11_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW12_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW13_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW14_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_SW_OP_EN_ADDR			0x1d34
+#define MT6359P_RG_LDO_VBBCK_HW0_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW1_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW2_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW3_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW4_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW5_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW6_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW7_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW8_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW9_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW10_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW11_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW12_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW13_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBBCK_HW14_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBBCK_SW_OP_CFG_ADDR			0x1d3a
+#define MT6359P_RG_LDO_VBIF28_OP_MODE_ADDR			0x1d42
+#define MT6359P_RG_LDO_VBIF28_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VBIF28_HW0_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW1_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW2_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW3_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW4_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW5_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW6_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW7_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW8_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW9_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW10_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW11_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW12_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW13_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW14_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_SW_OP_EN_ADDR			0x1d46
+#define MT6359P_RG_LDO_VBIF28_HW0_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW1_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW2_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW3_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW4_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW5_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW6_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW7_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW8_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW9_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW10_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW11_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW12_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW13_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VBIF28_HW14_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VBIF28_SW_OP_CFG_ADDR			0x1d4c
+#define MT6359P_RG_LDO_VIBR_OP_MODE_ADDR			0x1d54
+#define MT6359P_RG_LDO_VIBR_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VIBR_HW0_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_HW1_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_HW2_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_HW3_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_HW4_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_HW5_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_HW6_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_HW7_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_HW8_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_HW9_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_HW10_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_HW11_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_HW12_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_HW13_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_HW14_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_SW_OP_EN_ADDR			0x1d58
+#define MT6359P_RG_LDO_VIBR_HW0_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW1_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW2_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW3_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW4_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW5_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW6_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW7_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW8_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW9_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW10_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW11_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW12_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW13_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIBR_HW14_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIBR_SW_OP_CFG_ADDR			0x1d5e
+#define MT6359P_RG_LDO_VIO28_OP_MODE_ADDR			0x1d66
+#define MT6359P_RG_LDO_VIO28_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VIO28_HW0_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW1_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW2_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW3_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW4_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW5_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW6_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW7_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW8_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW9_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW10_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW11_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW12_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW13_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW14_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_SW_OP_EN_ADDR			0x1d6a
+#define MT6359P_RG_LDO_VIO28_HW0_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VIO28_HW1_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VIO28_HW2_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VIO28_HW3_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VIO28_HW4_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VIO28_HW5_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VIO28_HW6_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VIO28_HW7_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VIO28_HW8_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VIO28_HW9_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VIO28_HW10_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VIO28_HW11_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VIO28_HW12_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VIO28_HW13_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VIO28_HW14_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VIO28_SW_OP_CFG_ADDR			0x1d70
+#define MT6359P_RG_LDO_VM18_OP_MODE_ADDR			0x1d8a
+#define MT6359P_RG_LDO_VM18_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VM18_HW0_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_HW1_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_HW2_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_HW3_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_HW4_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_HW5_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_HW6_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_HW7_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_HW8_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_HW9_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_HW10_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_HW11_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_HW12_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_HW13_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_HW14_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_SW_OP_EN_ADDR			0x1d8e
+#define MT6359P_RG_LDO_VM18_HW0_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VM18_HW1_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VM18_HW2_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VM18_HW3_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VM18_HW4_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VM18_HW5_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VM18_HW6_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VM18_HW7_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VM18_HW8_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VM18_HW9_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VM18_HW10_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VM18_HW11_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VM18_HW12_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VM18_HW13_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VM18_HW14_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VM18_SW_OP_CFG_ADDR			0x1d94
+#define MT6359P_RG_LDO_VUFS_OP_MODE_ADDR			0x1d9c
+#define MT6359P_RG_LDO_VUFS_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VUFS_HW0_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_HW1_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_HW2_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_HW3_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_HW4_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_HW5_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_HW6_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_HW7_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_HW8_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_HW9_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_HW10_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_HW11_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_HW12_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_HW13_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_HW14_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_SW_OP_EN_ADDR			0x1da0
+#define MT6359P_RG_LDO_VUFS_HW0_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VUFS_HW1_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VUFS_HW2_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VUFS_HW3_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VUFS_HW4_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VUFS_HW5_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VUFS_HW6_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VUFS_HW7_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VUFS_HW8_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VUFS_HW9_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VUFS_HW10_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VUFS_HW11_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VUFS_HW12_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VUFS_HW13_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VUFS_HW14_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VUFS_SW_OP_CFG_ADDR			0x1da6
+#define MT6359P_RG_LDO_VSRAM_PROC1_OP_MODE_ADDR			0x1e8a
+#define MT6359P_RG_LDO_VSRAM_PROC1_OP_MODE_SHIFT		10
+#define MT6359P_RG_LDO_VSRAM_PROC1_VOSEL_SLEEP_ADDR		0x1e8e
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW0_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW1_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW2_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW3_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW4_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW5_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW6_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW7_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW8_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW9_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW10_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW11_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW12_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW13_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW14_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_SW_OP_EN_ADDR		0x1e96
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW0_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW1_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW2_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW3_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW4_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW5_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW6_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW7_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW8_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW9_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW10_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW11_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW12_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW13_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_HW14_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC1_SW_OP_CFG_ADDR		0x1e9c
+#define MT6359P_RG_LDO_VSRAM_PROC2_OP_MODE_ADDR			0x1eaa
+#define MT6359P_RG_LDO_VSRAM_PROC2_OP_MODE_SHIFT		10
+#define MT6359P_RG_LDO_VSRAM_PROC2_VOSEL_SLEEP_ADDR		0x1eae
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW0_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW1_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW2_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW3_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW4_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW5_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW6_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW7_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW8_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW9_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW10_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW11_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW12_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW13_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW14_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_SW_OP_EN_ADDR		0x1eb6
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW0_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW1_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW2_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW3_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW4_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW5_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW6_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW7_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW8_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW9_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW10_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW11_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW12_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW13_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_HW14_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_PROC2_SW_OP_CFG_ADDR		0x1ebc
+#define MT6359P_RG_LDO_VSRAM_OTHERS_OP_MODE_ADDR		0x1f0a
+#define MT6359P_RG_LDO_VSRAM_OTHERS_OP_MODE_SHIFT		10
+#define MT6359P_RG_LDO_VSRAM_OTHERS_VOSEL_SLEEP_ADDR		0x1f0e
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW0_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW1_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW2_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW3_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW4_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW5_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW6_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW7_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW8_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW9_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW10_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW11_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW12_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW13_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW14_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_SW_OP_EN_ADDR		0x1f16
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW0_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW1_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW2_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW3_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW4_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW5_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW6_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW7_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW8_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW9_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW10_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW11_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW12_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW13_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_HW14_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_SW_OP_CFG_ADDR		0x1f1c
+#define MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SLEEP_ADDR	0x1f28
+#define MT6359P_RG_LDO_VSRAM_MD_OP_MODE_ADDR			0x1f30
+#define MT6359P_RG_LDO_VSRAM_MD_OP_MODE_SHIFT			10
+#define MT6359P_RG_LDO_VSRAM_MD_VOSEL_SLEEP_ADDR		0x1f34
+#define MT6359P_RG_LDO_VSRAM_MD_HW0_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW1_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW2_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW3_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW4_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW5_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW6_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW7_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW8_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW9_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW10_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW11_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW12_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW13_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW14_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_SW_OP_EN_ADDR			0x1f3c
+#define MT6359P_RG_LDO_VSRAM_MD_HW0_OP_CFG_ADDR			0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW1_OP_CFG_ADDR			0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW2_OP_CFG_ADDR			0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW3_OP_CFG_ADDR			0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW4_OP_CFG_ADDR			0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW5_OP_CFG_ADDR			0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW6_OP_CFG_ADDR			0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW7_OP_CFG_ADDR			0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW8_OP_CFG_ADDR			0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW9_OP_CFG_ADDR			0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW10_OP_CFG_ADDR		0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW11_OP_CFG_ADDR		0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW12_OP_CFG_ADDR		0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW13_OP_CFG_ADDR		0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_HW14_OP_CFG_ADDR		0x1f42
+#define MT6359P_RG_LDO_VSRAM_MD_SW_OP_CFG_ADDR			0x1f42
+
+#endif /* MT6359P_LOWPOWER_REG_H */

diff --git a/plat/mediatek/include/drivers/pmic/mt6359p_set_lowpower.h b/plat/mediatek/include/drivers/pmic/mt6359p_set_lowpower.h
new file mode 100644
index 0000000..60b49bf
--- /dev/null
+++ b/plat/mediatek/include/drivers/pmic/mt6359p_set_lowpower.h

@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2025, Mediatek Inc. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT6359P_SET_LOWPOWER_H
+#define MT6359P_SET_LOWPOWER_H
+
+#include <stdint.h>
+
+#include "mt6359p_lowpower_reg.h"
+#include <pmic_wrap_init_common.h>
+
+#define OP_MODE_MU	(0)
+#define OP_MODE_LP	(1)
+
+#define HW_OFF		(0)
+#define HW_ON		(0)
+#define HW_LP		(1)
+
+enum {
+	HW0 = 0,
+	HW1,
+	HW2,
+	HW3,
+	HW4,
+	HW5,
+	HW6,
+	HW7,
+	HW8,
+	HW9,
+	HW10,
+	HW11,
+	HW12,
+	HW13,
+	HW14,
+};
+
+#define PMIC_BUCK_SET_LP(_chip, _name, _user, _en, _mode, _cfg) \
+{ \
+	pmic_wrap_update_bits(_chip##_RG_BUCK_##_name##_##_user##_OP_CFG_ADDR, \
+			      1 << _user, \
+			      (_cfg & 0x1) ? 1 << _user : 0); \
+	pmic_wrap_update_bits(_chip##_RG_BUCK_##_name##_##_user##_OP_MODE_ADDR, \
+			      1 << _user, \
+			      _mode ? 1 << _user : 0); \
+	pmic_wrap_update_bits(_chip##_RG_BUCK_##_name##_##_user##_OP_EN_ADDR, \
+			      1 << _user, \
+			      _en ? 1 << _user : 0); \
+}
+
+#define PMIC_LDO_SET_LP(_chip, _name, _user, _en, _mode, _cfg) \
+{ \
+	if (_user <= HW2) { \
+		pmic_wrap_update_bits(_chip##_RG_LDO_##_name##_OP_MODE_ADDR, \
+			1 << (_user + _chip##_RG_LDO_##_name##_OP_MODE_SHIFT), \
+			_mode ? 1 << (_user + _chip##_RG_LDO_##_name##_OP_MODE_SHIFT) : 0); \
+	} \
+	pmic_wrap_update_bits(_chip##_RG_LDO_##_name##_##_user##_OP_CFG_ADDR, \
+			      1 << _user, \
+			      (_cfg & 0x1) ? 1 << _user : 0); \
+	pmic_wrap_update_bits(_chip##_RG_LDO_##_name##_##_user##_OP_EN_ADDR, \
+			      1 << _user, \
+			      _en ? 1 << _user : 0); \
+}
+
+static inline int pmic_wrap_update_bits(uint32_t reg, uint32_t mask, uint32_t val)
+{
+	uint32_t orig = 0;
+	int ret = 0;
+
+	ret = pwrap_read(reg, &orig);
+	if (ret < 0)
+		return ret;
+
+	orig &= ~mask;
+	orig |= val & mask;
+
+	ret = pwrap_write(reg, orig);
+	return ret;
+}
+
+#endif /* MT6359P_MT6359P_SET_LOWPOWER_H */

diff --git a/plat/mediatek/include/drivers/pmic/pmic_set_lowpower.h b/plat/mediatek/include/drivers/pmic/pmic_set_lowpower.h
index f79612d..4f0517f 100644
--- a/plat/mediatek/include/drivers/pmic/pmic_set_lowpower.h
+++ b/plat/mediatek/include/drivers/pmic/pmic_set_lowpower.h

@@ -12,6 +12,7 @@
 #include <drivers/spmi_api.h>
 
 #include "mt6316_lowpower_reg.h"
+#include "mt6319_lowpower_reg.h"
 #include "mt6363_lowpower_reg.h"
 #include "mt6373_lowpower_reg.h"
 

diff --git a/plat/mediatek/include/mtk_bl31_interface.h b/plat/mediatek/include/mtk_bl31_interface.h
index 9650f71..208276c 100644
--- a/plat/mediatek/include/mtk_bl31_interface.h
+++ b/plat/mediatek/include/mtk_bl31_interface.h

@@ -8,8 +8,28 @@
 #define __MTK_BL31_INTERFACE_H__
 
 #include <stdbool.h>
+#include <stddef.h>
 #include <stdint.h>
 
+enum mtk_bl31_status {
+	MTK_BL31_STATUS_SUCCESS = 0,
+	MTK_BL31_STATUS_INVALID_PARAM = -1,
+	MTK_BL31_STATUS_NOT_SUPPORTED = -2,
+	MTK_BL31_STATUS_INVALID_RANGE = -3,
+	MTK_BL31_STATUS_PERMISSION_DENY = -4,
+	MTK_BL31_STATUS_LOCK_FAIL = -5,
+};
+
+int mtk_bl31_map_to_sip_error(enum mtk_bl31_status status);
+
+enum mtk_bl31_memory_type {
+	MTK_BL31_DEV_RW_SEC = 0,
+};
+
+int mtk_bl31_mmap_add_dynamic_region(unsigned long long base_pa, size_t size,
+				     enum mtk_bl31_memory_type attr);
+int mtk_bl31_mmap_remove_dynamic_region(uintptr_t base_va, size_t size);
+
 /* UFS definitions */
 enum ufs_mtk_mphy_op {
 	UFS_MPHY_BACKUP = 0,
@@ -31,4 +51,41 @@
 void ufs_mphy_ctrl(enum ufs_mtk_mphy_op op);
 void ufs_mtcmos_ctrl(bool on);
 
+/* UFS functions implemented in the public ATF repo */
+int ufs_rsc_ctrl_mem(bool hold);
+int ufs_rsc_ctrl_pmic(bool hold);
+void ufs_device_pwr_ctrl_soc(bool vcc_on, uint64_t ufs_version);
+int ufs_spm_mtcmos_power(bool on);
+int ufs_phy_spm_mtcmos_power(bool on);
+bool ufs_is_clk_status_off(void);
+void ufs_set_clk_status(bool on);
+
+/* EMI interfaces */
+uint64_t emi_mpu_read_addr(unsigned int region, unsigned int offset);
+uint64_t emi_mpu_read_enable(unsigned int region);
+uint64_t emi_mpu_read_aid(unsigned int region, unsigned int aid_shift);
+uint64_t emi_mpu_check_ns_cpu(void);
+enum mtk_bl31_status emi_mpu_set_protection(uint32_t start, uint32_t end,
+					    unsigned int region);
+enum mtk_bl31_status emi_kp_set_protection(size_t start, size_t end, unsigned int region);
+enum mtk_bl31_status emi_kp_clear_violation(unsigned int emiid);
+enum mtk_bl31_status emi_clear_protection(unsigned int region);
+enum mtk_bl31_status emi_clear_md_violation(void);
+uint64_t emi_mpu_check_region_info(unsigned int region, uint64_t *sa, uint64_t *ea);
+uint64_t emi_mpu_page_base_region(void);
+uint64_t emi_mpu_smc_hp_mod_check(void);
+enum mtk_bl31_status slb_clear_violation(unsigned int id);
+enum mtk_bl31_status emi_clear_violation(unsigned int id, unsigned int type);
+enum mtk_bl31_status slc_parity_select(unsigned int id, unsigned int port);
+enum mtk_bl31_status slc_parity_clear(unsigned int id);
+enum mtk_bl31_status emi_mpu_set_aid(unsigned int region, unsigned int num);
+void emi_protection_init(void);
+
+/* CPU QoS interfaces */
+void cpu_qos_change_dcc(uint32_t on, uint32_t is_auto);
+void *cpu_qos_handle_cluster_on_event(const void *arg);
+
+/* SMMU sid interfaces */
+int smmu_sid_init(void);
+
 #endif /* __MTK_BL31_INTERFACE_H__ */

diff --git a/plat/mediatek/mt8189/include/platform_def.h b/plat/mediatek/mt8189/include/platform_def.h
index e61aaa2..54bf5ba 100644
--- a/plat/mediatek/mt8189/include/platform_def.h
+++ b/plat/mediatek/mt8189/include/platform_def.h

@@ -45,6 +45,12 @@
 #define UART_BAUDRATE	(115200)
 
 /*******************************************************************************
+ * Infra IOMMU related constants
+ ******************************************************************************/
+#define PERICFG_AO_BASE		(IO_PHYS + 0x01036000)
+#define PERICFG_AO_REG_SIZE	(0x1000)
+
+/*******************************************************************************
  * CIRQ related constants
  ******************************************************************************/
 #define SYS_CIRQ_BASE		(IO_PHYS + 204000)
@@ -54,6 +60,29 @@
 #define CIRQ_IRQ_NUM		(598)
 
 /*******************************************************************************
+ * MM IOMMU & SMI related constants
+ ******************************************************************************/
+#define SMI_LARB_0_BASE		(IO_PHYS + 0x0401c000)
+#define SMI_LARB_1_BASE		(IO_PHYS + 0x0401d000)
+#define SMI_LARB_2_BASE		(IO_PHYS + 0x0f002000)
+#define SMI_LARB_4_BASE		(IO_PHYS + 0x0602e000)
+#define SMI_LARB_7_BASE		(IO_PHYS + 0x07010000)
+#define SMI_LARB_9_BASE		(IO_PHYS + 0x0502e000)
+#define SMI_LARB_11_BASE	(IO_PHYS + 0x0582e000)
+#define SMI_LARB_13_BASE	(IO_PHYS + 0x0a001000)
+#define SMI_LARB_14_BASE	(IO_PHYS + 0x0a002000)
+#define SMI_LARB_16_BASE	(IO_PHYS + 0x0a00f000)
+#define SMI_LARB_17_BASE	(IO_PHYS + 0x0a010000)
+#define SMI_LARB_19_BASE	(IO_PHYS + 0x0b10f000)
+#define SMI_LARB_20_BASE	(IO_PHYS + 0x0b00f000)
+#define SMI_LARB_REG_RNG_SIZE	(0x1000)
+
+#define MM_IOMMU_BASE		(IO_PHYS + 0x0e802000 + 0x4000)
+#define APU_IOMMU_BASE		(IO_PHYS + 0x09010000)
+
+#define IOMMU_REG_RNG_SIZE	(0x5000)
+
+/*******************************************************************************
  * System counter frequency related constants
  ******************************************************************************/
 #define SYS_COUNTER_FREQ_IN_HZ	(13000000)
@@ -114,4 +143,40 @@
  ******************************************************************************/
 #define SYSTIMER_BASE		(IO_PHYS + 0x0CC10000)
 
+/*******************************************************************************
+ * SPMI related definitions
+ ******************************************************************************/
+#define SPMI_MST_P_BASE			(IO_PHYS + 0x0CC00000)
+#define PMIF_SPMI_P_BASE		(IO_PHYS + 0x0CC06000)
+#define SPMI_MST_P_SIZE			(0x1000)
+
+/*******************************************************************************
+ * PWRAP related definitions
+ ******************************************************************************/
+#define PMICSPI_MST_BASE		(IO_PHYS + 0x0c013000)
+#define PMICSPI_MST_SIZE		(0x1000)
+#define PMIC_WRAP_BASE			(IO_PHYS + 0x0CC04000)
+#define PMIF_SPI_BASE			(0x1CC04000)
+#define PWRAP_REG_BASE			(0x1C013000)
+#define PWRAP_WRAP_EN			(PWRAP_REG_BASE + 0x14)
+
+/*******************************************************************************
+ * PMIC regsister related definitions
+ ******************************************************************************/
+#define PMIC_REG_BASE			(0x0000)
+#define PWRAP_SIZE			(0x1000)
+#define DEW_READ_TEST			(PMIC_REG_BASE + 0x040e)
+#define DEW_WRITE_TEST			(PMIC_REG_BASE + 0x0410)
+
+/*******************************************************************************
+ * Differentiate between 3G and 2.6G-related definitions
+ ******************************************************************************/
+#define EFUSEC_BASE			(IO_PHYS + 0x01F10000)
+#define CHIP_ID_REG			(EFUSEC_BASE + 0x7A0)
+#define CPU_SEG_ID_REG			(EFUSEC_BASE + 0x7E0)
+
+#define MTK_CPU_ID_MT8189		0x81890000
+#define MTK_CPU_SEG_ID_MT8189G		0x20
+#define MTK_CPU_SEG_ID_MT8189H		0x21
+
 #endif /* PLATFORM_DEF_H */

diff --git a/plat/mediatek/mt8189/plat_config.mk b/plat/mediatek/mt8189/plat_config.mk
index f06555b..6293052 100644
--- a/plat/mediatek/mt8189/plat_config.mk
+++ b/plat/mediatek/mt8189/plat_config.mk

@@ -23,6 +23,14 @@
 PLAT_EXTRA_RODATA_INCLUDES := 1
 CONFIG_MTK_DISABLE_CACHE_AS_RAM := $(COREBOOT)
 
+CONFIG_MTK_PMIC := y
+CONFIG_MTK_PMIC_LOWPOWER := y
+CONFIG_MTK_PMIC_SHUTDOWN_CFG := y
+CONFIG_MTK_PMIC_SHUTDOWN_V2 := y
+CONFIG_MTK_SPMI := y
+PMIC_CHIP := mt6359p
+USE_PMIC_WRAP_INIT_V3 := 1
+
 # Configs for A78 and A55
 CTX_INCLUDE_AARCH32_REGS := 0
 ERRATA_A55_1530923 := 1

diff --git a/plat/mediatek/mt8189/platform.mk b/plat/mediatek/mt8189/platform.mk
index 238c76d..381071a 100644
--- a/plat/mediatek/mt8189/platform.mk
+++ b/plat/mediatek/mt8189/platform.mk

@@ -29,8 +29,12 @@
 MODULES-y += $(MTK_PLAT)/topology
 MODULES-y += $(MTK_PLAT)/drivers/cirq
 MODULES-y += $(MTK_PLAT)/drivers/gic600
+MODULES-y += $(MTK_PLAT)/drivers/iommu
 MODULES-y += $(MTK_PLAT)/drivers/mcusys
+MODULES-y += $(MTK_PLAT)/drivers/pmic_wrap
 MODULES-y += $(MTK_PLAT)/drivers/timer
+MODULES-$(CONFIG_MTK_PMIC) += $(MTK_PLAT)/drivers/pmic
+MODULES-$(CONFIG_MTK_SPMI) += $(MTK_PLAT)/drivers/spmi
 
 PLAT_BL_COMMON_SOURCES := common/desc_image_load.c \
 			  drivers/ti/uart/aarch64/16550_console.S \

diff --git a/plat/mediatek/mt8195/plat_sip_calls.c b/plat/mediatek/mt8195/plat_sip_calls.c
index 2debeff..faa0ba5 100644
--- a/plat/mediatek/mt8195/plat_sip_calls.c
+++ b/plat/mediatek/mt8195/plat_sip_calls.c

@@ -31,7 +31,7 @@
 	case MTK_SIP_TEE_MPU_PERM_SET_AARCH64:
 	case MTK_SIP_TEE_MPU_PERM_SET_AARCH32:
 		ret = emi_mpu_sip_handler(x1, x2, x3);
-		SMC_RET2(handle, ret, ret_val);
+		SMC_RET1(handle, ret);
 		break;
 	case MTK_SIP_DP_CONTROL_AARCH32:
 	case MTK_SIP_DP_CONTROL_AARCH64:

diff --git a/plat/mediatek/mt8196/include/platform_def.h b/plat/mediatek/mt8196/include/platform_def.h
index 363c8cc..fb5212a 100644
--- a/plat/mediatek/mt8196/include/platform_def.h
+++ b/plat/mediatek/mt8196/include/platform_def.h

@@ -230,6 +230,7 @@
 #define SUB_EMI_APB_BASE		(IO_PHYS + 0x00529000)
 #define SUB_INFRA_EMI_DEBUG_CFG_BASE	(IO_PHYS + 0x00525000)
 #define SUB_INFRACFG_AO_MEM_BASE	(IO_PHYS + 0x00504000)
+#define EMI_MPU_ALIGN_BITS		12
 
 /*******************************************************************************
  * System counter frequency related constants
@@ -341,4 +342,10 @@
 #define SSPM_CFGREG_BASE	(IO_PHYS + 0x0C300000 + SSPM_REG_OFFSET)
 #define SSPM_CFGREG_SIZE	(0x1000)
 
+/*******************************************************************************
+ * MMinfra related constants
+ ******************************************************************************/
+#define MTK_VLP_TRACER_MON_BASE		(IO_PHYS + 0x0c000000)
+#define MTK_VLP_TRACER_MON_REG_SIZE	(0x1000)
+
 #endif /* PLATFORM_DEF_H */

diff --git a/plat/mediatek/mt8196/plat_config.mk b/plat/mediatek/mt8196/plat_config.mk
index 7412756..a7f17e1 100644
--- a/plat/mediatek/mt8196/plat_config.mk
+++ b/plat/mediatek/mt8196/plat_config.mk

@@ -27,7 +27,6 @@
 
 CONFIG_ARCH_ARM_V9 := y
 CONFIG_MTK_APUSYS_CE_SUPPORT := y
-CONFIG_MTK_APUSYS_EMI_SUPPORT := y
 CONFIG_MTK_APUSYS_LOGTOP_SUPPORT := y
 CONFIG_MTK_APUSYS_RV_APUMMU_SUPPORT := y
 CONFIG_MTK_APUSYS_RV_COREDUMP_WA_SUPPORT := y
@@ -60,7 +59,9 @@
 CONFIG_MTK_PMIC := y
 CONFIG_MTK_PMIC_LOWPOWER := y
 CONFIG_MTK_PMIC_SHUTDOWN_CFG := y
+CONFIG_MTK_PMIC_SHUTDOWN_V2 := y
 CONFIG_MTK_PMIC_SPT_SUPPORT := n
+CONFIG_MTK_SMMU_SID := y
 CONFIG_MTK_SPMI := y
 PMIC_CHIP := mt6363
 

diff --git a/plat/mediatek/mt8196/platform.mk b/plat/mediatek/mt8196/platform.mk
index 14cd5a0..e98ec4b 100644
--- a/plat/mediatek/mt8196/platform.mk
+++ b/plat/mediatek/mt8196/platform.mk

@@ -45,11 +45,13 @@
 MODULES-y += $(MTK_PLAT)/lib/system_reset
 MODULES-y += $(MTK_PLAT)/drivers/apusys
 MODULES-y += $(MTK_PLAT)/drivers/cirq
+MODULES-y += $(MTK_PLAT)/drivers/cpu_qos
 MODULES-y += $(MTK_PLAT)/drivers/dp
 MODULES-y += $(MTK_PLAT)/drivers/emi
 MODULES-y += $(MTK_PLAT)/drivers/gicv3
 MODULES-y += $(MTK_PLAT)/drivers/mcusys
 MODULES-y += $(MTK_PLAT)/drivers/mminfra
+MODULES-y += $(MTK_PLAT)/drivers/slbc
 MODULES-y += $(MTK_PLAT)/drivers/smmu
 MODULES-y += $(MTK_PLAT)/drivers/spm
 MODULES-y += $(MTK_PLAT)/drivers/timer
@@ -59,6 +61,7 @@
 MODULES-y += $(MTK_PLAT)/topology
 MODULES-$(CONFIG_MTK_CPU_PM_SUPPORT) += $(MTK_PLAT)/drivers/cpu_pm
 MODULES-$(CONFIG_MTK_PMIC) += $(MTK_PLAT)/drivers/pmic
+MODULES-$(CONFIG_MTK_SMMU_SID) += $(MTK_PLAT)/drivers/smmu_sid
 MODULES-$(CONFIG_MTK_SPMI) += $(MTK_PLAT)/drivers/spmi
 
 MODULES-$(CONFIG_MTK_MTCMOS) += $(MTK_PLAT)/drivers/mtcmos

diff --git a/plat/qemu/common/qemu_bl2_setup.c b/plat/qemu/common/qemu_bl2_setup.c
index 71f9cf7..3452fde 100644
--- a/plat/qemu/common/qemu_bl2_setup.c
+++ b/plat/qemu/common/qemu_bl2_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,7 +19,9 @@
 #include <common/fdt_fixup.h>
 #include <common/fdt_wrappers.h>
 #include <lib/optee_utils.h>
+#if TRANSFER_LIST
 #include <lib/transfer_list.h>
+#endif
 #include <lib/utils.h>
 #include <plat/common/platform.h>
 
@@ -50,7 +52,7 @@
 
 /* Data structure which holds the extents of the trusted SRAM for BL2 */
 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
-static struct transfer_list_header *bl2_tl;
+static struct transfer_list_header __maybe_unused *bl2_tl;
 
 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 			       u_register_t arg2, u_register_t arg3)
@@ -344,11 +346,11 @@
 
 		INFO("Handoff to BL32\n");
 		bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl32_entry();
-		if (TRANSFER_LIST &&
-			transfer_list_set_handoff_args(bl2_tl,
-				&bl_mem_params->ep_info))
+#if TRANSFER_LIST
+		if (transfer_list_set_handoff_args(bl2_tl,
+						   &bl_mem_params->ep_info))
 			break;
-
+#endif
 		INFO("Using default arguments\n");
 #if defined(SPMC_OPTEE)
 		/*

diff --git a/plat/qemu/common/qemu_bl31_setup.c b/plat/qemu/common/qemu_bl31_setup.c
index 1c5e0ea..51fee64 100644
--- a/plat/qemu/common/qemu_bl31_setup.c
+++ b/plat/qemu/common/qemu_bl31_setup.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,7 +9,9 @@
 #include <common/bl_common.h>
 #include <drivers/arm/pl061_gpio.h>
 #include <lib/gpt_rme/gpt_rme.h>
+#if TRANSFER_LIST
 #include <lib/transfer_list.h>
+#endif
 #include <plat/common/platform.h>
 #if ENABLE_RME
 #ifdef PLAT_qemu
@@ -79,7 +81,7 @@
 #if ENABLE_RME
 static entry_point_info_t rmm_image_ep_info;
 #endif
-static struct transfer_list_header *bl31_tl;
+static struct transfer_list_header __maybe_unused *bl31_tl;
 
 /*******************************************************************************
  * Perform any BL3-1 early platform setup.  Here is an opportunity to copy
@@ -92,8 +94,8 @@
 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 				u_register_t arg2, u_register_t arg3)
 {
-	bool is64 = false;
-	uint64_t hval;
+	bool __maybe_unused is64 = false;
+	uint64_t __maybe_unused hval;
 
 	/* Initialize the console to provide early debug support */
 	qemu_console_init();
@@ -119,11 +121,11 @@
 	 * They are stored in Secure RAM, in BL2's address space.
 	 */
 	while (bl_params) {
-#ifdef __aarch64__
+#if defined(__aarch64__) && TRANSFER_LIST
 		if (bl_params->image_id == BL31_IMAGE_ID &&
 		    GET_RW(bl_params->ep_info->spsr) == MODE_RW_64)
 			is64 = true;
-#endif
+#endif /* defined(__aarch64__) && TRANSFER_LIST */
 		if (bl_params->image_id == BL32_IMAGE_ID)
 			bl32_image_ep_info = *bl_params->ep_info;
 
@@ -145,8 +147,8 @@
 		panic();
 #endif
 
-	if (!TRANSFER_LIST ||
-	    !transfer_list_check_header((void *)arg3))
+#if TRANSFER_LIST
+	if (!transfer_list_check_header((void *)arg3))
 		return;
 
 	if (is64)
@@ -156,6 +158,7 @@
 
 	if (arg1 != hval)
 		return;
+#endif
 
 	bl31_tl = (void *)arg3; /* saved TL address from BL2 */
 }

diff --git a/plat/qemu/common/qemu_spm.c b/plat/qemu/common/qemu_spm.c
index abedbe4..873b97b 100644
--- a/plat/qemu/common/qemu_spm.c
+++ b/plat/qemu/common/qemu_spm.c

@@ -129,7 +129,9 @@
 {
 	uintptr_t ns_buf_base;
 
-	dt_add_ns_buf_node(&ns_buf_base);
+	if (dt_add_ns_buf_node(&ns_buf_base) != 0) {
+		panic();
+	}
 
 	plat_qemu_secure_partition_mmap[0].base_pa = ns_buf_base;
 	plat_qemu_secure_partition_mmap[0].base_va = ns_buf_base;

diff --git a/plat/st/common/common.mk b/plat/st/common/common.mk
index 4dbb949..56a8814 100644
--- a/plat/st/common/common.mk
+++ b/plat/st/common/common.mk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
+# Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved
 # Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
@@ -27,7 +27,10 @@
 STM32_HEADER_BL2_BINARY_TYPE	:=	0x10
 
 TF_CFLAGS			+=	-Wsign-compare
+ifeq ($(findstring clang,$(notdir $(CC))),)
+# Only for GCC
 TF_CFLAGS			+=	-Wformat-signedness
+endif
 
 # Number of TF-A copies in the device
 STM32_TF_A_COPIES		:=	2

diff --git a/plat/st/common/common_rules.mk b/plat/st/common/common_rules.mk
index 88c1087..bb7e3c5 100644
--- a/plat/st/common/common_rules.mk
+++ b/plat/st/common/common_rules.mk

@@ -71,8 +71,13 @@
 tf-a-%.stm32: tf-a-%.bin ${STM32_DEPS}
 	$(s)echo
 	$(s)echo "Generate $@"
+ifeq ($($(ARCH)-ld-id),llvm-lld)
+	$(eval LOADADDR = 0x$(shell cat $(@:.stm32=.map) | grep '\.data$$' | awk '{print $$1}'))
+	$(eval ENTRY = 0x$(shell cat $(@:.stm32=.map) | grep "__BL2_IMAGE_START" | awk '{print $$1}'))
+else
 	$(eval LOADADDR = $(shell cat $(@:.stm32=.map) | grep '^RAM' | awk '{print $$2}'))
 	$(eval ENTRY = $(shell cat $(@:.stm32=.map) | grep "__BL2_IMAGE_START" | awk '{print $$1}'))
+endif
 	$(q)${STM32IMAGE} -s $< -d $@ \
 		-l $(LOADADDR) -e ${ENTRY} \
 		-v ${STM32_TF_VERSION} \

diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index e700823..0e0586b 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk

@@ -17,6 +17,8 @@
 # Default Device tree
 DTB_FILE_NAME		?=	stm32mp157c-ev1.dtb
 
+TF_CFLAGS 		+=	-DSTM32MP1X
+
 STM32MP13		?=	0
 STM32MP15		?=	0
 

diff --git a/plat/st/stm32mp1/stm32mp1.S b/plat/st/stm32mp1/stm32mp1.S
index aee4f0e..a688f4d 100644
--- a/plat/st/stm32mp1/stm32mp1.S
+++ b/plat/st/stm32mp1/stm32mp1.S

@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-.section .bl2_image
+.section .bl2_image, "a"
 .incbin BL2_BIN_PATH
 
-.section .dtb_image
+.section .dtb_image, "a"
 .incbin DTB_BIN_PATH

diff --git a/plat/st/stm32mp1/stm32mp1.ld.S b/plat/st/stm32mp1/stm32mp1.ld.S
index 1be8219..c9d9873 100644
--- a/plat/st/stm32mp1/stm32mp1.ld.S
+++ b/plat/st/stm32mp1/stm32mp1.ld.S

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -33,17 +33,17 @@
     } >HEADER
 
     . = STM32MP_BINARY_BASE;
-    .data . : {
+    .data : {
         . = ALIGN(PAGE_SIZE);
         __DATA_START__ = .;
-        *(.data*)
+        FILL(0);
 
         /*
          * dtb.
          * The strongest and only alignment contraint is MMU 4K page.
          * Indeed as images below will be removed, 4K pages will be re-used.
          */
-        . = ( STM32MP_BL2_DTB_BASE - STM32MP_BINARY_BASE );
+        . = ABSOLUTE( STM32MP_BL2_DTB_BASE );
         __DTB_IMAGE_START__ = .;
         *(.dtb_image*)
         __DTB_IMAGE_END__ = .;
@@ -54,9 +54,9 @@
          * Indeed as images below will be removed, 4K pages will be re-used.
          */
 #if SEPARATE_CODE_AND_RODATA
-        . = ( STM32MP_BL2_RO_BASE - STM32MP_BINARY_BASE );
+        . = ABSOLUTE( STM32MP_BL2_RO_BASE );
 #else
-        . = ( STM32MP_BL2_BASE - STM32MP_BINARY_BASE );
+        . = ABSOLUTE( STM32MP_BL2_BASE );
 #endif
         __BL2_IMAGE_START__ = .;
         *(.bl2_image*)

diff --git a/plat/st/stm32mp2/aarch64/stm32mp2.S b/plat/st/stm32mp2/aarch64/stm32mp2.S
index 1866b8b..6c32972 100644
--- a/plat/st/stm32mp2/aarch64/stm32mp2.S
+++ b/plat/st/stm32mp2/aarch64/stm32mp2.S

@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2023, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-.section .bl2_image
+.section .bl2_image, "a"
 .incbin BL2_BIN_PATH
 
-.section .dtb_image
+.section .dtb_image, "a"
 .incbin DTB_BIN_PATH

diff --git a/plat/st/stm32mp2/aarch64/stm32mp2.ld.S b/plat/st/stm32mp2/aarch64/stm32mp2.ld.S
index 48bf424..cf71f27 100644
--- a/plat/st/stm32mp2/aarch64/stm32mp2.ld.S
+++ b/plat/st/stm32mp2/aarch64/stm32mp2.ld.S

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -33,17 +33,17 @@
     } >HEADER
 
     . = STM32MP_BINARY_BASE;
-    .data . : {
+    .data : {
         . = ALIGN(PAGE_SIZE);
         __DATA_START__ = .;
-        *(.data*)
+        FILL(0);
 
         /*
          * dtb.
          * The strongest and only alignment contraint is MMU 4K page.
          * Indeed as images below will be removed, 4K pages will be re-used.
          */
-        . = ( STM32MP_BL2_DTB_BASE - STM32MP_BINARY_BASE );
+        . = ABSOLUTE( STM32MP_BL2_DTB_BASE );
         __DTB_IMAGE_START__ = .;
         *(.dtb_image*)
         __DTB_IMAGE_END__ = .;
@@ -54,9 +54,9 @@
          * Indeed as images below will be removed, 4K pages will be re-used.
          */
 #if SEPARATE_CODE_AND_RODATA
-        . = ( STM32MP_BL2_RO_BASE - STM32MP_BINARY_BASE );
+        . = ABSOLUTE( STM32MP_BL2_RO_BASE );
 #else
-        . = ( STM32MP_BL2_BASE - STM32MP_BINARY_BASE );
+        . = ABSOLUTE( STM32MP_BL2_BASE );
 #endif
         __BL2_IMAGE_START__ = .;
         *(.bl2_image*)

diff --git a/plat/st/stm32mp2/bl2_plat_setup.c b/plat/st/stm32mp2/bl2_plat_setup.c
index 621b784..1d49fe7 100644
--- a/plat/st/stm32mp2/bl2_plat_setup.c
+++ b/plat/st/stm32mp2/bl2_plat_setup.c

@@ -34,97 +34,46 @@
 static void print_reset_reason(void)
 {
 	uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_C1BOOTRSTSCLRR);
+	const char *reason_str = "Unidentified";
 
-	if (rstsr == 0U) {
-		WARN("Reset reason unknown\n");
-		return;
+#if !STM32MP21
+	if ((rstsr & RCC_C1BOOTRSTSCLRR_C1P1RSTF) != 0U) {
+		INFO("CA35 processor core 1 reset\n");
 	}
-
-	INFO("Reset reason (0x%x):\n", rstsr);
+#endif /* !STM32MP21 */
 
 	if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) == 0U) {
 		if ((rstsr & RCC_C1BOOTRSTSCLRR_STBYC1RSTF) != 0U) {
-			INFO("System exits from Standby for CA35\n");
-			return;
+			reason_str = "System exits from Standby for CA35";
+		} else if ((rstsr & RCC_C1BOOTRSTSCLRR_D1STBYRSTF) != 0U) {
+			reason_str = "D1 domain exits from DStandby";
+		} else if ((rstsr & RCC_C1BOOTRSTSCLRR_VCPURSTF) != 0U) {
+			reason_str = "System reset from VCPU monitor";
+		} else if ((rstsr & RCC_C1BOOTRSTSCLRR_C1RSTF) != 0U) {
+			reason_str = "CA35 reset by CM33 (C1RST)";
+		} else {
+			reason_str = "Unidentified";
 		}
-
-		if ((rstsr & RCC_C1BOOTRSTSCLRR_D1STBYRSTF) != 0U) {
-			INFO("D1 domain exits from DStandby\n");
-			return;
+	} else {
+		if ((rstsr & RCC_C1BOOTRSTSCLRR_PORRSTF) != 0U) {
+			reason_str = "Power-on reset (por_rstn)";
+		} else if ((rstsr & RCC_C1BOOTRSTSCLRR_BORRSTF) != 0U) {
+			reason_str = "Brownout reset (bor_rstn)";
+		} else if ((rstsr & (RCC_C1BOOTRSTSSETR_SYSC2RSTF |
+				     RCC_C1BOOTRSTSSETR_SYSC1RSTF)) != 0U) {
+			reason_str = "System reset (SYSRST)";
+		} else if ((rstsr & RCC_C1BOOTRSTSCLRR_HCSSRSTF) != 0U) {
+			reason_str = "Clock failure on HSE";
+		} else if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDGXSYSRSTF) != 0U) {
+			reason_str = "IWDG system reset (iwdgX_out_rst)";
+		} else if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) != 0U) {
+			reason_str = "Pin reset from NRST";
+		} else {
+			reason_str = "Unidentified";
 		}
 	}
 
-	if ((rstsr & RCC_C1BOOTRSTSCLRR_PORRSTF) != 0U) {
-		INFO("  Power-on Reset (rst_por)\n");
-		return;
-	}
-
-	if ((rstsr & RCC_C1BOOTRSTSCLRR_BORRSTF) != 0U) {
-		INFO("  Brownout Reset (rst_bor)\n");
-		return;
-	}
-
-	if ((rstsr & RCC_C1BOOTRSTSSETR_SYSC2RSTF) != 0U) {
-		INFO("  System reset (SYSRST) by M33\n");
-		return;
-	}
-
-	if ((rstsr & RCC_C1BOOTRSTSSETR_SYSC1RSTF) != 0U) {
-		INFO("  System reset (SYSRST) by A35\n");
-		return;
-	}
-
-	if ((rstsr & RCC_C1BOOTRSTSCLRR_HCSSRSTF) != 0U) {
-		INFO("  Clock failure on HSE\n");
-		return;
-	}
-
-	if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF) != 0U) {
-		INFO("  IWDG1 system reset (rst_iwdg1)\n");
-		return;
-	}
-
-	if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF) != 0U) {
-		INFO("  IWDG2 system reset (rst_iwdg2)\n");
-		return;
-	}
-
-	if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF) != 0U) {
-		INFO("  IWDG3 system reset (rst_iwdg3)\n");
-		return;
-	}
-
-	if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF) != 0U) {
-		INFO("  IWDG4 system reset (rst_iwdg4)\n");
-		return;
-	}
-
-	if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG5SYSRSTF) != 0U) {
-		INFO("  IWDG5 system reset (rst_iwdg5)\n");
-		return;
-	}
-
-	if ((rstsr & RCC_C1BOOTRSTSCLRR_C1P1RSTF) != 0U) {
-		INFO("  A35 processor core 1 reset\n");
-		return;
-	}
-
-	if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) != 0U) {
-		INFO("  Pad Reset from NRST\n");
-		return;
-	}
-
-	if ((rstsr & RCC_C1BOOTRSTSCLRR_VCORERSTF) != 0U) {
-		INFO("  Reset due to a failure of VDD_CORE\n");
-		return;
-	}
-
-	if ((rstsr & RCC_C1BOOTRSTSCLRR_C1RSTF) != 0U) {
-		INFO("  A35 processor reset\n");
-		return;
-	}
-
-	ERROR("  Unidentified reset reason\n");
+	INFO("Reset reason: %s (0x%x)\n", reason_str, rstsr);
 }
 
 void bl2_el3_early_platform_setup(u_register_t arg0 __unused,
@@ -164,11 +113,19 @@
 	 * The protection is enable at each reset by hardware
 	 * and must be disabled by software.
 	 */
+#if STM32MP21
+	mmio_setbits_32(pwr_base + PWR_BDCR, PWR_BDCR_DBP);
+
+	while ((mmio_read_32(pwr_base + PWR_BDCR) & PWR_BDCR_DBP) == 0U) {
+		;
+	}
+#else /* STM32MP21 */
 	mmio_setbits_32(pwr_base + PWR_BDCR1, PWR_BDCR1_DBD3P);
 
 	while ((mmio_read_32(pwr_base + PWR_BDCR1) & PWR_BDCR1_DBD3P) == 0U) {
 		;
 	}
+#endif /* STM32MP21 */
 
 	/* Reset backup domain on cold boot cases */
 	if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCCKEN) == 0U) {

diff --git a/plat/st/stm32mp2/platform.mk b/plat/st/stm32mp2/platform.mk
index 06298a4..c20435b 100644
--- a/plat/st/stm32mp2/platform.mk
+++ b/plat/st/stm32mp2/platform.mk

@@ -30,11 +30,36 @@
 # Default Device tree
 DTB_FILE_NAME			?=	stm32mp257f-ev1.dtb
 
+TF_CFLAGS			+=	-DSTM32MP2X
+
+STM32MP21			?=	0
+STM32MP23			?=	0
+STM32MP25			?=	0
+
+ifneq ($(findstring stm32mp21,$(DTB_FILE_NAME)),)
+STM32MP21			:=	1
+endif
+ifneq ($(findstring stm32mp23,$(DTB_FILE_NAME)),)
+STM32MP23			:=	1
+endif
+ifneq ($(findstring stm32mp25,$(DTB_FILE_NAME)),)
 STM32MP25			:=	1
+endif
+ifneq ($(filter 1,$(STM32MP21) $(STM32MP23) $(STM32MP25)), 1)
+$(warning STM32MP21=$(STM32MP21))
+$(warning STM32MP23=$(STM32MP23))
+$(warning STM32MP25=$(STM32MP25))
+$(warning DTB_FILE_NAME=$(DTB_FILE_NAME))
+$(error Cannot enable more than one STM32MP2x flag)
+endif
 
-# STM32 image header version v2.2
+# STM32 image header version v2.2 or v2.3 for STM32MP21
 STM32_HEADER_VERSION_MAJOR	:=	2
+ifeq ($(STM32MP21),1)
+STM32_HEADER_VERSION_MINOR	:=	3
+else
 STM32_HEADER_VERSION_MINOR	:=	2
+endif
 
 # Set load address for serial boot devices
 DWL_BUFFER_BASE 		?=	0x87000000
@@ -110,6 +135,8 @@
 		STM32MP_DDR3_TYPE \
 		STM32MP_DDR4_TYPE \
 		STM32MP_LPDDR4_TYPE \
+		STM32MP21 \
+		STM32MP23 \
 		STM32MP25 \
 		STM32MP_BL33_EL1 \
 )))
@@ -133,6 +160,8 @@
 		STM32MP_DDR3_TYPE \
 		STM32MP_DDR4_TYPE \
 		STM32MP_LPDDR4_TYPE \
+		STM32MP21 \
+		STM32MP23 \
 		STM32MP25 \
 		STM32MP_BL33_EL1 \
 )))

diff --git a/plat/st/stm32mp2/stm32mp2_def.h b/plat/st/stm32mp2/stm32mp2_def.h
index 1b8c4f5..27fc5f9 100644
--- a/plat/st/stm32mp2/stm32mp2_def.h
+++ b/plat/st/stm32mp2/stm32mp2_def.h

@@ -10,16 +10,31 @@
 #include <common/tbbr/tbbr_img_def.h>
 #ifndef __ASSEMBLER__
 #include <drivers/st/bsec.h>
-#endif
-#include <drivers/st/stm32mp25_rcc.h>
-#ifndef __ASSEMBLER__
 #include <drivers/st/stm32mp2_clk.h>
 #endif
+#if STM32MP21
+#include <drivers/st/stm32mp21_pwr.h>
+#include <drivers/st/stm32mp21_rcc.h>
+#else /* STM32MP21 */
 #include <drivers/st/stm32mp2_pwr.h>
+#include <drivers/st/stm32mp25_rcc.h>
+#endif /* STM32MP21 */
+#if STM32MP21
+#include <dt-bindings/clock/st,stm32mp21-rcc.h>
+#include <dt-bindings/clock/stm32mp21-clksrc.h>
+#include <dt-bindings/reset/st,stm32mp21-rcc.h>
+#endif /* STM32MP21 */
+#if STM32MP23
 #include <dt-bindings/clock/stm32mp25-clks.h>
 #include <dt-bindings/clock/stm32mp25-clksrc.h>
-#include <dt-bindings/gpio/stm32-gpio.h>
 #include <dt-bindings/reset/stm32mp25-resets.h>
+#endif /* STM32MP23 */
+#if STM32MP25
+#include <dt-bindings/clock/stm32mp25-clks.h>
+#include <dt-bindings/clock/stm32mp25-clksrc.h>
+#include <dt-bindings/reset/stm32mp25-resets.h>
+#endif /* STM32MP25 */
+#include <dt-bindings/gpio/stm32-gpio.h>
 
 #ifndef __ASSEMBLER__
 #include <boot_api.h>
@@ -386,7 +401,7 @@
 #define DDRPHYC_BASE				U(0x48C00000)
 
 /*******************************************************************************
- * Miscellaneous STM32MP1 peripherals base address
+ * Miscellaneous STM32MP2 peripherals base address
  ******************************************************************************/
 #define BSEC_BASE				U(0x44000000)
 #define DBGMCU_BASE				U(0x4A010000)
@@ -422,7 +437,11 @@
 #define DT_BSEC_COMPAT				"st,stm32mp25-bsec"
 #define DT_DDR_COMPAT				"st,stm32mp2-ddr"
 #define DT_PWR_COMPAT				"st,stm32mp25-pwr"
+#if STM32MP21
+#define DT_RCC_CLK_COMPAT			"st,stm32mp21-rcc"
+#else
 #define DT_RCC_CLK_COMPAT			"st,stm32mp25-rcc"
+#endif
 #define DT_SDMMC2_COMPAT			"st,stm32mp25-sdmmc2"
 #define DT_UART_COMPAT				"st,stm32h7-uart"
 

diff --git a/plat/ti/k3/common/k3_psci.c b/plat/ti/k3/common/k3_psci.c
index df49f48..c679344 100644
--- a/plat/ti/k3/common/k3_psci.c
+++ b/plat/ti/k3/common/k3_psci.c

@@ -226,14 +226,6 @@
 		wfi();
 }
 
-static int k3_validate_power_state(unsigned int power_state,
-				   psci_power_state_t *req_state)
-{
-	/* TODO: perform the proper validation */
-
-	return PSCI_E_SUCCESS;
-}
-
 static void k3_pwr_domain_suspend_to_mode(const psci_power_state_t *target_state, uint8_t mode)
 {
 	unsigned int core, proc_id;
@@ -294,7 +286,6 @@
 	.get_sys_suspend_power_state = k3_get_sys_suspend_power_state,
 	.system_off = k3_system_off,
 	.system_reset = k3_system_reset,
-	.validate_power_state = k3_validate_power_state,
 };
 
 int plat_setup_psci_ops(uintptr_t sec_entrypoint,

diff --git a/plat/xilinx/zynqmp/custom_sip_svc.c b/plat/xilinx/common/custom_sip_svc.c
similarity index 90%
rename from plat/xilinx/zynqmp/custom_sip_svc.c
rename to plat/xilinx/common/custom_sip_svc.c
index c39e4be..2cefb78 100644
--- a/plat/xilinx/zynqmp/custom_sip_svc.c
+++ b/plat/xilinx/common/custom_sip_svc.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */

diff --git a/plat/xilinx/zynqmp/include/custom_svc.h b/plat/xilinx/common/include/custom_svc.h
similarity index 71%
rename from plat/xilinx/zynqmp/include/custom_svc.h
rename to plat/xilinx/common/include/custom_svc.h
index 242f3eb..2884b69 100644
--- a/plat/xilinx/zynqmp/include/custom_svc.h
+++ b/plat/xilinx/common/include/custom_svc.h

@@ -1,13 +1,13 @@
 /*
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 #ifndef CUSTOM_SVC_H
 #define CUSTOM_SVC_H
 
-#define ZYNQMP_SIP_SVC_CUSTOM   U(0x82002000)
-#define ZYNQMP_SIP_SVC64_CUSTOM U(0xC2002000)
+#define SOC_SIP_SVC_CUSTOM   U(0x82002000)
+#define SOC_SIP_SVC64_CUSTOM U(0xC2002000)
 
 uint64_t custom_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2,
 			    uint64_t x3, uint64_t x4, void *cookie,

diff --git a/plat/xilinx/common/include/ipi.h b/plat/xilinx/common/include/ipi.h
index 71c06c3..c628496 100644
--- a/plat/xilinx/common/include/ipi.h
+++ b/plat/xilinx/common/include/ipi.h

@@ -38,9 +38,9 @@
 
 /* structure to maintain IPI configuration information */
 struct ipi_config {
-	unsigned int ipi_bit_mask;
-	unsigned int ipi_reg_base;
-	unsigned char secure_only;
+	uint32_t ipi_bit_mask;
+	uint32_t ipi_reg_base;
+	uint8_t secure_only;
 };
 
 /*********************************************************************
@@ -52,7 +52,7 @@
 			   uint32_t total_ipi);
 
 /* Validate IPI mailbox access */
-int ipi_mb_validate(uint32_t local, uint32_t remote, unsigned int is_secure);
+int32_t ipi_mb_validate(uint32_t local, uint32_t remote, uint32_t is_secure);
 
 /* Open the IPI mailbox */
 void ipi_mb_open(uint32_t local, uint32_t remote);

diff --git a/plat/xilinx/common/include/pm_api_sys.h b/plat/xilinx/common/include/pm_api_sys.h
index 793b270..fc55cc3 100644
--- a/plat/xilinx/common/include/pm_api_sys.h
+++ b/plat/xilinx/common/include/pm_api_sys.h

@@ -60,7 +60,8 @@
  * Assigning of argument values into array elements.
  */
 #define PM_PACK_PAYLOAD1(pl, mid, flag, arg0) {	\
-	pl[0] = (uint32_t)(((uint32_t)(arg0) & 0xFFU) | ((mid) << 8U) | ((flag) << 24U)); \
+	pl[0] = (uint32_t)(((uint32_t)(arg0) & 0xFFU) | \
+		((uint32_t)(mid) << 8U) | ((uint32_t)(flag) << 24U)); \
 }
 
 #define PM_PACK_PAYLOAD2(pl, mid, flag, arg0, arg1) {		\

diff --git a/plat/xilinx/common/include/pm_common.h b/plat/xilinx/common/include/pm_common.h
index 68d1db2..5e53ec6 100644
--- a/plat/xilinx/common/include/pm_common.h
+++ b/plat/xilinx/common/include/pm_common.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.
- * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -29,9 +29,9 @@
 #define RET_PAYLOAD_ARG_CNT	6U
 #define PAYLOAD_ARG_SIZE	4U	/* size in bytes */
 
-#define TZ_VERSION_MAJOR	1
-#define TZ_VERSION_MINOR	0
-#define TZ_VERSION		((TZ_VERSION_MAJOR << 16) | \
+#define TZ_VERSION_MAJOR	1U
+#define TZ_VERSION_MINOR	0U
+#define TZ_VERSION		(((uint32_t)TZ_VERSION_MAJOR << 16U) | \
 				 TZ_VERSION_MINOR)
 
 /**

diff --git a/plat/xilinx/common/include/pm_defs.h b/plat/xilinx/common/include/pm_defs.h
index 352257a..3901555 100644
--- a/plat/xilinx/common/include/pm_defs.h
+++ b/plat/xilinx/common/include/pm_defs.h

@@ -22,7 +22,6 @@
 #define PM_STATE_SUSPEND_TO_RAM	0xFU
 
 #define MAX_LATENCY		(~0U)
-#define MAX_QOS			100U
 
 /* Processor core device IDs */
 #define APU_DEVID(IDX)	NODEID(XPM_NODECLASS_DEVICE, XPM_NODESUBCL_DEV_CORE, \
@@ -209,7 +208,7 @@
  * @PM_RET_SUCCESS: success.
  * @PM_RET_ERROR_ARGS: illegal arguments provided (deprecated).
  * @PM_RET_ERROR_NOTSUPPORTED: feature not supported  (deprecated).
- * @PM_RET_ERROR_NOFEATURE: feature is not available.
+ * @PM_RET_ERROR_IOCTL_NOT_SUPPORTED: IOCTL is not supported.
  * @PM_RET_ERROR_INVALID_CRC: invalid crc in IPI communication.
  * @PM_RET_ERROR_NOT_ENABLED: feature is not enabled.
  * @PM_RET_ERROR_INTERNAL: internal error.
@@ -224,21 +223,21 @@
  *                           supported.
  */
 enum pm_ret_status {
-	PM_RET_SUCCESS,
-	PM_RET_ERROR_ARGS = 1,
-	PM_RET_ERROR_NOTSUPPORTED = 4,
-	PM_RET_ERROR_NOFEATURE = 19,
-	PM_RET_ERROR_INVALID_CRC = 301,
-	PM_RET_ERROR_NOT_ENABLED = 29,
-	PM_RET_ERROR_INTERNAL = 2000,
-	PM_RET_ERROR_CONFLICT = 2001,
-	PM_RET_ERROR_ACCESS = 2002,
-	PM_RET_ERROR_INVALID_NODE = 2003,
-	PM_RET_ERROR_DOUBLE_REQ = 2004,
-	PM_RET_ERROR_ABORT_SUSPEND = 2005,
-	PM_RET_ERROR_TIMEOUT = 2006,
-	PM_RET_ERROR_NODE_USED = 2007,
-	PM_RET_ERROR_NO_FEATURE = 2008
+	PM_RET_SUCCESS = 0U,
+	PM_RET_ERROR_ARGS = 1U,
+	PM_RET_ERROR_NOTSUPPORTED = 4U,
+	PM_RET_ERROR_IOCTL_NOT_SUPPORTED = 19U,
+	PM_RET_ERROR_NOT_ENABLED = 29U,
+	PM_RET_ERROR_INVALID_CRC = 301U,
+	PM_RET_ERROR_INTERNAL = 2000U,
+	PM_RET_ERROR_CONFLICT = 2001U,
+	PM_RET_ERROR_ACCESS = 2002U,
+	PM_RET_ERROR_INVALID_NODE = 2003U,
+	PM_RET_ERROR_DOUBLE_REQ = 2004U,
+	PM_RET_ERROR_ABORT_SUSPEND = 2005U,
+	PM_RET_ERROR_TIMEOUT = 2006U,
+	PM_RET_ERROR_NODE_USED = 2007U,
+	PM_RET_ERROR_NO_FEATURE = 2008U
 };
 
 /*

diff --git a/plat/xilinx/common/include/pm_node.h b/plat/xilinx/common/include/pm_node.h
index 3ee55c2..982a410 100644
--- a/plat/xilinx/common/include/pm_node.h
+++ b/plat/xilinx/common/include/pm_node.h

@@ -23,9 +23,6 @@
 #define NODE_TYPE_MASK_BITS     GENMASK_32(5, 0)
 #define NODE_INDEX_MASK_BITS    GENMASK_32(13, 0)
 #define NODE_CLASS_MASK         (NODE_CLASS_MASK_BITS << NODE_CLASS_SHIFT)
-#define NODE_SUBCLASS_MASK      (NODE_SUBCLASS_MASK_BITS << NODE_SUBCLASS_SHIFT)
-#define NODE_TYPE_MASK          (NODE_TYPE_MASK_BITS << NODE_TYPE_SHIFT)
-#define NODE_INDEX_MASK         (NODE_INDEX_MASK_BITS << NODE_INDEX_SHIFT)
 
 #define NODEID(CLASS, SUBCLASS, TYPE, INDEX)	\
 	     ((((CLASS) & NODE_CLASS_MASK_BITS) << NODE_CLASS_SHIFT) | \
@@ -33,11 +30,7 @@
 	     (((TYPE) & NODE_TYPE_MASK_BITS) << NODE_TYPE_SHIFT) | \
 	     (((INDEX) & NODE_INDEX_MASK_BITS) << NODE_INDEX_SHIFT))
 
-#define NODECLASS(ID)		(((ID) & NODE_CLASS_MASK) >> NODE_CLASS_SHIFT)
-#define NODESUBCLASS(ID)	(((ID) & NODE_SUBCLASS_MASK) >> \
-				NODE_SUBCLASS_SHIFT)
-#define NODETYPE(ID)		(((ID) & NODE_TYPE_MASK) >> NODE_TYPE_SHIFT)
-#define NODEINDEX(ID)		(((ID) & NODE_INDEX_MASK) >> NODE_INDEX_SHIFT)
+#define NODECLASS(ID)           (((ID) & NODE_CLASS_MASK) >> NODE_CLASS_SHIFT)
 
 /*********************************************************************
  * Enum definitions

diff --git a/plat/xilinx/common/ipi.c b/plat/xilinx/common/ipi.c
index 18ae096..8dc6da0 100644
--- a/plat/xilinx/common/ipi.c
+++ b/plat/xilinx/common/ipi.c

@@ -67,12 +67,12 @@
  * Return: - 1 if within range, 0 if not.
  *
  */
-static inline int is_ipi_mb_within_range(uint32_t local, uint32_t remote)
+static inline uint32_t is_ipi_mb_within_range(uint32_t local, uint32_t remote)
 {
-	int ret = 1;
+	uint32_t ret = 1U;
 
 	if ((remote >= ipi_total) || (local >= ipi_total)) {
-		ret = 0;
+		ret = 0U;
 	}
 
 	return ret;
@@ -87,11 +87,11 @@
  * Return: 0 success, negative value for errors.
  *
  */
-int ipi_mb_validate(uint32_t local, uint32_t remote, unsigned int is_secure)
+int32_t ipi_mb_validate(uint32_t local, uint32_t remote, uint32_t is_secure)
 {
-	int ret = 0;
+	int32_t ret = 0;
 
-	if (is_ipi_mb_within_range(local, remote) == 0) {
+	if (is_ipi_mb_within_range(local, remote) == 0U) {
 		ret = -EINVAL;
 	} else if (IPI_IS_SECURE(local) && (is_secure == 0U)) {
 		ret = -EPERM;

diff --git a/plat/xilinx/common/pm_service/pm_api_sys.c b/plat/xilinx/common/pm_service/pm_api_sys.c
index 4390b55..efb9286 100644
--- a/plat/xilinx/common/pm_service/pm_api_sys.c
+++ b/plat/xilinx/common/pm_service/pm_api_sys.c

@@ -409,6 +409,7 @@
 		break;
 	default:
 		ret = PM_RET_ERROR_NO_FEATURE;
+		break;
 	}
 
 	return ret;
@@ -439,33 +440,31 @@
 	case PM_GET_TRUSTZONE_VERSION:
 		ret_payload[0] = PM_API_VERSION_2;
 		ret = PM_RET_SUCCESS;
-		goto exit_label;
+		break;
 	case TF_A_PM_REGISTER_SGI:
 		ret_payload[0] = PM_API_BASE_VERSION;
 		ret = PM_RET_SUCCESS;
-		goto exit_label;
-	default:
 		break;
-	}
+	default:
+		module_id = (api_id & MODULE_ID_MASK) >> 8U;
 
-	module_id = (api_id & MODULE_ID_MASK) >> 8U;
+		/*
+		 * feature check should be done only for LIBPM module
+		 * If module_id is 0, then we consider it LIBPM module as default id
+		 */
+		if ((module_id > 0U) && (module_id != LIBPM_MODULE_ID)) {
+			ret = PM_RET_SUCCESS;
+			break;
+		}
 
-	/*
-	 * feature check should be done only for LIBPM module
-	 * If module_id is 0, then we consider it LIBPM module as default id
-	 */
-	if ((module_id > 0U) && (module_id != LIBPM_MODULE_ID)) {
-		ret = PM_RET_SUCCESS;
-		goto exit_label;
-	}
+		PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, flag,
+				 PM_FEATURE_CHECK, api_id);
+		ret = pm_ipi_send_sync(primary_proc, payload, ret_payload, RET_PAYLOAD_ARG_CNT);
 
-	PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, flag,
-			PM_FEATURE_CHECK, api_id);
-	ret = pm_ipi_send_sync(primary_proc, payload, ret_payload, RET_PAYLOAD_ARG_CNT);
+		break;
+	}
 
-exit_label:
 	return ret;
-
 }
 
 /**

diff --git a/plat/xilinx/common/pm_service/pm_ipi.c b/plat/xilinx/common/pm_service/pm_ipi.c
index 86b55ab..38c36e5 100644
--- a/plat/xilinx/common/pm_service/pm_ipi.c
+++ b/plat/xilinx/common/pm_service/pm_ipi.c

@@ -312,7 +312,7 @@
 }
 
 #if IPI_CRC_CHECK
-uint32_t calculate_crc(uint32_t payload[PAYLOAD_ARG_CNT], uint32_t bufsize)
+uint32_t calculate_crc(uint32_t payload[PAYLOAD_ARG_CNT], uint32_t buffersize)
 {
 	uint32_t crcinit = CRC_INIT_VALUE;
 	uint32_t order   = CRC_ORDER;
@@ -320,20 +320,22 @@
 	uint32_t i, j, c, bit, datain, crcmask, crchighbit;
 	uint32_t crc = crcinit;
 
-	crcmask = ((uint32_t)((1U << (order - 1U)) - 1U) << 1U) | 1U;
-	crchighbit = (uint32_t)(1U << (order - 1U));
+	crcmask = ((((uint32_t)1U << (order - 1U)) - 1U) << 1U) | 1U;
+	crchighbit = ((uint32_t)1U << (order - 1U));
 
-	for (i = 0U; i < bufsize; i++) {
+	for (i = 0U; i < buffersize; i++) {
 		datain = mmio_read_8((unsigned long)payload + i);
 		c = datain;
 		j = 0x80U;
 		while (j != 0U) {
 			bit = crc & crchighbit;
 			crc <<= 1U;
-			if (0U != (c & j))
+			if (0U != (c & j)) {
 				bit ^= crchighbit;
-			if (bit != 0U)
+			}
+			if (bit != 0U) {
 				crc ^= polynom;
+			}
 			j >>= 1U;
 		}
 		crc &= crcmask;

diff --git a/plat/xilinx/common/pm_service/pm_svc_main.c b/plat/xilinx/common/pm_service/pm_svc_main.c
index cb9273a..b8ff926 100644
--- a/plat/xilinx/common/pm_service/pm_svc_main.c
+++ b/plat/xilinx/common/pm_service/pm_svc_main.c

@@ -29,7 +29,6 @@
 
 #define MODE				0x80000000U
 
-#define XSCUGIC_SGIR_EL1_INITID_SHIFT    24U
 #define INVALID_SGI    0xFFU
 #define PM_INIT_SUSPEND_CB	(30U)
 #define PM_NOTIFY_CB		(32U)
@@ -171,7 +170,8 @@
 		break;
 	case PM_NOTIFY_CB:
 		if (sgi != INVALID_SGI) {
-			if (payload[2] == EVENT_CPU_PWRDWN) {
+			if ((payload[2] == EVENT_CPU_PWRDWN) &&
+			    (NODECLASS(payload[1]) == (uint32_t)XPM_NODECLASS_DEVICE)) {
 				if (pwrdwn_req_received) {
 					pwrdwn_req_received = false;
 					request_cpu_pwrdwn();
@@ -183,7 +183,8 @@
 			}
 			notify_os();
 		} else {
-			if (payload[2] == EVENT_CPU_PWRDWN) {
+			if ((payload[2] == EVENT_CPU_PWRDWN) &&
+			    (NODECLASS(payload[1]) == (uint32_t)XPM_NODECLASS_DEVICE)) {
 				request_cpu_pwrdwn();
 				(void)psci_cpu_off();
 			}
@@ -303,7 +304,7 @@
  * until their use case in linux driver changes.
  *
  */
-static uintptr_t eemi_for_compatibility(uint32_t api_id, uint32_t *pm_arg,
+static uintptr_t eemi_for_compatibility(uint32_t api_id, const uint32_t *pm_arg,
 					void *handle, uint32_t security_flag)
 {
 	enum pm_ret_status ret;
@@ -348,7 +349,7 @@
  * Return: If EEMI API found then, uintptr_t type address, else 0.
  *
  */
-static uintptr_t eemi_psci_debugfs_handler(uint32_t api_id, uint32_t *pm_arg,
+static uintptr_t eemi_psci_debugfs_handler(uint32_t api_id, const uint32_t *pm_arg,
 					   void *handle, uint32_t security_flag)
 {
 	enum pm_ret_status ret;
@@ -396,7 +397,7 @@
  * Return: If TF-A specific API found then, uintptr_t type address, else 0
  *
  */
-static uintptr_t TF_A_specific_handler(uint32_t api_id, uint32_t *pm_arg,
+static uintptr_t TF_A_specific_handler(uint32_t api_id, const uint32_t *pm_arg,
 				       void *handle, uint32_t security_flag)
 {
 	switch (api_id) {
@@ -463,7 +464,7 @@
  * Return: If EEMI API found then, uintptr_t type address, else 0
  *
  */
-static uintptr_t eemi_handler(uint32_t api_id, uint32_t *pm_arg,
+static uintptr_t eemi_handler(uint32_t api_id, const uint32_t *pm_arg,
 			      void *handle, uint32_t security_flag)
 {
 	enum pm_ret_status ret;

diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c
index befe36c..70b0fa6 100644
--- a/plat/xilinx/versal/bl31_versal_setup.c
+++ b/plat/xilinx/versal/bl31_versal_setup.c

@@ -18,8 +18,9 @@
 #include <plat/common/platform.h>
 #include <plat_arm.h>
 #include <plat_console.h>
-#include <plat_clkfunc.h>
 
+#include <custom_svc.h>
+#include <plat_clkfunc.h>
 #include <plat_fdt.h>
 #include <plat_private.h>
 #include <plat_startup.h>
@@ -143,6 +144,8 @@
 
 	NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
 	NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
+
+	custom_early_setup();
 }
 
 static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3];
@@ -220,6 +223,8 @@
 	if (rc != 0) {
 		panic();
 	}
+
+	custom_runtime_setup();
 }
 
 /*
@@ -248,6 +253,8 @@
 		{0}
 	};
 
+	custom_mmap_add();
+
 	setup_page_tables(bl_regions, plat_get_mmap());
 	enable_mmu(0);
 }

diff --git a/plat/xilinx/versal/include/platform_def.h b/plat/xilinx/versal/include/platform_def.h
index a3886a4..d8b334a 100644
--- a/plat/xilinx/versal/include/platform_def.h
+++ b/plat/xilinx/versal/include/platform_def.h

@@ -17,7 +17,9 @@
  ******************************************************************************/
 
 /* Size of cacheable stacks */
+#ifndef PLATFORM_STACK_SIZE
 #define PLATFORM_STACK_SIZE	U(0x440)
+#endif
 
 #define PLATFORM_CORE_COUNT		U(2)
 #define PLAT_MAX_PWR_LVL		U(1)

diff --git a/plat/xilinx/versal/platform.mk b/plat/xilinx/versal/platform.mk
index 8be4be6..83d2d6f 100644
--- a/plat/xilinx/versal/platform.mk
+++ b/plat/xilinx/versal/platform.mk

@@ -144,3 +144,9 @@
 CORTEX_A72_H_INC	:= 1
 $(eval $(call add_define, CORTEX_A72_H_INC))
 endif
+
+ifdef CUSTOM_PKG_PATH
+include $(CUSTOM_PKG_PATH)/custom_pkg.mk
+else
+BL31_SOURCES		+=	plat/xilinx/common/custom_sip_svc.c
+endif

diff --git a/plat/xilinx/versal/sip_svc_setup.c b/plat/xilinx/versal/sip_svc_setup.c
index bb3f728..5e7ce9e 100644
--- a/plat/xilinx/versal/sip_svc_setup.c
+++ b/plat/xilinx/versal/sip_svc_setup.c

@@ -13,6 +13,7 @@
 #include <common/runtime_svc.h>
 #include <tools_share/uuid.h>
 
+#include <custom_svc.h>
 #include "ipi_mailbox_svc.h"
 #include "pm_svc_main.h"
 
@@ -105,6 +106,11 @@
 	case VERSAL_SIP_SVC_VERSION:
 		SMC_RET2(handle, SIP_SVC_VERSION_MAJOR, SIP_SVC_VERSION_MINOR);
 
+	case SOC_SIP_SVC_CUSTOM:
+	case SOC_SIP_SVC64_CUSTOM:
+		return custom_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
+					  handle, flags);
+
 	default:
 		WARN("Unimplemented SiP Service Call: 0x%x\n", smc_fid);
 		SMC_RET1(handle, SMC_UNK);

diff --git a/plat/xilinx/versal_net/plat_psci.c b/plat/xilinx/versal_net/plat_psci.c
index fcb32b9..399500d 100644
--- a/plat/xilinx/versal_net/plat_psci.c
+++ b/plat/xilinx/versal_net/plat_psci.c

@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
  * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -19,8 +19,6 @@
 #include <plat_private.h>
 #include <pm_defs.h>
 
-#define PM_RET_ERROR_NOFEATURE U(19)
-
 static uintptr_t versal_net_sec_entry;
 
 static void zynqmp_cpu_standby(plat_local_state_t cpu_state)
@@ -175,7 +173,7 @@
 		mmio_write_32(SLCR_OSPI_QSPI_IOU_AXI_MUX_SEL, arg1);
 		return 0;
 	}
-	return PM_RET_ERROR_NOFEATURE;
+	return PM_RET_ERROR_IOCTL_NOT_SUPPORTED;
 }
 
 static uint64_t no_pm_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,

diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
index b29e1c6..65616e5 100644
--- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
+++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c

@@ -64,6 +64,26 @@
 					  DISABLE_ALL_EXCEPTIONS);
 }
 
+static inline uint64_t read_cntvct_el0(void)
+{
+	uint64_t val;
+
+	asm volatile("mrs %0, cntvct_el0" : "=r" (val));
+	return val;
+}
+
+static inline void reset_cntvct_el0_to_zero(void)
+{
+	asm volatile(
+		"mrs x0, cntpct_el0\n"   /* Read physical counter into x0 */
+		"neg x0, x0\n"           /* Negate it: x0 = -x0 */
+		"msr cntvoff_el2, x0\n"  /* Write offset to virtual counter */
+		:
+		:
+		: "x0", "memory"
+	);
+}
+
 /*
  * Perform any BL31 specific platform actions. Here is an opportunity to copy
  * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they
@@ -93,6 +113,10 @@
 	/* Initialize the platform config for future decision making */
 	zynqmp_config_setup();
 
+	INFO("Counter TICK 0x%lx\n", read_cntvct_el0());
+	reset_cntvct_el0_to_zero();
+	INFO("Counter TICK after reset 0x%lx\n", read_cntvct_el0());
+
 	/*
 	 * Do initial security configuration to allow DRAM/device access. On
 	 * Base ZYNQMP only DRAM security is programmable (via TrustZone), but

diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
index 27e5427..d2cb220 100644
--- a/plat/xilinx/zynqmp/platform.mk
+++ b/plat/xilinx/zynqmp/platform.mk

@@ -162,7 +162,7 @@
 ifdef CUSTOM_PKG_PATH
 include $(CUSTOM_PKG_PATH)/custom_pkg.mk
 else
-BL31_SOURCES		+=	plat/xilinx/zynqmp/custom_sip_svc.c
+BL31_SOURCES		+=	plat/xilinx/common/custom_sip_svc.c
 endif
 
 ifneq (${RESET_TO_BL31},1)

diff --git a/plat/xilinx/zynqmp/sip_svc_setup.c b/plat/xilinx/zynqmp/sip_svc_setup.c
index 1baefb3..6d94422 100644
--- a/plat/xilinx/zynqmp/sip_svc_setup.c
+++ b/plat/xilinx/zynqmp/sip_svc_setup.c

@@ -105,8 +105,8 @@
 	case ZYNQMP_SIP_SVC_VERSION:
 		SMC_RET2(handle, SIP_SVC_VERSION_MAJOR, SIP_SVC_VERSION_MINOR);
 
-	case ZYNQMP_SIP_SVC_CUSTOM:
-	case ZYNQMP_SIP_SVC64_CUSTOM:
+	case SOC_SIP_SVC_CUSTOM:
+	case SOC_SIP_SVC64_CUSTOM:
 		return custom_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
 					  handle, flags);
 

diff --git a/pyproject.toml b/pyproject.toml
index 88c4753..0c39f49 100644
--- a/pyproject.toml
+++ b/pyproject.toml

@@ -1,6 +1,6 @@
 [tool.poetry]
 name = "trusted-firmware-a"
-version = "2.12.0"
+version = "2.13.0"
 description = "Trusted Firmware-A (TF-A) Python dependencies."
 authors = ["Arm Ltd."]
 license = "BSD-3-Clause"

diff --git a/services/el3/ven_el3_svc.c b/services/el3/ven_el3_svc.c
index 32a3dc2..431bfbf 100644
--- a/services/el3/ven_el3_svc.c
+++ b/services/el3/ven_el3_svc.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,6 +10,9 @@
 #include <common/runtime_svc.h>
 #include <lib/debugfs.h>
 #include <lib/pmf/pmf.h>
+#if PLAT_ARM_ACS_SMC_HANDLER
+#include <plat/arm/common/plat_acs_smc_handler.h>
+#endif /* PLAT_ARM_ACS_SMC_HANDLER */
 #include <services/ven_el3_svc.h>
 #include <tools_share/uuid.h>
 
@@ -71,6 +74,15 @@
 
 #endif /* ENABLE_PMF */
 
+#if PLAT_ARM_ACS_SMC_HANDLER
+	/*
+	 * Dispatch ACS calls to ACS SMC handler and return its return value
+	 */
+	if (is_acs_fid(smc_fid)) {
+		return plat_arm_acs_smc_handler(smc_fid, x1, x2, x3, x4, handle);
+	}
+#endif /* PLAT_ARM_ACS_SMC_HANDLER */
+
 	switch (smc_fid) {
 	case VEN_EL3_SVC_UID:
 		/* Return UID to the caller */

diff --git a/services/spd/opteed/opteed_main.c b/services/spd/opteed/opteed_main.c
index 8910ec6..5e232f9 100644
--- a/services/spd/opteed/opteed_main.c
+++ b/services/spd/opteed/opteed_main.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -27,7 +27,9 @@
 #include <lib/coreboot.h>
 #include <lib/el3_runtime/context_mgmt.h>
 #include <lib/optee_utils.h>
+#if TRANSFER_LIST
 #include <lib/transfer_list.h>
+#endif
 #include <lib/xlat_tables/xlat_tables_v2.h>
 #if OPTEE_ALLOW_SMC_LOAD
 #include <libfdt.h>
@@ -40,7 +42,7 @@
 #include "teesmc_opteed.h"
 
 #if OPTEE_ALLOW_SMC_LOAD
-static struct transfer_list_header *bl31_tl;
+static struct transfer_list_header __maybe_unused *bl31_tl;
 #endif
 
 /*******************************************************************************
@@ -163,9 +165,9 @@
 	uint64_t arg1;
 	uint64_t arg2;
 	uint64_t arg3;
-	struct transfer_list_header *tl = NULL;
-	struct transfer_list_entry *te = NULL;
-	void *dt = NULL;
+	struct transfer_list_header __maybe_unused *tl = NULL;
+	struct transfer_list_entry __maybe_unused *te = NULL;
+	void __maybe_unused *dt = NULL;
 
 	linear_id = plat_my_core_pos();
 
@@ -190,8 +192,10 @@
 	if (!optee_ep_info->pc)
 		return 1;
 
+#if TRANSFER_LIST
 	tl = (void *)optee_ep_info->args.arg3;
-	if (TRANSFER_LIST && transfer_list_check_header(tl)) {
+
+	if (transfer_list_check_header(tl)) {
 		te = transfer_list_find(tl, TL_TAG_FDT);
 		dt = transfer_list_entry_data(te);
 
@@ -199,7 +203,7 @@
 		if (opteed_rw == OPTEE_AARCH64) {
 			if (optee_ep_info->args.arg1 !=
 			    TRANSFER_LIST_HANDOFF_X1_VALUE(
-				REGISTER_CONVENTION_VERSION))
+				    REGISTER_CONVENTION_VERSION))
 				return 1;
 
 			arg0 = (uint64_t)dt;
@@ -207,7 +211,7 @@
 		} else {
 			if (optee_ep_info->args.arg1 !=
 			    TRANSFER_LIST_HANDOFF_R1_VALUE(
-				REGISTER_CONVENTION_VERSION))
+				    REGISTER_CONVENTION_VERSION))
 				return 1;
 
 			arg0 = 0;
@@ -216,7 +220,10 @@
 
 		arg1 = optee_ep_info->args.arg1;
 		arg3 = optee_ep_info->args.arg3;
-	} else {
+
+	} else
+#endif /* TRANSFER_LIST */
+	{
 		/* Default handoff arguments */
 		opteed_rw = optee_ep_info->args.arg0;
 		arg0 = optee_ep_info->args.arg1; /* opteed_pageable_part */
@@ -225,9 +232,9 @@
 		arg3 = 0;
 	}
 
-	opteed_init_optee_ep_state(optee_ep_info, opteed_rw, optee_ep_info->pc,
-				arg0, arg1, arg2, arg3,
-				&opteed_sp_context[linear_id]);
+	opteed_init_optee_ep_state(optee_ep_info, opteed_rw,
+				   optee_ep_info->pc, arg0, arg1, arg2,
+				   arg3, &opteed_sp_context[linear_id]);
 
 	/*
 	 * All OPTEED initialization done. Now register our init function with
@@ -430,9 +437,9 @@
 	return fdt_finish(fdt_buf);
 }
 
+#if TRANSFER_LIST
 static int32_t create_smc_tl(const void *fdt, uint32_t fdt_sz)
 {
-#if TRANSFER_LIST
 	bl31_tl = transfer_list_init((void *)(uintptr_t)FW_HANDOFF_BASE,
 				FW_HANDOFF_SIZE);
 	if (!bl31_tl) {
@@ -445,10 +452,8 @@
 		return -1;
 	}
 	return 0;
-#else
-	return -1;
-#endif
 }
+#endif
 
 /*******************************************************************************
  * This function is responsible for handling the SMC that loads the OP-TEE
@@ -546,8 +551,8 @@
 	dt_addr = (uint64_t)fdt_buf;
 	flush_dcache_range(dt_addr, OPTEED_FDT_SIZE);
 
-	if (TRANSFER_LIST &&
-	    !create_smc_tl((void *)dt_addr, OPTEED_FDT_SIZE)) {
+#if TRANSFER_LIST
+	if (!create_smc_tl((void *)dt_addr, OPTEED_FDT_SIZE)) {
 		struct transfer_list_entry *te = NULL;
 		void *dt = NULL;
 
@@ -565,7 +570,9 @@
 		}
 
 		arg3 = (uint64_t)bl31_tl;
-	} else {
+	} else
+#endif /* TRANSFER_LIST */
+	{
 		/* Default handoff arguments */
 		arg2 = dt_addr;
 	}

diff --git a/services/std_svc/drtm/drtm_dma_prot.h b/services/std_svc/drtm/drtm_dma_prot.h
index 79dc9cb..5ccff87 100644
--- a/services/std_svc/drtm/drtm_dma_prot.h
+++ b/services/std_svc/drtm/drtm_dma_prot.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2025 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier:    BSD-3-Clause
  *
@@ -20,7 +20,7 @@
 enum dma_prot_type {
 	PROTECT_NONE    = -1,
 	PROTECT_MEM_ALL = 0,
-	PROTECT_MEM_REGION = 2,
+	PROTECT_MEM_REGION = 1,
 };
 
 struct dma_prot {

diff --git a/services/std_svc/drtm/drtm_measurements.c b/services/std_svc/drtm/drtm_measurements.c
index 7214e23..4518d37 100644
--- a/services/std_svc/drtm/drtm_measurements.c
+++ b/services/std_svc/drtm/drtm_measurements.c

@@ -138,7 +138,8 @@
 	/* PCR-17: End of DCE measurements. */
 	rc = drtm_event_log_measure_and_record((uintptr_t)drtm_event_arm_sep_data,
 					       strlen(drtm_event_arm_sep_data),
-					       DRTM_EVENT_ARM_SEPARATOR, NULL,
+					       DRTM_EVENT_ARM_SEPARATOR,
+					       drtm_event_arm_sep_data,
 					       PCR_17);
 	CHECK_RC(rc, drtm_event_log_measure_and_record(DRTM_EVENT_ARM_SEPARATOR));
 
@@ -188,7 +189,7 @@
 
 	/* PCR-18: Measure the DLME image entry point. */
 	dlme_img_ep = DL_ARGS_GET_DLME_ENTRY_POINT(a);
-	drtm_event_log_measure_and_record((uintptr_t)&dlme_img_ep,
+	drtm_event_log_measure_and_record((uintptr_t)&(a->dlme_img_ep_off),
 					  sizeof(dlme_img_ep),
 					  DRTM_EVENT_ARM_DLME_EP, NULL,
 					  PCR_18);
@@ -197,7 +198,8 @@
 	/* PCR-18: End of DCE measurements. */
 	rc = drtm_event_log_measure_and_record((uintptr_t)drtm_event_arm_sep_data,
 					       strlen(drtm_event_arm_sep_data),
-					       DRTM_EVENT_ARM_SEPARATOR, NULL,
+					       DRTM_EVENT_ARM_SEPARATOR,
+					       drtm_event_arm_sep_data,
 					       PCR_18);
 	CHECK_RC(rc,
 		 drtm_event_log_measure_and_record(DRTM_EVENT_ARM_SEPARATOR));

diff --git a/services/std_svc/sdei/sdei_event.c b/services/std_svc/sdei/sdei_event.c
index cc8f557..9c7f74a 100644
--- a/services/std_svc/sdei/sdei_event.c
+++ b/services/std_svc/sdei/sdei_event.c

@@ -61,11 +61,13 @@
  * Both shared and private maps are stored in single-dimensional array. Private
  * event entries are kept for each PE forming a 2D array.
  */
-sdei_entry_t *get_event_entry_target_pe(long int mapsub, unsigned int nm, uint64_t target_pe)
+sdei_entry_t *get_event_entry_target_pe(long int mapsub, unsigned int nm,
+uint64_t target_pe)
 {
 	sdei_entry_t *cpu_priv_base;
-	unsigned int base_idx;
+	unsigned int base_idx = 0U;
 	long int idx;
+	int target_pos;
 
 	/*
 	 * For a private map, find the index of the mapping in the
@@ -74,9 +76,17 @@
 	idx = mapsub;
 
 	/* Base of private mappings for this CPU */
-	base_idx = (unsigned int) plat_core_pos_by_mpidr(target_pe);
+	target_pos = plat_core_pos_by_mpidr(target_pe);
+
+	if ((target_pos < 0) || ((unsigned int)target_pos >= PLATFORM_CORE_COUNT)) {
+		return NULL;
+	}
+
+	base_idx = (unsigned int) target_pos;
 	base_idx *= nm;
+
 	cpu_priv_base = &sdei_private_event_table[base_idx];
+
 	/*
 	 * Return the address of the entry at the same index in the
 	 * per-CPU event entry.

diff --git a/services/std_svc/sdei/sdei_intr_mgmt.c b/services/std_svc/sdei/sdei_intr_mgmt.c
index 4854b2e..40c3c24 100644
--- a/services/std_svc/sdei/sdei_intr_mgmt.c
+++ b/services/std_svc/sdei/sdei_intr_mgmt.c

@@ -61,9 +61,12 @@
 
 bool sdei_is_target_pe_masked(uint64_t target_pe)
 {
-	const sdei_cpu_state_t *state = sdei_get_target_pe_state(target_pe);
-
-	return state->pe_masked;
+	int errstat = plat_core_pos_by_mpidr(target_pe);
+	if (errstat >= 0) {
+		const sdei_cpu_state_t *state = &cpu_state[errstat];
+		return state->pe_masked;
+	}
+	return true;
 }
 
 int64_t sdei_pe_mask(void)

diff --git a/services/std_svc/sdei/sdei_main.c b/services/std_svc/sdei/sdei_main.c
index bbc9f73..52c01e8 100644
--- a/services/std_svc/sdei/sdei_main.c
+++ b/services/std_svc/sdei/sdei_main.c

@@ -948,6 +948,9 @@
 			if (map_priv->ev_num == SDEI_EVENT_0) {
 				se = get_event_entry_target_pe((long int) i,
 				(unsigned int) SDEI_PRIVATE_MAPPING()->num_maps, target_pe);
+				if (se == NULL) {
+					return SDEI_EINVAL;
+				}
 				if (!(GET_EV_STATE((se), REGISTERED))) {
 					return SDEI_EINVAL;
 				}

diff --git a/tools/conventional-changelog-tf-a/package.json b/tools/conventional-changelog-tf-a/package.json
index 9975ea3..81e9fb8 100644
--- a/tools/conventional-changelog-tf-a/package.json
+++ b/tools/conventional-changelog-tf-a/package.json

@@ -1,6 +1,6 @@
 {
   "name": "conventional-changelog-tf-a",
-  "version": "2.12.0",
+  "version": "2.13.0",
   "license": "BSD-3-Clause",
   "private": true,
   "main": "index.js",

diff --git a/tools/memory/poetry.lock b/tools/memory/poetry.lock
index 2747479..67641ee 100644
--- a/tools/memory/poetry.lock
+++ b/tools/memory/poetry.lock

@@ -40,6 +40,103 @@
 ]
 
 [[package]]
+name = "jinja2"
+version = "3.1.6"
+description = "A very fast and expressive template engine."
+optional = false
+python-versions = ">=3.7"
+files = [
+    {file = "jinja2-3.1.6-py3-none-any.whl", hash = "sha256:85ece4451f492d0c13c5dd7c13a64681a86afae63a5f347908daf103ce6d2f67"},
+    {file = "jinja2-3.1.6.tar.gz", hash = "sha256:0137fb05990d35f1275a587e9aee6d56da821fc83491a0fb838183be43f66d6d"},
+]
+
+[package.dependencies]
+MarkupSafe = ">=2.0"
+
+[package.extras]
+i18n = ["Babel (>=2.7)"]
+
+[[package]]
+name = "markupsafe"
+version = "2.1.5"
+description = "Safely add untrusted strings to HTML/XML markup."
+optional = false
+python-versions = ">=3.7"
+files = [
+    {file = "MarkupSafe-2.1.5-cp310-cp310-macosx_10_9_universal2.whl", hash = "sha256:a17a92de5231666cfbe003f0e4b9b3a7ae3afb1ec2845aadc2bacc93ff85febc"},
+    {file = "MarkupSafe-2.1.5-cp310-cp310-macosx_10_9_x86_64.whl", hash = "sha256:72b6be590cc35924b02c78ef34b467da4ba07e4e0f0454a2c5907f473fc50ce5"},
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+    {file = "MarkupSafe-2.1.5-cp38-cp38-manylinux_2_17_aarch64.manylinux2014_aarch64.whl", hash = "sha256:1f3fbcb7ef1f16e48246f704ab79d79da8a46891e2da03f8783a5b6fa41a9532"},
+    {file = "MarkupSafe-2.1.5-cp38-cp38-manylinux_2_17_x86_64.manylinux2014_x86_64.whl", hash = "sha256:fa9db3f79de01457b03d4f01b34cf91bc0048eb2c3846ff26f66687c2f6d16ab"},
+    {file = "MarkupSafe-2.1.5-cp38-cp38-manylinux_2_5_i686.manylinux1_i686.manylinux_2_17_i686.manylinux2014_i686.whl", hash = "sha256:ffee1f21e5ef0d712f9033568f8344d5da8cc2869dbd08d87c84656e6a2d2f68"},
+    {file = "MarkupSafe-2.1.5-cp38-cp38-musllinux_1_1_aarch64.whl", hash = "sha256:5dedb4db619ba5a2787a94d877bc8ffc0566f92a01c0ef214865e54ecc9ee5e0"},
+    {file = "MarkupSafe-2.1.5-cp38-cp38-musllinux_1_1_i686.whl", hash = "sha256:30b600cf0a7ac9234b2638fbc0fb6158ba5bdcdf46aeb631ead21248b9affbc4"},
+    {file = "MarkupSafe-2.1.5-cp38-cp38-musllinux_1_1_x86_64.whl", hash = "sha256:8dd717634f5a044f860435c1d8c16a270ddf0ef8588d4887037c5028b859b0c3"},
+    {file = "MarkupSafe-2.1.5-cp38-cp38-win32.whl", hash = "sha256:daa4ee5a243f0f20d528d939d06670a298dd39b1ad5f8a72a4275124a7819eff"},
+    {file = "MarkupSafe-2.1.5-cp38-cp38-win_amd64.whl", hash = "sha256:619bc166c4f2de5caa5a633b8b7326fbe98e0ccbfacabd87268a2b15ff73a029"},
+    {file = "MarkupSafe-2.1.5-cp39-cp39-macosx_10_9_universal2.whl", hash = "sha256:7a68b554d356a91cce1236aa7682dc01df0edba8d043fd1ce607c49dd3c1edcf"},
+    {file = "MarkupSafe-2.1.5-cp39-cp39-macosx_10_9_x86_64.whl", hash = "sha256:db0b55e0f3cc0be60c1f19efdde9a637c32740486004f20d1cff53c3c0ece4d2"},
+    {file = "MarkupSafe-2.1.5-cp39-cp39-manylinux_2_17_aarch64.manylinux2014_aarch64.whl", hash = "sha256:3e53af139f8579a6d5f7b76549125f0d94d7e630761a2111bc431fd820e163b8"},
+    {file = "MarkupSafe-2.1.5-cp39-cp39-manylinux_2_17_x86_64.manylinux2014_x86_64.whl", hash = "sha256:17b950fccb810b3293638215058e432159d2b71005c74371d784862b7e4683f3"},
+    {file = "MarkupSafe-2.1.5-cp39-cp39-manylinux_2_5_i686.manylinux1_i686.manylinux_2_17_i686.manylinux2014_i686.whl", hash = "sha256:4c31f53cdae6ecfa91a77820e8b151dba54ab528ba65dfd235c80b086d68a465"},
+    {file = "MarkupSafe-2.1.5-cp39-cp39-musllinux_1_1_aarch64.whl", hash = "sha256:bff1b4290a66b490a2f4719358c0cdcd9bafb6b8f061e45c7a2460866bf50c2e"},
+    {file = "MarkupSafe-2.1.5-cp39-cp39-musllinux_1_1_i686.whl", hash = "sha256:bc1667f8b83f48511b94671e0e441401371dfd0f0a795c7daa4a3cd1dde55bea"},
+    {file = "MarkupSafe-2.1.5-cp39-cp39-musllinux_1_1_x86_64.whl", hash = "sha256:5049256f536511ee3f7e1b3f87d1d1209d327e818e6ae1365e8653d7e3abb6a6"},
+    {file = "MarkupSafe-2.1.5-cp39-cp39-win32.whl", hash = "sha256:00e046b6dd71aa03a41079792f8473dc494d564611a8f89bbbd7cb93295ebdcf"},
+    {file = "MarkupSafe-2.1.5-cp39-cp39-win_amd64.whl", hash = "sha256:fa173ec60341d6bb97a89f5ea19c85c5643c1e7dedebc22f5181eb73573142c5"},
+    {file = "MarkupSafe-2.1.5.tar.gz", hash = "sha256:d283d37a890ba4c1ae73ffadf8046435c76e7bc2247bbb63c00bd1a709c6544b"},
+]
+
+[[package]]
+name = "nodeenv"
+version = "1.9.1"
+description = "Node.js virtual environment builder"
+optional = false
+python-versions = "!=3.0.*,!=3.1.*,!=3.2.*,!=3.3.*,!=3.4.*,!=3.5.*,!=3.6.*,>=2.7"
+files = [
+    {file = "nodeenv-1.9.1-py2.py3-none-any.whl", hash = "sha256:ba11c9782d29c27c70ffbdda2d7415098754709be8a7056d79a737cd901155c9"},
+    {file = "nodeenv-1.9.1.tar.gz", hash = "sha256:6ec12890a2dab7946721edbfbcd91f3319c6ccc9aec47be7c7e6b7011ee6645f"},
+]
+
+[[package]]
 name = "prettytable"
 version = "3.11.0"
 description = "A simple Python library for easily displaying tabular data in a visually appealing ASCII table format"
@@ -68,6 +165,53 @@
 ]
 
 [[package]]
+name = "pyright"
+version = "1.1.399"
+description = "Command line wrapper for pyright"
+optional = false
+python-versions = ">=3.7"
+files = [
+    {file = "pyright-1.1.399-py3-none-any.whl", hash = "sha256:55f9a875ddf23c9698f24208c764465ffdfd38be6265f7faf9a176e1dc549f3b"},
+    {file = "pyright-1.1.399.tar.gz", hash = "sha256:439035d707a36c3d1b443aec980bc37053fbda88158eded24b8eedcf1c7b7a1b"},
+]
+
+[package.dependencies]
+nodeenv = ">=1.6.0"
+typing-extensions = ">=4.1"
+
+[package.extras]
+all = ["nodejs-wheel-binaries", "twine (>=3.4.1)"]
+dev = ["twine (>=3.4.1)"]
+nodejs = ["nodejs-wheel-binaries"]
+
+[[package]]
+name = "ruff"
+version = "0.11.2"
+description = "An extremely fast Python linter and code formatter, written in Rust."
+optional = false
+python-versions = ">=3.7"
+files = [
+    {file = "ruff-0.11.2-py3-none-linux_armv6l.whl", hash = "sha256:c69e20ea49e973f3afec2c06376eb56045709f0212615c1adb0eda35e8a4e477"},
+    {file = "ruff-0.11.2-py3-none-macosx_10_12_x86_64.whl", hash = "sha256:2c5424cc1c4eb1d8ecabe6d4f1b70470b4f24a0c0171356290b1953ad8f0e272"},
+    {file = "ruff-0.11.2-py3-none-macosx_11_0_arm64.whl", hash = "sha256:ecf20854cc73f42171eedb66f006a43d0a21bfb98a2523a809931cda569552d9"},
+    {file = "ruff-0.11.2-py3-none-manylinux_2_17_aarch64.manylinux2014_aarch64.whl", hash = "sha256:0c543bf65d5d27240321604cee0633a70c6c25c9a2f2492efa9f6d4b8e4199bb"},
+    {file = "ruff-0.11.2-py3-none-manylinux_2_17_armv7l.manylinux2014_armv7l.whl", hash = "sha256:20967168cc21195db5830b9224be0e964cc9c8ecf3b5a9e3ce19876e8d3a96e3"},
+    {file = "ruff-0.11.2-py3-none-manylinux_2_17_i686.manylinux2014_i686.whl", hash = "sha256:955a9ce63483999d9f0b8f0b4a3ad669e53484232853054cc8b9d51ab4c5de74"},
+    {file = "ruff-0.11.2-py3-none-manylinux_2_17_ppc64.manylinux2014_ppc64.whl", hash = "sha256:86b3a27c38b8fce73bcd262b0de32e9a6801b76d52cdb3ae4c914515f0cef608"},
+    {file = "ruff-0.11.2-py3-none-manylinux_2_17_ppc64le.manylinux2014_ppc64le.whl", hash = "sha256:a3b66a03b248c9fcd9d64d445bafdf1589326bee6fc5c8e92d7562e58883e30f"},
+    {file = "ruff-0.11.2-py3-none-manylinux_2_17_s390x.manylinux2014_s390x.whl", hash = "sha256:0397c2672db015be5aa3d4dac54c69aa012429097ff219392c018e21f5085147"},
+    {file = "ruff-0.11.2-py3-none-manylinux_2_17_x86_64.manylinux2014_x86_64.whl", hash = "sha256:869bcf3f9abf6457fbe39b5a37333aa4eecc52a3b99c98827ccc371a8e5b6f1b"},
+    {file = "ruff-0.11.2-py3-none-musllinux_1_2_aarch64.whl", hash = "sha256:2a2b50ca35457ba785cd8c93ebbe529467594087b527a08d487cf0ee7b3087e9"},
+    {file = "ruff-0.11.2-py3-none-musllinux_1_2_armv7l.whl", hash = "sha256:7c69c74bf53ddcfbc22e6eb2f31211df7f65054bfc1f72288fc71e5f82db3eab"},
+    {file = "ruff-0.11.2-py3-none-musllinux_1_2_i686.whl", hash = "sha256:6e8fb75e14560f7cf53b15bbc55baf5ecbe373dd5f3aab96ff7aa7777edd7630"},
+    {file = "ruff-0.11.2-py3-none-musllinux_1_2_x86_64.whl", hash = "sha256:842a472d7b4d6f5924e9297aa38149e5dcb1e628773b70e6387ae2c97a63c58f"},
+    {file = "ruff-0.11.2-py3-none-win32.whl", hash = "sha256:aca01ccd0eb5eb7156b324cfaa088586f06a86d9e5314b0eb330cb48415097cc"},
+    {file = "ruff-0.11.2-py3-none-win_amd64.whl", hash = "sha256:3170150172a8f994136c0c66f494edf199a0bbea7a409f649e4bc8f4d7084080"},
+    {file = "ruff-0.11.2-py3-none-win_arm64.whl", hash = "sha256:52933095158ff328f4c77af3d74f0379e34fd52f175144cefc1b192e7ccd32b4"},
+    {file = "ruff-0.11.2.tar.gz", hash = "sha256:ec47591497d5a1050175bdf4e1a4e6272cddff7da88a2ad595e1e326041d8d94"},
+]
+
+[[package]]
 name = "six"
 version = "1.17.0"
 description = "Python 2 and 3 compatibility utilities"
@@ -79,6 +223,17 @@
 ]
 
 [[package]]
+name = "typing-extensions"
+version = "4.13.2"
+description = "Backported and Experimental Type Hints for Python 3.8+"
+optional = false
+python-versions = ">=3.8"
+files = [
+    {file = "typing_extensions-4.13.2-py3-none-any.whl", hash = "sha256:a439e7c04b49fec3e5d3e2beaa21755cadbbdc391694e28ccdd36ca4a1408f8c"},
+    {file = "typing_extensions-4.13.2.tar.gz", hash = "sha256:e6c81219bd689f51865d9e372991c540bda33a0379d5573cddb9a3a23f7caaef"},
+]
+
+[[package]]
 name = "wcwidth"
 version = "0.2.13"
 description = "Measures the displayed width of unicode strings in a terminal"
@@ -92,4 +247,4 @@
 [metadata]
 lock-version = "2.0"
 python-versions = "^3.8.0"
-content-hash = "d7c185b3dbfc9bba145f12146e18ce501caf081d7762f138bc5a7fde99f40543"
+content-hash = "72f05cdcfe5278c3fb4408ba76cc502c83a56615681d8307bf67fe759a9da442"

diff --git a/tools/memory/pyproject.toml b/tools/memory/pyproject.toml
index c2fdfcb..70d3de7 100644
--- a/tools/memory/pyproject.toml
+++ b/tools/memory/pyproject.toml

@@ -12,10 +12,18 @@
 prettytable = "^3.5.0"
 pyelftools = "^0.29.0"
 python = "^3.8.0"
+jinja2 = "^3.1.6"
 
 [tool.poetry.scripts]
 memory = "memory.memmap:main"
 
+[tool.poetry.group.dev]
+optional = true
+
+[tool.poetry.group.dev.dependencies]
+ruff = "^0.11.2"
+pyright = "^1.1.399"
+
 [build-system]
 requires = ["poetry-core"]
 build-backend = "poetry.core.masonry.api"

diff --git a/tools/memory/src/memory/buildparser.py b/tools/memory/src/memory/buildparser.py
deleted file mode 100755
index ea417e1..0000000
--- a/tools/memory/src/memory/buildparser.py
+++ /dev/null

@@ -1,88 +0,0 @@
-#
-# Copyright (c) 2023-2025, Arm Limited. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-import re
-from pathlib import Path
-
-from memory.elfparser import TfaElfParser
-from memory.mapparser import TfaMapParser
-
-
-class TfaBuildParser:
-    """A class for performing analysis on the memory layout of a TF-A build."""
-
-    def __init__(self, path: Path, map_backend=False):
-        self._modules = dict()
-        self._path = path
-        self.map_backend = map_backend
-        self._parse_modules()
-
-    def __getitem__(self, module: str):
-        """Returns an TfaElfParser instance indexed by module."""
-        return self._modules[module]
-
-    def _parse_modules(self):
-        """Parse the build files using the selected backend."""
-        backend = TfaElfParser
-        files = list(self._path.glob("**/*.elf"))
-        io_perms = "rb"
-
-        if self.map_backend or len(files) == 0:
-            backend = TfaMapParser
-            files = self._path.glob("**/*.map")
-            io_perms = "r"
-
-        for file in files:
-            module_name = file.name.split("/")[-1].split(".")[0]
-            with open(file, io_perms) as f:
-                self._modules[module_name] = backend(f)
-
-        if not len(self._modules):
-            raise FileNotFoundError(
-                f"failed to find files to analyse in path {self._path}!"
-            )
-
-    @property
-    def symbols(self) -> list:
-        return [
-            (*sym, k) for k, v in self._modules.items() for sym in v.symbols
-        ]
-
-    @staticmethod
-    def filter_symbols(symbols: list, regex: str = None) -> list:
-        """Returns a map of symbols to modules."""
-        regex = r".*" if not regex else regex
-        return sorted(
-            filter(lambda s: re.match(regex, s[0]), symbols),
-            key=lambda s: (-s[1], s[0]),
-            reverse=True,
-        )
-
-    def get_mem_usage_dict(self) -> dict:
-        """Returns map of memory usage per memory type for each module."""
-        mem_map = {}
-        for k, v in self._modules.items():
-            mod_mem_map = v.get_memory_layout()
-            if len(mod_mem_map):
-                mem_map[k] = mod_mem_map
-        return mem_map
-
-    def get_mem_tree_as_dict(self) -> dict:
-        """Returns _tree of modules, segments and segments and their total
-        memory usage."""
-        return {
-            k: {
-                "name": k,
-                **v.get_mod_mem_usage_dict(),
-                **{"children": v.get_seg_map_as_dict()},
-            }
-            for k, v in self._modules.items()
-        }
-
-    @property
-    def module_names(self):
-        """Returns sorted list of module names."""
-        return sorted(self._modules.keys())

diff --git a/tools/memory/src/memory/elfparser.py b/tools/memory/src/memory/elfparser.py
index e6581c9..019d6da 100644
--- a/tools/memory/src/memory/elfparser.py
+++ b/tools/memory/src/memory/elfparser.py

@@ -6,10 +6,23 @@
 
 import re
 from dataclasses import asdict, dataclass
-from typing import BinaryIO
+from typing import (
+    Any,
+    BinaryIO,
+    Dict,
+    Iterable,
+    List,
+    Optional,
+    Tuple,
+    Union,
+)
 
 from elftools.elf.elffile import ELFFile
+from elftools.elf.sections import Section, SymbolTableSection
+from elftools.elf.segments import Segment
 
+from memory.image import Image, Region
+
 
 @dataclass(frozen=True)
 class TfaMemObject:
@@ -17,10 +30,10 @@
     start: int
     end: int
     size: int
-    children: list
+    children: List["TfaMemObject"]
 
 
-class TfaElfParser:
+class TfaElfParser(Image):
     """A class representing an ELF file built for TF-A.
 
     Provides a basic interface for reading the symbol table and other
@@ -28,53 +41,70 @@
     the contents an ELF file.
     """
 
-    def __init__(self, elf_file: BinaryIO):
-        self._segments = {}
-        self._memory_layout = {}
+    def __init__(self, elf_file: BinaryIO) -> None:
+        self._segments: Dict[int, TfaMemObject] = {}
+        self._memory_layout: Dict[str, Dict[str, int]] = {}
 
         elf = ELFFile(elf_file)
 
-        self._symbols = {
-            sym.name: sym.entry["st_value"]
-            for sym in elf.get_section_by_name(".symtab").iter_symbols()
+        symtab = elf.get_section_by_name(".symtab")
+        assert isinstance(symtab, SymbolTableSection)
+
+        self._symbols: Dict[str, int] = {
+            sym.name: sym.entry["st_value"] for sym in symtab.iter_symbols()
         }
 
         self.set_segment_section_map(elf.iter_segments(), elf.iter_sections())
         self._memory_layout = self.get_memory_layout_from_symbols()
-        self._start = elf["e_entry"]
+        self._start: int = elf["e_entry"]
+        self._size: int
+        self._free: int
         self._size, self._free = self._get_mem_usage()
-        self._end = self._start + self._size
+        self._end: int = self._start + self._size
+
+        self._footprint: Dict[str, Region] = {}
+
+        for mem, attrs in self._memory_layout.items():
+            self._footprint[mem] = Region(
+                attrs["start"],
+                attrs["end"],
+                attrs["length"],
+            )
 
     @property
-    def symbols(self):
-        return self._symbols.items()
+    def symbols(self) -> Dict[str, int]:
+        return self._symbols
 
     @staticmethod
-    def tfa_mem_obj_factory(elf_obj, name=None, children=None, segment=False):
+    def tfa_mem_obj_factory(
+        elf_obj: Union[Segment, Section],
+        name: Optional[str] = None,
+        children: Optional[List[TfaMemObject]] = None,
+    ) -> TfaMemObject:
         """Converts a pyelfparser Segment or Section to a TfaMemObject."""
         # Ensure each segment is provided a name since they aren't in the
         # program header.
-        assert not (
-            segment and name is None
-        ), "Attempting to make segment without a name"
-
-        if children is None:
-            children = list()
+        assert not (isinstance(elf_obj, Segment) and name is None), (
+            "Attempting to make segment without a name"
+        )
 
         # Segment and sections header keys have different prefixes.
-        vaddr = "p_vaddr" if segment else "sh_addr"
-        size = "p_memsz" if segment else "sh_size"
+        vaddr = "p_vaddr" if isinstance(elf_obj, Segment) else "sh_addr"
+        size = "p_memsz" if isinstance(elf_obj, Segment) else "sh_size"
+
+        name = name if isinstance(elf_obj, Segment) else elf_obj.name
+        assert name is not None
 
         # TODO figure out how to handle free space for sections and segments
         return TfaMemObject(
-            name if segment else elf_obj.name,
+            name,
             elf_obj[vaddr],
             elf_obj[vaddr] + elf_obj[size],
             elf_obj[size],
-            [] if not children else children,
+            children or [],
         )
 
-    def _get_mem_usage(self) -> (int, int):
+    def _get_mem_usage(self) -> Tuple[int, int]:
         """Get total size and free space for this component."""
         size = free = 0
 
@@ -89,36 +119,37 @@
 
         return size, free
 
-    def set_segment_section_map(self, segments, sections):
+    def set_segment_section_map(
+        self,
+        segments: Iterable[Segment],
+        sections: Iterable[Section],
+    ) -> None:
         """Set segment to section mappings."""
-        segments = list(
-            filter(lambda seg: seg["p_type"] == "PT_LOAD", segments)
-        )
+        segments = filter(lambda seg: seg["p_type"] == "PT_LOAD", segments)
+        segments_list = list(segments)
 
         for sec in sections:
-            for n, seg in enumerate(segments):
+            for n, seg in enumerate(segments_list):
                 if seg.section_in_segment(sec):
-                    if n not in self._segments.keys():
+                    if n not in self._segments:
                         self._segments[n] = self.tfa_mem_obj_factory(
-                            seg, name=f"{n:#02}", segment=True
+                            seg, name=f"{n:#02}"
                         )
 
-                    self._segments[n].children.append(
-                        self.tfa_mem_obj_factory(sec)
-                    )
+                    self._segments[n].children.append(self.tfa_mem_obj_factory(sec))
 
-    def get_memory_layout_from_symbols(self, expr=None) -> dict:
+    def get_memory_layout_from_symbols(self) -> Dict[str, Dict[str, int]]:
         """Retrieve information about the memory configuration from the symbol
         table.
         """
-        assert len(self._symbols), "Symbol table is empty!"
+        assert self._symbols, "Symbol table is empty!"
 
-        expr = r".*(.?R.M)_REGION.*(START|END|LENGTH)" if not expr else expr
+        expr = r".*(.?R.M)_REGION.*(START|END|LENGTH)"
         region_symbols = filter(lambda s: re.match(expr, s), self._symbols)
-        memory_layout = {}
+        memory_layout: Dict[str, Dict[str, int]] = {}
 
         for symbol in region_symbols:
-            region, _, attr = tuple(symbol.lower().strip("__").split("_"))
+            region, _, attr = symbol.lower().strip("__").split("_")
             if region not in memory_layout:
                 memory_layout[region] = {}
 
@@ -127,29 +158,30 @@
 
         return memory_layout
 
-    def get_seg_map_as_dict(self):
+    def get_seg_map_as_dict(self) -> List[Dict[str, Any]]:
         """Get a dictionary of segments and their section mappings."""
-        return [asdict(v) for k, v in self._segments.items()]
+        return [asdict(segment) for segment in self._segments.values()]
 
-    def get_memory_layout(self):
+    def get_memory_layout(self) -> Dict[str, Region]:
         """Get the total memory consumed by this module from the memory
         configuration.
-            {"rom": {"start": 0x0, "end": 0xFF, "length": ... }
         """
-        mem_dict = {}
+        mem_dict: Dict[str, Region] = {}
 
         for mem, attrs in self._memory_layout.items():
-            limit = attrs["start"] + attrs["length"]
-            mem_dict[mem] = {
-                "start": attrs["start"],
-                "limit": limit,
-                "size": attrs["end"] - attrs["start"],
-                "free": limit - attrs["end"],
-                "total": attrs["length"],
-            }
+            mem_dict[mem] = Region(
+                attrs["start"],
+                attrs["end"],
+                attrs["length"],
+            )
+
         return mem_dict
 
+    @property
+    def footprint(self) -> Dict[str, Region]:
+        return self._footprint
+
-    def get_mod_mem_usage_dict(self):
+    def get_mod_mem_usage_dict(self) -> Dict[str, int]:
         """Get the total memory consumed by the module, this combines the
         information in the memory configuration.
         """

diff --git a/tools/memory/src/memory/image.py b/tools/memory/src/memory/image.py
new file mode 100644
index 0000000..cda1d8a
--- /dev/null
+++ b/tools/memory/src/memory/image.py

@@ -0,0 +1,77 @@
+#
+# Copyright (c) 2023-2025, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+from abc import ABC, abstractmethod
+from dataclasses import dataclass
+from typing import Dict, Optional
+
+
+@dataclass
+class Region:
+    """Represents a memory region."""
+
+    start: Optional[int] = None
+    """Memory address of the beginning of the region."""
+
+    end: Optional[int] = None
+    """Memory address of the end of the region."""
+
+    length: Optional[int] = None
+    """Current size of the region in bytes."""
+
+    @property
+    def limit(self) -> Optional[int]:
+        """Largest possible end memory address of the region."""
+
+        if self.start is None:
+            return None
+
+        if self.length is None:
+            return None
+
+        return self.start + self.length
+
+    @property
+    def size(self) -> Optional[int]:
+        """Maximum possible size of the region in bytes."""
+
+        if self.end is None:
+            return None
+
+        if self.start is None:
+            return None
+
+        return self.end - self.start
+
+    @property
+    def free(self) -> Optional[int]:
+        """Number of bytes that the region is permitted to further expand."""
+
+        if self.limit is None:
+            return None
+
+        if self.end is None:
+            return None
+
+        return self.limit - self.end
+
+
+class Image(ABC):
+    """An image under analysis."""
+
+    @property
+    @abstractmethod
+    def footprint(self) -> Dict[str, Region]:
+        """Get metrics about the memory regions that this image occupies."""
+
+        pass
+
+    @property
+    @abstractmethod
+    def symbols(self) -> Dict[str, int]:
+        """Get a dictionary of the image's symbols and their corresponding addresses."""
+
+        pass

diff --git a/tools/memory/src/memory/mapparser.py b/tools/memory/src/memory/mapparser.py
index 1c28e71..24ee264 100644
--- a/tools/memory/src/memory/mapparser.py
+++ b/tools/memory/src/memory/mapparser.py

@@ -4,11 +4,14 @@
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
+from collections import defaultdict
 from re import match, search
-from typing import TextIO
+from typing import Dict, TextIO
 
+from memory.image import Image, Region
 
-class TfaMapParser:
+
+class TfaMapParser(Image):
     """A class representing a map file built for TF-A.
 
     Provides a basic interface for reading the symbol table. The constructor
@@ -16,17 +19,31 @@
     are supported at this stage.
     """
 
+    def __init__(self, map_file: TextIO) -> None:
+        self._symbols: Dict[str, int] = self.read_symbols(map_file)
+        assert self._symbols, "Symbol table is empty!"
+
+        self._footprint: Dict[str, Region] = defaultdict(Region)
+
-    def __init__(self, map_file: TextIO):
-        self._symbols = self.read_symbols(map_file)
+        expr = r".*(.?R.M)_REGION.*(START|END|LENGTH)"
+        for symbol in filter(lambda s: match(expr, s), self._symbols):
+            region, _, attr = symbol.lower().strip("__").split("_")
+
+            if attr == "start":
+                self._footprint[region].start = self._symbols[symbol]
+            elif attr == "end":
+                self._footprint[region].end = self._symbols[symbol]
+            if attr == "length":
+                self._footprint[region].length = self._symbols[symbol]
 
     @property
-    def symbols(self):
-        return self._symbols.items()
+    def symbols(self) -> Dict[str, int]:
+        return self._symbols
 
     @staticmethod
-    def read_symbols(file: TextIO, pattern: str = None) -> dict:
-        pattern = r"\b(0x\w*)\s*(\w*)\s=" if not pattern else pattern
-        symbols = {}
+    def read_symbols(file: TextIO) -> Dict[str, int]:
+        pattern = r"\b(0x\w*)\s*(\w*)\s="
+        symbols: Dict[str, int] = {}
 
         for line in file.readlines():
             match = search(pattern, line)
@@ -37,39 +54,6 @@
 
         return symbols
 
-    def get_memory_layout(self) -> dict:
-        """Get the total memory consumed by this module from the memory
-        configuration.
-            {"rom": {"start": 0x0, "end": 0xFF, "length": ... }
-        """
-        assert len(self._symbols), "Symbol table is empty!"
-        expr = r".*(.?R.M)_REGION.*(START|END|LENGTH)"
-        memory_layout = {}
-
-        region_symbols = filter(lambda s: match(expr, s), self._symbols)
-
-        for symbol in region_symbols:
-            region, _, attr = tuple(symbol.lower().strip("__").split("_"))
-            if region not in memory_layout:
-                memory_layout[region] = {}
-
-            memory_layout[region][attr] = self._symbols[symbol]
-
-            if "start" and "length" and "end" in memory_layout[region]:
-                memory_layout[region]["limit"] = (
-                    memory_layout[region]["start"]
-                    + memory_layout[region]["length"]
-                )
-                memory_layout[region]["free"] = (
-                    memory_layout[region]["limit"]
-                    - memory_layout[region]["end"]
-                )
-                memory_layout[region]["total"] = memory_layout[region][
-                    "length"
-                ]
-                memory_layout[region]["size"] = (
-                    memory_layout[region]["end"]
-                    - memory_layout[region]["start"]
-                )
-
-        return memory_layout
+    @property
+    def footprint(self) -> Dict[str, Region]:
+        return self._footprint

diff --git a/tools/memory/src/memory/memmap.py b/tools/memory/src/memory/memmap.py
index f46db8c..e02010b 100755
--- a/tools/memory/src/memory/memmap.py
+++ b/tools/memory/src/memory/memmap.py

@@ -1,19 +1,32 @@
-#!/usr/bin/env python3
-
 #
 # Copyright (c) 2023-2025, Arm Limited. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
+import re
+import shutil
+from dataclasses import dataclass
 from pathlib import Path
+from typing import Any, Dict, List, Optional
 
 import click
-from memory.buildparser import TfaBuildParser
+
+from memory.elfparser import TfaElfParser
+from memory.image import Image
+from memory.mapparser import TfaMapParser
 from memory.printer import TfaPrettyPrinter
+from memory.summary import MapParser
 
 
-@click.command()
+@dataclass
+class Context:
+    build_path: Optional[Path] = None
+    printer: Optional[TfaPrettyPrinter] = None
+
+
+@click.group()
+@click.pass_obj
 @click.option(
     "-r",
     "--root",
@@ -36,75 +49,171 @@
     type=click.Choice(["debug", "release"], case_sensitive=False),
 )
 @click.option(
-    "-f",
-    "--footprint",
+    "-w",
+    "--width",
+    type=int,
+    default=shutil.get_terminal_size().columns,
+    help="Column width for printing.",
+)
+@click.option(
+    "-d",
     is_flag=True,
-    show_default=True,
-    help="Generate a high level view of memory usage by memory types.",
+    default=False,
+    help="Display numbers in decimal base.",
 )
+def cli(
+    obj: Context,
+    root: Optional[Path],
+    platform: str,
+    build_type: str,
+    width: int,
+    d: bool,
+):
+    obj.build_path = root if root is not None else Path("build", platform, build_type)
+    click.echo(f"build-path: {obj.build_path.resolve()}")
+
+    obj.printer = TfaPrettyPrinter(columns=width, as_decimal=d)
+
+
+@cli.command()
+@click.pass_obj
 @click.option(
-    "-t",
-    "--tree",
+    "--no-elf-images",
     is_flag=True,
-    help="Generate a hierarchical view of the modules, segments and sections.",
+    help="Analyse the build's map files instead of ELF images.",
 )
+def footprint(obj: Context, no_elf_images: bool):
+    """Generate a high level view of memory usage by memory types."""
+
+    assert obj.build_path is not None
+    assert obj.printer is not None
+
+    elf_image_paths: List[Path] = (
+        [] if no_elf_images else list(obj.build_path.glob("**/*.elf"))
+    )
+
+    map_file_paths: List[Path] = (
+        [] if not no_elf_images else list(obj.build_path.glob("**/*.map"))
+    )
+
+    images: Dict[str, Image] = dict()
+
+    for elf_image_path in elf_image_paths:
+        with open(elf_image_path, "rb") as elf_image_io:
+            images[elf_image_path.stem.upper()] = TfaElfParser(elf_image_io)
+
+    for map_file_path in map_file_paths:
+        with open(map_file_path, "r") as map_file_io:
+            images[map_file_path.stem.upper()] = TfaMapParser(map_file_io)
+
+    obj.printer.print_footprint({k: v.footprint for k, v in images.items()})
+
+
+@cli.command()
+@click.pass_obj
 @click.option(
     "--depth",
     default=3,
+    show_default=True,
     help="Generate a virtual address map of important TF symbols.",
 )
-@click.option(
-    "-s",
-    "--symbols",
-    is_flag=True,
-    help="Generate a map of important TF symbols.",
-)
-@click.option("-w", "--width", type=int, envvar="COLUMNS")
-@click.option(
-    "-d",
-    is_flag=True,
-    default=False,
-    help="Display numbers in decimal base.",
-)
+def tree(obj: Context, depth: int):
+    """Generate a hierarchical view of the modules, segments and sections."""
+
+    assert obj.build_path is not None
+    assert obj.printer is not None
+
+    paths: List[Path] = list(obj.build_path.glob("**/*.elf"))
+    images: Dict[str, TfaElfParser] = dict()
+
+    for path in paths:
+        with open(path, "rb") as io:
+            images[path.stem] = TfaElfParser(io)
+
+    mtree: Dict[str, Dict[str, Any]] = {
+        k: {
+            "name": k,
+            **v.get_mod_mem_usage_dict(),
+            **{"children": v.get_seg_map_as_dict()},
+        }
+        for k, v in images.items()
+    }
+
+    obj.printer.print_mem_tree(mtree, list(mtree.keys()), depth=depth)
+
+
+@cli.command()
+@click.pass_obj
 @click.option(
     "--no-elf-images",
     is_flag=True,
     help="Analyse the build's map files instead of ELF images.",
 )
-def main(
-    root: Path,
-    platform: str,
-    build_type: str,
-    footprint: str,
-    tree: bool,
-    symbols: bool,
-    depth: int,
-    width: int,
-    d: bool,
-    no_elf_images: bool,
-):
-    build_path = root if root else Path("build/", platform, build_type)
-    click.echo(f"build-path: {build_path.resolve()}")
+def symbols(obj: Context, no_elf_images: bool):
+    """Generate a map of important TF symbols."""
+
+    assert obj.build_path is not None
+    assert obj.printer is not None
+
+    expr: str = (
+        r"(.*)(TEXT|BSS|RO|RODATA|STACKS|_OPS|PMF|XLAT|GOT|FCONF|RELA"
+        r"|R.M)(.*)(START|UNALIGNED|END)__$"
+    )
+
+    elf_image_paths: List[Path] = (
+        [] if no_elf_images else list(obj.build_path.glob("**/*.elf"))
+    )
+
+    map_file_paths: List[Path] = (
+        [] if not no_elf_images else list(obj.build_path.glob("**/*.map"))
+    )
+
+    images: Dict[str, Image] = dict()
+
+    for elf_image_path in elf_image_paths:
+        with open(elf_image_path, "rb") as elf_image_io:
+            images[elf_image_path.stem] = TfaElfParser(elf_image_io)
 
-    parser = TfaBuildParser(build_path, map_backend=no_elf_images)
-    printer = TfaPrettyPrinter(columns=width, as_decimal=d)
+    for map_file_path in map_file_paths:
+        with open(map_file_path, "r") as map_file_io:
+            images[map_file_path.stem] = TfaMapParser(map_file_io)
 
-    if footprint or not (tree or symbols):
-        printer.print_footprint(parser.get_mem_usage_dict())
+    symbols = {k: v.symbols for k, v in images.items()}
+    symbols = {
+        image: {
+            symbol: symbol_value
+            for symbol, symbol_value in symbols.items()
+            if re.match(expr, symbol)
+        }
+        for image, symbols in symbols.items()
+    }
 
-    if tree:
-        printer.print_mem_tree(
-            parser.get_mem_tree_as_dict(), parser.module_names, depth=depth
-        )
+    obj.printer.print_symbol_table(symbols, list(images.keys()))
+
+
+@cli.command()
+@click.option("-o", "--old", type=click.Path(exists=True))
+@click.option("-d", "--depth", type=int, default=2)
+@click.option("-e", "--exclude-fill")
+@click.option(
+    "-t",
+    "--type",
+    type=click.Choice(MapParser.export_formats, case_sensitive=False),
+    default="table",
+)
+@click.argument("file", type=click.Path(exists=True))
+def summary(file: Path, old: Optional[Path], depth: int, exclude_fill: bool, type: str):
+    """Summarize the sizes of translation units within the resulting binary"""
+    memap = MapParser()
+
+    if not memap.parse(file, old, exclude_fill):
+        exit(1)
+
+    memap.generate_output(type, depth)
+
 
-    if symbols:
-        expr = (
-            r"(.*)(TEXT|BSS|RO|RODATA|STACKS|_OPS|PMF|XLAT|GOT|FCONF|RELA"
-            r"|R.M)(.*)(START|UNALIGNED|END)__$"
-        )
-        printer.print_symbol_table(
-            parser.filter_symbols(parser.symbols, expr), parser.module_names
-        )
+def main():
+    cli(obj=Context())
 
 
 if __name__ == "__main__":

diff --git a/tools/memory/src/memory/printer.py b/tools/memory/src/memory/printer.py
index f797139..6debf53 100755
--- a/tools/memory/src/memory/printer.py
+++ b/tools/memory/src/memory/printer.py

@@ -4,10 +4,14 @@
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
+from typing import Any, Dict, List, Optional, Tuple
+
 from anytree import RenderTree
 from anytree.importer import DictImporter
 from prettytable import PrettyTable
 
+from memory.image import Region
+
 
 class TfaPrettyPrinter:
     """A class for printing the memory layout of ELF files.
@@ -17,19 +21,29 @@
     structured and consumed.
     """
 
-    def __init__(self, columns: int = None, as_decimal: bool = False):
-        self.term_size = columns if columns and columns > 120 else 120
-        self._tree = None
-        self._footprint = None
-        self._symbol_map = None
-        self.as_decimal = as_decimal
+    def __init__(self, columns: int, as_decimal: bool = False) -> None:
+        self.term_size: int = columns
+        self._tree: Optional[List[str]] = None
+        self._symbol_map: Optional[List[str]] = None
+        self.as_decimal: bool = as_decimal
 
-    def format_args(self, *args, width=10, fmt=None):
-        if not fmt and type(args[0]) is int:
+    def format_args(
+        self,
+        *args: Any,
+        width: int = 10,
+        fmt: Optional[str] = None,
+    ) -> List[str]:
+        if not fmt and isinstance(args[0], int):
             fmt = f">{width}x" if not self.as_decimal else f">{width}"
-        return [f"{arg:{fmt}}" if fmt else arg for arg in args]
+        return [f"{arg:{fmt}}" if fmt else str(arg) for arg in args]
 
-    def format_row(self, leading, *args, width=10, fmt=None):
+    def format_row(
+        self,
+        leading: str,
+        *args: Any,
+        width: int = 10,
+        fmt: Optional[str] = None,
+    ) -> str:
         formatted_args = self.format_args(*args, width=width, fmt=fmt)
         return leading + " ".join(formatted_args)
 
@@ -39,9 +53,9 @@
         section_name: str,
         rel_pos: int,
         columns: int,
-        width: int = None,
+        width: int,
         is_edge: bool = False,
-    ):
+    ) -> str:
         empty_col = "{:{}{}}"
 
         # Some symbols are longer than the column width, truncate them until
@@ -50,28 +64,26 @@
         if len_over > 0:
             section_name = section_name[len_over:-len_over]
 
-        sec_row = f"+{section_name:-^{width-1}}+"
+        sec_row = f"+{section_name:-^{width - 1}}+"
         sep, fill = ("+", "-") if is_edge else ("|", "")
 
         sec_row_l = empty_col.format(sep, fill + "<", width) * rel_pos
-        sec_row_r = empty_col.format(sep, fill + ">", width) * (
-            columns - rel_pos - 1
-        )
+        sec_row_r = empty_col.format(sep, fill + ">", width) * (columns - rel_pos - 1)
 
         return leading + sec_row_l + sec_row + sec_row_r
 
     def print_footprint(
-        self, app_mem_usage: dict, sort_key: str = None, fields: list = None
+        self,
+        app_mem_usage: Dict[str, Dict[str, Region]],
     ):
-        assert len(app_mem_usage), "Empty memory layout dictionary!"
-        if not fields:
-            fields = ["Component", "Start", "Limit", "Size", "Free", "Total"]
+        assert app_mem_usage, "Empty memory layout dictionary!"
 
-        sort_key = fields[0] if not sort_key else sort_key
+        fields = ["Component", "Start", "Limit", "Size", "Free", "Total"]
+        sort_key = fields[0]
 
         # Iterate through all the memory types, create a table for each
         # type, rows represent a single module.
-        for mem in sorted(set(k for _, v in app_mem_usage.items() for k in v)):
+        for mem in sorted({k for v in app_mem_usage.values() for k in v}):
             table = PrettyTable(
                 sortby=sort_key,
                 title=f"Memory Usage (bytes) [{mem.upper()}]",
@@ -79,13 +91,19 @@
             )
 
             for mod, vals in app_mem_usage.items():
-                if mem in vals.keys():
+                if mem in vals:
                     val = vals[mem]
                     table.add_row(
                         [
-                            mod.upper(),
+                            mod,
                             *self.format_args(
-                                *[val[k.lower()] for k in fields[1:]]
+                                *[
+                                    val.start if val.start is not None else "?",
+                                    val.limit if val.limit is not None else "?",
+                                    val.size if val.size is not None else "?",
+                                    val.free if val.free is not None else "?",
+                                    val.length if val.length is not None else "?",
+                                ]
                             ),
                         ]
                     )
@@ -93,31 +111,34 @@
 
     def print_symbol_table(
         self,
-        symbols: list,
-        modules: list,
+        symbol_table: Dict[str, Dict[str, int]],
+        modules: List[str],
         start: int = 12,
-    ):
-        assert len(symbols), "Empty symbol list!"
+    ) -> None:
+        assert len(symbol_table), "Empty symbol list!"
         modules = sorted(modules)
-        col_width = int((self.term_size - start) / len(modules))
+        col_width = (self.term_size - start) // len(modules)
         address_fixed_width = 11
 
-        num_fmt = (
-            f"0=#0{address_fixed_width}x" if not self.as_decimal else ">10"
-        )
+        num_fmt = f"0=#0{address_fixed_width}x" if not self.as_decimal else ">10"
 
         _symbol_map = [
-            " " * start
-            + "".join(self.format_args(*modules, fmt=f"^{col_width}"))
+            " " * start + "".join(self.format_args(*modules, fmt=f"^{col_width}"))
         ]
         last_addr = None
 
-        for i, (name, addr, mod) in enumerate(symbols):
+        symbols_list: List[Tuple[str, int, str]] = [
+            (name, addr, mod)
+            for mod, syms in symbol_table.items()
+            for name, addr in syms.items()
+        ]
+
+        symbols_list.sort(key=lambda x: (-x[1], x[0]), reverse=True)
+
+        for i, (name, addr, mod) in enumerate(symbols_list):
             # Do not print out an address twice if two symbols overlap,
             # for example, at the end of one region and start of another.
-            leading = (
-                f"{addr:{num_fmt}}" + " " if addr != last_addr else " " * start
-            )
+            leading = f"{addr:{num_fmt}}" + " " if addr != last_addr else " " * start
 
             _symbol_map.append(
                 self.map_elf_symbol(
@@ -125,28 +146,30 @@
                     name,
                     modules.index(mod),
                     len(modules),
-                    width=col_width,
-                    is_edge=(not i or i == len(symbols) - 1),
+                    col_width,
+                    is_edge=(i == 0 or i == len(symbols_list) - 1),
                 )
             )
 
             last_addr = addr
 
-        self._symbol_map = ["Memory Layout:"]
-        self._symbol_map += list(reversed(_symbol_map))
+        self._symbol_map = ["Memory Layout:"] + list(reversed(_symbol_map))
         print("\n".join(self._symbol_map))
 
     def print_mem_tree(
-        self, mem_map_dict, modules, depth=1, min_pad=12, node_right_pad=12
-    ):
+        self,
+        mem_map_dict: Dict[str, Any],
+        modules: List[str],
+        depth: int = 1,
+        min_pad: int = 12,
+        node_right_pad: int = 12,
+    ) -> None:
         # Start column should have some padding between itself and its data
         # values.
         anchor = min_pad + node_right_pad * (depth - 1)
         headers = ["start", "end", "size"]
 
-        self._tree = [
-            (f"{'name':<{anchor}}" + " ".join(f"{arg:>10}" for arg in headers))
-        ]
+        self._tree = [f"{'name':<{anchor}}" + " ".join(f"{arg:>10}" for arg in headers)]
 
         for mod in sorted(modules):
             root = DictImporter().import_(mem_map_dict[mod])

diff --git a/tools/memory/src/memory/summary.py b/tools/memory/src/memory/summary.py
new file mode 100644
index 0000000..b116caa
--- /dev/null
+++ b/tools/memory/src/memory/summary.py

@@ -0,0 +1,557 @@
+#
+# Copyright (c) 2016-2025, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+import json
+import os
+import re
+from collections import defaultdict
+from copy import deepcopy
+from os.path import (
+    abspath,
+    basename,
+    commonprefix,
+    dirname,
+    join,
+    relpath,
+    splitext,
+)
+from pathlib import Path
+from sys import stdout
+from typing import IO, Any, Dict, List, Optional, Pattern, Tuple, Union
+
+from jinja2 import FileSystemLoader, StrictUndefined
+from jinja2.environment import Environment
+from prettytable import HEADER, PrettyTable
+
+ModuleStats = Dict[str, int]
+Modules = Dict[str, ModuleStats]
+
+SECTIONS: Tuple[str, ...] = (".text", ".data", ".bss", ".heap", ".stack")
+MISC_FLASH_SECTIONS: Tuple[str, ...] = (".interrupts", ".flash_config")
+OTHER_SECTIONS: Tuple[str, ...] = (
+    ".interrupts_ram",
+    ".init",
+    ".ARM.extab",
+    ".ARM.exidx",
+    ".ARM.attributes",
+    ".eh_frame",
+    ".init_array",
+    ".fini_array",
+    ".jcr",
+    ".stab",
+    ".stabstr",
+    ".ARM.exidx",
+    ".ARM",
+)
+ALL_SECTIONS: Tuple[str, ...] = (
+    SECTIONS + OTHER_SECTIONS + MISC_FLASH_SECTIONS + ("unknown", "OUTPUT")
+)
+
+
+class Parser:
+    """Internal interface for parsing"""
+
+    _RE_OBJECT_FILE: Pattern[str] = re.compile(r"^(.+\/.+\.o(bj)?)$")
+    _RE_LIBRARY_OBJECT: Pattern[str] = re.compile(
+        r"((^.+" + r"" + r"lib.+\.a)\((.+\.o(bj)?)\))$"
+    )
+    _RE_STD_SECTION: Pattern[str] = re.compile(r"^\s+.*0x(\w{8,16})\s+0x(\w+)\s(.+)$")
+    _RE_FILL_SECTION: Pattern[str] = re.compile(
+        r"^\s*\*fill\*\s+0x(\w{8,16})\s+0x(\w+).*$"
+    )
+    _RE_TRANS_FILE: Pattern[str] = re.compile(r"^(.+\/|.+\.ltrans.o(bj)?)$")
+    _OBJECT_EXTENSIONS: Tuple[str, ...] = (".o", ".obj")
+
+    _modules: Modules
+    _fill: bool
+
+    def __init__(self, fill: bool = True):
+        self._modules: Modules = {}
+        self._fill = fill
+
+    def module_add(self, object_name: str, size: int, section: str):
+        """Adds a module or section to the list
+
+        Positional arguments:
+        object_name - name of the entry to add
+        size - the size of the module being added
+        section - the section the module contributes to
+        """
+        if (
+            not object_name
+            or not size
+            or not section
+            or (not self._fill and object_name == "[fill]")
+        ):
+            return
+
+        if object_name in self._modules:
+            self._modules[object_name].setdefault(section, 0)
+            self._modules[object_name][section] += size
+            return
+
+        obj_split = os.sep + basename(object_name)
+        for module_path, contents in self._modules.items():
+            if module_path.endswith(obj_split) or module_path == object_name:
+                contents.setdefault(section, 0)
+                contents[section] += size
+                return
+
+        new_module: ModuleStats = defaultdict(int)
+        new_module[section] = size
+        self._modules[object_name] = new_module
+
+    def module_replace(self, old_object: str, new_object: str):
+        """Replaces an object name with a new one"""
+        if old_object in self._modules:
+            self._modules[new_object] = self._modules.pop(old_object)
+
+    def check_new_section(self, line: str) -> Optional[str]:
+        """Check whether a new section in a map file has been detected
+
+        Positional arguments:
+        line - the line to check for a new section
+
+        return value - A section name, if a new section was found, None
+                       otherwise
+        """
+        line_s = line.strip()
+        for i in ALL_SECTIONS:
+            if line_s.startswith(i):
+                return i
+        if line.startswith("."):
+            return "unknown"
+        else:
+            return None
+
+    def parse_object_name(self, line: str) -> str:
+        """Parse a path to object file
+
+        Positional arguments:
+        line - the path to parse the object and module name from
+
+        return value - an object file name
+        """
+        if re.match(self._RE_TRANS_FILE, line):
+            return "[misc]"
+
+        test_re_file_name = re.match(self._RE_OBJECT_FILE, line)
+
+        if test_re_file_name:
+            object_name = test_re_file_name.group(1)
+
+            return object_name
+        else:
+            test_re_obj_name = re.match(self._RE_LIBRARY_OBJECT, line)
+
+            if test_re_obj_name:
+                return join(test_re_obj_name.group(2), test_re_obj_name.group(3))
+            else:
+                if not line.startswith("LONG") and not line.startswith("linker stubs"):
+                    print("Unknown object name found in GCC map file: %s" % line)
+                return "[misc]"
+
+    def parse_section(self, line: str) -> Tuple[str, int]:
+        """Parse data from a section of gcc map file
+
+        examples:
+                        0x00004308       0x7c ./BUILD/K64F/GCC_ARM/spi_api.o
+         .text          0x00000608      0x198 ./BUILD/K64F/HAL_CM4.o
+
+        Positional arguments:
+        line - the line to parse a section from
+        """
+        is_fill = re.match(self._RE_FILL_SECTION, line)
+        if is_fill:
+            o_name: str = "[fill]"
+            o_size: int = int(is_fill.group(2), 16)
+            return o_name, o_size
+
+        is_section = re.match(self._RE_STD_SECTION, line)
+        if is_section:
+            o_size: int = int(is_section.group(2), 16)
+            if o_size:
+                o_name: str = self.parse_object_name(is_section.group(3))
+                return o_name, o_size
+
+        return "", 0
+
+    def parse_mapfile(self, file_desc: IO[str]) -> Modules:
+        """Main logic to decode gcc map files
+
+        Positional arguments:
+        file_desc - a stream object to parse as a gcc map file
+        """
+        current_section: str = "unknown"
+
+        with file_desc as infile:
+            for line in infile:
+                if line.startswith("Linker script and memory map"):
+                    current_section = "unknown"
+                    break
+
+            for line in infile:
+                next_section = self.check_new_section(line)
+
+                if next_section == "OUTPUT":
+                    break
+                elif next_section:
+                    current_section = next_section
+
+                object_name, object_size = self.parse_section(line)
+                self.module_add(object_name, object_size, current_section)
+
+        def is_obj(name: str) -> bool:
+            return not name.startswith("[") or not name.endswith("]")
+
+        common_prefix: str = dirname(
+            commonprefix([o for o in self._modules.keys() if is_obj(o)])
+        )
+        new_modules: Modules = {}
+        for name, stats in self._modules.items():
+            if is_obj(name):
+                new_modules[relpath(name, common_prefix)] = stats
+            else:
+                new_modules[name] = stats
+        return new_modules
+
+
+class MapParser(object):
+    """An object that represents parsed results, parses the memory map files,
+    and writes out different file types of memory results
+    """
+
+    print_sections: Tuple[str, ...] = (".text", ".data", ".bss")
+    delta_sections: Tuple[str, ...] = (".text-delta", ".data-delta", ".bss-delta")
+
+    # sections to print info (generic for all toolchains)
+    sections: Tuple[str, ...] = SECTIONS
+    misc_flash_sections: Tuple[str, ...] = MISC_FLASH_SECTIONS
+    other_sections: Tuple[str, ...] = OTHER_SECTIONS
+
+    modules: Modules
+    old_modules: Modules
+    short_modules: Modules
+    mem_report: List[Dict[str, Union[str, ModuleStats]]]
+    mem_summary: Dict[str, int]
+    subtotal: Dict[str, int]
+    tc_name: Optional[str]
+
+    RAM_FORMAT_STR: str = "Total Static RAM memory (data + bss): {}({:+}) bytes\n"
+    ROM_FORMAT_STR: str = "Total Flash memory (text + data): {}({:+}) bytes\n"
+
+    def __init__(self):
+        # list of all modules and their sections
+        # full list - doesn't change with depth
+        self.modules: Modules = {}
+        self.old_modules = {}
+        # short version with specific depth
+        self.short_modules: Modules = {}
+
+        # Memory report (sections + summary)
+        self.mem_report: List[Dict[str, Union[str, ModuleStats]]] = []
+
+        # Memory summary
+        self.mem_summary: Dict[str, int] = {}
+
+        # Totals of ".text", ".data" and ".bss"
+        self.subtotal: Dict[str, int] = {}
+
+        # Name of the toolchain, for better headings
+        self.tc_name = None
+
+    def reduce_depth(self, depth: Optional[int]):
+        """
+        populates the short_modules attribute with a truncated module list
+
+        (1) depth = 1:
+        main.o
+        mbed-os
+
+        (2) depth = 2:
+        main.o
+        mbed-os/test.o
+        mbed-os/drivers
+
+        """
+        if depth == 0 or depth is None:
+            self.short_modules = deepcopy(self.modules)
+        else:
+            self.short_modules = dict()
+            for module_name, v in self.modules.items():
+                split_name = module_name.split(os.sep)
+                if split_name[0] == "":
+                    split_name = split_name[1:]
+                new_name = join(*split_name[:depth])
+                self.short_modules.setdefault(new_name, defaultdict(int))
+                for section_idx, value in v.items():
+                    self.short_modules[new_name][section_idx] += value
+                    delta_name = section_idx + "-delta"
+                    self.short_modules[new_name][delta_name] += value
+
+            for module_name, v in self.old_modules.items():
+                split_name = module_name.split(os.sep)
+                if split_name[0] == "":
+                    split_name = split_name[1:]
+                new_name = join(*split_name[:depth])
+                self.short_modules.setdefault(new_name, defaultdict(int))
+                for section_idx, value in v.items():
+                    delta_name = section_idx + "-delta"
+                    self.short_modules[new_name][delta_name] -= value
+
+    export_formats: List[str] = ["json", "html", "table"]
+
+    def generate_output(
+        self,
+        export_format: str,
+        depth: Optional[int],
+        file_output: Optional[str] = None,
+    ) -> Optional[bool]:
+        """Generates summary of memory map data
+
+        Positional arguments:
+        export_format - the format to dump
+
+        Keyword arguments:
+        file_desc - descriptor (either stdout or file)
+        depth - directory depth on report
+
+        Returns: generated string for the 'table' format, otherwise Nonef
+        """
+        if depth is None or depth > 0:
+            self.reduce_depth(depth)
+        self.compute_report()
+        try:
+            if file_output:
+                file_desc = open(file_output, "w")
+            else:
+                file_desc = stdout
+        except IOError as error:
+            print("I/O error({0}): {1}".format(error.errno, error.strerror))
+            return False
+
+        to_call = {
+            "json": self.generate_json,
+            "html": self.generate_html,
+            "table": self.generate_table,
+        }[export_format]
+        to_call(file_desc)
+
+        if file_desc is not stdout:
+            file_desc.close()
+
+    @staticmethod
+    def _move_up_tree(tree: Dict[str, Any], next_module: str) -> Dict[str, Any]:
+        tree.setdefault("children", [])
+        for child in tree["children"]:
+            if child["name"] == next_module:
+                return child
+
+        new_module = {"name": next_module, "value": 0, "delta": 0}
+        tree["children"].append(new_module)
+
+        return new_module
+
+    def generate_html(self, file_desc: IO[str]):
+        """Generate a json file from a memory map for D3
+
+        Positional arguments:
+        file_desc - the file to write out the final report to
+        """
+
+        tree_text = {"name": ".text", "value": 0, "delta": 0}
+        tree_bss = {"name": ".bss", "value": 0, "delta": 0}
+        tree_data = {"name": ".data", "value": 0, "delta": 0}
+
+        def accumulate(tree_root: Dict[str, Any], size_key: str, stats: ModuleStats):
+            parts = module_name.split(os.sep)
+
+            val = stats.get(size_key, 0)
+            tree_root["value"] += val
+            tree_root["delta"] += val
+
+            cur = tree_root
+            for part in parts:
+                cur = self._move_up_tree(cur, part)
+                cur["value"] += val
+                cur["delta"] += val
+
+        def subtract(tree_root: Dict[str, Any], size_key: str, stats: ModuleStats):
+            parts = module_name.split(os.sep)
+
+            cur = tree_root
+            cur["delta"] -= stats.get(size_key, 0)
+
+            for part in parts:
+                children = {c["name"]: c for c in cur.get("children", [])}
+                if part not in children:
+                    return
+
+                cur = children[part]
+                cur["delta"] -= stats.get(size_key, 0)
+
+        for module_name, dct in self.modules.items():
+            accumulate(tree_text, ".text", dct)
+            accumulate(tree_data, ".data", dct)
+            accumulate(tree_bss, ".bss", dct)
+
+        for module_name, dct in self.old_modules.items():
+            subtract(tree_text, ".text", dct)
+            subtract(tree_data, ".data", dct)
+            subtract(tree_bss, ".bss", dct)
+
+        jinja_loader = FileSystemLoader(dirname(abspath(__file__)))
+        jinja_environment = Environment(loader=jinja_loader, undefined=StrictUndefined)
+        template = jinja_environment.get_template("templates/summary-flamegraph.html")
+
+        name, _ = splitext(basename(file_desc.name))
+
+        if name.endswith("_map"):
+            name = name[:-4]
+        if self.tc_name:
+            name = f"{name} {self.tc_name}"
+
+        file_desc.write(
+            template.render(
+                {
+                    "name": name,
+                    "rom": json.dumps(
+                        {
+                            "name": "ROM",
+                            "value": tree_text["value"] + tree_data["value"],
+                            "delta": tree_text["delta"] + tree_data["delta"],
+                            "children": [tree_text, tree_data],
+                        }
+                    ),
+                    "ram": json.dumps(
+                        {
+                            "name": "RAM",
+                            "value": tree_bss["value"] + tree_data["value"],
+                            "delta": tree_bss["delta"] + tree_data["delta"],
+                            "children": [tree_bss, tree_data],
+                        }
+                    ),
+                }
+            )
+        )
+
+    def generate_json(self, file_desc: IO[str]):
+        """Generate a json file from a memory map
+
+        Positional arguments:
+        file_desc - the file to write out the final report to
+        """
+        file_desc.write(json.dumps(self.mem_report, indent=4))
+        file_desc.write("\n")
+
+    def generate_table(self, file_desc: IO[str]):
+        """Generate a table from a memory map
+
+        Returns: string of the generated table
+        """
+        # Create table
+        columns = ["Module"]
+        columns.extend(self.print_sections)
+
+        table = PrettyTable(columns, junction_char="|", hrules=HEADER)
+        table.align["Module"] = "l"
+
+        for col in self.print_sections:
+            table.align[col] = "r"
+
+        for i in sorted(self.short_modules):
+            row = [i]
+
+            for k in self.print_sections:
+                row.append(
+                    "{}({:+})".format(
+                        self.short_modules[i][k], self.short_modules[i][k + "-delta"]
+                    )
+                )
+
+            table.add_row(row)
+
+        subtotal_row = ["Subtotals"]
+        for k in self.print_sections:
+            subtotal_row.append(
+                "{}({:+})".format(self.subtotal[k], self.subtotal[k + "-delta"])
+            )
+
+        table.add_row(subtotal_row)
+
+        output = table.get_string()
+        output += "\n"
+
+        output += self.RAM_FORMAT_STR.format(
+            self.mem_summary["static_ram"], self.mem_summary["static_ram_delta"]
+        )
+        output += self.ROM_FORMAT_STR.format(
+            self.mem_summary["total_flash"], self.mem_summary["total_flash_delta"]
+        )
+        file_desc.write(output)
+
+    def compute_report(self):
+        """Generates summary of memory usage for main areas"""
+        self.subtotal = defaultdict(int)
+
+        for mod in self.modules.values():
+            for k in self.sections:
+                self.subtotal[k] += mod[k]
+                self.subtotal[k + "-delta"] += mod[k]
+
+        for mod in self.old_modules.values():
+            for k in self.sections:
+                self.subtotal[k + "-delta"] -= mod[k]
+
+        self.mem_summary = {
+            "static_ram": self.subtotal[".data"] + self.subtotal[".bss"],
+            "static_ram_delta": self.subtotal[".data-delta"]
+            + self.subtotal[".bss-delta"],
+            "total_flash": (self.subtotal[".text"] + self.subtotal[".data"]),
+            "total_flash_delta": self.subtotal[".text-delta"]
+            + self.subtotal[".data-delta"],
+        }
+
+        self.mem_report = []
+        if self.short_modules:
+            for name, sizes in sorted(self.short_modules.items()):
+                self.mem_report.append(
+                    {
+                        "module": name,
+                        "size": {
+                            k: sizes.get(k, 0)
+                            for k in (self.print_sections + self.delta_sections)
+                        },
+                    }
+                )
+
+        self.mem_report.append({"summary": self.mem_summary})
+
+    def parse(
+        self, mapfile: Path, oldfile: Optional[Path] = None, no_fill: bool = False
+    ) -> bool:
+        """Parse and decode map file depending on the toolchain
+
+        Positional arguments:
+        mapfile - the file name of the memory map file
+        toolchain - the toolchain used to create the file
+        """
+        try:
+            with open(mapfile, "r") as file_input:
+                self.modules = Parser(not no_fill).parse_mapfile(file_input)
+            try:
+                if oldfile is not None:
+                    with open(oldfile, "r") as old_input:
+                        self.old_modules = Parser(not no_fill).parse_mapfile(old_input)
+                else:
+                    self.old_modules = self.modules
+            except IOError:
+                self.old_modules = {}
+            return True
+
+        except IOError as error:
+            print("I/O error({0}): {1}".format(error.errno, error.strerror))
+            return False

diff --git a/tools/memory/src/memory/templates/summary-flamegraph.html b/tools/memory/src/memory/templates/summary-flamegraph.html
new file mode 100644
index 0000000..9ec8ecb
--- /dev/null
+++ b/tools/memory/src/memory/templates/summary-flamegraph.html

@@ -0,0 +1,110 @@
+<!DOCTYPE html>
+<html lang="en">
+
+<head>
+  <meta charset="utf-8">
+  <meta http-equiv="X-UA-Compatible" content="IE=edge">
+  <meta name="viewport" content="width=device-width, initial-scale=1">
+
+  <link rel="stylesheet" type="text/css" href="https://maxcdn.bootstrapcdn.com/bootstrap/3.3.7/css/bootstrap.min.css"
+    integrity="sha256-916EbMg70RQy9LHiGkXzG8hSg9EdNy97GazNG/aiY1w=" crossorigin="anonymous" />
+  <link rel="stylesheet" type="text/css"
+    href="https://cdn.jsdelivr.net/gh/spiermar/d3-flame-graph@1.0.4/dist/d3.flameGraph.min.css"
+    integrity="sha256-w762vSe6WGrkVZ7gEOpnn2Y+FSmAGlX77jYj7nhuCyY=" crossorigin="anonymous" />
+
+  <style>
+    /* Space out content a bit */
+    body {
+      padding-top: 20px;
+      padding-bottom: 20px;
+    }
+
+    /* Custom page header */
+    .header {
+      padding-bottom: 20px;
+      padding-right: 15px;
+      padding-left: 15px;
+      border-bottom: 1px solid #e5e5e5;
+    }
+
+    /* Make the masthead heading the same height as the navigation */
+    .header h3 {
+      margin-top: 0;
+      margin-bottom: 0;
+      line-height: 40px;
+    }
+  </style>
+
+  <title>{{name}} Memory Details</title>
+</head>
+
+<body>
+  <div class="container">
+    <div class="header clearfix">
+      <h3 class="text-muted">{{name}} Memory Details</h3>
+    </div>
+    <div id="chart-rom">
+    </div>
+    <hr />
+    <div id="chart-ram">
+    </div>
+    <hr />
+    <div id="details"></div>
+  </div>
+
+  <script type="text/javascript" src="https://cdnjs.cloudflare.com/ajax/libs/d3/4.10.0/d3.min.js"
+    integrity="sha256-r7j1FXNTvPzHR41+V71Jvej6fIq4v4Kzu5ee7J/RitM=" crossorigin="anonymous">
+    </script>
+  <script type="text/javascript" src="https://cdnjs.cloudflare.com/ajax/libs/d3-tip/0.7.1/d3-tip.min.js"
+    integrity="sha256-z0A2CQF8xxCKuOJsn4sJ5HBjxiHHRAfTX8hDF4RSN5s=" crossorigin="anonymous">
+    </script>
+  <script type="text/javascript"
+    src="https://cdn.jsdelivr.net/gh/spiermar/d3-flame-graph@1.0.4/dist/d3.flameGraph.min.js"
+    integrity="sha256-I1CkrWbmjv+GWjgbulJ4i0vbzdrDGfxqdye2qNlhG3Q=" crossorigin="anonymous">
+    </script>
+
+  <script type="text/javascript">
+    var tip = d3.tip()
+      .direction("s")
+      .offset([8, 0])
+      .attr('class', 'd3-flame-graph-tip')
+      .html(function (d) { return "module: " + d.data.name + ", bytes: " + d.data.value + ", delta: " + d.data.delta; });
+    var colorizer = function (d) {
+      if (d.data.delta > 0) {
+        ratio = (d.data.value - d.data.delta) / d.data.value;
+        green = ("0" + (Number(ratio * 0xFF | 0).toString(16))).slice(-2).toUpperCase();
+        blue = ("0" + (Number(ratio * 0xEE | 0).toString(16))).slice(-2).toUpperCase();
+        console.log(d.data.name, green, blue);
+        return "#EE" + green + blue
+      } else if (d.data.delta < 0) {
+        ratio = (d.data.value + d.data.delta) / d.data.value;
+        green = ("0" + (Number(ratio * 0xFF | 0).toString(16))).slice(-2).toUpperCase();
+        red = ("0" + (Number(ratio * 0xFF | 0).toString(16))).slice(-2).toUpperCase();
+        console.log(d.data.name, red, green);
+        return "#" + red + green + "EE";
+      } else {
+        return "#FFFFEE";
+      }
+    }
+    var flameGraph_rom = d3.flameGraph()
+      .transitionDuration(250)
+      .transitionEase(d3.easeCubic)
+      .sort(true)
+      .color(colorizer)
+      .tooltip(tip);
+    var flameGraph_ram = d3.flameGraph()
+      .transitionDuration(250)
+      .transitionEase(d3.easeCubic)
+      .sort(true)
+      .color(colorizer)
+      .tooltip(tip);
+    var rom_elem = d3.select("#chart-rom");
+    flameGraph_rom.width(rom_elem.node().getBoundingClientRect().width);
+    rom_elem.datum({{ rom }}).call(flameGraph_rom);
+    var ram_elem = d3.select("#chart-ram");
+    flameGraph_ram.width(ram_elem.node().getBoundingClientRect().width);
+    ram_elem.datum({{ ram }}).call(flameGraph_ram);
+  </script>
+</body>
+
+</html>
commit	1b98861a780a43352f1ea8aaaa2ec06e89855e28	[log] [tgz]
author	Manish V Badarkhe <manish.badarkhe@arm.com>	Fri Jun 20 07:23:29 2025 +0000
committer	TrustedFirmware Code Review <review@review.trustedfirmware.org>	Fri Jun 20 07:23:29 2025 +0000
tree	9c3e61cc13356ff04bc70795d5863d708846b61a
parent	68461b13c891e2f2ac4d639970b8b4384cb5cde2 [diff]
parent	5b940ec3ee0319d8c06b4522d038d665eb06f892 [diff]