amlogic: Fix prefixes in the helpers file
The code is the common directory is now generic, no need to have the SoC
prefix hardcoded in the function names.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Ied3a5e506b9abd4c2d6f893bafef50019bff24f1
diff --git a/plat/amlogic/gxl/gxl_common.c b/plat/amlogic/gxl/gxl_common.c
index e3bd604..cede8d8 100644
--- a/plat/amlogic/gxl/gxl_common.c
+++ b/plat/amlogic/gxl/gxl_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -107,9 +107,9 @@
void gxbb_console_init(void)
{
- int rc = console_meson_register(GXBB_UART0_AO_BASE,
- GXBB_UART0_AO_CLK_IN_HZ,
- GXBB_UART_BAUDRATE,
+ int rc = console_meson_register(AML_UART0_AO_BASE,
+ AML_UART0_AO_CLK_IN_HZ,
+ AML_UART_BAUDRATE,
&gxbb_console);
if (rc == 0) {
/*
diff --git a/plat/amlogic/gxl/gxl_def.h b/plat/amlogic/gxl/gxl_def.h
index 089fa8d..ced811d 100644
--- a/plat/amlogic/gxl/gxl_def.h
+++ b/plat/amlogic/gxl/gxl_def.h
@@ -79,9 +79,9 @@
/*******************************************************************************
* UART definitions
******************************************************************************/
-#define GXBB_UART0_AO_BASE UL(0xC81004C0)
-#define GXBB_UART0_AO_CLK_IN_HZ GXBB_OSC24M_CLK_IN_HZ
-#define GXBB_UART_BAUDRATE U(115200)
+#define AML_UART0_AO_BASE UL(0xC81004C0)
+#define AML_UART0_AO_CLK_IN_HZ GXBB_OSC24M_CLK_IN_HZ
+#define AML_UART_BAUDRATE U(115200)
/*******************************************************************************
* Memory-mapped I/O Registers
diff --git a/plat/amlogic/gxl/gxl_pm.c b/plat/amlogic/gxl/gxl_pm.c
index 544ae20..d6071bf 100644
--- a/plat/amlogic/gxl/gxl_pm.c
+++ b/plat/amlogic/gxl/gxl_pm.c
@@ -29,7 +29,7 @@
static void gxl_pm_set_reset_addr(u_register_t mpidr, uint64_t value)
{
- unsigned int core = plat_gxbb_calc_core_pos(mpidr);
+ unsigned int core = plat_calc_core_pos(mpidr);
uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4);
mmio_write_64(cpu_mailbox_addr, value);
@@ -37,7 +37,7 @@
static void gxl_pm_reset(u_register_t mpidr)
{
- unsigned int core = plat_gxbb_calc_core_pos(mpidr);
+ unsigned int core = plat_calc_core_pos(mpidr);
uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4) + 8;
mmio_write_32(cpu_mailbox_addr, 0);
@@ -99,10 +99,10 @@
static int32_t gxbb_pwr_domain_on(u_register_t mpidr)
{
- unsigned int core = plat_gxbb_calc_core_pos(mpidr);
+ unsigned int core = plat_calc_core_pos(mpidr);
/* CPU0 can't be turned OFF, emulate it with a WFE loop */
- if (core == GXBB_PRIMARY_CPU) {
+ if (core == AML_PRIMARY_CPU) {
VERBOSE("BL31: Releasing CPU0 from wait loop...\n");
gxbb_cpu0_go = 1;
@@ -127,12 +127,12 @@
static void gxbb_pwr_domain_on_finish(const psci_power_state_t *target_state)
{
- unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1());
+ unsigned int core = plat_calc_core_pos(read_mpidr_el1());
assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] ==
PLAT_LOCAL_STATE_OFF);
- if (core == GXBB_PRIMARY_CPU) {
+ if (core == AML_PRIMARY_CPU) {
gxbb_cpu0_go = 0;
flush_dcache_range((uintptr_t)&gxbb_cpu0_go,
sizeof(gxbb_cpu0_go));
@@ -147,12 +147,12 @@
static void gxbb_pwr_domain_off(const psci_power_state_t *target_state)
{
u_register_t mpidr = read_mpidr_el1();
- unsigned int core = plat_gxbb_calc_core_pos(mpidr);
+ unsigned int core = plat_calc_core_pos(mpidr);
gicv2_cpuif_disable();
/* CPU0 can't be turned OFF, emulate it with a WFE loop */
- if (core == GXBB_PRIMARY_CPU)
+ if (core == AML_PRIMARY_CPU)
return;
scpi_set_css_power_state(mpidr,
@@ -163,10 +163,10 @@
*target_state)
{
u_register_t mpidr = read_mpidr_el1();
- unsigned int core = plat_gxbb_calc_core_pos(mpidr);
+ unsigned int core = plat_calc_core_pos(mpidr);
/* CPU0 can't be turned OFF, emulate it with a WFE loop */
- if (core == GXBB_PRIMARY_CPU) {
+ if (core == AML_PRIMARY_CPU) {
VERBOSE("BL31: CPU0 entering wait loop...\n");
while (gxbb_cpu0_go == 0)
diff --git a/plat/amlogic/gxl/include/platform_def.h b/plat/amlogic/gxl/include/platform_def.h
index b32ec56..80b0d64 100644
--- a/plat/amlogic/gxl/include/platform_def.h
+++ b/plat/amlogic/gxl/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -25,7 +25,7 @@
#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT
-#define GXBB_PRIMARY_CPU U(0)
+#define AML_PRIMARY_CPU U(0)
#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \