diff --git a/plat/amlogic/gxbb/gxbb_common.c b/plat/amlogic/gxbb/gxbb_common.c
index eb688f7..06ff008 100644
--- a/plat/amlogic/gxbb/gxbb_common.c
+++ b/plat/amlogic/gxbb/gxbb_common.c
@@ -109,9 +109,9 @@
 
 void gxbb_console_init(void)
 {
-	int rc = console_meson_register(GXBB_UART0_AO_BASE,
-					GXBB_UART0_AO_CLK_IN_HZ,
-					GXBB_UART_BAUDRATE,
+	int rc = console_meson_register(AML_UART0_AO_BASE,
+					AML_UART0_AO_CLK_IN_HZ,
+					AML_UART_BAUDRATE,
 					&gxbb_console);
 	if (rc == 0) {
 		/*
diff --git a/plat/amlogic/gxbb/gxbb_def.h b/plat/amlogic/gxbb/gxbb_def.h
index 3e27097..e43bb1d 100644
--- a/plat/amlogic/gxbb/gxbb_def.h
+++ b/plat/amlogic/gxbb/gxbb_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -75,9 +75,9 @@
 /*******************************************************************************
  * UART definitions
  ******************************************************************************/
-#define GXBB_UART0_AO_BASE			UL(0xC81004C0)
-#define GXBB_UART0_AO_CLK_IN_HZ			GXBB_OSC24M_CLK_IN_HZ
-#define GXBB_UART_BAUDRATE			U(115200)
+#define AML_UART0_AO_BASE			UL(0xC81004C0)
+#define AML_UART0_AO_CLK_IN_HZ			GXBB_OSC24M_CLK_IN_HZ
+#define AML_UART_BAUDRATE			U(115200)
 
 /*******************************************************************************
  * Memory-mapped I/O Registers
diff --git a/plat/amlogic/gxbb/gxbb_pm.c b/plat/amlogic/gxbb/gxbb_pm.c
index 4b0d755..0d542a5 100644
--- a/plat/amlogic/gxbb/gxbb_pm.c
+++ b/plat/amlogic/gxbb/gxbb_pm.c
@@ -31,7 +31,7 @@
 
 static void gxbb_program_mailbox(u_register_t mpidr, uint64_t value)
 {
-	unsigned int core = plat_gxbb_calc_core_pos(mpidr);
+	unsigned int core = plat_calc_core_pos(mpidr);
 	uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4);
 
 	mmio_write_64(cpu_mailbox_addr, value);
@@ -86,10 +86,10 @@
 
 static int32_t gxbb_pwr_domain_on(u_register_t mpidr)
 {
-	unsigned int core = plat_gxbb_calc_core_pos(mpidr);
+	unsigned int core = plat_calc_core_pos(mpidr);
 
 	/* CPU0 can't be turned OFF, emulate it with a WFE loop */
-	if (core == GXBB_PRIMARY_CPU) {
+	if (core == AML_PRIMARY_CPU) {
 		VERBOSE("BL31: Releasing CPU0 from wait loop...\n");
 
 		gxbb_cpu0_go = 1;
@@ -113,12 +113,12 @@
 
 static void gxbb_pwr_domain_on_finish(const psci_power_state_t *target_state)
 {
-	unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1());
+	unsigned int core = plat_calc_core_pos(read_mpidr_el1());
 
 	assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] ==
 					PLAT_LOCAL_STATE_OFF);
 
-	if (core == GXBB_PRIMARY_CPU) {
+	if (core == AML_PRIMARY_CPU) {
 		gxbb_cpu0_go = 0;
 		flush_dcache_range((uintptr_t)&gxbb_cpu0_go, sizeof(gxbb_cpu0_go));
 		dsb();
@@ -132,7 +132,7 @@
 static void gxbb_pwr_domain_off(const psci_power_state_t *target_state)
 {
 	u_register_t mpidr = read_mpidr_el1();
-	unsigned int core = plat_gxbb_calc_core_pos(mpidr);
+	unsigned int core = plat_calc_core_pos(mpidr);
 	uintptr_t addr = GXBB_PSCI_MAILBOX_BASE + 8 + (core << 4);
 
 	mmio_write_32(addr, 0xFFFFFFFF);
@@ -141,7 +141,7 @@
 	gicv2_cpuif_disable();
 
 	/* CPU0 can't be turned OFF, emulate it with a WFE loop */
-	if (core == GXBB_PRIMARY_CPU)
+	if (core == AML_PRIMARY_CPU)
 		return;
 
 	scpi_set_css_power_state(mpidr,
@@ -151,10 +151,10 @@
 static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t
 						 *target_state)
 {
-	unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1());
+	unsigned int core = plat_calc_core_pos(read_mpidr_el1());
 
 	/* CPU0 can't be turned OFF, emulate it with a WFE loop */
-	if (core == GXBB_PRIMARY_CPU) {
+	if (core == AML_PRIMARY_CPU) {
 		VERBOSE("BL31: CPU0 entering wait loop...\n");
 
 		while (gxbb_cpu0_go == 0)
diff --git a/plat/amlogic/gxbb/include/platform_def.h b/plat/amlogic/gxbb/include/platform_def.h
index da4aedd..bd6ce32 100644
--- a/plat/amlogic/gxbb/include/platform_def.h
+++ b/plat/amlogic/gxbb/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -25,7 +25,7 @@
 #define PLATFORM_CLUSTER0_CORE_COUNT	PLATFORM_MAX_CPUS_PER_CLUSTER
 #define PLATFORM_CORE_COUNT		PLATFORM_CLUSTER0_CORE_COUNT
 
-#define GXBB_PRIMARY_CPU		U(0)
+#define AML_PRIMARY_CPU			U(0)
 
 #define PLAT_MAX_PWR_LVL		MPIDR_AFFLVL1
 #define PLAT_NUM_PWR_DOMAINS		(PLATFORM_CLUSTER_COUNT + \