Merge changes from topic "add_s32cc_fxosc_clk" into integration
* changes:
feat(s32g274a): enable BL2 early clocks
feat(nxp-clk): implement set_rate for oscillators
feat(nxp-clk): add oscillator clock objects
feat(nxp-clk): add minimal set of S32CC clock ids
diff --git a/changelog.yaml b/changelog.yaml
index 4d84fb7..6a235cd 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -1416,6 +1416,9 @@
- title: Certificate Creation Tool
scope: cert-create
+ - title: Firmware Encryption Tool
+ scope: encrypt-fw
+
- title: Memory Mapping Tool
scope: memmap
diff --git a/docs/design_documents/rse.rst b/docs/design_documents/rse.rst
index 7296a45..e0e0fb3 100644
--- a/docs/design_documents/rse.rst
+++ b/docs/design_documents/rse.rst
@@ -482,74 +482,101 @@
INFO: Get platform token start
INFO: Get platform token succeeds, len: 1086
INFO: Platform attestation token:
- INFO: d2 84 44 a1 01 38 22 a0 59 03 d1 a9 0a 58 20 00
- INFO: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
- INFO: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 19
- INFO: 01 00 58 21 01 cb 8c 79 f7 a0 0a 6c ce 12 66 f8
- INFO: 64 45 48 42 0e c5 10 bf 84 ee 22 18 b9 8f 11 04
- INFO: c7 22 31 9d fb 19 09 5c 58 20 aa aa aa aa aa aa
- INFO: aa aa bb bb bb bb bb bb bb bb cc cc cc cc cc cc
- INFO: cc cc dd dd dd dd dd dd dd dd 19 09 5b 19 30 00
- INFO: 19 09 5f 89 a4 05 58 20 bf e6 d8 6f 88 26 f4 ff
- INFO: 97 fb 96 c4 e6 fb c4 99 3e 46 19 fc 56 5d a2 6a
- INFO: df 34 c3 29 48 9a dc 38 04 67 31 2e 36 2e 30 2b
- INFO: 30 01 64 52 54 5f 30 02 58 20 90 27 f2 46 ab 31
- INFO: 85 36 46 c4 d7 c6 60 ed 31 0d 3c f0 14 de f0 6c
- INFO: 24 0b de b6 7a 84 fc 3f 5b b7 a4 05 58 20 b3 60
- INFO: ca f5 c9 8c 6b 94 2a 48 82 fa 9d 48 23 ef b1 66
- INFO: a9 ef 6a 6e 4a a3 7c 19 19 ed 1f cc c0 49 04 67
- INFO: 30 2e 30 2e 30 2b 30 01 64 52 54 5f 31 02 58 20
- INFO: 52 13 15 d4 9d b2 cf 54 e4 99 37 44 40 68 f0 70
- INFO: 7d 73 64 ae f7 08 14 b0 f7 82 ad c6 17 db a3 91
- INFO: a4 05 58 20 bf e6 d8 6f 88 26 f4 ff 97 fb 96 c4
- INFO: e6 fb c4 99 3e 46 19 fc 56 5d a2 6a df 34 c3 29
- INFO: 48 9a dc 38 04 67 31 2e 35 2e 30 2b 30 01 64 52
- INFO: 54 5f 32 02 58 20 8e 5d 64 7e 6f 6c c6 6f d4 4f
- INFO: 54 b6 06 e5 47 9a cc 1b f3 7f ce 87 38 49 c5 92
- INFO: d8 2f 85 2e 85 42 a4 05 58 20 bf e6 d8 6f 88 26
- INFO: f4 ff 97 fb 96 c4 e6 fb c4 99 3e 46 19 fc 56 5d
- INFO: a2 6a df 34 c3 29 48 9a dc 38 04 67 31 2e 35 2e
- INFO: 30 2b 30 01 60 02 58 20 b8 01 65 a7 78 8b c6 59
- INFO: 42 8d 33 10 85 d1 49 0a dc 9e c3 ee df 85 1b d2
- INFO: f0 73 73 6a 0c 07 11 b8 a4 05 58 20 b0 f3 82 09
- INFO: 12 97 d8 3a 37 7a 72 47 1b ec 32 73 e9 92 32 e2
- INFO: 49 59 f6 5e 8b 4a 4a 46 d8 22 9a da 04 60 01 6a
- INFO: 46 57 5f 43 4f 4e 46 49 47 00 02 58 20 21 9e a0
- INFO: 13 82 e6 d7 97 5a 11 13 a3 5f 45 39 68 b1 d9 a3
- INFO: ea 6a ab 84 23 3b 8c 06 16 98 20 ba b9 a4 05 58
- INFO: 20 b0 f3 82 09 12 97 d8 3a 37 7a 72 47 1b ec 32
- INFO: 73 e9 92 32 e2 49 59 f6 5e 8b 4a 4a 46 d8 22 9a
- INFO: da 04 60 01 6d 54 42 5f 46 57 5f 43 4f 4e 46 49
- INFO: 47 00 02 58 20 41 39 f6 c2 10 84 53 c5 17 ae 9a
- INFO: e5 be c1 20 7b cc 24 24 f3 9d 20 a8 fb c7 b3 10
- INFO: e3 ee af 1b 05 a4 05 58 20 b0 f3 82 09 12 97 d8
- INFO: 3a 37 7a 72 47 1b ec 32 73 e9 92 32 e2 49 59 f6
- INFO: 5e 8b 4a 4a 46 d8 22 9a da 04 60 01 65 42 4c 5f
- INFO: 32 00 02 58 20 5c 96 20 e1 e3 3b 0f 2c eb c1 8e
- INFO: 1a 02 a6 65 86 dd 34 97 a7 4c 98 13 bf 74 14 45
- INFO: 2d 30 28 05 c3 a4 05 58 20 b0 f3 82 09 12 97 d8
- INFO: 3a 37 7a 72 47 1b ec 32 73 e9 92 32 e2 49 59 f6
- INFO: 5e 8b 4a 4a 46 d8 22 9a da 04 60 01 6e 53 45 43
- INFO: 55 52 45 5f 52 54 5f 45 4c 33 00 02 58 20 f6 fb
- INFO: 62 99 a5 0c df db 02 0b 72 5b 1c 0b 63 6e 94 ee
- INFO: 66 50 56 3a 29 9c cb 38 f0 ec 59 99 d4 2e a4 05
- INFO: 58 20 b0 f3 82 09 12 97 d8 3a 37 7a 72 47 1b ec
- INFO: 32 73 e9 92 32 e2 49 59 f6 5e 8b 4a 4a 46 d8 22
- INFO: 9a da 04 60 01 6a 48 57 5f 43 4f 4e 46 49 47 00
- INFO: 02 58 20 98 5d 87 21 84 06 33 9d c3 1f 91 f5 68
- INFO: 8d a0 5a f0 d7 7e 20 51 ce 3b f2 a5 c3 05 2e 3c
- INFO: 8b 52 31 19 01 09 78 1c 68 74 74 70 3a 2f 2f 61
- INFO: 72 6d 2e 63 6f 6d 2f 43 43 41 2d 53 53 44 2f 31
- INFO: 2e 30 2e 30 19 09 62 71 6e 6f 74 2d 68 61 73 68
- INFO: 2d 65 78 74 65 6e 64 65 64 19 09 61 44 ef be ad
- INFO: de 19 09 60 77 77 77 77 2e 74 72 75 73 74 65 64
- INFO: 66 69 72 6d 77 61 72 65 2e 6f 72 67 58 60 29 4e
- INFO: 4a d3 98 1e 3b 70 9f b6 66 ed 47 33 0e 99 f0 b1
- INFO: c3 f2 bc b2 1d b0 ae 90 0c c4 82 ff a2 6f ae 45
- INFO: f6 87 09 4a 09 21 77 ec 36 1c 53 b8 a7 9b 8e f7
- INFO: 27 eb 7a 09 da 6f fb bf cb fd b3 e5 e9 36 91 b1
- INFO: 92 13 c1 30 16 b4 5c 49 5e c0 c1 b9 01 5c 88 2c
- INFO: f8 2f 3e a4 a2 6d e4 9d 31 6a 06 f7 a7 73
+ INFO: d2 84 44 a1 01 38 22 a0 59 05 7a a9 19 01 09 78
+ INFO: 1c 68 74 74 70 3a 2f 2f 61 72 6d 2e 63 6f 6d 2f
+ INFO: 43 43 41 2d 53 53 44 2f 31 2e 30 2e 30 0a 58 20
+ INFO: b5 97 3c b6 8b aa 9f c5 55 58 78 6b 7e c6 7f 69
+ INFO: e4 0d f5 ba 5a a9 21 cd 0c 27 f4 05 87 a0 11 ea
+ INFO: 19 09 5c 58 20 7f 45 4c 46 02 01 01 00 00 00 00
+ INFO: 00 00 00 00 00 03 00 3e 00 01 00 00 00 50 58 00
+ INFO: 00 00 00 00 00 19 01 00 58 21 01 07 06 05 04 03
+ INFO: 02 01 00 0f 0e 0d 0c 0b 0a 09 08 17 16 15 14 13
+ INFO: 12 11 10 1f 1e 1d 1c 1b 1a 19 18 19 09 61 44 cf
+ INFO: cf cf cf 19 09 5b 19 30 03 19 09 62 67 73 68 61
+ INFO: 2d 32 35 36 19 09 60 78 3a 68 74 74 70 73 3a 2f
+ INFO: 2f 76 65 72 61 69 73 6f 6e 2e 65 78 61 6d 70 6c
+ INFO: 65 2f 2e 77 65 6c 6c 2d 6b 6e 6f 77 6e 2f 76 65
+ INFO: 72 61 69 73 6f 6e 2f 76 65 72 69 66 69 63 61 74
+ INFO: 69 6f 6e 19 09 5f 8d a4 01 69 52 53 45 5f 42 4c
+ INFO: 31 5f 32 05 58 20 53 78 79 63 07 53 5d f3 ec 8d
+ INFO: 8b 15 a2 e2 dc 56 41 41 9c 3d 30 60 cf e3 22 38
+ INFO: c0 fa 97 3f 7a a3 02 58 20 9a 27 1f 2a 91 6b 0b
+ INFO: 6e e6 ce cb 24 26 f0 b3 20 6e f0 74 57 8b e5 5d
+ INFO: 9b c9 4f 6f 3f e3 ab 86 aa 06 67 73 68 61 2d 32
+ INFO: 35 36 a4 01 67 52 53 45 5f 42 4c 32 05 58 20 53
+ INFO: 78 79 63 07 53 5d f3 ec 8d 8b 15 a2 e2 dc 56 41
+ INFO: 41 9c 3d 30 60 cf e3 22 38 c0 fa 97 3f 7a a3 02
+ INFO: 58 20 53 c2 34 e5 e8 47 2b 6a c5 1c 1a e1 ca b3
+ INFO: fe 06 fa d0 53 be b8 eb fd 89 77 b0 10 65 5b fd
+ INFO: d3 c3 06 67 73 68 61 2d 32 35 36 a4 01 65 52 53
+ INFO: 45 5f 53 05 58 20 53 78 79 63 07 53 5d f3 ec 8d
+ INFO: 8b 15 a2 e2 dc 56 41 41 9c 3d 30 60 cf e3 22 38
+ INFO: c0 fa 97 3f 7a a3 02 58 20 11 21 cf cc d5 91 3f
+ INFO: 0a 63 fe c4 0a 6f fd 44 ea 64 f9 dc 13 5c 66 63
+ INFO: 4b a0 01 d1 0b cf 43 02 a2 06 67 73 68 61 2d 32
+ INFO: 35 36 a4 01 66 41 50 5f 42 4c 31 05 58 20 53 78
+ INFO: 79 63 07 53 5d f3 ec 8d 8b 15 a2 e2 dc 56 41 41
+ INFO: 9c 3d 30 60 cf e3 22 38 c0 fa 97 3f 7a a3 02 58
+ INFO: 20 15 71 b5 ec 78 bd 68 51 2b f7 83 0b b6 a2 a4
+ INFO: 4b 20 47 c7 df 57 bc e7 9e b8 a1 c0 e5 be a0 a5
+ INFO: 01 06 67 73 68 61 2d 32 35 36 a4 01 66 41 50 5f
+ INFO: 42 4c 32 05 58 20 53 78 79 63 07 53 5d f3 ec 8d
+ INFO: 8b 15 a2 e2 dc 56 41 41 9c 3d 30 60 cf e3 22 38
+ INFO: c0 fa 97 3f 7a a3 02 58 20 10 15 9b af 26 2b 43
+ INFO: a9 2d 95 db 59 da e1 f7 2c 64 51 27 30 16 61 e0
+ INFO: a3 ce 4e 38 b2 95 a9 7c 58 06 67 73 68 61 2d 32
+ INFO: 35 36 a4 01 67 53 43 50 5f 42 4c 31 05 58 20 53
+ INFO: 78 79 63 07 53 5d f3 ec 8d 8b 15 a2 e2 dc 56 41
+ INFO: 41 9c 3d 30 60 cf e3 22 38 c0 fa 97 3f 7a a3 02
+ INFO: 58 20 10 12 2e 85 6b 3f cd 49 f0 63 63 63 17 47
+ INFO: 61 49 cb 73 0a 1a a1 cf aa d8 18 55 2b 72 f5 6d
+ INFO: 6f 68 06 67 73 68 61 2d 32 35 36 a4 01 67 53 43
+ INFO: 50 5f 42 4c 32 05 58 20 f1 4b 49 87 90 4b cb 58
+ INFO: 14 e4 45 9a 05 7e d4 d2 0f 58 a6 33 15 22 88 a7
+ INFO: 61 21 4d cd 28 78 0b 56 02 58 20 aa 67 a1 69 b0
+ INFO: bb a2 17 aa 0a a8 8a 65 34 69 20 c8 4c 42 44 7c
+ INFO: 36 ba 5f 7e a6 5f 42 2c 1f e5 d8 06 67 73 68 61
+ INFO: 2d 32 35 36 a4 01 67 41 50 5f 42 4c 33 31 05 58
+ INFO: 20 53 78 79 63 07 53 5d f3 ec 8d 8b 15 a2 e2 dc
+ INFO: 56 41 41 9c 3d 30 60 cf e3 22 38 c0 fa 97 3f 7a
+ INFO: a3 02 58 20 2e 6d 31 a5 98 3a 91 25 1b fa e5 ae
+ INFO: fa 1c 0a 19 d8 ba 3c f6 01 d0 e8 a7 06 b4 cf a9
+ INFO: 66 1a 6b 8a 06 67 73 68 61 2d 32 35 36 a4 01 63
+ INFO: 52 4d 4d 05 58 20 53 78 79 63 07 53 5d f3 ec 8d
+ INFO: 8b 15 a2 e2 dc 56 41 41 9c 3d 30 60 cf e3 22 38
+ INFO: c0 fa 97 3f 7a a3 02 58 20 a1 fb 50 e6 c8 6f ae
+ INFO: 16 79 ef 33 51 29 6f d6 71 34 11 a0 8c f8 dd 17
+ INFO: 90 a4 fd 05 fa e8 68 81 64 06 67 73 68 61 2d 32
+ INFO: 35 36 a4 01 69 48 57 5f 43 4f 4e 46 49 47 05 58
+ INFO: 20 53 78 79 63 07 53 5d f3 ec 8d 8b 15 a2 e2 dc
+ INFO: 56 41 41 9c 3d 30 60 cf e3 22 38 c0 fa 97 3f 7a
+ INFO: a3 02 58 20 1a 25 24 02 97 2f 60 57 fa 53 cc 17
+ INFO: 2b 52 b9 ff ca 69 8e 18 31 1f ac d0 f3 b0 6e ca
+ INFO: ae f7 9e 17 06 67 73 68 61 2d 32 35 36 a4 01 69
+ INFO: 46 57 5f 43 4f 4e 46 49 47 05 58 20 53 78 79 63
+ INFO: 07 53 5d f3 ec 8d 8b 15 a2 e2 dc 56 41 41 9c 3d
+ INFO: 30 60 cf e3 22 38 c0 fa 97 3f 7a a3 02 58 20 9a
+ INFO: 92 ad bc 0c ee 38 ef 65 8c 71 ce 1b 1b f8 c6 56
+ INFO: 68 f1 66 bf b2 13 64 4c 89 5c cb 1a d0 7a 25 06
+ INFO: 67 73 68 61 2d 32 35 36 a4 01 6c 54 42 5f 46 57
+ INFO: 5f 43 4f 4e 46 49 47 05 58 20 53 78 79 63 07 53
+ INFO: 5d f3 ec 8d 8b 15 a2 e2 dc 56 41 41 9c 3d 30 60
+ INFO: cf e3 22 38 c0 fa 97 3f 7a a3 02 58 20 23 89 03
+ INFO: 18 0c c1 04 ec 2c 5d 8b 3f 20 c5 bc 61 b3 89 ec
+ INFO: 0a 96 7d f8 cc 20 8c dc 7c d4 54 17 4f 06 67 73
+ INFO: 68 61 2d 32 35 36 a4 01 6d 53 4f 43 5f 46 57 5f
+ INFO: 43 4f 4e 46 49 47 05 58 20 53 78 79 63 07 53 5d
+ INFO: f3 ec 8d 8b 15 a2 e2 dc 56 41 41 9c 3d 30 60 cf
+ INFO: e3 22 38 c0 fa 97 3f 7a a3 02 58 20 e6 c2 1e 8d
+ INFO: 26 0f e7 18 82 de bd b3 39 d2 40 2a 2c a7 64 85
+ INFO: 29 bc 23 03 f4 86 49 bc e0 38 00 17 06 67 73 68
+ INFO: 61 2d 32 35 36 58 60 21 51 20 92 d6 d0 2a e6 be
+ INFO: 2f e3 93 0e a5 1f d6 98 96 32 24 56 e9 df c7 32
+ INFO: 5e 0b 78 68 b6 90 73 2a 0c 0f 07 77 c1 15 40 4b
+ INFO: e1 fc 83 9b 7d 30 4f 4f e6 fa 46 ae 12 a3 08 3a
+ INFO: cf 24 06 67 91 06 bf ae 50 31 79 dd 50 33 49 12
+ INFO: bf c6 da 33 6d d6 18 25 43 54 4d b5 88 d6 ae 67
+ INFO: 35 7a fd b0 5f 95 b7
INFO: DELEGATED ATTEST TEST END
JSON format:
@@ -557,70 +584,94 @@
.. code-block:: JSON
{
- "CCA_PLATFORM_CHALLENGE": "b'0000000000000000000000000000000000000000000000000000000000000000'",
- "CCA_PLATFORM_INSTANCE_ID": "b'01CB8C79F7A00A6CCE1266F8644548420EC510BF84EE2218B98F1104C722319DFB'",
- "CCA_PLATFORM_IMPLEMENTATION_ID": "b'AAAAAAAAAAAAAAAABBBBBBBBBBBBBBBBCCCCCCCCCCCCCCCCDDDDDDDDDDDDDDDD'",
- "CCA_PLATFORM_LIFECYCLE": "secured_3000",
+ "CCA_ATTESTATION_PROFILE": "http://arm.com/CCA-SSD/1.0.0",
+ "CCA_PLATFORM_CHALLENGE": "b'B5973CB68BAA9FC55558786B7EC67F69E40DF5BA5AA921CD0C27F40587A011EA'",
+ "CCA_PLATFORM_IMPLEMENTATION_ID": "b'7F454C4602010100000000000000000003003E00010000005058000000000000'",
+ "CCA_PLATFORM_INSTANCE_ID": "b'0107060504030201000F0E0D0C0B0A090817161514131211101F1E1D1C1B1A1918'",
+ "CCA_PLATFORM_CONFIG": "b'CFCFCFCF'",
+ "CCA_PLATFORM_LIFECYCLE": "secured_3003",
+ "CCA_PLATFORM_HASH_ALGO_ID": "sha-256",
+ "CCA_PLATFORM_VERIFICATION_SERVICE": "https://veraison.example/.well-known/veraison/verification",
"CCA_PLATFORM_SW_COMPONENTS": [
{
+ "SW_COMPONENT_TYPE": "RSE_BL1_2",
+ "SIGNER_ID": "b'5378796307535DF3EC8D8B15A2E2DC5641419C3D3060CFE32238C0FA973F7AA3'",
+ "MEASUREMENT_VALUE": "b'9A271F2A916B0B6EE6CECB2426F0B3206EF074578BE55D9BC94F6F3FE3AB86AA'",
+ "CCA_SW_COMPONENT_HASH_ID": "sha-256"
+ },
+ {
+ "SW_COMPONENT_TYPE": "RSE_BL2",
+ "SIGNER_ID": "b'5378796307535DF3EC8D8B15A2E2DC5641419C3D3060CFE32238C0FA973F7AA3'",
+ "MEASUREMENT_VALUE": "b'53C234E5E8472B6AC51C1AE1CAB3FE06FAD053BEB8EBFD8977B010655BFDD3C3'",
+ "CCA_SW_COMPONENT_HASH_ID": "sha-256"
+ },
+ {
- "SIGNER_ID": "b'BFE6D86F8826F4FF97FB96C4E6FBC4993E4619FC565DA26ADF34C329489ADC38'",
- "SW_COMPONENT_VERSION": "1.6.0+0",
- "SW_COMPONENT_TYPE": "RT_0",
- "MEASUREMENT_VALUE": "b'9027F246AB31853646C4D7C660ED310D3CF014DEF06C240BDEB67A84FC3F5BB7'"
+ "SW_COMPONENT_TYPE": "RSE_S",
+ "SIGNER_ID": "b'5378796307535DF3EC8D8B15A2E2DC5641419C3D3060CFE32238C0FA973F7AA3'",
+ "MEASUREMENT_VALUE": "b'1121CFCCD5913F0A63FEC40A6FFD44EA64F9DC135C66634BA001D10BCF4302A2'",
+ "CCA_SW_COMPONENT_HASH_ID": "sha-256"
},
{
- "SIGNER_ID": "b'B360CAF5C98C6B942A4882FA9D4823EFB166A9EF6A6E4AA37C1919ED1FCCC049'",
- "SW_COMPONENT_VERSION": "0.0.0+0",
- "SW_COMPONENT_TYPE": "RT_1",
- "MEASUREMENT_VALUE": "b'521315D49DB2CF54E49937444068F0707D7364AEF70814B0F782ADC617DBA391'"
+ "SW_COMPONENT_TYPE": "AP_BL1",
+ "SIGNER_ID": "b'5378796307535DF3EC8D8B15A2E2DC5641419C3D3060CFE32238C0FA973F7AA3'",
+ "MEASUREMENT_VALUE": "b'1571B5EC78BD68512BF7830BB6A2A44B2047C7DF57BCE79EB8A1C0E5BEA0A501'",
+ "CCA_SW_COMPONENT_HASH_ID": "sha-256"
},
{
- "SIGNER_ID": "b'BFE6D86F8826F4FF97FB96C4E6FBC4993E4619FC565DA26ADF34C329489ADC38'",
- "SW_COMPONENT_VERSION": "1.5.0+0",
- "SW_COMPONENT_TYPE": "RT_2",
- "MEASUREMENT_VALUE": "b'8E5D647E6F6CC66FD44F54B606E5479ACC1BF37FCE873849C592D82F852E8542'"
+ "SW_COMPONENT_TYPE": "AP_BL2",
+ "SIGNER_ID": "b'5378796307535DF3EC8D8B15A2E2DC5641419C3D3060CFE32238C0FA973F7AA3'",
+ "MEASUREMENT_VALUE": "b'10159BAF262B43A92D95DB59DAE1F72C645127301661E0A3CE4E38B295A97C58'",
+ "CCA_SW_COMPONENT_HASH_ID": "sha-256"
},
{
- "SIGNER_ID": "b'BFE6D86F8826F4FF97FB96C4E6FBC4993E4619FC565DA26ADF34C329489ADC38'",
- "SW_COMPONENT_VERSION": "1.5.0+0",
- "SW_COMPONENT_TYPE": "",
- "MEASUREMENT_VALUE": "b'B80165A7788BC659428D331085D1490ADC9EC3EEDF851BD2F073736A0C0711B8'"
+ "SW_COMPONENT_TYPE": "SCP_BL1",
+ "SIGNER_ID": "b'5378796307535DF3EC8D8B15A2E2DC5641419C3D3060CFE32238C0FA973F7AA3'",
+ "MEASUREMENT_VALUE": "b'10122E856B3FCD49F063636317476149CB730A1AA1CFAAD818552B72F56D6F68'",
+ "CCA_SW_COMPONENT_HASH_ID": "sha-256"
},
{
- "SIGNER_ID": "b'b0f382091297d83a377a72471bec3273e99232e24959f65e8b4a4a46d8229ada'",
- "SW_COMPONENT_VERSION": "",
- "SW_COMPONENT_TYPE": "FW_CONFIG\u0000",
- "MEASUREMENT_VALUE": "b'219EA01382E6D7975A1113A35F453968B1D9A3EA6AAB84233B8C06169820BAB9'"
+ "SW_COMPONENT_TYPE": "SCP_BL2",
+ "SIGNER_ID": "b'F14B4987904BCB5814E4459A057ED4D20F58A633152288A761214DCD28780B56'",
+ "MEASUREMENT_VALUE": "b'AA67A169B0BBA217AA0AA88A65346920C84C42447C36BA5F7EA65F422C1FE5D8'",
+ "CCA_SW_COMPONENT_HASH_ID": "sha-256"
},
{
- "SIGNER_ID": "b'b0f382091297d83a377a72471bec3273e99232e24959f65e8b4a4a46d8229ada'",
- "SW_COMPONENT_VERSION": "",
- "SW_COMPONENT_TYPE": "TB_FW_CONFIG\u0000",
- "MEASUREMENT_VALUE": "b'4139F6C2108453C517AE9AE5BEC1207BCC2424F39D20A8FBC7B310E3EEAF1B05'"
+ "SW_COMPONENT_TYPE": "AP_BL31",
+ "SIGNER_ID": "b'5378796307535DF3EC8D8B15A2E2DC5641419C3D3060CFE32238C0FA973F7AA3'",
+ "MEASUREMENT_VALUE": "b'2E6D31A5983A91251BFAE5AEFA1C0A19D8BA3CF601D0E8A706B4CFA9661A6B8A'",
+ "CCA_SW_COMPONENT_HASH_ID": "sha-256"
},
{
- "SIGNER_ID": "b'b0f382091297d83a377a72471bec3273e99232e24959f65e8b4a4a46d8229ada'",
- "SW_COMPONENT_VERSION": "",
- "SW_COMPONENT_TYPE": "BL_2\u0000",
- "MEASUREMENT_VALUE": "b'5C9620E1E33B0F2CEBC18E1A02A66586DD3497A74C9813BF7414452D302805C3'"
+ "SW_COMPONENT_TYPE": "RMM",
+ "SIGNER_ID": "b'5378796307535DF3EC8D8B15A2E2DC5641419C3D3060CFE32238C0FA973F7AA3'",
+ "MEASUREMENT_VALUE": "b'A1FB50E6C86FAE1679EF3351296FD6713411A08CF8DD1790A4FD05FAE8688164'",
+ "CCA_SW_COMPONENT_HASH_ID": "sha-256"
},
{
- "SIGNER_ID": "b'b0f382091297d83a377a72471bec3273e99232e24959f65e8b4a4a46d8229ada'",
- "SW_COMPONENT_VERSION": "",
- "SW_COMPONENT_TYPE": "SECURE_RT_EL3\u0000",
- "MEASUREMENT_VALUE": "b'F6FB6299A50CDFDB020B725B1C0B636E94EE6650563A299CCB38F0EC5999D42E'"
+ "SW_COMPONENT_TYPE": "HW_CONFIG",
+ "SIGNER_ID": "b'5378796307535DF3EC8D8B15A2E2DC5641419C3D3060CFE32238C0FA973F7AA3'",
+ "MEASUREMENT_VALUE": "b'1A252402972F6057FA53CC172B52B9FFCA698E18311FACD0F3B06ECAAEF79E17'",
+ "CCA_SW_COMPONENT_HASH_ID": "sha-256"
},
{
- "SIGNER_ID": "b'b0f382091297d83a377a72471bec3273e99232e24959f65e8b4a4a46d8229ada'",
- "SW_COMPONENT_VERSION": "",
- "SW_COMPONENT_TYPE": "HW_CONFIG\u0000",
- "MEASUREMENT_VALUE": "b'985D87218406339DC31F91F5688DA05AF0D77E2051CE3BF2A5C3052E3C8B5231'"
+ "SW_COMPONENT_TYPE": "FW_CONFIG",
+ "SIGNER_ID": "b'5378796307535DF3EC8D8B15A2E2DC5641419C3D3060CFE32238C0FA973F7AA3'",
+ "MEASUREMENT_VALUE": "b'9A92ADBC0CEE38EF658C71CE1B1BF8C65668F166BFB213644C895CCB1AD07A25'",
+ "CCA_SW_COMPONENT_HASH_ID": "sha-256"
+ },
+ {
+ "SW_COMPONENT_TYPE": "TB_FW_CONFIG",
+ "SIGNER_ID": "b'5378796307535DF3EC8D8B15A2E2DC5641419C3D3060CFE32238C0FA973F7AA3'",
+ "MEASUREMENT_VALUE": "b'238903180CC104EC2C5D8B3F20C5BC61B389EC0A967DF8CC208CDC7CD454174F'",
+ "CCA_SW_COMPONENT_HASH_ID": "sha-256"
+ },
+ {
+ "SW_COMPONENT_TYPE": "SOC_FW_CONFIG",
+ "SIGNER_ID": "b'5378796307535DF3EC8D8B15A2E2DC5641419C3D3060CFE32238C0FA973F7AA3'",
+ "MEASUREMENT_VALUE": "b'E6C21E8D260FE71882DEBDB339D2402A2CA7648529BC2303F48649BCE0380017'",
+ "CCA_SW_COMPONENT_HASH_ID": "sha-256"
}
- ],
- "CCA_ATTESTATION_PROFILE": "http://arm.com/CCA-SSD/1.0.0",
- "CCA_PLATFORM_HASH_ALGO_ID": "not-hash-extended",
- "CCA_PLATFORM_CONFIG": "b'EFBEADDE'",
- "CCA_PLATFORM_VERIFICATION_SERVICE": "www.trustedfirmware.org"
+ ]
}
RSE OTP Assets Management
@@ -688,3 +739,4 @@
--------------
*Copyright (c) 2023, Arm Limited. All rights reserved.*
+*Copyright (c) 2024, Linaro Limited. All rights reserved.*
diff --git a/docs/plat/st/stm32mp2.rst b/docs/plat/st/stm32mp2.rst
index 43e131d..5d4ab4e 100644
--- a/docs/plat/st/stm32mp2.rst
+++ b/docs/plat/st/stm32mp2.rst
@@ -4,6 +4,8 @@
STM32MP2 is a microprocessor designed by STMicroelectronics
based on Arm Cortex-A35.
+More information can be found on `STM32MP2 Series`_ page.
+
For TF-A common configuration of STM32 MPUs, please check
:ref:`STM32 MPUs` page.
@@ -19,11 +21,13 @@
Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
-- A Basic + Cortex-A35 @ 1GHz
-- C Secure Boot + HW Crypto + Cortex-A35 @ 1GHz
+- A Basic + Cortex-A35 @ 1.2GHz
+- C Secure Boot + HW Crypto + Cortex-A35 @ 1.2GHz
- D Basic + Cortex-A35 @ 1.5GHz
- F Secure Boot + HW Crypto + Cortex-A35 @ 1.5GHz
+The `STM32MP2 part number codification`_ page gives more information about part numbers.
+
Memory mapping
--------------
@@ -130,4 +134,7 @@
BL32_EXTRA1=<optee_directory>/tee-pager_v2.bin
fip
-*Copyright (c) 2023, STMicroelectronics - All Rights Reserved*
+.. _STM32MP2 Series: https://www.st.com/en/microcontrollers-microprocessors/stm32mp2-series.html
+.. _STM32MP2 part number codification: https://wiki.st.com/stm32mpu/wiki/STM32MP25_microprocessor#Part_number_codification
+
+*Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved*
diff --git a/drivers/measured_boot/rse/dice_prot_env.c b/drivers/measured_boot/rse/dice_prot_env.c
index da98afe..dad30b2 100644
--- a/drivers/measured_boot/rse/dice_prot_env.c
+++ b/drivers/measured_boot/rse/dice_prot_env.c
@@ -115,7 +115,7 @@
metadata->allow_new_context_to_derive,
metadata->create_certificate,
&dice_inputs,
- 0, /* target_locality */
+ metadata->target_locality,
false, /* return_certificate */
true, /* allow_new_context_to_export */
false, /* export_cdi */
diff --git a/drivers/partition/partition.c b/drivers/partition/partition.c
index 888a824..c4f7493 100644
--- a/drivers/partition/partition.c
+++ b/drivers/partition/partition.c
@@ -50,7 +50,7 @@
{
size_t bytes_read;
int result;
- mbr_entry_t *tmp;
+ mbr_entry_t tmp;
assert(mbr_entry != NULL);
/* MBR partition table is in LBA0. */
@@ -73,19 +73,19 @@
return -ENOENT;
}
- tmp = (mbr_entry_t *)(&mbr_sector[MBR_PRIMARY_ENTRY_OFFSET]);
+ memcpy(&tmp, mbr_sector + MBR_PRIMARY_ENTRY_OFFSET, sizeof(tmp));
- if (tmp->first_lba != 1) {
+ if (tmp.first_lba != 1) {
VERBOSE("MBR header may have an invalid first LBA\n");
return -EINVAL;
}
- if ((tmp->sector_nums == 0) || (tmp->sector_nums == UINT32_MAX)) {
+ if ((tmp.sector_nums == 0) || (tmp.sector_nums == UINT32_MAX)) {
VERBOSE("MBR header entry has an invalid number of sectors\n");
return -EINVAL;
}
- memcpy(mbr_entry, tmp, sizeof(mbr_entry_t));
+ memcpy(mbr_entry, &tmp, sizeof(mbr_entry_t));
return 0;
}
diff --git a/include/drivers/measured_boot/rse/dice_prot_env.h b/include/drivers/measured_boot/rse/dice_prot_env.h
index e453198..e5aef51 100644
--- a/include/drivers/measured_boot/rse/dice_prot_env.h
+++ b/include/drivers/measured_boot/rse/dice_prot_env.h
@@ -27,6 +27,7 @@
bool allow_new_context_to_derive;
bool retain_parent_context;
bool create_certificate;
+ int target_locality;
void *pk_oid;
};
diff --git a/plat/arm/board/fvp/fvp_plat_attest_token.c b/plat/arm/board/fvp/fvp_plat_attest_token.c
index f5bd722..83b52fc 100644
--- a/plat/arm/board/fvp/fvp_plat_attest_token.c
+++ b/plat/arm/board/fvp/fvp_plat_attest_token.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2024, Linaro Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,91 +10,200 @@
#include <plat/common/platform.h>
+/*
+ * This is the CBOR serialization of the CCA platform token described at
+ * https://git.trustedfirmware.org/TF-M/tf-m-tools/+/refs/heads/main/iat-verifier/tests/data/cca_example_platform_token.yaml
+ */
static const uint8_t sample_platform_token[] = {
- 0xD2, 0x84, 0x44, 0xA1, 0x01, 0x38, 0x22, 0xA0,
- 0x59, 0x02, 0x33, 0xA9, 0x19, 0x01, 0x09, 0x78,
- 0x1C, 0x68, 0x74, 0x74, 0x70, 0x3A, 0x2F, 0x2F,
- 0x61, 0x72, 0x6D, 0x2E, 0x63, 0x6F, 0x6D, 0x2F,
- 0x43, 0x43, 0x41, 0x2D, 0x53, 0x53, 0x44, 0x2F,
- 0x31, 0x2E, 0x30, 0x2E, 0x30, 0x0A, 0x58, 0x20,
- 0xB5, 0x97, 0x3C, 0xB6, 0x8B, 0xAA, 0x9F, 0xC5,
- 0x55, 0x58, 0x78, 0x6B, 0x7E, 0xC6, 0x7F, 0x69,
- 0xE4, 0x0D, 0xF5, 0xBA, 0x5A, 0xA9, 0x21, 0xCD,
- 0x0C, 0x27, 0xF4, 0x05, 0x87, 0xA0, 0x11, 0xEA,
- 0x19, 0x09, 0x5C, 0x58, 0x20, 0x7F, 0x45, 0x4C,
+ 0xd2, 0x84, 0x44, 0xa1, 0x01, 0x38, 0x22, 0xa0,
+ 0x59, 0x05, 0x7a, 0xa9, 0x19, 0x01, 0x09, 0x78,
+ 0x1c, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f,
+ 0x61, 0x72, 0x6d, 0x2e, 0x63, 0x6f, 0x6d, 0x2f,
+ 0x43, 0x43, 0x41, 0x2d, 0x53, 0x53, 0x44, 0x2f,
+ 0x31, 0x2e, 0x30, 0x2e, 0x30, 0x0a, 0x58, 0x20,
+ 0xb5, 0x97, 0x3c, 0xb6, 0x8b, 0xaa, 0x9f, 0xc5,
+ 0x55, 0x58, 0x78, 0x6b, 0x7e, 0xc6, 0x7f, 0x69,
+ 0xe4, 0x0d, 0xf5, 0xba, 0x5a, 0xa9, 0x21, 0xcd,
+ 0x0c, 0x27, 0xf4, 0x05, 0x87, 0xa0, 0x11, 0xea,
+ 0x19, 0x09, 0x5c, 0x58, 0x20, 0x7f, 0x45, 0x4c,
0x46, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x3E,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x3e,
0x00, 0x01, 0x00, 0x00, 0x00, 0x50, 0x58, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x01, 0x00,
0x58, 0x21, 0x01, 0x07, 0x06, 0x05, 0x04, 0x03,
- 0x02, 0x01, 0x00, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B,
- 0x0A, 0x09, 0x08, 0x17, 0x16, 0x15, 0x14, 0x13,
- 0x12, 0x11, 0x10, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B,
- 0x1A, 0x19, 0x18, 0x19, 0x09, 0x61, 0x58, 0x21,
- 0x01, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01,
- 0x00, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09,
- 0x08, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11,
- 0x10, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19,
- 0x18, 0x19, 0x09, 0x5B, 0x19, 0x30, 0x03, 0x19,
- 0x09, 0x62, 0x67, 0x73, 0x68, 0x61, 0x2D, 0x32,
- 0x35, 0x36, 0x19, 0x09, 0x5F, 0x84, 0xA5, 0x01,
- 0x62, 0x42, 0x4C, 0x05, 0x58, 0x20, 0x07, 0x06,
- 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E,
- 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16,
- 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E,
- 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, 0x65,
- 0x33, 0x2E, 0x34, 0x2E, 0x32, 0x02, 0x58, 0x20,
- 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00,
- 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08,
- 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10,
- 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18,
- 0x06, 0x74, 0x54, 0x46, 0x2D, 0x4D, 0x5F, 0x53,
- 0x48, 0x41, 0x32, 0x35, 0x36, 0x4D, 0x65, 0x6D,
- 0x50, 0x72, 0x65, 0x58, 0x49, 0x50, 0xA4, 0x01,
- 0x62, 0x4D, 0x31, 0x05, 0x58, 0x20, 0x07, 0x06,
- 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E,
- 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16,
- 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E,
- 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, 0x63,
- 0x31, 0x2E, 0x32, 0x02, 0x58, 0x20, 0x07, 0x06,
- 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E,
- 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16,
- 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E,
- 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0xA4, 0x01,
- 0x62, 0x4D, 0x32, 0x05, 0x58, 0x20, 0x07, 0x06,
- 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E,
- 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16,
- 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E,
- 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, 0x65,
- 0x31, 0x2E, 0x32, 0x2E, 0x33, 0x02, 0x58, 0x20,
- 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00,
- 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08,
- 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10,
- 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18,
- 0xA4, 0x01, 0x62, 0x4D, 0x33, 0x05, 0x58, 0x20,
- 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00,
- 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08,
- 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10,
- 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18,
- 0x04, 0x61, 0x31, 0x02, 0x58, 0x20, 0x07, 0x06,
- 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E,
- 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16,
- 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E,
- 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x19, 0x09,
- 0x60, 0x6C, 0x77, 0x68, 0x61, 0x74, 0x65, 0x76,
- 0x65, 0x72, 0x2E, 0x63, 0x6F, 0x6D, 0x58, 0x60,
- 0xE6, 0xB6, 0x38, 0x4F, 0xAE, 0x3F, 0x6E, 0x67,
- 0xF5, 0xD4, 0x97, 0x4B, 0x3F, 0xFD, 0x0A, 0xFA,
- 0x1D, 0xF0, 0x2F, 0x73, 0xB8, 0xFF, 0x5F, 0x02,
- 0xC0, 0x0F, 0x40, 0xAC, 0xF3, 0xA2, 0x9D, 0xB5,
- 0x31, 0x50, 0x16, 0x4F, 0xFA, 0x34, 0x3D, 0x0E,
- 0xAF, 0xE0, 0xD0, 0xD1, 0x6C, 0xF0, 0x9D, 0xC1,
- 0x01, 0x42, 0xA2, 0x3C, 0xCE, 0xD4, 0x4A, 0x59,
- 0xDC, 0x29, 0x0A, 0x30, 0x93, 0x5F, 0xB4, 0x98,
- 0x61, 0xBA, 0xE3, 0x91, 0x22, 0x95, 0x24, 0xF4,
- 0xAE, 0x47, 0x93, 0xD3, 0x84, 0xA3, 0x76, 0xD0,
- 0xC1, 0x26, 0x96, 0x53, 0xA3, 0x60, 0x3F, 0x6C,
- 0x75, 0x96, 0x90, 0x6A, 0xF9, 0x4E, 0xDA, 0x30
+ 0x02, 0x01, 0x00, 0x0f, 0x0e, 0x0d, 0x0c, 0x0b,
+ 0x0a, 0x09, 0x08, 0x17, 0x16, 0x15, 0x14, 0x13,
+ 0x12, 0x11, 0x10, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b,
+ 0x1a, 0x19, 0x18, 0x19, 0x09, 0x61, 0x44, 0xcf,
+ 0xcf, 0xcf, 0xcf, 0x19, 0x09, 0x5b, 0x19, 0x30,
+ 0x03, 0x19, 0x09, 0x62, 0x67, 0x73, 0x68, 0x61,
+ 0x2d, 0x32, 0x35, 0x36, 0x19, 0x09, 0x60, 0x78,
+ 0x3a, 0x68, 0x74, 0x74, 0x70, 0x73, 0x3a, 0x2f,
+ 0x2f, 0x76, 0x65, 0x72, 0x61, 0x69, 0x73, 0x6f,
+ 0x6e, 0x2e, 0x65, 0x78, 0x61, 0x6d, 0x70, 0x6c,
+ 0x65, 0x2f, 0x2e, 0x77, 0x65, 0x6c, 0x6c, 0x2d,
+ 0x6b, 0x6e, 0x6f, 0x77, 0x6e, 0x2f, 0x76, 0x65,
+ 0x72, 0x61, 0x69, 0x73, 0x6f, 0x6e, 0x2f, 0x76,
+ 0x65, 0x72, 0x69, 0x66, 0x69, 0x63, 0x61, 0x74,
+ 0x69, 0x6f, 0x6e, 0x19, 0x09, 0x5f, 0x8d, 0xa4,
+ 0x01, 0x69, 0x52, 0x53, 0x45, 0x5f, 0x42, 0x4c,
+ 0x31, 0x5f, 0x32, 0x05, 0x58, 0x20, 0x53, 0x78,
+ 0x79, 0x63, 0x07, 0x53, 0x5d, 0xf3, 0xec, 0x8d,
+ 0x8b, 0x15, 0xa2, 0xe2, 0xdc, 0x56, 0x41, 0x41,
+ 0x9c, 0x3d, 0x30, 0x60, 0xcf, 0xe3, 0x22, 0x38,
+ 0xc0, 0xfa, 0x97, 0x3f, 0x7a, 0xa3, 0x02, 0x58,
+ 0x20, 0x9a, 0x27, 0x1f, 0x2a, 0x91, 0x6b, 0x0b,
+ 0x6e, 0xe6, 0xce, 0xcb, 0x24, 0x26, 0xf0, 0xb3,
+ 0x20, 0x6e, 0xf0, 0x74, 0x57, 0x8b, 0xe5, 0x5d,
+ 0x9b, 0xc9, 0x4f, 0x6f, 0x3f, 0xe3, 0xab, 0x86,
+ 0xaa, 0x06, 0x67, 0x73, 0x68, 0x61, 0x2d, 0x32,
+ 0x35, 0x36, 0xa4, 0x01, 0x67, 0x52, 0x53, 0x45,
+ 0x5f, 0x42, 0x4c, 0x32, 0x05, 0x58, 0x20, 0x53,
+ 0x78, 0x79, 0x63, 0x07, 0x53, 0x5d, 0xf3, 0xec,
+ 0x8d, 0x8b, 0x15, 0xa2, 0xe2, 0xdc, 0x56, 0x41,
+ 0x41, 0x9c, 0x3d, 0x30, 0x60, 0xcf, 0xe3, 0x22,
+ 0x38, 0xc0, 0xfa, 0x97, 0x3f, 0x7a, 0xa3, 0x02,
+ 0x58, 0x20, 0x53, 0xc2, 0x34, 0xe5, 0xe8, 0x47,
+ 0x2b, 0x6a, 0xc5, 0x1c, 0x1a, 0xe1, 0xca, 0xb3,
+ 0xfe, 0x06, 0xfa, 0xd0, 0x53, 0xbe, 0xb8, 0xeb,
+ 0xfd, 0x89, 0x77, 0xb0, 0x10, 0x65, 0x5b, 0xfd,
+ 0xd3, 0xc3, 0x06, 0x67, 0x73, 0x68, 0x61, 0x2d,
+ 0x32, 0x35, 0x36, 0xa4, 0x01, 0x65, 0x52, 0x53,
+ 0x45, 0x5f, 0x53, 0x05, 0x58, 0x20, 0x53, 0x78,
+ 0x79, 0x63, 0x07, 0x53, 0x5d, 0xf3, 0xec, 0x8d,
+ 0x8b, 0x15, 0xa2, 0xe2, 0xdc, 0x56, 0x41, 0x41,
+ 0x9c, 0x3d, 0x30, 0x60, 0xcf, 0xe3, 0x22, 0x38,
+ 0xc0, 0xfa, 0x97, 0x3f, 0x7a, 0xa3, 0x02, 0x58,
+ 0x20, 0x11, 0x21, 0xcf, 0xcc, 0xd5, 0x91, 0x3f,
+ 0x0a, 0x63, 0xfe, 0xc4, 0x0a, 0x6f, 0xfd, 0x44,
+ 0xea, 0x64, 0xf9, 0xdc, 0x13, 0x5c, 0x66, 0x63,
+ 0x4b, 0xa0, 0x01, 0xd1, 0x0b, 0xcf, 0x43, 0x02,
+ 0xa2, 0x06, 0x67, 0x73, 0x68, 0x61, 0x2d, 0x32,
+ 0x35, 0x36, 0xa4, 0x01, 0x66, 0x41, 0x50, 0x5f,
+ 0x42, 0x4c, 0x31, 0x05, 0x58, 0x20, 0x53, 0x78,
+ 0x79, 0x63, 0x07, 0x53, 0x5d, 0xf3, 0xec, 0x8d,
+ 0x8b, 0x15, 0xa2, 0xe2, 0xdc, 0x56, 0x41, 0x41,
+ 0x9c, 0x3d, 0x30, 0x60, 0xcf, 0xe3, 0x22, 0x38,
+ 0xc0, 0xfa, 0x97, 0x3f, 0x7a, 0xa3, 0x02, 0x58,
+ 0x20, 0x15, 0x71, 0xb5, 0xec, 0x78, 0xbd, 0x68,
+ 0x51, 0x2b, 0xf7, 0x83, 0x0b, 0xb6, 0xa2, 0xa4,
+ 0x4b, 0x20, 0x47, 0xc7, 0xdf, 0x57, 0xbc, 0xe7,
+ 0x9e, 0xb8, 0xa1, 0xc0, 0xe5, 0xbe, 0xa0, 0xa5,
+ 0x01, 0x06, 0x67, 0x73, 0x68, 0x61, 0x2d, 0x32,
+ 0x35, 0x36, 0xa4, 0x01, 0x66, 0x41, 0x50, 0x5f,
+ 0x42, 0x4c, 0x32, 0x05, 0x58, 0x20, 0x53, 0x78,
+ 0x79, 0x63, 0x07, 0x53, 0x5d, 0xf3, 0xec, 0x8d,
+ 0x8b, 0x15, 0xa2, 0xe2, 0xdc, 0x56, 0x41, 0x41,
+ 0x9c, 0x3d, 0x30, 0x60, 0xcf, 0xe3, 0x22, 0x38,
+ 0xc0, 0xfa, 0x97, 0x3f, 0x7a, 0xa3, 0x02, 0x58,
+ 0x20, 0x10, 0x15, 0x9b, 0xaf, 0x26, 0x2b, 0x43,
+ 0xa9, 0x2d, 0x95, 0xdb, 0x59, 0xda, 0xe1, 0xf7,
+ 0x2c, 0x64, 0x51, 0x27, 0x30, 0x16, 0x61, 0xe0,
+ 0xa3, 0xce, 0x4e, 0x38, 0xb2, 0x95, 0xa9, 0x7c,
+ 0x58, 0x06, 0x67, 0x73, 0x68, 0x61, 0x2d, 0x32,
+ 0x35, 0x36, 0xa4, 0x01, 0x67, 0x53, 0x43, 0x50,
+ 0x5f, 0x42, 0x4c, 0x31, 0x05, 0x58, 0x20, 0x53,
+ 0x78, 0x79, 0x63, 0x07, 0x53, 0x5d, 0xf3, 0xec,
+ 0x8d, 0x8b, 0x15, 0xa2, 0xe2, 0xdc, 0x56, 0x41,
+ 0x41, 0x9c, 0x3d, 0x30, 0x60, 0xcf, 0xe3, 0x22,
+ 0x38, 0xc0, 0xfa, 0x97, 0x3f, 0x7a, 0xa3, 0x02,
+ 0x58, 0x20, 0x10, 0x12, 0x2e, 0x85, 0x6b, 0x3f,
+ 0xcd, 0x49, 0xf0, 0x63, 0x63, 0x63, 0x17, 0x47,
+ 0x61, 0x49, 0xcb, 0x73, 0x0a, 0x1a, 0xa1, 0xcf,
+ 0xaa, 0xd8, 0x18, 0x55, 0x2b, 0x72, 0xf5, 0x6d,
+ 0x6f, 0x68, 0x06, 0x67, 0x73, 0x68, 0x61, 0x2d,
+ 0x32, 0x35, 0x36, 0xa4, 0x01, 0x67, 0x53, 0x43,
+ 0x50, 0x5f, 0x42, 0x4c, 0x32, 0x05, 0x58, 0x20,
+ 0xf1, 0x4b, 0x49, 0x87, 0x90, 0x4b, 0xcb, 0x58,
+ 0x14, 0xe4, 0x45, 0x9a, 0x05, 0x7e, 0xd4, 0xd2,
+ 0x0f, 0x58, 0xa6, 0x33, 0x15, 0x22, 0x88, 0xa7,
+ 0x61, 0x21, 0x4d, 0xcd, 0x28, 0x78, 0x0b, 0x56,
+ 0x02, 0x58, 0x20, 0xaa, 0x67, 0xa1, 0x69, 0xb0,
+ 0xbb, 0xa2, 0x17, 0xaa, 0x0a, 0xa8, 0x8a, 0x65,
+ 0x34, 0x69, 0x20, 0xc8, 0x4c, 0x42, 0x44, 0x7c,
+ 0x36, 0xba, 0x5f, 0x7e, 0xa6, 0x5f, 0x42, 0x2c,
+ 0x1f, 0xe5, 0xd8, 0x06, 0x67, 0x73, 0x68, 0x61,
+ 0x2d, 0x32, 0x35, 0x36, 0xa4, 0x01, 0x67, 0x41,
+ 0x50, 0x5f, 0x42, 0x4c, 0x33, 0x31, 0x05, 0x58,
+ 0x20, 0x53, 0x78, 0x79, 0x63, 0x07, 0x53, 0x5d,
+ 0xf3, 0xec, 0x8d, 0x8b, 0x15, 0xa2, 0xe2, 0xdc,
+ 0x56, 0x41, 0x41, 0x9c, 0x3d, 0x30, 0x60, 0xcf,
+ 0xe3, 0x22, 0x38, 0xc0, 0xfa, 0x97, 0x3f, 0x7a,
+ 0xa3, 0x02, 0x58, 0x20, 0x2e, 0x6d, 0x31, 0xa5,
+ 0x98, 0x3a, 0x91, 0x25, 0x1b, 0xfa, 0xe5, 0xae,
+ 0xfa, 0x1c, 0x0a, 0x19, 0xd8, 0xba, 0x3c, 0xf6,
+ 0x01, 0xd0, 0xe8, 0xa7, 0x06, 0xb4, 0xcf, 0xa9,
+ 0x66, 0x1a, 0x6b, 0x8a, 0x06, 0x67, 0x73, 0x68,
+ 0x61, 0x2d, 0x32, 0x35, 0x36, 0xa4, 0x01, 0x63,
+ 0x52, 0x4d, 0x4d, 0x05, 0x58, 0x20, 0x53, 0x78,
+ 0x79, 0x63, 0x07, 0x53, 0x5d, 0xf3, 0xec, 0x8d,
+ 0x8b, 0x15, 0xa2, 0xe2, 0xdc, 0x56, 0x41, 0x41,
+ 0x9c, 0x3d, 0x30, 0x60, 0xcf, 0xe3, 0x22, 0x38,
+ 0xc0, 0xfa, 0x97, 0x3f, 0x7a, 0xa3, 0x02, 0x58,
+ 0x20, 0xa1, 0xfb, 0x50, 0xe6, 0xc8, 0x6f, 0xae,
+ 0x16, 0x79, 0xef, 0x33, 0x51, 0x29, 0x6f, 0xd6,
+ 0x71, 0x34, 0x11, 0xa0, 0x8c, 0xf8, 0xdd, 0x17,
+ 0x90, 0xa4, 0xfd, 0x05, 0xfa, 0xe8, 0x68, 0x81,
+ 0x64, 0x06, 0x67, 0x73, 0x68, 0x61, 0x2d, 0x32,
+ 0x35, 0x36, 0xa4, 0x01, 0x69, 0x48, 0x57, 0x5f,
+ 0x43, 0x4f, 0x4e, 0x46, 0x49, 0x47, 0x05, 0x58,
+ 0x20, 0x53, 0x78, 0x79, 0x63, 0x07, 0x53, 0x5d,
+ 0xf3, 0xec, 0x8d, 0x8b, 0x15, 0xa2, 0xe2, 0xdc,
+ 0x56, 0x41, 0x41, 0x9c, 0x3d, 0x30, 0x60, 0xcf,
+ 0xe3, 0x22, 0x38, 0xc0, 0xfa, 0x97, 0x3f, 0x7a,
+ 0xa3, 0x02, 0x58, 0x20, 0x1a, 0x25, 0x24, 0x02,
+ 0x97, 0x2f, 0x60, 0x57, 0xfa, 0x53, 0xcc, 0x17,
+ 0x2b, 0x52, 0xb9, 0xff, 0xca, 0x69, 0x8e, 0x18,
+ 0x31, 0x1f, 0xac, 0xd0, 0xf3, 0xb0, 0x6e, 0xca,
+ 0xae, 0xf7, 0x9e, 0x17, 0x06, 0x67, 0x73, 0x68,
+ 0x61, 0x2d, 0x32, 0x35, 0x36, 0xa4, 0x01, 0x69,
+ 0x46, 0x57, 0x5f, 0x43, 0x4f, 0x4e, 0x46, 0x49,
+ 0x47, 0x05, 0x58, 0x20, 0x53, 0x78, 0x79, 0x63,
+ 0x07, 0x53, 0x5d, 0xf3, 0xec, 0x8d, 0x8b, 0x15,
+ 0xa2, 0xe2, 0xdc, 0x56, 0x41, 0x41, 0x9c, 0x3d,
+ 0x30, 0x60, 0xcf, 0xe3, 0x22, 0x38, 0xc0, 0xfa,
+ 0x97, 0x3f, 0x7a, 0xa3, 0x02, 0x58, 0x20, 0x9a,
+ 0x92, 0xad, 0xbc, 0x0c, 0xee, 0x38, 0xef, 0x65,
+ 0x8c, 0x71, 0xce, 0x1b, 0x1b, 0xf8, 0xc6, 0x56,
+ 0x68, 0xf1, 0x66, 0xbf, 0xb2, 0x13, 0x64, 0x4c,
+ 0x89, 0x5c, 0xcb, 0x1a, 0xd0, 0x7a, 0x25, 0x06,
+ 0x67, 0x73, 0x68, 0x61, 0x2d, 0x32, 0x35, 0x36,
+ 0xa4, 0x01, 0x6c, 0x54, 0x42, 0x5f, 0x46, 0x57,
+ 0x5f, 0x43, 0x4f, 0x4e, 0x46, 0x49, 0x47, 0x05,
+ 0x58, 0x20, 0x53, 0x78, 0x79, 0x63, 0x07, 0x53,
+ 0x5d, 0xf3, 0xec, 0x8d, 0x8b, 0x15, 0xa2, 0xe2,
+ 0xdc, 0x56, 0x41, 0x41, 0x9c, 0x3d, 0x30, 0x60,
+ 0xcf, 0xe3, 0x22, 0x38, 0xc0, 0xfa, 0x97, 0x3f,
+ 0x7a, 0xa3, 0x02, 0x58, 0x20, 0x23, 0x89, 0x03,
+ 0x18, 0x0c, 0xc1, 0x04, 0xec, 0x2c, 0x5d, 0x8b,
+ 0x3f, 0x20, 0xc5, 0xbc, 0x61, 0xb3, 0x89, 0xec,
+ 0x0a, 0x96, 0x7d, 0xf8, 0xcc, 0x20, 0x8c, 0xdc,
+ 0x7c, 0xd4, 0x54, 0x17, 0x4f, 0x06, 0x67, 0x73,
+ 0x68, 0x61, 0x2d, 0x32, 0x35, 0x36, 0xa4, 0x01,
+ 0x6d, 0x53, 0x4f, 0x43, 0x5f, 0x46, 0x57, 0x5f,
+ 0x43, 0x4f, 0x4e, 0x46, 0x49, 0x47, 0x05, 0x58,
+ 0x20, 0x53, 0x78, 0x79, 0x63, 0x07, 0x53, 0x5d,
+ 0xf3, 0xec, 0x8d, 0x8b, 0x15, 0xa2, 0xe2, 0xdc,
+ 0x56, 0x41, 0x41, 0x9c, 0x3d, 0x30, 0x60, 0xcf,
+ 0xe3, 0x22, 0x38, 0xc0, 0xfa, 0x97, 0x3f, 0x7a,
+ 0xa3, 0x02, 0x58, 0x20, 0xe6, 0xc2, 0x1e, 0x8d,
+ 0x26, 0x0f, 0xe7, 0x18, 0x82, 0xde, 0xbd, 0xb3,
+ 0x39, 0xd2, 0x40, 0x2a, 0x2c, 0xa7, 0x64, 0x85,
+ 0x29, 0xbc, 0x23, 0x03, 0xf4, 0x86, 0x49, 0xbc,
+ 0xe0, 0x38, 0x00, 0x17, 0x06, 0x67, 0x73, 0x68,
+ 0x61, 0x2d, 0x32, 0x35, 0x36, 0x58, 0x60, 0x21,
+ 0x51, 0x20, 0x92, 0xd6, 0xd0, 0x2a, 0xe6, 0xbe,
+ 0x2f, 0xe3, 0x93, 0x0e, 0xa5, 0x1f, 0xd6, 0x98,
+ 0x96, 0x32, 0x24, 0x56, 0xe9, 0xdf, 0xc7, 0x32,
+ 0x5e, 0x0b, 0x78, 0x68, 0xb6, 0x90, 0x73, 0x2a,
+ 0x0c, 0x0f, 0x07, 0x77, 0xc1, 0x15, 0x40, 0x4b,
+ 0xe1, 0xfc, 0x83, 0x9b, 0x7d, 0x30, 0x4f, 0x4f,
+ 0xe6, 0xfa, 0x46, 0xae, 0x12, 0xa3, 0x08, 0x3a,
+ 0xcf, 0x24, 0x06, 0x67, 0x91, 0x06, 0xbf, 0xae,
+ 0x50, 0x31, 0x79, 0xdd, 0x50, 0x33, 0x49, 0x12,
+ 0xbf, 0xc6, 0xda, 0x33, 0x6d, 0xd6, 0x18, 0x25,
+ 0x43, 0x54, 0x4d, 0xb5, 0x88, 0xd6, 0xae, 0x67,
+ 0x35, 0x7a, 0xfd, 0xb0, 0x5f, 0x95, 0xb7
};
/*
diff --git a/plat/arm/board/tc/fdts/tc_spmc_manifest.dtsi b/plat/arm/board/tc/fdts/tc_spmc_manifest.dtsi
index dc6c7d8..a6b63a1 100644
--- a/plat/arm/board/tc/fdts/tc_spmc_manifest.dtsi
+++ b/plat/arm/board/tc/fdts/tc_spmc_manifest.dtsi
@@ -112,4 +112,9 @@
device_type = "device-memory";
reg = <0x0 0x25000000 0x0 0x10000>; /* For cactus tertiary dummy device. */
};
+
+ s_uart {
+ device_type = "device-memory";
+ reg = <0x0 PLAT_ARM_BOOT_UART_BASE 0x0 0x01000>;
+ };
};
diff --git a/plat/arm/board/tc/tc_bl1_dpe.c b/plat/arm/board/tc/tc_bl1_dpe.c
index a073dc3..de5702a 100644
--- a/plat/arm/board/tc/tc_bl1_dpe.c
+++ b/plat/arm/board/tc/tc_bl1_dpe.c
@@ -18,7 +18,7 @@
#include <platform_def.h>
#include <tools_share/zero_oid.h>
-#include "tc_dpe_cert.h"
+#include "tc_dpe.h"
struct dpe_metadata tc_dpe_metadata[] = {
{
@@ -29,6 +29,7 @@
.allow_new_context_to_derive = false,
.retain_parent_context = true,
.create_certificate = false,
+ .target_locality = LOCALITY_NONE, /* won't derive don't care */
.pk_oid = ZERO_OID },
{
.id = TB_FW_CONFIG_ID,
@@ -38,6 +39,7 @@
.allow_new_context_to_derive = false,
.retain_parent_context = true,
.create_certificate = false,
+ .target_locality = LOCALITY_NONE, /* won't derive don't care */
.pk_oid = ZERO_OID },
{
.id = BL2_IMAGE_ID,
@@ -46,6 +48,7 @@
.sw_type = MBOOT_BL2_IMAGE_STRING,
.allow_new_context_to_derive = true,
.retain_parent_context = true, /* To handle restart */
+ .target_locality = LOCALITY_AP_S,
.create_certificate = false,
.pk_oid = ZERO_OID },
{
diff --git a/plat/arm/board/tc/tc_bl2_dpe.c b/plat/arm/board/tc/tc_bl2_dpe.c
index fb70fef..c56612b 100644
--- a/plat/arm/board/tc/tc_bl2_dpe.c
+++ b/plat/arm/board/tc/tc_bl2_dpe.c
@@ -15,7 +15,7 @@
#include <platform_def.h>
#include <tools_share/tbbr_oid.h>
-#include "tc_dpe_cert.h"
+#include "tc_dpe.h"
/*
* The content and the values of this array depends on:
@@ -39,6 +39,7 @@
.allow_new_context_to_derive = false,
.retain_parent_context = true,
.create_certificate = false,
+ .target_locality = LOCALITY_NONE, /* won't derive don't care */
.pk_oid = BL31_IMAGE_KEY_OID },
{
.id = BL32_IMAGE_ID,
@@ -48,6 +49,7 @@
.allow_new_context_to_derive = false,
.retain_parent_context = true,
.create_certificate = false,
+ .target_locality = LOCALITY_NONE, /* won't derive don't care */
.pk_oid = BL32_IMAGE_KEY_OID },
{
.id = BL33_IMAGE_ID,
@@ -57,6 +59,7 @@
.allow_new_context_to_derive = true,
.retain_parent_context = true,
.create_certificate = false,
+ .target_locality = LOCALITY_AP_NS,
.pk_oid = BL33_IMAGE_KEY_OID },
{
@@ -67,6 +70,7 @@
.allow_new_context_to_derive = false,
.retain_parent_context = true,
.create_certificate = false,
+ .target_locality = LOCALITY_NONE, /* won't derive don't care */
.pk_oid = HW_CONFIG_KEY_OID },
{
.id = NT_FW_CONFIG_ID,
@@ -76,6 +80,7 @@
.allow_new_context_to_derive = false,
.retain_parent_context = true,
.create_certificate = false,
+ .target_locality = LOCALITY_NONE, /* won't derive don't care */
.pk_oid = NT_FW_CONFIG_KEY_OID },
{
.id = SCP_BL2_IMAGE_ID,
@@ -85,6 +90,7 @@
.allow_new_context_to_derive = false,
.retain_parent_context = true,
.create_certificate = false,
+ .target_locality = LOCALITY_NONE, /* won't derive don't care */
.pk_oid = SCP_BL2_IMAGE_KEY_OID },
{
.id = SOC_FW_CONFIG_ID,
@@ -94,6 +100,7 @@
.allow_new_context_to_derive = false,
.retain_parent_context = true,
.create_certificate = false,
+ .target_locality = LOCALITY_NONE, /* won't derive don't care */
.pk_oid = SOC_FW_CONFIG_KEY_OID },
{
.id = TOS_FW_CONFIG_ID,
@@ -103,6 +110,7 @@
.allow_new_context_to_derive = false,
.retain_parent_context = true,
.create_certificate = false,
+ .target_locality = LOCALITY_NONE, /* won't derive don't care */
.pk_oid = TOS_FW_CONFIG_KEY_OID },
#if defined(SPD_spmd)
{
@@ -113,6 +121,7 @@
.allow_new_context_to_derive = false,
.retain_parent_context = true,
.create_certificate = true, /* With Trusty only one SP is loaded */
+ .target_locality = LOCALITY_NONE, /* won't derive don't care */
.pk_oid = NULL },
{
.id = SP_PKG2_ID,
@@ -122,6 +131,7 @@
.allow_new_context_to_derive = false,
.retain_parent_context = true,
.create_certificate = false,
+ .target_locality = LOCALITY_NONE, /* won't derive don't care */
.pk_oid = NULL },
{
.id = SP_PKG3_ID,
@@ -131,6 +141,7 @@
.allow_new_context_to_derive = false,
.retain_parent_context = true,
.create_certificate = false,
+ .target_locality = LOCALITY_NONE, /* won't derive don't care */
.pk_oid = NULL },
{
.id = SP_PKG4_ID,
@@ -140,6 +151,7 @@
.allow_new_context_to_derive = false,
.retain_parent_context = true,
.create_certificate = false,
+ .target_locality = LOCALITY_NONE, /* won't derive don't care */
.pk_oid = NULL },
{
.id = SP_PKG5_ID,
@@ -149,6 +161,7 @@
.allow_new_context_to_derive = false,
.retain_parent_context = true,
.create_certificate = false,
+ .target_locality = LOCALITY_NONE, /* won't derive don't care */
.pk_oid = NULL },
{
.id = SP_PKG6_ID,
@@ -158,6 +171,7 @@
.allow_new_context_to_derive = false,
.retain_parent_context = true,
.create_certificate = false,
+ .target_locality = LOCALITY_NONE, /* won't derive don't care */
.pk_oid = NULL },
{
.id = SP_PKG7_ID,
@@ -167,6 +181,7 @@
.allow_new_context_to_derive = false,
.retain_parent_context = true,
.create_certificate = false,
+ .target_locality = LOCALITY_NONE, /* won't derive don't care */
.pk_oid = NULL },
{
.id = SP_PKG8_ID,
@@ -176,6 +191,7 @@
.allow_new_context_to_derive = false,
.retain_parent_context = true,
.create_certificate = false,
+ .target_locality = LOCALITY_NONE, /* won't derive don't care */
.pk_oid = NULL },
#endif
diff --git a/plat/arm/board/tc/tc_dpe_cert.h b/plat/arm/board/tc/tc_dpe.h
similarity index 79%
rename from plat/arm/board/tc/tc_dpe_cert.h
rename to plat/arm/board/tc/tc_dpe.h
index d0632e8..3e1af5a 100644
--- a/plat/arm/board/tc/tc_dpe_cert.h
+++ b/plat/arm/board/tc/tc_dpe.h
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef TC_DPE_CERT_H
-#define TC_DPE_CERT_H
+#ifndef TC_DPE_H
+#define TC_DPE_H
/*
* The certificate structure on the TC platform:
@@ -36,4 +36,18 @@
/* Common definition */
#define DPE_CERT_ID_SAME_AS_PARENT 0xFFFFFFFF
-#endif /* TC_DPE_CERT_H */
+/*
+ * Target Locality:
+ * The goal is to specify that a certain component is expected to run and
+ * thereby send DPE commands from a given security domain. RSE is capable of
+ * of distinguishing the client's locality based on the MHU channel used for
+ * communication.
+ * Defines here must match with RSE side:
+ */
+#define LOCALITY_NONE -1
+/* #define LOCALITY_RSE_S 0 */ /* Not applicable on AP side */
+/* #define LOCALITY_RSE_NS 1 */ /* Not applicable on AP side */
+#define LOCALITY_AP_S 2
+#define LOCALITY_AP_NS 3
+
+#endif /* TC_DPE_H */
diff --git a/plat/aspeed/ast2700/include/platform_def.h b/plat/aspeed/ast2700/include/platform_def.h
index 8be26c3..e668115 100644
--- a/plat/aspeed/ast2700/include/platform_def.h
+++ b/plat/aspeed/ast2700/include/platform_def.h
@@ -21,9 +21,6 @@
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
PLATFORM_CORE_COUNT_PER_CLUSTER)
-/* arch timer */
-#define PLAT_SYSCNT_CLKIN_HZ U(1600000000)
-
/* power domain */
#define PLAT_MAX_PWR_LVL U(1)
#define PLAT_NUM_PWR_DOMAINS U(5)
@@ -55,4 +52,12 @@
#define CONSOLE_UART_CLKIN_HZ U(1846153)
#define CONSOLE_UART_BAUDRATE U(115200)
+/* CLK information */
+#define CLKIN_25M UL(25000000)
+
+#define PLAT_CLK_GATE_NUM U(29)
+#define PLAT_CLK_HPLL (PLAT_CLK_GATE_NUM + 5)
+#define PLAT_CLK_DPLL (PLAT_CLK_GATE_NUM + 6)
+#define PLAT_CLK_MPLL (PLAT_CLK_GATE_NUM + 7)
+
#endif /* PLATFORM_DEF_H */
diff --git a/plat/aspeed/ast2700/include/platform_reg.h b/plat/aspeed/ast2700/include/platform_reg.h
index 7f26865..3c164a4 100644
--- a/plat/aspeed/ast2700/include/platform_reg.h
+++ b/plat/aspeed/ast2700/include/platform_reg.h
@@ -19,6 +19,10 @@
/* CPU-die SCU */
#define SCU_CPU_BASE U(0x12c02000)
+#define SCU_CPU_HW_STRAP1 (SCU_CPU_BASE + 0x010)
+#define SCU_CPU_HPLL (SCU_CPU_BASE + 0x300)
+#define SCU_CPU_DPLL (SCU_CPU_BASE + 0x308)
+#define SCU_CPU_MPLL (SCU_CPU_BASE + 0x310)
#define SCU_CPU_SMP_EP0 (SCU_CPU_BASE + 0x780)
#define SCU_CPU_SMP_EP1 (SCU_CPU_BASE + 0x788)
#define SCU_CPU_SMP_EP2 (SCU_CPU_BASE + 0x790)
diff --git a/plat/aspeed/ast2700/plat_bl31_setup.c b/plat/aspeed/ast2700/plat_bl31_setup.c
index 92a48ff..9fec3e8 100644
--- a/plat/aspeed/ast2700/plat_bl31_setup.c
+++ b/plat/aspeed/ast2700/plat_bl31_setup.c
@@ -4,6 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <errno.h>
#include <arch.h>
#include <common/debug.h>
#include <common/desc_image_load.h>
@@ -112,3 +113,90 @@
return ep_info;
}
+
+/*
+ * Clock divider/multiplier configuration struct.
+ * For H-PLL and M-PLL the formula is
+ * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1)
+ * M - Numerator
+ * N - Denumerator
+ * P - Post Divider
+ * They have the same layout in their control register.
+ *
+ */
+union plat_pll_reg {
+ uint32_t w;
+ struct {
+ uint16_t m : 13; /* bit[12:0] */
+ uint8_t n : 6; /* bit[18:13] */
+ uint8_t p : 4; /* bit[22:19] */
+ uint8_t off : 1; /* bit[23] */
+ uint8_t bypass : 1; /* bit[24] */
+ uint8_t reset : 1; /* bit[25] */
+ uint8_t reserved : 6; /* bit[31:26] */
+ } b;
+};
+
+static uint32_t plat_get_pll_rate(int pll_idx)
+{
+ union plat_pll_reg pll_reg;
+ uint32_t mul = 1, div = 1;
+ uint32_t rate = 0;
+
+ switch (pll_idx) {
+ case PLAT_CLK_HPLL:
+ pll_reg.w = mmio_read_32(SCU_CPU_HPLL);
+ break;
+ case PLAT_CLK_DPLL:
+ pll_reg.w = mmio_read_32(SCU_CPU_DPLL);
+ break;
+ case PLAT_CLK_MPLL:
+ pll_reg.w = mmio_read_32(SCU_CPU_MPLL);
+ break;
+ default:
+ ERROR("%s: invalid PSP clock source (%d)\n", __func__, pll_idx);
+ return -EINVAL;
+ }
+
+ if (pll_idx == PLAT_CLK_HPLL && ((mmio_read_32(SCU_CPU_HW_STRAP1) & GENMASK(3, 2)) != 0U)) {
+ switch ((mmio_read_32(SCU_CPU_HW_STRAP1) & GENMASK(3, 2)) >> 2) {
+ case 1U:
+ rate = 1900000000;
+ break;
+ case 2U:
+ rate = 1800000000;
+ break;
+ case 3U:
+ rate = 1700000000;
+ break;
+ default:
+ rate = 2000000000;
+ break;
+ }
+ } else {
+ if (pll_reg.b.bypass != 0U) {
+ if (pll_idx == PLAT_CLK_MPLL) {
+ /* F = 25Mhz * [M / (n + 1)] / (p + 1) */
+ mul = (pll_reg.b.m) / ((pll_reg.b.n + 1));
+ div = (pll_reg.b.p + 1);
+ } else {
+ /* F = 25Mhz * [(M + 2) / 2 * (n + 1)] / (p + 1) */
+ mul = (pll_reg.b.m + 1) / ((pll_reg.b.n + 1) * 2);
+ div = (pll_reg.b.p + 1);
+ }
+ }
+
+ rate = ((CLKIN_25M * mul) / div);
+ }
+
+ return rate;
+}
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+ if (mmio_read_32(SCU_CPU_HW_STRAP1) & BIT(4)) {
+ return plat_get_pll_rate(PLAT_CLK_HPLL);
+ } else {
+ return plat_get_pll_rate(PLAT_CLK_MPLL);
+ }
+}
diff --git a/plat/aspeed/ast2700/plat_helpers.S b/plat/aspeed/ast2700/plat_helpers.S
index c6d987e..e4a283c 100644
--- a/plat/aspeed/ast2700/plat_helpers.S
+++ b/plat/aspeed/ast2700/plat_helpers.S
@@ -59,12 +59,6 @@
br x0
endfunc plat_secondary_cold_boot_setup
-/* unsigned int plat_get_syscnt_freq2(void); */
-func plat_get_syscnt_freq2
- mov_imm w0, PLAT_SYSCNT_CLKIN_HZ
- ret
-endfunc plat_get_syscnt_freq2
-
/* int plat_crash_console_init(void); */
func plat_crash_console_init
mov_imm x0, CONSOLE_UART_BASE
diff --git a/plat/mediatek/drivers/gic600/mt_gic_v3.c b/plat/mediatek/drivers/gic600/mt_gic_v3.c
index 85f9e37..2f9765c 100644
--- a/plat/mediatek/drivers/gic600/mt_gic_v3.c
+++ b/plat/mediatek/drivers/gic600/mt_gic_v3.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2024, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -27,6 +27,10 @@
/* we save and restore the GICv3 context on system suspend */
gicv3_dist_ctx_t dist_ctx;
+static const interrupt_prop_t mtk_interrupt_props[] = {
+ PLAT_MTK_G1S_IRQ_PROPS(INTR_GROUP1S)
+};
+
static unsigned int mt_mpidr_to_core_pos(u_register_t mpidr)
{
return plat_core_pos_by_mpidr(mpidr);
@@ -35,6 +39,8 @@
gicv3_driver_data_t mt_gicv3_data = {
.gicd_base = MT_GIC_BASE,
.gicr_base = MT_GIC_RDIST_BASE,
+ .interrupt_props = mtk_interrupt_props,
+ .interrupt_props_num = ARRAY_SIZE(mtk_interrupt_props),
.rdistif_num = PLATFORM_CORE_COUNT,
.rdistif_base_addrs = rdistif_base_addrs,
.mpidr_to_core_pos = mt_mpidr_to_core_pos,
diff --git a/plat/mediatek/mt8186/include/platform_def.h b/plat/mediatek/mt8186/include/platform_def.h
index 850ce2f..98b88bd 100644
--- a/plat/mediatek/mt8186/include/platform_def.h
+++ b/plat/mediatek/mt8186/include/platform_def.h
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2021-2022, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2021-2024, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2024, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -83,6 +83,8 @@
#define BASE_GICD_BASE MT_GIC_BASE
#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
+#define PLAT_MTK_G1S_IRQ_PROPS(grp)
+
#define SYS_CIRQ_BASE (IO_PHYS + 0x204000)
#define CIRQ_REG_NUM (11)
#define CIRQ_IRQ_NUM (326)
diff --git a/plat/mediatek/mt8188/include/platform_def.h b/plat/mediatek/mt8188/include/platform_def.h
index 71a4e97..8e0f5f9 100644
--- a/plat/mediatek/mt8188/include/platform_def.h
+++ b/plat/mediatek/mt8188/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -96,6 +96,11 @@
/* Base MTK_platform compatible GIC memory map */
#define BASE_GICD_BASE (MT_GIC_BASE)
#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
+#define DEV_IRQ_ID 580
+
+#define PLAT_MTK_G1S_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(DEV_IRQ_ID, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_LEVEL)
/*******************************************************************************
* CIRQ related constants
diff --git a/plat/mediatek/mt8192/include/platform_def.h b/plat/mediatek/mt8192/include/platform_def.h
index ec377b5..1b25e00 100644
--- a/plat/mediatek/mt8192/include/platform_def.h
+++ b/plat/mediatek/mt8192/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -82,6 +82,8 @@
#define BASE_GICD_BASE MT_GIC_BASE
#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
+#define PLAT_MTK_G1S_IRQ_PROPS(grp)
+
#define SYS_CIRQ_BASE (IO_PHYS + 0x204000)
#define CIRQ_REG_NUM 14
#define CIRQ_IRQ_NUM 439
diff --git a/plat/mediatek/mt8195/include/platform_def.h b/plat/mediatek/mt8195/include/platform_def.h
index 8696f2a..a70abec 100644
--- a/plat/mediatek/mt8195/include/platform_def.h
+++ b/plat/mediatek/mt8195/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -95,6 +95,11 @@
/* Base MTK_platform compatible GIC memory map */
#define BASE_GICD_BASE MT_GIC_BASE
#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
+#define DEV_IRQ_ID 580
+
+#define PLAT_MTK_G1S_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(DEV_IRQ_ID, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_LEVEL)
#define SYS_CIRQ_BASE (IO_PHYS + 0x204000)
#define CIRQ_REG_NUM 23
diff --git a/plat/qemu/common/qemu_bl2_setup.c b/plat/qemu/common/qemu_bl2_setup.c
index 60acb25..d752b6c 100644
--- a/plat/qemu/common/qemu_bl2_setup.c
+++ b/plat/qemu/common/qemu_bl2_setup.c
@@ -173,7 +173,8 @@
* moment we use a 8KB table, which covers 1TB of RAM (40-bit PA).
*/
if (gpt_init_l0_tables(GPCCR_PPS_1TB, PLAT_QEMU_L0_GPT_BASE,
- PLAT_QEMU_L0_GPT_SIZE) < 0) {
+ PLAT_QEMU_L0_GPT_SIZE +
+ PLAT_QEMU_GPT_BITLOCK_SIZE) < 0) {
ERROR("gpt_init_l0_tables() failed!\n");
panic();
}
diff --git a/plat/qemu/qemu/include/platform_def.h b/plat/qemu/qemu/include/platform_def.h
index 95620d3..db9d65a 100644
--- a/plat/qemu/qemu/include/platform_def.h
+++ b/plat/qemu/qemu/include/platform_def.h
@@ -342,8 +342,11 @@
* Tables
*/
#define PLAT_QEMU_L0_GPT_BASE (PLAT_QEMU_L1_GPT_BASE - \
- PLAT_QEMU_L0_GPT_SIZE)
+ (PLAT_QEMU_L0_GPT_SIZE + \
+ PLAT_QEMU_GPT_BITLOCK_SIZE))
#define PLAT_QEMU_L0_GPT_SIZE (2 * PAGE_SIZE)
+/* Two pages so the L0 GPT is naturally aligned. */
+#define PLAT_QEMU_GPT_BITLOCK_SIZE (2 * PAGE_SIZE)
#define PLAT_QEMU_L1_GPT_BASE (SEC_DRAM_BASE + SEC_DRAM_SIZE - \
PLAT_QEMU_L1_GPT_SIZE)
@@ -353,7 +356,8 @@
#define RME_GPT_DRAM_BASE PLAT_QEMU_L0_GPT_BASE
#define RME_GPT_DRAM_SIZE (PLAT_QEMU_L1_GPT_SIZE + \
- PLAT_QEMU_L0_GPT_SIZE)
+ PLAT_QEMU_L0_GPT_SIZE + \
+ PLAT_QEMU_GPT_BITLOCK_SIZE)
#ifndef __ASSEMBLER__
/* L0 table greater than 4KB must be naturally aligned */
diff --git a/plat/qemu/qemu/include/qemu_pas_def.h b/plat/qemu/qemu/include/qemu_pas_def.h
index c108920..bcbea21 100644
--- a/plat/qemu/qemu/include/qemu_pas_def.h
+++ b/plat/qemu/qemu/include/qemu_pas_def.h
@@ -22,7 +22,7 @@
* | 1GB |L0 GPT|ANY |Flash |
* 00000000 | | | |IO |
* ---------------------------------------------------------------------------
- * 224MB | 1KB |L0 GPT|ANY |Secure RAM (EL3) |
+ * 224MB | 1KB |L1 GPT|ANY |Secure RAM (EL3) |
* 0e000000 | | | | (shared) |
* ---------------------------------------------------------------------------
* | 1MB-1KB |L1 GPT|ROOT |Secure RAM (EL3) |
@@ -31,10 +31,10 @@
* 225MB | 14MB |L1 GPT|SECURE|Secure RAM |
* 0e100000 | | | | (EL2, EL1) |
* ---------------------------------------------------------------------------
- * | 1MB+8KB |L1 GPT|ROOT |L0 and L1 GPTs |
- * 0eefe000 | | | | |
+ * | 2MB |L1 GPT|ROOT |L0 and L1 GPTs, |
+ * 0edfc000 | +16KB | | | bitlocks |
* ---------------------------------------------------------------------------
- * 240MB | 800MB |L0 GPT|ANY |IO |
+ * 240MB | 800MB |L1 GPT|ANY |IO |
* 0f000000 | | | | |
* ---------------------------------------------------------------------------
* 1GB | 1MB |L1 GPT|NS |DRAM |
diff --git a/plat/st/common/stm32mp_gic.c b/plat/st/common/stm32mp_gic.c
index d02b635..a4cc4a5 100644
--- a/plat/st/common/stm32mp_gic.c
+++ b/plat/st/common/stm32mp_gic.c
@@ -1,11 +1,12 @@
/*
- * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/bl_common.h>
#include <common/debug.h>
+#include <common/fdt_wrappers.h>
#include <drivers/arm/gicv2.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <lib/utils.h>
@@ -45,25 +46,29 @@
int node;
void *fdt;
const fdt32_t *cuint;
- struct dt_node_info dt_gic;
+ uintptr_t addr;
+ int err;
if (fdt_get_address(&fdt) == 0) {
panic();
}
- node = dt_get_node(&dt_gic, -1, "arm,cortex-a7-gic");
+ node = fdt_node_offset_by_compatible(fdt, -1, "arm,cortex-a7-gic");
if (node < 0) {
panic();
}
- platform_gic_data.gicd_base = dt_gic.base;
-
- cuint = fdt_getprop(fdt, node, "reg", NULL);
- if (cuint == NULL) {
+ err = fdt_get_reg_props_by_index(fdt, node, 0, &addr, NULL);
+ if (err < 0) {
panic();
}
+ platform_gic_data.gicd_base = addr;
- platform_gic_data.gicc_base = fdt32_to_cpu(*(cuint + 2));
+ err = fdt_get_reg_props_by_index(fdt, node, 1, &addr, NULL);
+ if (err < 0) {
+ panic();
+ }
+ platform_gic_data.gicc_base = addr;
cuint = fdt_getprop(fdt, node, "#interrupt-cells", NULL);
if (cuint == NULL) {
diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
index e266615..3a752b2 100644
--- a/plat/xilinx/zynqmp/platform.mk
+++ b/plat/xilinx/zynqmp/platform.mk
@@ -2,7 +2,7 @@
# Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.
# Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved.
# Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
-# Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
@@ -16,6 +16,7 @@
IPI_CRC_CHECK := 0
override RESET_TO_BL31 := 1
override WARMBOOT_ENABLE_DCACHE_EARLY := 1
+ENABLE_LTO := 1
EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT)
diff --git a/tools/cert_create/Makefile b/tools/cert_create/Makefile
index 7670939..16f4aa3 100644
--- a/tools/cert_create/Makefile
+++ b/tools/cert_create/Makefile
@@ -18,6 +18,7 @@
include ${MAKE_HELPERS_DIRECTORY}common.mk
include ${MAKE_HELPERS_DIRECTORY}defaults.mk
include ${MAKE_HELPERS_DIRECTORY}toolchain.mk
+include ${MAKE_HELPERS_DIRECTORY}utilities.mk
ifneq (${PLAT},none)
TF_PLATFORM_ROOT := ../../plat/
@@ -60,7 +61,7 @@
HOSTCCFLAGS += -O2 -DLOG_LEVEL=20
endif
-HOSTCCFLAGS += ${DEFINES}
+HOSTCCFLAGS += ${DEFINES} -DPLAT_MSG=$(call escape-shell,"$(PLAT_MSG)")
# USING_OPENSSL3 flag will be added to the HOSTCCFLAGS variable with the proper
# computed value.
HOSTCCFLAGS += -DUSING_OPENSSL3=$(USING_OPENSSL3)
@@ -84,10 +85,7 @@
${BINARY}: ${OBJECTS} Makefile
$(s)echo " HOSTLD $@"
- $(q)echo 'const char build_msg[] = "Built : "__TIME__", "__DATE__; \
- const char platform_msg[] = "${PLAT_MSG}";' | \
- $(host-cc) -c ${HOSTCCFLAGS} -xc - -o src/build_msg.o
- $(q)$(host-cc) src/build_msg.o ${OBJECTS} ${LIB_DIR} ${LIB} -o $@
+ $(q)$(host-cc) ${OBJECTS} ${LIB_DIR} ${LIB} -o $@
%.o: %.c
$(s)echo " HOSTCC $<"
@@ -99,7 +97,7 @@
endif
clean:
- $(call SHELL_DELETE_ALL, src/build_msg.o ${OBJECTS})
+ $(call SHELL_DELETE_ALL,${OBJECTS})
realclean: clean
$(call SHELL_DELETE,${BINARY})
diff --git a/tools/cert_create/src/main.c b/tools/cert_create/src/main.c
index 14610ed..edc2d68 100644
--- a/tools/cert_create/src/main.c
+++ b/tools/cert_create/src/main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -66,10 +66,8 @@
static int save_keys;
static int print_cert;
-/* Info messages created in the Makefile */
-extern const char build_msg[];
-extern const char platform_msg[];
-
+static const char build_msg[] = "Built : " __TIME__ ", " __DATE__;
+static const char platform_msg[] = PLAT_MSG;
static char *strdup(const char *str)
{
diff --git a/tools/encrypt_fw/Makefile b/tools/encrypt_fw/Makefile
index 21309f7..0210c36 100644
--- a/tools/encrypt_fw/Makefile
+++ b/tools/encrypt_fw/Makefile
@@ -1,4 +1,5 @@
#
+# Copyright (c) 2024, Arm Limited. All rights reserved.
# Copyright (c) 2019-2022, Linaro Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
@@ -64,9 +65,7 @@
${BINARY}: ${OBJECTS} Makefile
$(s)echo " HOSTLD $@"
- $(q)echo 'const char build_msg[] = "Built : "__TIME__", "__DATE__;' | \
- $(host-cc) -c ${HOSTCCFLAGS} -xc - -o src/build_msg.o
- $(q)$(host-cc) src/build_msg.o ${OBJECTS} ${LIB_DIR} ${LIB} -o $@
+ $(q)$(host-cc) ${OBJECTS} ${LIB_DIR} ${LIB} -o $@
%.o: %.c
$(s)echo " HOSTCC $<"
@@ -78,7 +77,7 @@
endif
clean:
- $(call SHELL_DELETE_ALL, src/build_msg.o ${OBJECTS})
+ $(call SHELL_DELETE_ALL,${OBJECTS})
realclean: clean
$(call SHELL_DELETE,${BINARY})
diff --git a/tools/encrypt_fw/src/main.c b/tools/encrypt_fw/src/main.c
index 39b7af7..6e43e73 100644
--- a/tools/encrypt_fw/src/main.c
+++ b/tools/encrypt_fw/src/main.c
@@ -1,4 +1,5 @@
/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2019, Linaro Limited. All rights reserved.
* Author: Sumit Garg <sumit.garg@linaro.org>
*
@@ -25,8 +26,7 @@
/* Global options */
-/* Info messages created in the Makefile */
-extern const char build_msg[];
+static const char build_msg[] = "Built : " __TIME__ ", " __DATE__;
static char *key_algs_str[] = {
[KEY_ALG_GCM] = "gcm",