Merge "Add myself and Venkatesh Yadav Abbarapu as code owners for Xilinx platforms" into integration
diff --git a/Makefile b/Makefile
index 9614238..5c9186e 100644
--- a/Makefile
+++ b/Makefile
@@ -8,7 +8,7 @@
# Trusted Firmware Version
#
VERSION_MAJOR := 2
-VERSION_MINOR := 3
+VERSION_MINOR := 4
# Default goal is build all images
.DEFAULT_GOAL := all
diff --git a/bl32/tsp/aarch64/tsp_request.S b/bl32/tsp/aarch64/tsp_request.S
index 5ad16da..6e238ea 100644
--- a/bl32/tsp/aarch64/tsp_request.S
+++ b/bl32/tsp/aarch64/tsp_request.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,28 +9,19 @@
.globl tsp_get_magic
-
/*
* This function raises an SMC to retrieve arguments from secure
* monitor/dispatcher, saves the returned arguments the array received in x0,
* and then returns to the caller
*/
func tsp_get_magic
- /* Save address to stack */
- stp x0, xzr, [sp, #-16]!
-
/* Load arguments */
ldr w0, _tsp_fid_get_magic
/* Raise SMC */
smc #0
- /* Restore address from stack */
- ldp x4, xzr, [sp], #16
-
- /* Store returned arguments to the array */
- stp x0, x1, [x4, #0]
-
+ /* Return arguments in x1:x0 */
ret
endfunc tsp_get_magic
diff --git a/bl32/tsp/tsp_main.c b/bl32/tsp/tsp_main.c
index e947838..01c9ec5 100644
--- a/bl32/tsp/tsp_main.c
+++ b/bl32/tsp/tsp_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -363,8 +363,10 @@
uint64_t arg6,
uint64_t arg7)
{
+ uint128_t service_args;
+ uint64_t service_arg0;
+ uint64_t service_arg1;
uint64_t results[2];
- uint64_t service_args[2];
uint32_t linear_id = plat_my_core_pos();
/* Update this cpu's statistics */
@@ -387,10 +389,12 @@
results[1] = arg2;
/*
- * Request a service back from dispatcher/secure monitor. This call
- * return and thereafter resume execution
+ * Request a service back from dispatcher/secure monitor.
+ * This call returns and thereafter resumes execution.
*/
- tsp_get_magic(service_args);
+ service_args = tsp_get_magic();
+ service_arg0 = (uint64_t)service_args;
+ service_arg1 = (uint64_t)(service_args >> 64U);
#if CTX_INCLUDE_MTE_REGS
/*
@@ -403,20 +407,20 @@
/* Determine the function to perform based on the function ID */
switch (TSP_BARE_FID(func)) {
case TSP_ADD:
- results[0] += service_args[0];
- results[1] += service_args[1];
+ results[0] += service_arg0;
+ results[1] += service_arg1;
break;
case TSP_SUB:
- results[0] -= service_args[0];
- results[1] -= service_args[1];
+ results[0] -= service_arg0;
+ results[1] -= service_arg1;
break;
case TSP_MUL:
- results[0] *= service_args[0];
- results[1] *= service_args[1];
+ results[0] *= service_arg0;
+ results[1] *= service_arg1;
break;
case TSP_DIV:
- results[0] /= service_args[0] ? service_args[0] : 1;
- results[1] /= service_args[1] ? service_args[1] : 1;
+ results[0] /= service_arg0 ? service_arg0 : 1;
+ results[1] /= service_arg1 ? service_arg1 : 1;
break;
default:
break;
diff --git a/bl32/tsp/tsp_private.h b/bl32/tsp/tsp_private.h
index cbd527f..38d9732 100644
--- a/bl32/tsp/tsp_private.h
+++ b/bl32/tsp/tsp_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -61,7 +61,7 @@
*/
CASSERT(TSP_ARGS_SIZE == sizeof(tsp_args_t), assert_sp_args_size_mismatch);
-void tsp_get_magic(uint64_t args[4]);
+uint128_t tsp_get_magic(void);
tsp_args_t *tsp_cpu_resume_main(uint64_t max_off_pwrlvl,
uint64_t arg1,
diff --git a/docs/change-log.rst b/docs/change-log.rst
index 7befba4..3b8f836 100644
--- a/docs/change-log.rst
+++ b/docs/change-log.rst
@@ -4,6 +4,560 @@
This document contains a summary of the new features, changes, fixes and known
issues in each release of Trusted Firmware-A.
+Version 2.4
+-----------
+
+New Features
+^^^^^^^^^^^^
+
+- Architecture support
+ - Armv8.6-A
+ - Added support for Armv8.6 Enhanced Counter Virtualization (ECV)
+ - Added support for Armv8.6 Fine Grained Traps (FGT)
+ - Added support for Armv8.6 WFE trap delays
+
+- Bootloader images
+ - Added support for Measured Boot
+
+- Build System
+ - Added build option ``COT_DESC_IN_DTB`` to create Chain of Trust at runtime
+ - Added build option ``OPENSSL_DIR`` to direct tools to OpenSSL libraries
+ - Added build option ``RAS_TRAP_LOWER_EL_ERR_ACCESS`` to enable trapping RAS
+ register accesses from EL1/EL2 to EL3
+ - Extended build option ``BRANCH_PROTECTION`` to support branch target
+ identification
+
+- Common components
+ - Added support for exporting CPU nodes to the device tree
+ - Added support for single and dual-root Chains of Trust in secure
+ partitions
+
+- Drivers
+ - Added Broadcom RNG driver
+ - Added Marvell ``mg_conf_cm3`` driver
+ - Added System Control and Management Interface (SCMI) driver
+ - Added STMicroelectronics ETZPC driver
+
+ - Arm GICv3
+ - Added support for detecting topology at runtime
+
+ - Dual Root
+ - Added support for platform certificates
+
+ - Marvell Cache LLC
+ - Added support for mapping the entire LLC into SRAM
+
+ - Marvell CCU
+ - Added workaround for erratum 3033912
+
+ - Marvell CP110 COMPHY
+ - Added support for SATA COMPHY polarity inversion
+ - Added support for USB COMPHY polarity inversion
+ - Added workaround for erratum IPCE_COMPHY-1353
+
+ - STM32MP1 Clocks
+ - Added ``RTC`` as a gateable clock
+ - Added support for shifted clock selector bit masks
+ - Added support for using additional clocks as parents
+
+- Libraries
+ - C standard library
+ - Added support for hexadecimal and pointer format specifiers in
+ ``snprint()``
+ - Added assembly alternatives for various library functions
+
+ - CPU support
+ - Arm Cortex-A53
+ - Added workaround for erratum 1530924
+
+ - Arm Cortex-A55
+ - Added workaround for erratum 1530923
+
+ - Arm Cortex-A57
+ - Added workaround for erratum 1319537
+
+ - Arm Cortex-A76
+ - Added workaround for erratum 1165522
+ - Added workaround for erratum 1791580
+ - Added workaround for erratum 1868343
+
+ - Arm Cortex-A72
+ - Added workaround for erratum 1319367
+
+ - Arm Cortex-A77
+ - Added workaround for erratum 1508412
+ - Added workaround for erratum 1800714
+ - Added workaround for erratum 1925769
+
+ - Arm Neoverse N1
+ - Added workaround for erratum 1868343
+
+ - EL3 Runtime
+ - Added support for saving/restoring registers related to nested
+ virtualization in EL2 context switches if the architecture supports it
+
+ - FCONF
+ - Added support for Measured Boot
+ - Added support for populating Chain of Trust properties
+ - Added support for loading the ``fw_config`` image
+
+ - Measured Boot
+ - Added support for event logging
+
+- Platforms
+ - Added support for Arm Morello
+ - Added support for Arm TC0
+ - Added support for iEi PUZZLE-M801
+ - Added support for Marvell OCTEON TX2 T9130
+ - Added support for MediaTek MT8192
+ - Added support for NXP i.MX 8M Nano
+ - Added support for NXP i.MX 8M Plus
+ - Added support for QTI CHIP SC7180
+ - Added support for STM32MP151F
+ - Added support for STM32MP153F
+ - Added support for STM32MP157F
+ - Added support for STM32MP151D
+ - Added support for STM32MP153D
+ - Added support for STM32MP157D
+
+ - Arm
+ - Added support for platform-owned SPs
+ - Added support for resetting to BL31
+
+ - Arm FPGA
+ - Added support for Klein
+ - Added support for Matterhorn
+ - Added support for additional CPU clusters
+
+ - Arm FVP
+ - Added support for performing SDEI platform setup at runtime
+ - Added support for SMCCC's ``SMCCC_ARCH_SOC_ID`` command
+ - Added an ``id`` field under the NV-counter node in the device tree to
+ differentiate between trusted and non-trusted NV-counters
+ - Added support for extracting the clock frequency from the timer node
+ in the device tree
+
+ - Arm Juno
+ - Added support for SMCCC's ``SMCCC_ARCH_SOC_ID`` command
+
+ - Arm N1SDP
+ - Added support for cross-chip PCI-e
+
+ - Marvell
+ - Added support for AVS reduction
+
+ - Marvell ARMADA
+ - Added support for twin-die combined memory device
+
+ - Marvell ARMADA A8K
+ - Added support for DDR with 32-bit bus width (both ECC and non-ECC)
+
+ - Marvell AP806
+ - Added workaround for erratum FE-4265711
+
+ - Marvell AP807
+ - Added workaround for erratum 3033912
+
+ - Nvidia Tegra
+ - Added debug printouts indicating SC7 entry sequence completion
+ - Added support for SDEI
+ - Added support for stack protection
+ - Added support for GICv3
+ - Added support for SMCCC's ``SMCCC_ARCH_SOC_ID`` command
+
+ - Nvidia Tegra194
+ - Added support for RAS exception handling
+ - Added support for SPM
+
+ - NXP i.MX
+ - Added support for SDEI
+
+ - QEMU SBSA
+ - Added support for the Secure Partition Manager
+
+ - QTI
+ - Added RNG driver
+ - Added SPMI PMIC arbitrator driver
+ - Added support for SMCCC's ``SMCCC_ARCH_SOC_ID`` command
+
+ - STM32MP1
+ - Added support for exposing peripheral interfaces to the non-secure
+ world at runtime
+ - Added support for SCMI clock and reset services
+ - Added support for STM32MP15x CPU revision Z
+ - Added support for SMCCC services in ``SP_MIN``
+
+- Services
+ - Secure Payload Dispatcher
+ - Added a provision to allow clients to retrieve the service UUID
+
+ - SPMC
+ - Added secondary core endpoint information to the SPMC context
+ structure
+
+ - SPMD
+ - Added support for booting OP-TEE as a guest S-EL1 Secure Partition on
+ top of Hafnium in S-EL2
+ - Added a provision for handling SPMC messages to register secondary
+ core entry points
+ - Added support for power management operations
+
+- Tools
+ - CertCreate
+ - Added support for secure partitions
+
+ - CertTool
+ - Added support for the ``fw_config`` image
+
+ - FIPTool
+ - Added support for the ``fw_config`` image
+
+Changed
+^^^^^^^
+
+- Architecture support
+
+- Bootloader images
+
+- Build System
+ - The top-level Makefile now supports building FipTool on Windows
+ - The default value of ``KEY_SIZE`` has been changed to to 2048 when RSA is
+ in use
+ - The previously-deprecated macro ``__ASSEMBLY__`` has now been removed
+
+- Common components
+ - Certain functions that flush the console will no longer return error
+ information
+
+- Drivers
+ - Arm GIC
+ - Usage of ``drivers/arm/gic/common/gic_common.c`` has now been
+ deprecated in favour of ``drivers/arm/gic/vX/gicvX.mk``
+ - Added support for detecting the presence of a GIC600-AE
+ - Added support for detecting the presence of a GIC-Clayton
+
+ - Marvell MCI
+ - Now performs link tuning for all MCI interfaces to improve performance
+
+ - Marvell MoChi
+ - PIDI masters are no longer forced into a non-secure access level when
+ ``LLC_SRAM`` is enabled
+ - The SD/MMC controllers are now accessible from guest virtual machines
+
+ - Mbed TLS
+ - Migrated to Mbed TLS v2.24.0
+
+ - STM32 FMC2 NAND
+ - Adjusted FMC node bindings to include an EBI controller node
+
+ - STM32 Reset
+ - Added an optional timeout argument to assertion functions
+
+ - STM32MP1 Clocks
+ - Enabled several additional system clocks during initialization
+
+- Libraries
+ - C Standard Library
+ - Improved ``memset`` performance by avoiding single-byte writes
+ - Added optimized assembly variants of ``memset``
+
+ - CPU support
+ - Renamed Cortex-Hercules to Cortex-A78
+ - Renamed Cortex-Hercules AE to Cortex-A78 AE
+ - Renamed Neoverse Zeus to Neoverse V1
+
+ - Coreboot
+ - Updated ‘coreboot_get_memory_type’ API to take an extra argument as a
+ ’memory size’ that used to return a valid memory type.
+
+ - libfdt
+ - Updated to latest upstream version
+
+- Platforms
+ - Allwinner
+ - Disabled non-secure access to PRCM power control registers
+
+ - Arm
+ - ``BL32_BASE`` is now platform-dependent when ``SPD_spmd`` is enabled
+ - Added support for loading the Chain of Trust from the device tree
+ - The firmware update check is now executed only once
+ - NV-counter base addresses are now loaded from the device tree when
+ ``COT_DESC_IN_DTB`` is enabled
+ - Now loads and populates ``fw_config`` and ``tb_fw_config``
+ - FCONF population now occurs after caches have been enabled in order
+ to reduce boot times
+
+ - Arm Corstone-700
+ - Platform support has been split into both an FVP and an FPGA variant
+
+ - Arm FPGA
+ - DTB and BL33 load addresses have been given sensible default values
+ - Now reads generic timer counter frequency, GICD and GICR base
+ addresses, and UART address from DT
+ - Now treats the primary PL011 UART as an SBSA Generic UART
+
+ - Arm FVP
+ - Secure interrupt descriptions, UART parameters, clock frequencies and
+ GICv3 parameters are now queried through FCONF
+ - UART parameters are now queried through the device tree
+ - Added an owner field to Cactus secure partitions
+ - Increased the maximum size of BL2 when the Chain of Trust is loaded
+ from the device tree
+ - Reduces the maximum size of BL31
+ - The ``FVP_USE_SP804_TIMER`` and ``FVP_VE_USE_SP804_TIMER`` build
+ options have been removed in favour of a common ``USE_SP804_TIMER``
+ option
+ - Added a third Cactus partition to manifests
+ - Device tree nodes now store UUIDs in big-endian
+
+ - Arm Juno
+ - Increased the maximum size of BL2 when optimizations have not been
+ applied
+ - Reduced the maximum size of BL31 and BL32
+
+ - Marvell AP807
+ - Enabled snoop filters
+
+ - Marvell ARMADA A3K
+ - UART recovery images are now suffixed with ``.bin``
+
+ - Marvell ARMADA A8K
+ - Option ``BL31_CACHE_DISABLE`` is now disabled (``0``) by default
+
+ - Nvidia Tegra
+ - Added VPR resize supported check when processing video memory resize
+ requests
+ - Added SMMU verification to prevent potential issues caused by
+ undetected corruption of the SMMU configuration during boot
+ - The GIC CPU interface is now properly disabled after CPU off
+ - The GICv2 sources list and the ``BL31_SIZE`` definition have been made
+ platform-specific
+ - The SPE driver will no longer flush the console when writing
+ individual characters
+
+ - Nvidia Tegra194
+ - TZDRAM setup has been moved to platform-specific early boot handlers
+ - Increased verbosity of debug prints for RAS SErrors
+ - Support for powering down CPUs during CPU suspend has been removed
+ - Now verifies firewall settings before using resources
+
+ - TI K3
+ - The UART number has been made configurable through ``K3_USART``
+
+ - Rockchip RK3368
+ - The maximum number of memory map regions has been increased to 20
+
+ - Socionext Uniphier
+ - The maximum size of BL33 has been increased to support larger
+ bootloaders
+
+ - STM32
+ - Removed platform-specific DT functions in favour of using existing
+ generic alternatives
+
+ - STM32MP1
+ - Increased verbosity of exception reports in debug builds
+ - Device trees have been updated to align with the Linux kernel
+ - Now uses the ETZPC driver to configure secure-aware interfaces for
+ assignment to the non-secure world
+ - Finished good variants have been added to the board identifier
+ enumerations
+ - Non-secure access to clocks and reset domains now depends on their
+ state of registration
+ - NEON is now disabled in ``SP_MIN``
+ - The last page of ``SYSRAM`` is now used as SCMI shared memory
+ - Checks to verify platform compatibility have been added to verify that
+ an image is compatible with the chip ID of the running platform
+
+ - QEMU SBSA
+ - Removed support for Arm's Cortex-A53
+
+- Services
+ - Renamed SPCI to FF-A
+
+ - SPMD
+ - No longer forwards requests to the non-secure world when retrieving
+ partition information
+ - SPMC manifest size is now retrieved directly from SPMD instead of the
+ device tree
+ - The FF-A version handler now returns SPMD's version when the origin
+ of the call is secure, and SPMC's version when the origin of the call
+ is non-secure
+
+ - SPMC
+ - Updated the manifest to declare CPU nodes in descending order as per
+ the SPM (Hafnium) multicore requirement
+ - Updated the device tree to mark 2GB as device memory for the first
+ partition excluding trusted DRAM region (which is reserved for SPMC)
+ - Increased the number of EC contexts to the maximum number of PEs as
+ per the FF-A specification
+
+- Tools
+ - FIPTool
+ - Now returns ``0`` on ``help`` and ``help <command>``
+
+ - Marvell DoImage
+ - Updated Mbed TLS support to v2.8
+
+ - SPTool
+ - Now appends CertTool arguments
+
+Resolved Issues
+^^^^^^^^^^^^^^^
+
+- Bootloader images
+ - Fixed compilation errors for dual-root Chains of Trust caused by symbol
+ collision
+
+ - BL31
+ - Fixed compilation errors on platforms with fewer than 4 cores caused
+ by initialization code exceeding the end of the stacks
+ - Fixed compilation errors when building a position-independent image
+
+- Build System
+ - Fixed invalid empty version strings
+ - Fixed compilation errors on Windows caused by a non-portable architecture
+ revision comparison
+
+- Drivers
+ - Arm GIC
+ - Fixed spurious interrupts caused by a missing barrier
+
+ - STM32 Flexible Memory Controller 2 (FMC2) NAND driver
+ - Fixed runtime instability caused by incorrect error detection logic
+
+ - STM32MP1 Clock driver
+ - Fixed incorrectly-formatted log messages
+ - Fixed runtime instability caused by improper clock gating procedures
+
+ - STMicroelectronics Raw NAND driver
+ - Fixed runtime instability caused by incorrect unit conversion when
+ waiting for NAND readiness
+
+- Libraries
+ - AMU
+ - Fixed timeout errors caused by excess error logging
+
+ - EL3 Runtime
+ - Fixed runtime instability caused by improper register save/restore
+ routine in EL2
+
+ - FCONF
+ - Fixed failure to initialize GICv3 caused by overly-strict device tree
+ requirements
+
+ - Measured Boot
+ - Fixed driver errors caused by a missing default value for the
+ ``HASH_ALG`` build option
+
+ - SPE
+ - Fixed feature detection check that prevented CPUs supporting SVE from
+ detecting support for SPE in the non-secure world
+
+ - Translation Tables
+ - Fixed various MISRA-C 2012 static analysis violations
+
+- Platforms
+ - Allwinner A64
+ - Fixed USB issues on certain battery-powered device caused by
+ improperly activated USB power rail
+
+ - Arm
+ - Fixed compilation errors caused by increase in BL2 size
+ - Fixed compilation errors caused by missing Makefile dependencies to
+ generated files when building the FIP
+ - Fixed MISRA-C 2012 static analysis violations caused by unused
+ structures in include directives intended to be feature-gated
+
+ - Arm FPGA
+ - Fixed initialization issues caused by incorrect MPIDR topology mapping
+ logic
+
+ - Arm RD-N1-edge
+ - Fixed compilation errors caused by mismatched parentheses in Makefile
+
+ - Arm SGI
+ - Fixed crashes due to the flash memory used for cold reboot attack
+ protection not being mapped
+
+ - Intel Agilex
+ - Fixed initialization issues caused by several compounding bugs
+
+ - Marvell
+ - Fixed compilation warnings caused by multiple Makefile inclusions
+
+ - Marvell ARMADA A3K
+ - Fixed boot issue in debug builds caused by checks on the BL33 load
+ address that are not appropriate for this platform
+
+ - Nvidia Tegra
+ - Fixed incorrect delay timer reads
+ - Fixed spurious interrupts in the non-secure world during cold boot
+ caused by the arbitration bit in the memory controller not being
+ cleared
+ - Fixed faulty video memory resize sequence
+
+ - Nvidia Tegra194
+ - Fixed incorrect alignment of TZDRAM base address
+
+ - NXP iMX8M
+ - Fixed CPU hot-plug issues caused by race condition
+
+ - STM32MP1
+ - Fixed compilation errors in highly-parallel builds caused by incorrect
+ Makefile dependencies
+
+ - STM32MP157C-ED1
+ - Fixed initialization issues caused by missing device tree hash node
+
+ - Raspberry Pi 3
+ - Fixed compilation errors caused by incorrect dependency ordering in
+ Makefile
+
+ - Rockchip
+ - Fixed initialization issues caused by non-critical errors when parsing
+ FDT being treated as critical
+
+ - Rockchip RK3368
+ - Fixed runtime instability caused by incorrect CPUID shift value
+
+ - QEMU
+ - Fixed compilation errors caused by incorrect dependency ordering in
+ Makefile
+
+ - QEMU SBSA
+ - Fixed initialization issues caused by FDT exceeding reserved memory
+ size
+
+ - QTI
+ - Fixed compilation errors caused by inclusion of a non-existent file
+
+- Services
+ - FF-A (previously SPCI)
+ - Fixed SPMD aborts caused by incorrect behaviour when the manifest is
+ page-aligned
+
+- Tools
+ - Fixed compilation issues when compiling tools from within their respective
+ directories
+
+ - FIPTool
+ - Fixed command line parsing issues on Windows when using arguments
+ whose names also happen to be a subset of another's
+
+ - Marvell DoImage
+ - Fixed PKCS signature verification errors at boot on some platforms
+ caused by generation of misaligned images
+
+Known Issues
+^^^^^^^^^^^^
+
+- Platforms
+ - NVIDIA Tegra
+ - Signed comparison compiler warnings occurring in libfdt are currently
+ being worked around by disabling the warning for the platform until
+ the underlying issue is resolved in libfdt
+
Version 2.3
-----------
@@ -32,7 +586,7 @@
- Build System
- Add support for documentation build as a target in Makefile
- - Add ``COT`` build option to select the chain of trust to use when the
+ - Add ``COT`` build option to select the Chain of Trust to use when the
Trusted Boot feature is enabled (default: ``tbbr``).
- Added creation and injection of secure partition packages into the FIP.
diff --git a/docs/components/psa-ffa-manifest-binding.rst b/docs/components/psa-ffa-manifest-binding.rst
index 09894ae..af79074 100644
--- a/docs/components/psa-ffa-manifest-binding.rst
+++ b/docs/components/psa-ffa-manifest-binding.rst
@@ -13,7 +13,7 @@
- compatible [mandatory]
- value type: <string>
- Must be the string "arm,ffa-manifest-X.Y" which specifies the major and
- minor versions fo the device tree binding for the FFA manifest represented
+ minor versions of the device tree binding for the FFA manifest represented
by this node. The minor number is incremented if the binding changes in a
backwards compatible manner.
@@ -240,7 +240,7 @@
- exclusive-access
- value type: <empty>
- Presence of this field implies that this endpoint must be granted exclusive
- access and ownership of this devices's MMIO region.
+ access and ownership of this device's MMIO region.
--------------
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index c976b8b..e901e0c 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -241,9 +241,6 @@
- ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76
CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
-- ``ERRATA_A76_1800710``: This applies errata 1800710 workaround to Cortex-A76
- CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
-
- ``ERRATA_A76_1165522``: This applies errata 1165522 workaround to all
revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to
limitation of errata framework this errata is applied to all revisions
@@ -257,9 +254,6 @@
- ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77
CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
-- ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77
- CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
-
- ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77
CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
@@ -369,10 +363,11 @@
Cortex-A57 based platform must make its own decision on whether to use
the optimization. This flag is disabled by default.
-- ``NEOVERSE_N1_EXTERNAL_LLC``: This flag indicates that an external last
+- ``NEOVERSE_Nx_EXTERNAL_LLC``: This flag indicates that an external last
level cache(LLC) is present in the system, and that the DataSource field
on the master CHI interface indicates when data is returned from the LLC.
This is used to control how the LL_CACHE* PMU events count.
+ Default value is 0 (Disabled).
--------------
diff --git a/docs/getting_started/porting-guide.rst b/docs/getting_started/porting-guide.rst
index 19e26e4..d063ec7 100644
--- a/docs/getting_started/porting-guide.rst
+++ b/docs/getting_started/porting-guide.rst
@@ -116,7 +116,7 @@
by ``plat/common/aarch64/platform_mp_stack.S`` and
``plat/common/aarch64/platform_up_stack.S``.
-- **define : CACHE_WRITEBACK_GRANULE**
+- **#define : CACHE_WRITEBACK_GRANULE**
Defines the size in bits of the largest cache line across all the cache
levels in the platform.
diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst
index e21fb3c..54182cb 100644
--- a/docs/plat/marvell/armada/build.rst
+++ b/docs/plat/marvell/armada/build.rst
@@ -61,17 +61,17 @@
Defines the level of logging which will be purged to the default output port.
- LOG_LEVEL_NONE 0
- LOG_LEVEL_ERROR 10
- LOG_LEVEL_NOTICE 20
- LOG_LEVEL_WARNING 30
- LOG_LEVEL_INFO 40
- LOG_LEVEL_VERBOSE 50
+ - 0 - LOG_LEVEL_NONE
+ - 10 - LOG_LEVEL_ERROR
+ - 20 - LOG_LEVEL_NOTICE (default for DEBUG=0)
+ - 30 - LOG_LEVEL_WARNING
+ - 40 - LOG_LEVEL_INFO (default for DEBUG=1)
+ - 50 - LOG_LEVEL_VERBOSE
- USE_COHERENT_MEM
This flag determines whether to include the coherent memory region in the
- BL memory map or not.
+ BL memory map or not. Enabled by default.
- LLC_ENABLE
@@ -122,25 +122,25 @@
For Armada37x0 only, the DDR topology map index/name, default is 0.
Supported Options:
- - DDR3 1CS (0): DB-88F3720-DDR3-Modular (512MB); EspressoBIN (512MB)
- - DDR4 1CS (1): DB-88F3720-DDR4-Modular (512MB)
- - DDR3 2CS (2): EspressoBIN V3-V5 (1GB 2CS)
- - DDR4 2CS (3): DB-88F3720-DDR4-Modular (4GB)
- - DDR3 1CS (4): DB-88F3720-DDR3-Modular (1GB); EspressoBIN V3-V5 (1GB 1CS)
- - DDR4 1CS (5): EspressoBin V7 (1GB)
- - DDR4 2CS (6): EspressoBin V7 (2GB)
- - DDR3 2CS (7): EspressoBin V3-V5 (2GB)
- - CUSTOMER (CUST): Customer board, DDR3 1CS 512MB
+ - 0 - DDR3 1CS: DB-88F3720-DDR3-Modular (512MB); EspressoBIN (512MB)
+ - 1 - DDR4 1CS: DB-88F3720-DDR4-Modular (512MB)
+ - 2 - DDR3 2CS: EspressoBIN V3-V5 (1GB 2CS)
+ - 3 - DDR4 2CS: DB-88F3720-DDR4-Modular (4GB)
+ - 4 - DDR3 1CS: DB-88F3720-DDR3-Modular (1GB); EspressoBIN V3-V5 (1GB 1CS)
+ - 5 - DDR4 1CS: EspressoBin V7 (1GB)
+ - 6 - DDR4 2CS: EspressoBin V7 (2GB)
+ - 7 - DDR3 2CS: EspressoBin V3-V5 (2GB)
+ - CUST - CUSTOMER: Customer board, DDR3 1CS 512MB
- CLOCKSPRESET
For Armada37x0 only, the clock tree configuration preset including CPU and DDR frequency,
default is CPU_800_DDR_800.
- - CPU_600_DDR_600 - CPU at 600 MHz, DDR at 600 MHz
- - CPU_800_DDR_800 - CPU at 800 MHz, DDR at 800 MHz
- - CPU_1000_DDR_800 - CPU at 1000 MHz, DDR at 800 MHz
- - CPU_1200_DDR_750 - CPU at 1200 MHz, DDR at 750 MHz
+ - CPU_600_DDR_600 - CPU at 600 MHz, DDR at 600 MHz
+ - CPU_800_DDR_800 - CPU at 800 MHz, DDR at 800 MHz
+ - CPU_1000_DDR_800 - CPU at 1000 MHz, DDR at 800 MHz
+ - CPU_1200_DDR_750 - CPU at 1200 MHz, DDR at 750 MHz
- BOOTDEV
@@ -176,33 +176,48 @@
- WTP
- For Armada37x0 only, use this parameter to point to wtptools source code
- directory, which can be found as a3700_utils.zip in the release. Usage
- example: ``WTP=/path/to/a3700_utils``
+ For Armada37x0 only, use this parameter to point to wtptools source code
+ directory, which can be found as a3700_utils.zip in the release. Usage
+ example: ``WTP=/path/to/a3700_utils``
- For example, in order to build the image in debug mode with log level up to 'notice' level run
+- CRYPTOPP_PATH
- .. code:: shell
+ For Armada37x0 only, use this parameter tp point to Crypto++ source code
+ directory, which is required for building WTP image tool.
- > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 PLAT=<MARVELL_PLATFORM> all fip
- And if we want to build a Armada37x0 image in debug mode with log level up to 'notice' level,
- the image has the preset CPU at 1000 MHz, preset DDR3 at 800 MHz, the DDR topology of DDR4 2CS,
- the image boot from SPI NOR flash partition 0, and the image is non trusted in WTP, the command
- line is as following
+For example, in order to build the image in debug mode with log level up to 'notice' level run
- .. code:: shell
+.. code:: shell
+
+ > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 PLAT=<MARVELL_PLATFORM> mrvl_flash
- > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 CLOCKSPRESET=CPU_1000_DDR_800 \
- MARVELL_SECURE_BOOT=0 DDR_TOPOLOGY=3 BOOTDEV=SPINOR PARTNUM=0 PLAT=a3700 all fip
+And if we want to build a Armada37x0 image in debug mode with log level up to 'notice' level,
+the image has the preset CPU at 1000 MHz, preset DDR3 at 800 MHz, the DDR topology of DDR4 2CS,
+the image boot from SPI NOR flash partition 0, and the image is non trusted in WTP, the command
+line is as following
- Supported MARVELL_PLATFORM are:
- - a3700 (for both A3720 DB and EspressoBin)
- - a70x0
- - a70x0_amc (for AMC board)
- - a80x0
- - a80x0_mcbin (for MacchiatoBin)
- - t9130 (OcteonTX2 CN913x)
+.. code:: shell
+
+ > make DEBUG=1 USE_COHERENT_MEM=0 LOG_LEVEL=20 CLOCKSPRESET=CPU_1000_DDR_800 \
+ MARVELL_SECURE_BOOT=0 DDR_TOPOLOGY=3 BOOTDEV=SPINOR PARTNUM=0 PLAT=a3700 \
+ MV_DDR_PATH=/path/to/mv-ddr-marvell/ WTP=/path/to/A3700-utils-marvell/ \
+ CRYPTOPP_PATH=/path/to/cryptopp/ BL33=/path/to/u-boot.bin \
+ all fip mrvl_bootimage mrvl_flash
+
+To build just TF-A without WTMI image (useful for A3720 Turris MOX board), run following command:
+
+.. code:: shell
+
+ > make USE_COHERENT_MEM=0 PLAT=a3700 BL33=/path/to/u-boot.bin CROSS_COMPILE=aarch64-linux-gnu- mrvl_bootimage
+
+Supported MARVELL_PLATFORM are:
+ - a3700 (for both A3720 DB and EspressoBin)
+ - a70x0
+ - a70x0_amc (for AMC board)
+ - a80x0
+ - a80x0_mcbin (for MacchiatoBin)
+ - t9130 (OcteonTX2 CN913x)
Special Build Flags
--------------------
@@ -224,7 +239,7 @@
Build output
------------
-Marvell's TF-A compilation generates 7 files:
+Marvell's TF-A compilation generates 8 files:
- ble.bin - BLe image
- bl1.bin - BL1 image
@@ -234,7 +249,13 @@
- boot-image.bin - TF-A image (contains BL1 and FIP images)
- flash-image.bin - Image which contains boot-image.bin and SPL image.
Should be placed on the boot flash/device.
+ - uart-images.tgz.bin - GZIPed TAR archive which contains Armada37x0 images
+ for booting via UART. Could be loaded via Marvell's WtpDownload tool from
+ A3700-utils-marvell repository.
+Additional make target ``mrvl_bootimage`` produce ``boot-image.bin`` file and target
+``mrvl_flash`` produce final ``flash-image.bin`` and ``uart-images.tgz.bin`` files.
+
Tools and external components installation
------------------------------------------
@@ -269,6 +290,10 @@
https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git
+(4) Crypto++ library available at the following repository:
+
+ https://github.com/weidai11/cryptopp.git
+
Armada70x0 and Armada80x0 Builds require installation of an additional component
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/docs/process/coding-style.rst b/docs/process/coding-style.rst
index 94fd85e..be13b14 100644
--- a/docs/process/coding-style.rst
+++ b/docs/process/coding-style.rst
@@ -101,7 +101,7 @@
parentheses.
Control statements (``if``, ``for``, ``switch``, ``while``, etc) must be
-separated from the following open paranthesis by a single space. The previous
+separated from the following open parenthesis by a single space. The previous
example illustrates this for an ``if`` statement.
Line Length
diff --git a/fdts/morello-fvp.dts b/fdts/morello-fvp.dts
index 2218b2a..699dc23 100644
--- a/fdts/morello-fvp.dts
+++ b/fdts/morello-fvp.dts
@@ -80,8 +80,14 @@
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
};
+ virtio_net@1c180000 {
+ compatible = "virtio,mmio";
+ reg = <0x0 0x1c180000 0x0 0x200>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
virtio_rng@1c190000 {
- compatible = "virtio,mmio","virtio-rng";
+ compatible = "virtio,mmio";
reg = <0x0 0x1c190000 0x0 0x200>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
};
diff --git a/include/lib/cpus/aarch64/cortex_a76.h b/include/lib/cpus/aarch64/cortex_a76.h
index b522e8e..a61825f 100644
--- a/include/lib/cpus/aarch64/cortex_a76.h
+++ b/include/lib/cpus/aarch64/cortex_a76.h
@@ -20,7 +20,6 @@
#define CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 (ULL(3) << 24)
#define CORTEX_A76_CPUECTLR_EL1_BIT_51 (ULL(1) << 51)
-#define CORTEX_A76_CPUECTLR_EL1_BIT_53 (ULL(1) << 53)
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
diff --git a/include/lib/cpus/aarch64/cortex_a77.h b/include/lib/cpus/aarch64/cortex_a77.h
index ed84c0f..0a42a5d 100644
--- a/include/lib/cpus/aarch64/cortex_a77.h
+++ b/include/lib/cpus/aarch64/cortex_a77.h
@@ -17,7 +17,6 @@
******************************************************************************/
#define CORTEX_A77_CPUECTLR_EL1 S3_0_C15_C1_4
#define CORTEX_A77_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
-#define CORTEX_A77_CPUECTLR_EL1_BIT_53 (ULL(1) << 53)
/*******************************************************************************
* CPU Power Control register specific definitions.
diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h
index 9998b93..b50befa 100644
--- a/include/lib/cpus/aarch64/neoverse_n1.h
+++ b/include/lib/cpus/aarch64/neoverse_n1.h
@@ -64,12 +64,4 @@
#define CPUPOR_EL3 S3_6_C15_C8_2
#define CPUPMR_EL3 S3_6_C15_C8_3
-/******************************************************************************
- * CPU Configuration register definitions.
- *****************************************************************************/
-#define CPUCFR_EL1 S3_0_C15_C0_0
-
-/* SCU bit of CPU Configuration Register, EL1 */
-#define SCU_SHIFT U(2)
-
#endif /* NEOVERSE_N1_H */
diff --git a/include/lib/cpus/aarch64/neoverse_n2.h b/include/lib/cpus/aarch64/neoverse_n2.h
new file mode 100644
index 0000000..7cbd8c1
--- /dev/null
+++ b/include/lib/cpus/aarch64/neoverse_n2.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NEOVERSE_N2_H
+#define NEOVERSE_N2_H
+
+/* Neoverse N2 ID register for revision r0p0 */
+#define NEOVERSE_N2_MIDR U(0x410FD490)
+
+/*******************************************************************************
+ * CPU Power control register
+ ******************************************************************************/
+#define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions.
+ ******************************************************************************/
+#define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4
+#define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
+
+/*******************************************************************************
+ * CPU Auxiliary Control register specific definitions.
+ ******************************************************************************/
+#define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1
+#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
+
+#endif /* NEOVERSE_N2_H */
diff --git a/include/lib/cpus/aarch64/neoverse_n_common.h b/include/lib/cpus/aarch64/neoverse_n_common.h
new file mode 100644
index 0000000..7cb91cd
--- /dev/null
+++ b/include/lib/cpus/aarch64/neoverse_n_common.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NEOVERSE_N_COMMON_H
+#define NEOVERSE_N_COMMON_H
+
+/******************************************************************************
+ * Neoverse Nx CPU Configuration register definitions
+ *****************************************************************************/
+#define CPUCFR_EL1 S3_0_C15_C0_0
+
+/* SCU bit of CPU Configuration Register, EL1 */
+#define SCU_SHIFT U(2)
+
+#endif /* NEOVERSE_N_COMMON_H */
diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S
index 98a1183..2c99cdc 100644
--- a/lib/cpus/aarch64/cortex_a76.S
+++ b/lib/cpus/aarch64/cortex_a76.S
@@ -382,35 +382,6 @@
endfunc check_errata_1791580
/* --------------------------------------------------
- * Errata Workaround for Cortex A76 Errata #1800710.
- * This applies to revision <= r4p0 of Cortex A76.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a76_1800710_wa
- /* Compare x0 against revision <= r4p0 */
- mov x17, x30
- bl check_errata_1800710
- cbz x0, 1f
-
- /* Disable allocation of splintered pages in the L2 TLB */
- mrs x1, CORTEX_A76_CPUECTLR_EL1
- orr x1, x1, CORTEX_A76_CPUECTLR_EL1_BIT_53
- msr CORTEX_A76_CPUECTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a76_1800710_wa
-
-func check_errata_1800710
- /* Applies to everything <= r4p0 */
- mov x1, #0x40
- b cpu_rev_var_ls
-endfunc check_errata_1800710
-
- /* --------------------------------------------------
* Errata Workaround for Cortex A76 Errata #1262606,
* #1275112, and #1868343. #1262606 and #1275112
* apply to revisions <= r3p0 and #1868343 applies to
@@ -538,11 +509,6 @@
bl errata_a76_1791580_wa
#endif
-#if ERRATA_A76_1800710
- mov x0, x18
- bl errata_a76_1800710_wa
-#endif
-
#if WORKAROUND_CVE_2018_3639
/* If the PE implements SSBS, we don't need the dynamic workaround */
mrs x0, id_aa64pfr1_el1
@@ -624,7 +590,6 @@
report_errata ERRATA_A76_1275112, cortex_a76, 1275112
report_errata ERRATA_A76_1286807, cortex_a76, 1286807
report_errata ERRATA_A76_1791580, cortex_a76, 1791580
- report_errata ERRATA_A76_1800710, cortex_a76, 1800710
report_errata ERRATA_A76_1165522, cortex_a76, 1165522
report_errata ERRATA_A76_1868343, cortex_a76, 1868343
report_errata WORKAROUND_CVE_2018_3639, cortex_a76, cve_2018_3639
diff --git a/lib/cpus/aarch64/cortex_a77.S b/lib/cpus/aarch64/cortex_a77.S
index 04a610e..e3a6f5f 100644
--- a/lib/cpus/aarch64/cortex_a77.S
+++ b/lib/cpus/aarch64/cortex_a77.S
@@ -86,35 +86,6 @@
endfunc check_errata_1508412_0
/* --------------------------------------------------
- * Errata Workaround for Cortex A77 Errata #1800714.
- * This applies to revision <= r1p1 of Cortex A77.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a77_1800714_wa
- /* Compare x0 against revision <= r1p1 */
- mov x17, x30
- bl check_errata_1800714
- cbz x0, 1f
-
- /* Disable allocation of splintered pages in the L2 TLB */
- mrs x1, CORTEX_A77_CPUECTLR_EL1
- orr x1, x1, CORTEX_A77_CPUECTLR_EL1_BIT_53
- msr CORTEX_A77_CPUECTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a77_1800714_wa
-
-func check_errata_1800714
- /* Applies to everything <= r1p1 */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_1800714
-
- /* --------------------------------------------------
* Errata Workaround for Cortex A77 Errata #1925769.
* This applies to revision <= r1p1 of Cortex A77.
* Inputs:
@@ -158,11 +129,6 @@
bl errata_a77_1508412_wa
#endif
-#if ERRATA_A77_1800714
- mov x0, x18
- bl errata_a77_1800714_wa
-#endif
-
#if ERRATA_A77_1925769
mov x0, x18
bl errata_a77_1925769_wa
@@ -202,7 +168,6 @@
* checking functions of each errata.
*/
report_errata ERRATA_A77_1508412, cortex_a77, 1508412
- report_errata ERRATA_A77_1800714, cortex_a77, 1800714
report_errata ERRATA_A77_1925769, cortex_a77, 1925769
ldp x8, x30, [sp], #16
diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S
index 03ee472..96891be 100644
--- a/lib/cpus/aarch64/neoverse_n1.S
+++ b/lib/cpus/aarch64/neoverse_n1.S
@@ -1,15 +1,15 @@
/*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
-#include <neoverse_n1.h>
#include <cpuamu.h>
#include <cpu_macros.S>
#include <context.h>
+#include <neoverse_n1.h>
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
@@ -22,19 +22,6 @@
#endif
.global neoverse_n1_errata_ic_trap_handler
- .global is_scu_present_in_dsu
-
-/*
- * Check DSU is configured with SCU and L3 unit
- * 1-> SCU present
- * 0-> SCU not present
- */
-func is_scu_present_in_dsu
- mrs x0, CPUCFR_EL1
- ubfx x0, x0, #SCU_SHIFT, #1
- eor x0, x0, #1
- ret
-endfunc is_scu_present_in_dsu
/* --------------------------------------------------
* Errata Workaround for Neoverse N1 Erratum 1043202.
@@ -515,7 +502,7 @@
msr CPUAMCNTENSET_EL0, x0
#endif
-#if NEOVERSE_N1_EXTERNAL_LLC
+#if NEOVERSE_Nx_EXTERNAL_LLC
/* Some system may have External LLC, core needs to be made aware */
mrs x0, NEOVERSE_N1_CPUECTLR_EL1
orr x0, x0, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT
diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S
new file mode 100644
index 0000000..8d646cb
--- /dev/null
+++ b/lib/cpus/aarch64/neoverse_n2.S
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <cpu_macros.S>
+#include <neoverse_n2.h>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Neoverse N2 must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+ /* -------------------------------------------------
+ * The CPU Ops reset function for Neoverse N2.
+ * -------------------------------------------------
+ */
+func neoverse_n2_reset_func
+ /* Check if the PE implements SSBS */
+ mrs x0, id_aa64pfr1_el1
+ tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT)
+ b.eq 1f
+
+ /* Disable speculative loads */
+ msr SSBS, xzr
+1:
+ /* Force all cacheable atomic instructions to be near */
+ mrs x0, NEOVERSE_N2_CPUACTLR2_EL1
+ orr x0, x0, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_2
+ msr NEOVERSE_N2_CPUACTLR2_EL1, x0
+
+#if ENABLE_AMU
+ /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
+ mrs x0, cptr_el3
+ orr x0, x0, #TAM_BIT
+ msr cptr_el3, x0
+
+ /* Make sure accesses from EL0/EL1 are not trapped to EL2 */
+ mrs x0, cptr_el2
+ orr x0, x0, #TAM_BIT
+ msr cptr_el2, x0
+
+ /* No need to enable the counters as this would be done at el3 exit */
+#endif
+
+#if NEOVERSE_Nx_EXTERNAL_LLC
+ /* Some systems may have External LLC, core needs to be made aware */
+ mrs x0, NEOVERSE_N2_CPUECTLR_EL1
+ orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT
+ msr NEOVERSE_N2_CPUECTLR_EL1, x0
+#endif
+
+ isb
+ ret
+endfunc neoverse_n2_reset_func
+
+func neoverse_n2_core_pwr_dwn
+ /* ---------------------------------------------
+ * Enable CPU power down bit in power control register
+ * No need to do cache maintenance here.
+ * ---------------------------------------------
+ */
+ mrs x0, NEOVERSE_N2_CPUPWRCTLR_EL1
+ orr x0, x0, #NEOVERSE_N2_CORE_PWRDN_EN_BIT
+ msr NEOVERSE_N2_CPUPWRCTLR_EL1, x0
+ isb
+ ret
+endfunc neoverse_n2_core_pwr_dwn
+
+#if REPORT_ERRATA
+/*
+ * Errata printing function for Neoverse N2 cores. Must follow AAPCS.
+ */
+func neoverse_n2_errata_report
+ /* No errata reported for Neoverse N2 cores */
+ ret
+endfunc neoverse_n2_errata_report
+#endif
+
+ /* ---------------------------------------------
+ * This function provides Neoverse N2 specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ASCII and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.neoverse_n2_regs, "aS"
+neoverse_n2_regs: /* The ASCII list of register names to be reported */
+ .asciz "cpupwrctlr_el1", ""
+
+func neoverse_n2_cpu_reg_dump
+ adr x6, neoverse_n2_regs
+ mrs x8, NEOVERSE_N2_CPUPWRCTLR_EL1
+ ret
+endfunc neoverse_n2_cpu_reg_dump
+
+declare_cpu_ops neoverse_n2, NEOVERSE_N2_MIDR, \
+ neoverse_n2_reset_func, \
+ neoverse_n2_core_pwr_dwn
diff --git a/lib/cpus/aarch64/neoverse_n_common.S b/lib/cpus/aarch64/neoverse_n_common.S
new file mode 100644
index 0000000..b816342
--- /dev/null
+++ b/lib/cpus/aarch64/neoverse_n_common.S
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <asm_macros.S>
+#include <neoverse_n_common.h>
+
+ .global is_scu_present_in_dsu
+
+/*
+ * Check if the SCU L3 Unit is present on the DSU
+ * 1-> SCU present
+ * 0-> SCU not present
+ *
+ * This function is implemented as weak on dsu_helpers.S and must be
+ * overwritten for Neoverse Nx cores.
+ */
+
+func is_scu_present_in_dsu
+ mrs x0, CPUCFR_EL1
+ ubfx x0, x0, #SCU_SHIFT, #1
+ eor x0, x0, #1
+ ret
+endfunc is_scu_present_in_dsu
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 1210538..084e6e7 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -25,9 +25,9 @@
WORKAROUND_CVE_2018_3639 ?=1
DYNAMIC_WORKAROUND_CVE_2018_3639 ?=0
-# Flag to indicate internal or external Last level cache
+# Flags to indicate internal or external Last level cache
# By default internal
-NEOVERSE_N1_EXTERNAL_LLC ?=0
+NEOVERSE_Nx_EXTERNAL_LLC ?=0
# Process A57_ENABLE_NONCACHEABLE_LOAD_FWD flag
$(eval $(call assert_boolean,A57_ENABLE_NONCACHEABLE_LOAD_FWD))
@@ -56,8 +56,8 @@
$(eval $(call assert_boolean,DYNAMIC_WORKAROUND_CVE_2018_3639))
$(eval $(call add_define,DYNAMIC_WORKAROUND_CVE_2018_3639))
-$(eval $(call assert_boolean,NEOVERSE_N1_EXTERNAL_LLC))
-$(eval $(call add_define,NEOVERSE_N1_EXTERNAL_LLC))
+$(eval $(call assert_boolean,NEOVERSE_Nx_EXTERNAL_LLC))
+$(eval $(call add_define,NEOVERSE_Nx_EXTERNAL_LLC))
ifneq (${DYNAMIC_WORKAROUND_CVE_2018_3639},0)
ifeq (${WORKAROUND_CVE_2018_3639},0)
@@ -270,10 +270,6 @@
# only to revision <= r4p0 of the Cortex A76 cpu.
ERRATA_A76_1791580 ?=0
-# Flag to apply erratum 1800710 workaround during reset. This erratum applies
-# only to revision <= r4p0 of the Cortex A76 cpu.
-ERRATA_A76_1800710 ?=0
-
# Flag to apply erratum 1165522 workaround during reset. This erratum applies
# to all revisions of Cortex A76 cpu.
ERRATA_A76_1165522 ?=0
@@ -286,10 +282,6 @@
# only to revision <= r1p0 of the Cortex A77 cpu.
ERRATA_A77_1508412 ?=0
-# Flag to apply erratum 1800714 workaround during reset. This erratum applies
-# only to revision <= r1p1 of the Cortex A77 cpu.
-ERRATA_A77_1800714 ?=0
-
# Flag to apply erratum 1925769 workaround during reset. This erratum applies
# only to revision <= r1p1 of the Cortex A77 cpu.
ERRATA_A77_1925769 ?=0
@@ -555,10 +547,6 @@
$(eval $(call assert_boolean,ERRATA_A76_1791580))
$(eval $(call add_define,ERRATA_A76_1791580))
-# Process ERRATA_A76_1800710 flag
-$(eval $(call assert_boolean,ERRATA_A76_1800710))
-$(eval $(call add_define,ERRATA_A76_1800710))
-
# Process ERRATA_A76_1165522 flag
$(eval $(call assert_boolean,ERRATA_A76_1165522))
$(eval $(call add_define,ERRATA_A76_1165522))
@@ -571,10 +559,6 @@
$(eval $(call assert_boolean,ERRATA_A77_1508412))
$(eval $(call add_define,ERRATA_A77_1508412))
-# Process ERRATA_A77_1800714 flag
-$(eval $(call assert_boolean,ERRATA_A77_1800714))
-$(eval $(call add_define,ERRATA_A77_1800714))
-
# Process ERRATA_A77_1925769 flag
$(eval $(call assert_boolean,ERRATA_A77_1925769))
$(eval $(call add_define,ERRATA_A77_1925769))
diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk
index 4b751fb..3ac1c01 100644
--- a/plat/arm/board/arm_fpga/platform.mk
+++ b/plat/arm/board/arm_fpga/platform.mk
@@ -59,7 +59,9 @@
lib/cpus/aarch64/cortex_a76ae.S \
lib/cpus/aarch64/cortex_a77.S \
lib/cpus/aarch64/cortex_a78.S \
+ lib/cpus/aarch64/neoverse_n_common.S \
lib/cpus/aarch64/neoverse_n1.S \
+ lib/cpus/aarch64/neoverse_n2.S \
lib/cpus/aarch64/neoverse_e1.S \
lib/cpus/aarch64/neoverse_v1.S \
lib/cpus/aarch64/cortex_a78_ae.S \
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 4da0d76..0a6fa56 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -118,7 +118,9 @@
lib/cpus/aarch64/cortex_a76ae.S \
lib/cpus/aarch64/cortex_a77.S \
lib/cpus/aarch64/cortex_a78.S \
+ lib/cpus/aarch64/neoverse_n_common.S \
lib/cpus/aarch64/neoverse_n1.S \
+ lib/cpus/aarch64/neoverse_n2.S \
lib/cpus/aarch64/neoverse_e1.S \
lib/cpus/aarch64/neoverse_v1.S \
lib/cpus/aarch64/cortex_a78_ae.S \
diff --git a/plat/arm/board/n1sdp/platform.mk b/plat/arm/board/n1sdp/platform.mk
index 4b621e3..f20397a 100644
--- a/plat/arm/board/n1sdp/platform.mk
+++ b/plat/arm/board/n1sdp/platform.mk
@@ -69,7 +69,7 @@
USE_COHERENT_MEM := 0
# Enable the flag since N1SDP has a system level cache
-NEOVERSE_N1_EXTERNAL_LLC := 1
+NEOVERSE_Nx_EXTERNAL_LLC := 1
include plat/arm/common/arm_common.mk
include plat/arm/css/common/css_common.mk
include plat/arm/board/common/board_common.mk
diff --git a/plat/common/aarch64/platform_mp_stack.S b/plat/common/aarch64/platform_mp_stack.S
index c34a4cf..c0668ea 100644
--- a/plat/common/aarch64/platform_mp_stack.S
+++ b/plat/common/aarch64/platform_mp_stack.S
@@ -14,7 +14,7 @@
.weak plat_set_my_stack
/* ---------------------------------------------------------------------
- * When the compatility layer is disabled, the platform APIs
+ * When the compatibility layer is disabled, the platform APIs
* plat_get_my_stack() and plat_set_my_stack() are supported by the
* platform and the previous APIs platform_get_stack() and
* platform_set_stack() are defined in terms of new APIs making use of
diff --git a/plat/marvell/armada/a3k/common/a3700_common.mk b/plat/marvell/armada/a3k/common/a3700_common.mk
index 2050d59..5e2f8e2 100644
--- a/plat/marvell/armada/a3k/common/a3700_common.mk
+++ b/plat/marvell/armada/a3k/common/a3700_common.mk
@@ -15,6 +15,8 @@
MARVELL_COMMON_BASE := $(MARVELL_PLAT_BASE)/common
HANDLE_EA_EL3_FIRST := 1
+include plat/marvell/marvell.mk
+
#*********** A3700 *************
# GICV3
@@ -65,9 +67,7 @@
ifneq (${WTP},)
DOIMAGEPATH := $(WTP)
-DOIMAGETOOL := $(DOIMAGEPATH)/wtptp/linux/tbb_linux
-
-include plat/marvell/marvell.mk
+DOIMAGETOOL := $(DOIMAGEPATH)/wtptp/src/TBB_Linux/release/TBB_linux
ifeq ($(MARVELL_SECURE_BOOT),1)
DOIMAGE_CFG := $(DOIMAGEPATH)/atf-tim.txt
@@ -120,10 +120,12 @@
$(DDR_TOPOLOGY) 0 0 $(DOIMAGE_CFG) $(TIMNCFG) $(TIMNSIG) 0
DOIMAGE_FLAGS := -r $(DOIMAGE_CFG) -v -D
-mrvl_flash: ${BUILD_PLAT}/${FIP_NAME} ${DOIMAGETOOL}
- $(shell truncate -s %128K ${BUILD_PLAT}/bl1.bin)
- $(shell cat ${BUILD_PLAT}/bl1.bin ${BUILD_PLAT}/${FIP_NAME} > ${BUILD_PLAT}/${BOOT_IMAGE})
- $(shell truncate -s %4 ${BUILD_PLAT}/${BOOT_IMAGE})
+$(DOIMAGETOOL):
+ $(if $(value CRYPTOPP_PATH),,$(error "Platform '${PLAT}' for WTP image tool requires CRYPTOPP_PATH. Please set CRYPTOPP_PATH to point to the right directory"))
+ $(Q)$(MAKE) --no-print-directory -C $(CRYPTOPP_PATH) -f GNUmakefile
+ $(Q)$(MAKE) --no-print-directory -C $(DOIMAGEPATH)/wtptp/src/TBB_Linux -f TBB_linux.mak LIBDIR=$(CRYPTOPP_PATH)
+
+mrvl_flash: ${BUILD_PLAT}/${BOOT_IMAGE} ${DOIMAGETOOL}
$(if $(value MV_DDR_PATH),,$(error "Platform '${PLAT}' for target '$@' requires MV_DDR_PATH. Please set MV_DDR_PATH to point to the right directory"))
${Q}${MAKE} --no-print-directory -C ${DOIMAGEPATH} WTMI_IMG=$(WTMI_IMG) MV_DDR_PATH=$(MV_DDR_PATH)
$(shell truncate -s %4 $(WTMI_IMG))
diff --git a/plat/marvell/armada/a8k/common/a8k_common.mk b/plat/marvell/armada/a8k/common/a8k_common.mk
index c827326..58394a4 100644
--- a/plat/marvell/armada/a8k/common/a8k_common.mk
+++ b/plat/marvell/armada/a8k/common/a8k_common.mk
@@ -160,8 +160,6 @@
@$(DOIMAGE_LIBS_CHECK)
${Q}${MAKE} --no-print-directory -C ${DOIMAGEPATH}
-mrvl_flash: ${BUILD_PLAT}/${FIP_NAME} ${DOIMAGETOOL} ${BUILD_PLAT}/ble.bin
- $(shell truncate -s %128K ${BUILD_PLAT}/bl1.bin)
- $(shell cat ${BUILD_PLAT}/bl1.bin ${BUILD_PLAT}/${FIP_NAME} > ${BUILD_PLAT}/${BOOT_IMAGE})
+mrvl_flash: ${BUILD_PLAT}/${BOOT_IMAGE} ${DOIMAGETOOL}
${DOIMAGETOOL} ${DOIMAGE_FLAGS} ${BUILD_PLAT}/${BOOT_IMAGE} ${BUILD_PLAT}/${FLASH_IMAGE}
diff --git a/plat/marvell/armada/common/marvell_common.mk b/plat/marvell/armada/common/marvell_common.mk
index af149fa..7f8dffa 100644
--- a/plat/marvell/armada/common/marvell_common.mk
+++ b/plat/marvell/armada/common/marvell_common.mk
@@ -85,3 +85,12 @@
ifeq (${MSS_SUPPORT}, 1)
include $(MARVELL_PLAT_BASE)/common/mss/mss_common.mk
endif
+
+$(BUILD_PLAT)/$(BOOT_IMAGE): $(BUILD_PLAT)/bl1.bin $(BUILD_PLAT)/$(FIP_NAME)
+ @cp $(BUILD_PLAT)/bl1.bin $(BUILD_PLAT)/$(BOOT_IMAGE) || { rm -f $(BUILD_PLAT)/$(BOOT_IMAGE); false; }
+ @truncate -s %128K $(BUILD_PLAT)/$(BOOT_IMAGE) || { rm -f $(BUILD_PLAT)/$(BOOT_IMAGE); false; }
+ @cat $(BUILD_PLAT)/$(FIP_NAME) >> $(BUILD_PLAT)/$(BOOT_IMAGE) || { rm -f $(BUILD_PLAT)/$(BOOT_IMAGE); false; }
+ @truncate -s %4 $(BUILD_PLAT)/$(BOOT_IMAGE) || { rm -f $(BUILD_PLAT)/$(BOOT_IMAGE); false; }
+ @echo "Built $@ successfully"
+
+mrvl_bootimage: $(BUILD_PLAT)/$(BOOT_IMAGE)
diff --git a/plat/mediatek/mt8183/bl31_plat_setup.c b/plat/mediatek/mt8183/bl31_plat_setup.c
index e96b4ad..7dac8a4 100644
--- a/plat/mediatek/mt8183/bl31_plat_setup.c
+++ b/plat/mediatek/mt8183/bl31_plat_setup.c
@@ -16,6 +16,7 @@
#include <drivers/generic_delay_timer.h>
#include <mcucfg.h>
#include <mt_gic_v3.h>
+#include <mt_timer.h>
#include <lib/coreboot.h>
#include <lib/mmio.h>
#include <mtk_mcdi.h>
@@ -148,6 +149,8 @@
mt_gic_driver_init();
mt_gic_init();
+ mt_systimer_init();
+
/* Init mcsi SF */
plat_mtk_cci_init_sf();
diff --git a/plat/mediatek/mt8183/drivers/timer/mt_timer.c b/plat/mediatek/mt8183/drivers/timer/mt_timer.c
new file mode 100644
index 0000000..0da4815
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/timer/mt_timer.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <mcucfg.h>
+#include <mt_timer.h>
+#include <platform_def.h>
+
+static void enable_systimer_compensation(void)
+{
+ unsigned int reg;
+
+ reg = mmio_read_32(CNTCR_REG);
+ reg &= ~COMP_15_EN;
+ reg |= COMP_20_EN;
+ mmio_write_32(CNTCR_REG, reg);
+
+ NOTICE("[systimer] CNTCR_REG(0x%x)\n", mmio_read_32(CNTCR_REG));
+}
+
+void mt_systimer_init(void)
+{
+ /* systimer is default on, so we only enable systimer compensation */
+ enable_systimer_compensation();
+}
diff --git a/plat/mediatek/mt8183/drivers/timer/mt_timer.h b/plat/mediatek/mt8183/drivers/timer/mt_timer.h
new file mode 100644
index 0000000..0b8edc5
--- /dev/null
+++ b/plat/mediatek/mt8183/drivers/timer/mt_timer.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_TIMER_H
+#define MT_TIMER_H
+
+
+#define SYSTIMER_BASE (0x10017000)
+#define CNTCR_REG (SYSTIMER_BASE + 0x0)
+#define CNTSR_REG (SYSTIMER_BASE + 0x4)
+
+#define COMP_15_EN (1 << 10)
+#define COMP_20_EN (1 << 11)
+
+void mt_systimer_init(void);
+
+#endif /* MT_TIMER_H */
diff --git a/plat/mediatek/mt8183/platform.mk b/plat/mediatek/mt8183/platform.mk
index 3ccc928..f290a4e 100644
--- a/plat/mediatek/mt8183/platform.mk
+++ b/plat/mediatek/mt8183/platform.mk
@@ -14,6 +14,7 @@
-I${MTK_PLAT_SOC}/drivers/mcdi/ \
-I${MTK_PLAT_SOC}/drivers/spmc/ \
-I${MTK_PLAT_SOC}/drivers/gpio/ \
+ -I${MTK_PLAT_SOC}/drivers/timer/ \
-I${MTK_PLAT_SOC}/drivers/pmic/ \
-I${MTK_PLAT_SOC}/drivers/spm/ \
-I${MTK_PLAT_SOC}/drivers/sspm/ \
@@ -58,6 +59,7 @@
${MTK_PLAT_SOC}/drivers/spm/spm_suspend.c \
${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \
${MTK_PLAT_SOC}/drivers/uart/uart.c \
+ ${MTK_PLAT_SOC}/drivers/timer/mt_timer.c \
${MTK_PLAT_SOC}/drivers/emi_mpu/emi_mpu.c \
${MTK_PLAT_SOC}/plat_pm.c \
${MTK_PLAT_SOC}/plat_topology.c \
diff --git a/plat/nvidia/tegra/common/tegra_platform.c b/plat/nvidia/tegra/common/tegra_platform.c
index 7c73e8f..d45d988 100644
--- a/plat/nvidia/tegra/common/tegra_platform.c
+++ b/plat/nvidia/tegra/common/tegra_platform.c
@@ -297,14 +297,14 @@
}
/*****************************************************************************
- * plat_smccc_feature_available() - This function checks whether SMCCC feature
+ * plat_is_smccc_feature_available() - This function checks whether SMCCC feature
* is availabile for the platform or not.
* @fid: SMCCC function id
*
* Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and
* SMC_ARCH_CALL_NOT_SUPPORTED otherwise.
*****************************************************************************/
-int32_t plat_smccc_feature_available(u_register_t fid)
+int32_t plat_is_smccc_feature_available(u_register_t fid)
{
switch (fid) {
case SMCCC_ARCH_SOC_ID:
diff --git a/plat/qemu/qemu_sbsa/platform.mk b/plat/qemu/qemu_sbsa/platform.mk
index 9be56a3..acaa43f 100644
--- a/plat/qemu/qemu_sbsa/platform.mk
+++ b/plat/qemu/qemu_sbsa/platform.mk
@@ -47,7 +47,8 @@
${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \
${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c
-BL1_SOURCES += lib/cpus/aarch64/cortex_a57.S
+BL1_SOURCES += lib/cpus/aarch64/cortex_a57.S \
+ lib/cpus/aarch64/cortex_a72.S
BL2_SOURCES += drivers/io/io_semihosting.c \
drivers/io/io_storage.c \
@@ -74,6 +75,7 @@
${PLAT_QEMU_COMMON_PATH}/qemu_gicv3.c
BL31_SOURCES += lib/cpus/aarch64/cortex_a57.S \
+ lib/cpus/aarch64/cortex_a72.S \
lib/semihosting/semihosting.c \
lib/semihosting/${ARCH}/semihosting_call.S \
plat/common/plat_psci_common.c \
diff --git a/plat/qti/common/src/qti_common.c b/plat/qti/common/src/qti_common.c
index 9355eb7..da0eaec 100644
--- a/plat/qti/common/src/qti_common.c
+++ b/plat/qti/common/src/qti_common.c
@@ -176,14 +176,14 @@
}
/*****************************************************************************
- * plat_smccc_feature_available() - This function checks whether SMCCC feature
+ * plat_is_smccc_feature_available() - This function checks whether SMCCC feature
* is availabile for the platform or not.
* @fid: SMCCC function id
*
* Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and
* SMC_ARCH_CALL_NOT_SUPPORTED otherwise.
*****************************************************************************/
-int32_t plat_smccc_feature_available(u_register_t fid)
+int32_t plat_is_smccc_feature_available(u_register_t fid)
{
switch (fid) {
case SMCCC_ARCH_SOC_ID:
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_sys.c b/plat/xilinx/zynqmp/pm_service/pm_api_sys.c
index b1720d9..cd9d597 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_sys.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_sys.c
@@ -907,7 +907,13 @@
/* Send request to the PMU */
PM_PACK_PAYLOAD2(payload, api_id, clock_id);
- return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
+ status = pm_ipi_send_sync(primary_proc, payload, NULL, 0);
+
+ /* If action fails due to the lack of permissions filter the error */
+ if (status == PM_RET_ERROR_ACCESS)
+ status = PM_RET_SUCCESS;
+
+ return status;
}
/**
diff --git a/plat/xilinx/zynqmp/pm_service/pm_defs.h b/plat/xilinx/zynqmp/pm_service/pm_defs.h
index cae36c9..4776d42 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_defs.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_defs.h
@@ -215,26 +215,29 @@
/**
* @PM_RET_SUCCESS: success
- * @PM_RET_ERROR_ARGS: illegal arguments provided
+ * @PM_RET_ERROR_ARGS: illegal arguments provided (deprecated)
+ * @PM_RET_ERROR_NOTSUPPORTED: feature not supported (deprecated)
+ * @PM_RET_ERROR_INTERNAL: internal error
+ * @PM_RET_ERROR_CONFLICT: conflict
* @PM_RET_ERROR_ACCESS: access rights violation
+ * @PM_RET_ERROR_INVALID_NODE: invalid node
+ * @PM_RET_ERROR_DOUBLE_REQ: duplicate request for same node
+ * @PM_RET_ERROR_ABORT_SUSPEND: suspend procedure has been aborted
* @PM_RET_ERROR_TIMEOUT: timeout in communication with PMU
- * @PM_RET_ERROR_NOTSUPPORTED: feature not supported
- * @PM_RET_ERROR_PROC: node is not a processor node
- * @PM_RET_ERROR_API_ID: illegal API ID
- * @PM_RET_ERROR_OTHER: other error
+ * @PM_RET_ERROR_NODE_USED: node is already in use
*/
enum pm_ret_status {
PM_RET_SUCCESS,
- PM_RET_ERROR_ARGS,
- PM_RET_ERROR_ACCESS,
- PM_RET_ERROR_TIMEOUT,
- PM_RET_ERROR_NOTSUPPORTED,
- PM_RET_ERROR_PROC,
- PM_RET_ERROR_API_ID,
- PM_RET_ERROR_FAILURE,
- PM_RET_ERROR_COMMUNIC,
- PM_RET_ERROR_DOUBLEREQ,
- PM_RET_ERROR_OTHER,
+ PM_RET_ERROR_ARGS = 1,
+ PM_RET_ERROR_NOTSUPPORTED = 4,
+ PM_RET_ERROR_INTERNAL = 2000,
+ PM_RET_ERROR_CONFLICT = 2001,
+ PM_RET_ERROR_ACCESS = 2002,
+ PM_RET_ERROR_INVALID_NODE = 2003,
+ PM_RET_ERROR_DOUBLE_REQ = 2004,
+ PM_RET_ERROR_ABORT_SUSPEND = 2005,
+ PM_RET_ERROR_TIMEOUT = 2006,
+ PM_RET_ERROR_NODE_USED = 2007
};
/**