Merge "drivers: marvell: comphy-a3700: support SGMII COMPHY power off" into integration
diff --git a/Makefile b/Makefile
index 54d332c..b9584ca 100644
--- a/Makefile
+++ b/Makefile
@@ -248,7 +248,6 @@
# Additional warnings
# Level 1
WARNING1 := -Wextra
-WARNING1 += -Wmissing-declarations
WARNING1 += -Wmissing-format-attribute
WARNING1 += -Wmissing-prototypes
WARNING1 += -Wold-style-definition
@@ -262,7 +261,6 @@
WARNING3 += -Wcast-qual
WARNING3 += -Wconversion
WARNING3 += -Wpacked
-WARNING3 += -Wpadded
WARNING3 += -Wpointer-arith
WARNING3 += -Wredundant-decls
WARNING3 += -Wswitch-default
diff --git a/bl1/aarch64/bl1_entrypoint.S b/bl1/aarch64/bl1_entrypoint.S
index 855add3..00f2718 100644
--- a/bl1/aarch64/bl1_entrypoint.S
+++ b/bl1/aarch64/bl1_entrypoint.S
@@ -30,7 +30,8 @@
_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
_init_memory=1 \
_init_c_runtime=1 \
- _exception_vectors=bl1_exceptions
+ _exception_vectors=bl1_exceptions \
+ _pie_fixup_size=0
/* --------------------------------------------------------------------
* Perform BL1 setup
diff --git a/bl2/aarch64/bl2_el3_entrypoint.S b/bl2/aarch64/bl2_el3_entrypoint.S
index 6fe2dd9..f97121e 100644
--- a/bl2/aarch64/bl2_el3_entrypoint.S
+++ b/bl2/aarch64/bl2_el3_entrypoint.S
@@ -26,7 +26,8 @@
_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
_init_memory=1 \
_init_c_runtime=1 \
- _exception_vectors=bl2_el3_exceptions
+ _exception_vectors=bl2_el3_exceptions \
+ _pie_fixup_size=0
/* ---------------------------------------------
* Restore parameters of boot rom
diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S
index 1ad26e4..74b0993 100644
--- a/bl31/aarch64/bl31_entrypoint.S
+++ b/bl31/aarch64/bl31_entrypoint.S
@@ -32,17 +32,6 @@
mov x22, x2
mov x23, x3
- /* --------------------------------------------------------------------
- * If PIE is enabled, fixup the Global descriptor Table and dynamic
- * relocations
- * --------------------------------------------------------------------
- */
-#if ENABLE_PIE
- mov_imm x0, BL31_BASE
- mov_imm x1, BL31_LIMIT
- bl fixup_gdt_reloc
-#endif /* ENABLE_PIE */
-
#if !RESET_TO_BL31
/* ---------------------------------------------------------------------
* For !RESET_TO_BL31 systems, only the primary CPU ever reaches
@@ -59,7 +48,8 @@
_secondary_cold_boot=0 \
_init_memory=0 \
_init_c_runtime=1 \
- _exception_vectors=runtime_exceptions
+ _exception_vectors=runtime_exceptions \
+ _pie_fixup_size=BL31_LIMIT - BL31_BASE
#else
/* ---------------------------------------------------------------------
@@ -74,7 +64,8 @@
_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
_init_memory=1 \
_init_c_runtime=1 \
- _exception_vectors=runtime_exceptions
+ _exception_vectors=runtime_exceptions \
+ _pie_fixup_size=BL31_LIMIT - BL31_BASE
/* ---------------------------------------------------------------------
* For RESET_TO_BL31 systems, BL31 is the first bootloader to run so
@@ -174,7 +165,8 @@
_secondary_cold_boot=0 \
_init_memory=0 \
_init_c_runtime=0 \
- _exception_vectors=runtime_exceptions
+ _exception_vectors=runtime_exceptions \
+ _pie_fixup_size=0
/*
* We're about to enable MMU and participate in PSCI state coordination.
diff --git a/bl31/aarch64/ea_delegate.S b/bl31/aarch64/ea_delegate.S
index 3cc4d56..1d28d5e 100644
--- a/bl31/aarch64/ea_delegate.S
+++ b/bl31/aarch64/ea_delegate.S
@@ -102,9 +102,11 @@
/* Setup exception class and syndrome arguments for platform handler */
mov x0, #ERROR_EA_SYNC
mrs x1, esr_el3
- adr x30, el3_exit
- b delegate_sync_ea
+ bl delegate_sync_ea
+ /* el3_exit assumes SP_EL0 on entry */
+ msr spsel, #MODE_SP_EL0
+ b el3_exit
2:
ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
@@ -146,8 +148,11 @@
/* Setup exception class and syndrome arguments for platform handler */
mov x0, #ERROR_EA_ASYNC
mrs x1, esr_el3
- adr x30, el3_exit
- b delegate_async_ea
+ bl delegate_async_ea
+
+ /* el3_exit assumes SP_EL0 on entry */
+ msr spsel, #MODE_SP_EL0
+ b el3_exit
endfunc enter_lower_el_async_ea
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 68f84ea..d9d7f84 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -17,10 +17,18 @@
:G: `sandrine-bailleux-arm`_
:M: Alexei Fedorov <alexei.fedorov@arm.com>
:G: `AlexeiFedorov`_
-:M: Paul Beesley <paul.beesley@arm.com>
-:G: `pbeesley-arm`_
:M: György Szing <gyorgy.szing@arm.com>
:G: `gyuri-szing`_
+:M: Manish Pandey <manish.pandey2@arm.com>
+:G: `manish-pandey-arm`_
+:M: Mark Dykes <mark.dykes@arm.com>
+:G: `mardyk01`_
+:M: Olivier Deprez <olivier.deprez@arm.com>
+:G: `odeprez`_
+:M: Bipin Ravi <bipin.ravi@arm.com>
+:G: `bipinravi-arm`_
+:M: Joanna Farley <joanna.farley@arm.com>
+:G: `joannafarley-arm`_
Allwinner ARMv8 platform port
-----------------------------
@@ -300,7 +308,6 @@
.. _mtk09422: https://github.com/mtk09422
.. _niej: https://github.com/niej
.. _npoushin: https://github.com/npoushin
-.. _pbeesley-arm: https://github.com/pbeesley-arm
.. _qoriq-open-source: https://github.com/qoriq-open-source
.. _remi-triplefault: https://github.com/repk
.. _rockchip-linux: https://github.com/rockchip-linux
@@ -314,3 +321,8 @@
.. _TonyXie06: https://github.com/TonyXie06
.. _vwadekar: https://github.com/vwadekar
.. _Yann-lms: https://github.com/Yann-lms
+.. _manish-pandey-arm: https://github.com/manish-pandey-arm
+.. _mardyk01: https://github.com/mardyk01
+.. _odeprez: https://github.com/odeprez
+.. _bipinravi-arm: https://github.com/bipinravi-arm
+.. _joannafarley-arm: https://github.com/joannafarley-arm
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 051586b..731b876 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -196,7 +196,7 @@
builds, but this behaviour can be overridden in each platform's Makefile or
in the build command line.
- - ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO)
+- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO)
support in GCC for TF-A. This option is currently only supported for
AArch64. Default is 0.
@@ -354,6 +354,21 @@
compliant and is retained only for compatibility. The default value of this
flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme.
+- ``KEY_SIZE``: This build flag enables the user to select the key size for
+ the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE``
+ depend on the chosen algorithm and the cryptographic module.
+
+ +-----------+------------------------------------+
+ | KEY_ALG | Possible key sizes |
+ +===========+====================================+
+ | rsa | 1024 , 2048 (default), 3072, 4096* |
+ +-----------+------------------------------------+
+ | ecdsa | unavailable |
+ +-----------+------------------------------------+
+
+ * Only 2048 bits size is available with CryptoCell 712 SBROM release 1.
+ Only 3072 bits size is available with CryptoCell 712 SBROM release 2.
+
- ``HASH_ALG``: This build flag enables the user to select the secure hash
algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``.
The default value of this flag is ``sha256``.
diff --git a/docs/plat/nvidia-tegra.rst b/docs/plat/nvidia-tegra.rst
index bc9e35b..02ff38b 100644
--- a/docs/plat/nvidia-tegra.rst
+++ b/docs/plat/nvidia-tegra.rst
@@ -1,6 +1,17 @@
NVIDIA Tegra
============
+- .. rubric:: T194
+ :name: t194
+
+T194 has eight NVIDIA Carmel CPU cores in a coherent multi-processor
+configuration. The Carmel cores support the ARM Architecture version 8.2,
+executing both 64-bit AArch64 code, and 32-bit AArch32 code. The Carmel
+processors are organized as four dual-core clusters, where each cluster has
+a dedicated 2 MiB Level-2 unified cache. A high speed coherency fabric connects
+these processor complexes and allows heterogeneous multi-processing with all
+eight cores if required.
+
- .. rubric:: T186
:name: t186
@@ -78,9 +89,10 @@
These are the supported Trusted OS' by Tegra platforms.
-Tegra132: TLK
-Tegra210: TLK and Trusty
-Tegra186: Trusty
+- Tegra132: TLK
+- Tegra210: TLK and Trusty
+- Tegra186: Trusty
+- Tegra194: Trusty
Scatter files
-------------
@@ -98,7 +110,7 @@
.. code:: shell
CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- make PLAT=tegra \
- TARGET_SOC=<target-soc e.g. t186|t210|t132> SPD=<dispatcher e.g. trusty|tlkd>
+ TARGET_SOC=<target-soc e.g. t194|t186|t210|t132> SPD=<dispatcher e.g. trusty|tlkd>
bl31
Platforms wanting to use different TZDRAM\_BASE, can add ``TZDRAM_BASE=<value>``
diff --git a/docs/process/security-hardening.rst b/docs/process/security-hardening.rst
index 4967871..a18a792 100644
--- a/docs/process/security-hardening.rst
+++ b/docs/process/security-hardening.rst
@@ -30,9 +30,8 @@
- W=1
- Adds ``Wextra``, ``Wmissing-declarations``, ``Wmissing-format-attribute``,
- ``Wmissing-prototypes``, ``Wold-style-definition`` and
- ``Wunused-const-variable``.
+ Adds ``Wextra``, ``Wmissing-format-attribute``, ``Wmissing-prototypes``,
+ ``Wold-style-definition`` and ``Wunused-const-variable``.
- W=2
@@ -42,7 +41,7 @@
- W=3
Adds ``Wbad-function-cast``, ``Wcast-qual``, ``Wconversion``, ``Wpacked``,
- ``Wpadded``, ``Wpointer-arith``, ``Wredundant-decls`` and
+ ``Wpointer-arith``, ``Wredundant-decls`` and
``Wswitch-default``.
Refer to the GCC or Clang documentation for more information on the individual
diff --git a/drivers/allwinner/axp/axp803.c b/drivers/allwinner/axp/axp803.c
new file mode 100644
index 0000000..53b11c1
--- /dev/null
+++ b/drivers/allwinner/axp/axp803.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/allwinner/axp.h>
+
+const uint8_t axp_chip_id = AXP803_CHIP_ID;
+const char *const axp_compatible = "x-powers,axp803";
+
+const struct axp_regulator axp_regulators[] = {
+ {"dcdc1", 1600, 3400, 100, NA, 0x20, 0x10, 0},
+ {"dcdc5", 800, 1840, 10, 32, 0x24, 0x10, 4},
+ {"dcdc6", 600, 1520, 10, 50, 0x25, 0x10, 5},
+ {"dldo1", 700, 3300, 100, NA, 0x15, 0x12, 3},
+ {"dldo2", 700, 4200, 100, 27, 0x16, 0x12, 4},
+ {"dldo3", 700, 3300, 100, NA, 0x17, 0x12, 5},
+ {"dldo4", 700, 3300, 100, NA, 0x18, 0x12, 6},
+ {"fldo1", 700, 1450, 50, NA, 0x1c, 0x13, 2},
+ {}
+};
diff --git a/drivers/allwinner/axp/axp805.c b/drivers/allwinner/axp/axp805.c
new file mode 100644
index 0000000..8d029c0
--- /dev/null
+++ b/drivers/allwinner/axp/axp805.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/allwinner/axp.h>
+
+const uint8_t axp_chip_id = AXP805_CHIP_ID;
+const char *const axp_compatible = "x-powers,axp805";
+
+/*
+ * The "dcdcd" split changes the step size by a factor of 5, not 2;
+ * disallow values above the split to maintain accuracy.
+ */
+const struct axp_regulator axp_regulators[] = {
+ {"dcdca", 600, 1520, 10, 50, 0x12, 0x10, 0},
+ {"dcdcb", 1000, 2550, 50, NA, 0x13, 0x10, 1},
+ {"dcdcc", 600, 1520, 10, 50, 0x14, 0x10, 2},
+ {"dcdcd", 600, 1500, 20, NA, 0x15, 0x10, 3},
+ {"dcdce", 1100, 3400, 100, NA, 0x16, 0x10, 4},
+ {"aldo1", 700, 3300, 100, NA, 0x17, 0x10, 5},
+ {"aldo2", 700, 3300, 100, NA, 0x18, 0x10, 6},
+ {"aldo3", 700, 3300, 100, NA, 0x19, 0x10, 7},
+ {"bldo1", 700, 1900, 100, NA, 0x20, 0x11, 0},
+ {"bldo2", 700, 1900, 100, NA, 0x21, 0x11, 1},
+ {"bldo3", 700, 1900, 100, NA, 0x22, 0x11, 2},
+ {"bldo4", 700, 1900, 100, NA, 0x23, 0x11, 3},
+ {"cldo1", 700, 3300, 100, NA, 0x24, 0x11, 4},
+ {"cldo2", 700, 4200, 100, 27, 0x25, 0x11, 5},
+ {"cldo3", 700, 3300, 100, NA, 0x26, 0x11, 6},
+ {}
+};
diff --git a/drivers/allwinner/axp/common.c b/drivers/allwinner/axp/common.c
new file mode 100644
index 0000000..13437fe
--- /dev/null
+++ b/drivers/allwinner/axp/common.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+
+#include <libfdt.h>
+
+#include <common/debug.h>
+#include <drivers/allwinner/axp.h>
+
+int axp_check_id(void)
+{
+ int ret;
+
+ ret = axp_read(0x03);
+ if (ret < 0)
+ return ret;
+
+ ret &= 0xcf;
+ if (ret != axp_chip_id) {
+ ERROR("PMIC: Found unknown PMIC %02x\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+int axp_clrsetbits(uint8_t reg, uint8_t clr_mask, uint8_t set_mask)
+{
+ uint8_t val;
+ int ret;
+
+ ret = axp_read(reg);
+ if (ret < 0)
+ return ret;
+
+ val = (ret & ~clr_mask) | set_mask;
+
+ return axp_write(reg, val);
+}
+
+void axp_power_off(void)
+{
+ /* Set "power disable control" bit */
+ axp_setbits(0x32, BIT(7));
+}
+
+/*
+ * Retrieve the voltage from a given regulator DTB node.
+ * Both the regulator-{min,max}-microvolt properties must be present and
+ * have the same value. Return that value in millivolts.
+ */
+static int fdt_get_regulator_millivolt(const void *fdt, int node)
+{
+ const fdt32_t *prop;
+ uint32_t min_volt;
+
+ prop = fdt_getprop(fdt, node, "regulator-min-microvolt", NULL);
+ if (prop == NULL)
+ return -EINVAL;
+ min_volt = fdt32_to_cpu(*prop);
+
+ prop = fdt_getprop(fdt, node, "regulator-max-microvolt", NULL);
+ if (prop == NULL)
+ return -EINVAL;
+
+ if (fdt32_to_cpu(*prop) != min_volt)
+ return -EINVAL;
+
+ return min_volt / 1000;
+}
+
+static int setup_regulator(const void *fdt, int node,
+ const struct axp_regulator *reg)
+{
+ uint8_t val;
+ int mvolt;
+
+ mvolt = fdt_get_regulator_millivolt(fdt, node);
+ if (mvolt < reg->min_volt || mvolt > reg->max_volt)
+ return -EINVAL;
+
+ val = (mvolt / reg->step) - (reg->min_volt / reg->step);
+ if (val > reg->split)
+ val = ((val - reg->split) / 2) + reg->split;
+
+ axp_write(reg->volt_reg, val);
+ axp_setbits(reg->switch_reg, BIT(reg->switch_bit));
+
+ INFO("PMIC: %s voltage: %d.%03dV\n", reg->dt_name,
+ mvolt / 1000, mvolt % 1000);
+
+ return 0;
+}
+
+static bool should_enable_regulator(const void *fdt, int node)
+{
+ if (fdt_getprop(fdt, node, "phandle", NULL) != NULL)
+ return true;
+ if (fdt_getprop(fdt, node, "regulator-always-on", NULL) != NULL)
+ return true;
+ return false;
+}
+
+void axp_setup_regulators(const void *fdt)
+{
+ int node;
+ bool sw = false;
+
+ if (fdt == NULL)
+ return;
+
+ /* locate the PMIC DT node, bail out if not found */
+ node = fdt_node_offset_by_compatible(fdt, -1, axp_compatible);
+ if (node < 0) {
+ WARN("PMIC: No PMIC DT node, skipping setup\n");
+ return;
+ }
+
+ /* This applies to AXP803 only. */
+ if (fdt_getprop(fdt, node, "x-powers,drive-vbus-en", NULL)) {
+ axp_clrbits(0x8f, BIT(4));
+ axp_setbits(0x30, BIT(2));
+ INFO("PMIC: Enabling DRIVEVBUS\n");
+ }
+
+ /* descend into the "regulators" subnode */
+ node = fdt_subnode_offset(fdt, node, "regulators");
+ if (node < 0) {
+ WARN("PMIC: No regulators DT node, skipping setup\n");
+ return;
+ }
+
+ /* iterate over all regulators to find used ones */
+ fdt_for_each_subnode(node, fdt, node) {
+ const struct axp_regulator *reg;
+ const char *name;
+ int length;
+
+ /* We only care if it's always on or referenced. */
+ if (!should_enable_regulator(fdt, node))
+ continue;
+
+ name = fdt_get_name(fdt, node, &length);
+
+ /* Enable the switch last to avoid overheating. */
+ if (!strncmp(name, "dc1sw", length) ||
+ !strncmp(name, "sw", length)) {
+ sw = true;
+ continue;
+ }
+
+ for (reg = axp_regulators; reg->dt_name; reg++) {
+ if (!strncmp(name, reg->dt_name, length)) {
+ setup_regulator(fdt, node, reg);
+ break;
+ }
+ }
+ }
+
+ /*
+ * On the AXP803, if DLDO2 is enabled after DC1SW, the PMIC overheats
+ * and shuts down. So always enable DC1SW as the very last regulator.
+ */
+ if (sw) {
+ INFO("PMIC: Enabling DC SW\n");
+ if (axp_chip_id == AXP803_CHIP_ID)
+ axp_setbits(0x12, BIT(7));
+ if (axp_chip_id == AXP805_CHIP_ID)
+ axp_setbits(0x11, BIT(7));
+ }
+}
diff --git a/drivers/auth/cryptocell/712/cryptocell_crypto.c b/drivers/auth/cryptocell/712/cryptocell_crypto.c
index 395c550..25eb6bc 100644
--- a/drivers/auth/cryptocell/712/cryptocell_crypto.c
+++ b/drivers/auth/cryptocell/712/cryptocell_crypto.c
@@ -225,7 +225,7 @@
/* Verify the signature */
error = CCSbVerifySignature((uintptr_t)PLAT_CRYPTOCELL_BASE,
(uint32_t *)data_ptr, &pk, &signature,
- data_len, RSA_PSS_2048);
+ data_len, RSA_PSS);
if (error != CC_OK)
return CRYPTO_ERR_SIGNATURE;
diff --git a/drivers/auth/cryptocell/cryptocell_crypto.mk b/drivers/auth/cryptocell/cryptocell_crypto.mk
index d42a2e7..2fc4ddb 100644
--- a/drivers/auth/cryptocell/cryptocell_crypto.mk
+++ b/drivers/auth/cryptocell/cryptocell_crypto.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -12,6 +12,8 @@
# Needs to be set to drive mbed TLS configuration correctly
$(eval $(call add_define,TF_MBEDTLS_KEY_ALG_ID))
+$(eval $(call add_define,KEY_SIZE))
+
# CCSBROM_LIB_PATH must be set to the Cryptocell SBROM library path
ifeq (${CCSBROM_LIB_PATH},)
$(error Error: CCSBROM_LIB_PATH not set)
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 3ff2912..1fcd0f9 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -140,6 +140,8 @@
#define ID_AA64PFR0_GIC_MASK ULL(0xf)
#define ID_AA64PFR0_SVE_SHIFT U(32)
#define ID_AA64PFR0_SVE_MASK ULL(0xf)
+#define ID_AA64PFR0_SEL2_SHIFT U(36)
+#define ID_AA64PFR0_SEL2_MASK ULL(0xf)
#define ID_AA64PFR0_MPAM_SHIFT U(40)
#define ID_AA64PFR0_MPAM_MASK ULL(0xf)
#define ID_AA64PFR0_DIT_SHIFT U(48)
@@ -285,6 +287,7 @@
#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
#define SCR_ATA_BIT (U(1) << 26)
#define SCR_FIEN_BIT (U(1) << 21)
+#define SCR_EEL2_BIT (U(1) << 18)
#define SCR_API_BIT (U(1) << 17)
#define SCR_APK_BIT (U(1) << 16)
#define SCR_TWE_BIT (U(1) << 13)
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index 378e827..b14b7b6 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S
@@ -232,11 +232,18 @@
*
* _exception_vectors:
* Address of the exception vectors to program in the VBAR_EL3 register.
+ *
+ * _pie_fixup_size:
+ * Size of memory region to fixup Global Descriptor Table (GDT).
+ *
+ * A non-zero value is expected when firmware needs GDT to be fixed-up.
+ *
* -----------------------------------------------------------------------------
*/
.macro el3_entrypoint_common \
_init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \
- _init_memory, _init_c_runtime, _exception_vectors
+ _init_memory, _init_c_runtime, _exception_vectors, \
+ _pie_fixup_size
.if \_init_sctlr
/* -------------------------------------------------------------
@@ -283,6 +290,26 @@
do_cold_boot:
.endif /* _warm_boot_mailbox */
+ .if \_pie_fixup_size
+#if ENABLE_PIE
+ /*
+ * ------------------------------------------------------------
+ * If PIE is enabled fixup the Global descriptor Table only
+ * once during primary core cold boot path.
+ *
+ * Compile time base address, required for fixup, is calculated
+ * using "pie_fixup" label present within first page.
+ * ------------------------------------------------------------
+ */
+ pie_fixup:
+ ldr x0, =pie_fixup
+ and x0, x0, #~(PAGE_SIZE - 1)
+ mov_imm x1, \_pie_fixup_size
+ add x1, x1, x0
+ bl fixup_gdt_reloc
+#endif /* ENABLE_PIE */
+ .endif /* _pie_fixup_size */
+
/* ---------------------------------------------------------------------
* Set the exception vectors.
* ---------------------------------------------------------------------
diff --git a/include/drivers/allwinner/axp.h b/include/drivers/allwinner/axp.h
new file mode 100644
index 0000000..9c0035f
--- /dev/null
+++ b/include/drivers/allwinner/axp.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef AXP_H
+#define AXP_H
+
+#include <stdint.h>
+
+#define NA 0xff
+
+enum {
+ AXP803_CHIP_ID = 0x41,
+ AXP805_CHIP_ID = 0x40,
+};
+
+struct axp_regulator {
+ const char *dt_name;
+ uint16_t min_volt;
+ uint16_t max_volt;
+ uint16_t step;
+ unsigned char split;
+ unsigned char volt_reg;
+ unsigned char switch_reg;
+ unsigned char switch_bit;
+};
+
+extern const uint8_t axp_chip_id;
+extern const char *const axp_compatible;
+extern const struct axp_regulator axp_regulators[];
+
+/*
+ * Since the PMIC can be connected to multiple bus types,
+ * low-level read/write functions must be provided by the platform
+ */
+int axp_read(uint8_t reg);
+int axp_write(uint8_t reg, uint8_t val);
+int axp_clrsetbits(uint8_t reg, uint8_t clr_mask, uint8_t set_mask);
+#define axp_clrbits(reg, clr_mask) axp_clrsetbits(reg, clr_mask, 0)
+#define axp_setbits(reg, set_mask) axp_clrsetbits(reg, 0, set_mask)
+
+int axp_check_id(void);
+void axp_power_off(void);
+void axp_setup_regulators(const void *fdt);
+
+#endif /* AXP_H */
diff --git a/include/drivers/arm/cryptocell/712/rsa.h b/include/drivers/arm/cryptocell/712/rsa.h
index cd9925b..825214d 100644
--- a/include/drivers/arm/cryptocell/712/rsa.h
+++ b/include/drivers/arm/cryptocell/712/rsa.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,19 +21,21 @@
/************************ Defines ******************************/
-/* the modulus size ion bits */
+/* the modulus size in bits */
+#if (KEY_SIZE == 2048)
#define RSA_MOD_SIZE_IN_BITS 2048UL
+#elif (KEY_SIZE == 3072)
+#define RSA_MOD_SIZE_IN_BITS 3072UL
+#else
+#error Unsupported CryptoCell key size requested
+#endif
+
#define RSA_MOD_SIZE_IN_BYTES (CALC_FULL_BYTES(RSA_MOD_SIZE_IN_BITS))
#define RSA_MOD_SIZE_IN_WORDS (CALC_FULL_32BIT_WORDS(RSA_MOD_SIZE_IN_BITS))
#define RSA_MOD_SIZE_IN_256BITS (RSA_MOD_SIZE_IN_WORDS/8)
#define RSA_EXP_SIZE_IN_BITS 17UL
#define RSA_EXP_SIZE_IN_BYTES (CALC_FULL_BYTES(RSA_EXP_SIZE_IN_BITS))
-/* size of buffer for Barrett modulus tag NP, used in PKA algorithms */
-#define RSA_HW_PKI_PKA_BARRETT_MOD_TAG_SIZE_IN_BITS 132
-#define RSA_HW_PKI_PKA_BARRETT_MOD_TAG_SIZE_IN_BYTES (CALC_FULL_BYTES(RSA_HW_PKI_PKA_BARRETT_MOD_TAG_SIZE_IN_BITS))
-#define RSA_HW_PKI_PKA_BARRETT_MOD_TAG_SIZE_IN_WORDS (CALC_FULL_32BIT_WORDS(RSA_HW_PKI_PKA_BARRETT_MOD_TAG_SIZE_IN_BITS))
-
/*
* @brief The RSA_CalcNp calculates Np value and saves it into Np_ptr:
*
diff --git a/include/drivers/arm/cryptocell/712/secureboot_gen_defs.h b/include/drivers/arm/cryptocell/712/secureboot_gen_defs.h
index 68b9ef8..ed1f283 100644
--- a/include/drivers/arm/cryptocell/712/secureboot_gen_defs.h
+++ b/include/drivers/arm/cryptocell/712/secureboot_gen_defs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -24,7 +24,14 @@
/***********************/
/*RSA definitions*/
+#if (KEY_SIZE == 2048)
#define SB_RSA_MOD_SIZE_IN_WORDS 64
+#elif (KEY_SIZE == 3072)
+#define SB_RSA_MOD_SIZE_IN_WORDS 96
+#else
+#error Unsupported CryptoCell key size requested
+#endif
+
#define SB_RSA_HW_PKI_PKA_BARRETT_MOD_TAG_SIZE_IN_WORDS 5
@@ -43,9 +50,12 @@
/********* Supported algorithms definitions ***********/
/*! RSA supported algorithms */
+/* Note: this applies to either 2k or 3k based on CryptoCell SBROM library
+ * version - it means 2k in version 1 and 3k in version 2 (yes, really).
+ */
typedef enum {
- RSA_PSS_2048 = 0x01, /*!< RSA PSS 2048 after hash SHA 256 */
- RSA_PKCS15_2048 = 0x02, /*!< RSA PKX15 */
+ RSA_PSS = 0x01, /*!< RSA PSS after hash SHA 256 */
+ RSA_PKCS15 = 0x02, /*!< RSA PKX15 */
RSA_Last = 0x7FFFFFFF
} CCSbRsaAlg_t;
diff --git a/include/lib/libc/stdint.h b/include/lib/libc/stdint.h
index 80b3e96..818870e 100644
--- a/include/lib/libc/stdint.h
+++ b/include/lib/libc/stdint.h
@@ -72,7 +72,7 @@
#define PTRDIFF_MIN LONG_MIN
#define PTRDIFF_MAX LONG_MAX
-#define SIZE_MAX UINT64_MAX
+#define SIZE_MAX ULONG_MAX
#define INT8_C(x) x
#define INT16_C(x) x
diff --git a/include/lib/utils.h b/include/lib/utils.h
index cdb125c..17ee936 100644
--- a/include/lib/utils.h
+++ b/include/lib/utils.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -79,13 +79,11 @@
* which is constant and does not depend on the execute address of the binary.
*/
#define DEFINE_LOAD_SYM_ADDR(_name) \
-static inline u_register_t load_addr_## _name(void) \
-{ \
- u_register_t v; \
- /* Create a void reference to silence compiler */ \
- (void) _name; \
- __asm__ volatile ("ldr %0, =" #_name : "=r" (v)); \
- return v; \
+static inline u_register_t load_addr_## _name(void) \
+{ \
+ u_register_t v; \
+ __asm__ volatile ("ldr %0, =" #_name : "=r" (v) : "X" (#_name));\
+ return v; \
}
/* Helper to invoke the function defined by DEFINE_LOAD_SYM_ADDR() */
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index 1101425..1bbd610 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -6,6 +6,7 @@
#include <arch.h>
#include <asm_macros.S>
+#include <assert_macros.S>
#include <context.h>
.global el1_sysregs_context_save
@@ -477,6 +478,13 @@
* ------------------------------------------------------------------
*/
func el3_exit
+#if ENABLE_ASSERTIONS
+ /* el3_exit assumes SP_EL0 on entry */
+ mrs x17, spsel
+ cmp x17, #MODE_SP_EL0
+ ASM_ASSERT(eq)
+#endif
+
/* ----------------------------------------------------------
* Save the current SP_EL0 i.e. the EL3 runtime stack which
* will be used for handling the next SMC.
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index d65e02d..b7908ad 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -181,6 +181,16 @@
scr_el3 |= SCR_HCE_BIT;
}
+ /* Enable S-EL2 if the next EL is EL2 and security state is secure */
+ if ((security_state == SECURE) && (GET_EL(ep->spsr) == MODE_EL2)) {
+ if (GET_RW(ep->spsr) != MODE_RW_64) {
+ ERROR("S-EL2 can not be used in AArch32.");
+ panic();
+ }
+
+ scr_el3 |= SCR_EEL2_BIT;
+ }
+
/*
* Initialise SCTLR_EL1 to the reset value corresponding to the target
* execution state setting all fields rather than relying of the hw.
diff --git a/plat/allwinner/common/allwinner-common.mk b/plat/allwinner/common/allwinner-common.mk
index 6866bd6..5e8885d 100644
--- a/plat/allwinner/common/allwinner-common.mk
+++ b/plat/allwinner/common/allwinner-common.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -20,7 +20,8 @@
${AW_PLAT}/common/plat_helpers.S \
${AW_PLAT}/common/sunxi_common.c
-BL31_SOURCES += drivers/arm/gic/common/gic_common.c \
+BL31_SOURCES += drivers/allwinner/axp/common.c \
+ drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v2/gicv2_helpers.c \
drivers/arm/gic/v2/gicv2_main.c \
drivers/delay_timer/delay_timer.c \
diff --git a/plat/allwinner/common/include/sunxi_private.h b/plat/allwinner/common/include/sunxi_private.h
index 1166879..dcf3dc9 100644
--- a/plat/allwinner/common/include/sunxi_private.h
+++ b/plat/allwinner/common/include/sunxi_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,7 +12,7 @@
void sunxi_cpu_on(u_register_t mpidr);
void sunxi_cpu_off(u_register_t mpidr);
void sunxi_disable_secondary_cpus(u_register_t primary_mpidr);
-void __dead2 sunxi_power_down(void);
+void sunxi_power_down(void);
int sunxi_pmic_setup(uint16_t socid, const void *fdt);
void sunxi_security_setup(void);
@@ -20,7 +20,6 @@
uint16_t sunxi_read_soc_id(void);
void sunxi_set_gpio_out(char port, int pin, bool level_high);
int sunxi_init_platform_r_twi(uint16_t socid, bool use_rsb);
-void sunxi_execute_arisc_code(uint32_t *code, size_t size,
- int patch_offset, uint16_t param);
+void sunxi_execute_arisc_code(uint32_t *code, size_t size, uint16_t param);
#endif /* SUNXI_PRIVATE_H */
diff --git a/plat/allwinner/common/sunxi_common.c b/plat/allwinner/common/sunxi_common.c
index 3b44aab..1e21a42 100644
--- a/plat/allwinner/common/sunxi_common.c
+++ b/plat/allwinner/common/sunxi_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -150,16 +150,16 @@
/* set both pins to pull-up */
mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x1c, 0x0fU, 0x5U);
- /* assert, then de-assert reset of I2C/RSB controller */
- mmio_clrbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit);
- mmio_setbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit);
-
/* un-gate clock */
if (socid != SUNXI_SOC_H6)
mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, device_bit);
else
mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x19c, device_bit | BIT(0));
+ /* assert, then de-assert reset of I2C/RSB controller */
+ mmio_clrbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit);
+ mmio_setbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit);
+
return 0;
}
@@ -172,8 +172,7 @@
* in SRAM, put the address of that into the reset vector and release the
* arisc reset line. The SCP will execute that code and pull the line up again.
*/
-void sunxi_execute_arisc_code(uint32_t *code, size_t size,
- int patch_offset, uint16_t param)
+void sunxi_execute_arisc_code(uint32_t *code, size_t size, uint16_t param)
{
uintptr_t arisc_reset_vec = SUNXI_SRAM_A2_BASE - 0x4000 + 0x100;
@@ -187,8 +186,7 @@
} while (1);
/* Patch up the code to feed in an input parameter. */
- if (patch_offset >= 0 && patch_offset <= (size - 4))
- code[patch_offset] = (code[patch_offset] & ~0xffff) | param;
+ code[0] = (code[0] & ~0xffff) | param;
clean_dcache_range((uintptr_t)code, size);
/*
diff --git a/plat/allwinner/common/sunxi_cpu_ops.c b/plat/allwinner/common/sunxi_cpu_ops.c
index b4c9fcc..6e29b69 100644
--- a/plat/allwinner/common/sunxi_cpu_ops.c
+++ b/plat/allwinner/common/sunxi_cpu_ops.c
@@ -78,7 +78,7 @@
* patched into the first instruction.
*/
sunxi_execute_arisc_code(arisc_core_off, sizeof(arisc_core_off),
- 0, BIT_32(core));
+ BIT_32(core));
}
void sunxi_cpu_on(u_register_t mpidr)
diff --git a/plat/allwinner/common/sunxi_pm.c b/plat/allwinner/common/sunxi_pm.c
index 13e1353..9b074d2 100644
--- a/plat/allwinner/common/sunxi_pm.c
+++ b/plat/allwinner/common/sunxi_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -65,6 +65,11 @@
sunxi_disable_secondary_cpus(read_mpidr());
sunxi_power_down();
+
+ udelay(1000);
+ ERROR("PSCI: Cannot turn off system, halting\n");
+ wfi();
+ panic();
}
static void __dead2 sunxi_system_reset(void)
diff --git a/plat/allwinner/sun50i_a64/platform.mk b/plat/allwinner/sun50i_a64/platform.mk
index b46fbc2..f6d5aa9 100644
--- a/plat/allwinner/sun50i_a64/platform.mk
+++ b/plat/allwinner/sun50i_a64/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -7,4 +7,5 @@
# The differences between the platform are covered by the include files.
include plat/allwinner/common/allwinner-common.mk
-PLAT_BL_COMMON_SOURCES += drivers/allwinner/sunxi_rsb.c
+BL31_SOURCES += drivers/allwinner/axp/axp803.c \
+ drivers/allwinner/sunxi_rsb.c
diff --git a/plat/allwinner/sun50i_a64/sunxi_power.c b/plat/allwinner/sun50i_a64/sunxi_power.c
index 07a3716..5b7d76a 100644
--- a/plat/allwinner/sun50i_a64/sunxi_power.c
+++ b/plat/allwinner/sun50i_a64/sunxi_power.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2018, Icenowy Zheng <icenowy@aosc.io>
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -7,14 +7,11 @@
#include <errno.h>
-#include <libfdt.h>
-
#include <platform_def.h>
-#include <arch_helpers.h>
#include <common/debug.h>
+#include <drivers/allwinner/axp.h>
#include <drivers/allwinner/sunxi_rsb.h>
-#include <drivers/delay_timer.h>
#include <lib/mmio.h>
#include <sunxi_def.h>
@@ -22,6 +19,7 @@
#include <sunxi_private.h>
static enum pmic_type {
+ UNKNOWN,
GENERIC_H5,
GENERIC_A64,
REF_DESIGN_H5, /* regulators controlled by GPIO pins on port L */
@@ -38,7 +36,7 @@
* disabled.
* This function only cares about peripherals.
*/
-void sunxi_turn_off_soc(uint16_t socid)
+static void sunxi_turn_off_soc(uint16_t socid)
{
int i;
@@ -113,174 +111,22 @@
return ret;
/* Associate the 8-bit runtime address with the 12-bit bus address. */
- return rsb_assign_runtime_address(AXP803_HW_ADDR,
- AXP803_RT_ADDR);
-}
-
-static int axp_write(uint8_t reg, uint8_t val)
-{
- return rsb_write(AXP803_RT_ADDR, reg, val);
-}
-
-static int axp_clrsetbits(uint8_t reg, uint8_t clr_mask, uint8_t set_mask)
-{
- uint8_t regval;
- int ret;
-
- ret = rsb_read(AXP803_RT_ADDR, reg);
- if (ret < 0)
+ ret = rsb_assign_runtime_address(AXP803_HW_ADDR,
+ AXP803_RT_ADDR);
+ if (ret)
return ret;
- regval = (ret & ~clr_mask) | set_mask;
-
- return rsb_write(AXP803_RT_ADDR, reg, regval);
-}
-
-#define axp_clrbits(reg, clr_mask) axp_clrsetbits(reg, clr_mask, 0)
-#define axp_setbits(reg, set_mask) axp_clrsetbits(reg, 0, set_mask)
-
-static bool should_enable_regulator(const void *fdt, int node)
-{
- if (fdt_getprop(fdt, node, "phandle", NULL) != NULL)
- return true;
- if (fdt_getprop(fdt, node, "regulator-always-on", NULL) != NULL)
- return true;
- return false;
+ return axp_check_id();
}
-/*
- * Retrieve the voltage from a given regulator DTB node.
- * Both the regulator-{min,max}-microvolt properties must be present and
- * have the same value. Return that value in millivolts.
- */
-static int fdt_get_regulator_millivolt(const void *fdt, int node)
+int axp_read(uint8_t reg)
{
- const fdt32_t *prop;
- uint32_t min_volt;
-
- prop = fdt_getprop(fdt, node, "regulator-min-microvolt", NULL);
- if (prop == NULL)
- return -EINVAL;
- min_volt = fdt32_to_cpu(*prop);
-
- prop = fdt_getprop(fdt, node, "regulator-max-microvolt", NULL);
- if (prop == NULL)
- return -EINVAL;
-
- if (fdt32_to_cpu(*prop) != min_volt)
- return -EINVAL;
-
- return min_volt / 1000;
+ return rsb_read(AXP803_RT_ADDR, reg);
}
-#define NO_SPLIT 0xff
-
-static const struct axp_regulator {
- char *dt_name;
- uint16_t min_volt;
- uint16_t max_volt;
- uint16_t step;
- unsigned char split;
- unsigned char volt_reg;
- unsigned char switch_reg;
- unsigned char switch_bit;
-} regulators[] = {
- {"dcdc1", 1600, 3400, 100, NO_SPLIT, 0x20, 0x10, 0},
- {"dcdc5", 800, 1840, 10, 32, 0x24, 0x10, 4},
- {"dcdc6", 600, 1520, 10, 50, 0x25, 0x10, 5},
- {"dldo1", 700, 3300, 100, NO_SPLIT, 0x15, 0x12, 3},
- {"dldo2", 700, 4200, 100, 27, 0x16, 0x12, 4},
- {"dldo3", 700, 3300, 100, NO_SPLIT, 0x17, 0x12, 5},
- {"fldo1", 700, 1450, 50, NO_SPLIT, 0x1c, 0x13, 2},
- {}
-};
-
-static int setup_regulator(const void *fdt, int node,
- const struct axp_regulator *reg)
+int axp_write(uint8_t reg, uint8_t val)
{
- int mvolt;
- uint8_t regval;
-
- if (!should_enable_regulator(fdt, node))
- return -ENOENT;
-
- mvolt = fdt_get_regulator_millivolt(fdt, node);
- if (mvolt < reg->min_volt || mvolt > reg->max_volt)
- return -EINVAL;
-
- regval = (mvolt / reg->step) - (reg->min_volt / reg->step);
- if (regval > reg->split)
- regval = ((regval - reg->split) / 2) + reg->split;
-
- axp_write(reg->volt_reg, regval);
- if (reg->switch_reg < 0xff)
- axp_setbits(reg->switch_reg, BIT(reg->switch_bit));
-
- INFO("PMIC: AXP803: %s voltage: %d.%03dV\n", reg->dt_name,
- mvolt / 1000, mvolt % 1000);
-
- return 0;
-}
-
-static void setup_axp803_rails(const void *fdt)
-{
- int node;
- bool dc1sw = false;
-
- /* locate the PMIC DT node, bail out if not found */
- node = fdt_node_offset_by_compatible(fdt, -1, "x-powers,axp803");
- if (node < 0) {
- WARN("BL31: PMIC: Cannot find AXP803 DT node, skipping initial setup.\n");
- return;
- }
-
- if (fdt_getprop(fdt, node, "x-powers,drive-vbus-en", NULL)) {
- axp_clrbits(0x8f, BIT(4));
- axp_setbits(0x30, BIT(2));
- INFO("PMIC: AXP803: Enabling DRIVEVBUS\n");
- }
-
- /* descend into the "regulators" subnode */
- node = fdt_subnode_offset(fdt, node, "regulators");
- if (node < 0) {
- WARN("BL31: PMIC: Cannot find regulators subnode, skipping initial setup.\n");
- return;
- }
-
- /* iterate over all regulators to find used ones */
- for (node = fdt_first_subnode(fdt, node);
- node >= 0;
- node = fdt_next_subnode(fdt, node)) {
- const struct axp_regulator *reg;
- const char *name;
- int length;
-
- /* We only care if it's always on or referenced. */
- if (!should_enable_regulator(fdt, node))
- continue;
-
- name = fdt_get_name(fdt, node, &length);
- for (reg = regulators; reg->dt_name; reg++) {
- if (!strncmp(name, reg->dt_name, length)) {
- setup_regulator(fdt, node, reg);
- break;
- }
- }
-
- if (!strncmp(name, "dc1sw", length)) {
- /* Delay DC1SW enablement to avoid overheating. */
- dc1sw = true;
- continue;
- }
- }
- /*
- * If DLDO2 is enabled after DC1SW, the PMIC overheats and shuts
- * down. So always enable DC1SW as the very last regulator.
- */
- if (dc1sw) {
- INFO("PMIC: AXP803: Enabling DC1SW\n");
- axp_setbits(0x12, BIT(7));
- }
+ return rsb_write(AXP803_RT_ADDR, reg, val);
}
int sunxi_pmic_setup(uint16_t socid, const void *fdt)
@@ -289,11 +135,16 @@
switch (socid) {
case SUNXI_SOC_H5:
+ NOTICE("PMIC: Assuming H5 reference regulator design\n");
+
pmic = REF_DESIGN_H5;
- NOTICE("BL31: PMIC: Defaulting to PortL GPIO according to H5 reference design.\n");
+
break;
case SUNXI_SOC_A64:
pmic = GENERIC_A64;
+
+ INFO("PMIC: Probing AXP803 on RSB\n");
+
ret = sunxi_init_platform_r_twi(socid, true);
if (ret)
return ret;
@@ -303,20 +154,16 @@
return ret;
pmic = AXP803_RSB;
- NOTICE("BL31: PMIC: Detected AXP803 on RSB.\n");
-
- if (fdt)
- setup_axp803_rails(fdt);
+ axp_setup_regulators(fdt);
break;
default:
- NOTICE("BL31: PMIC: No support for Allwinner %x SoC.\n", socid);
return -ENODEV;
}
return 0;
}
-void __dead2 sunxi_power_down(void)
+void sunxi_power_down(void)
{
switch (pmic) {
case GENERIC_H5:
@@ -354,16 +201,10 @@
/* (Re-)init RSB in case the rich OS has disabled it. */
sunxi_init_platform_r_twi(SUNXI_SOC_A64, true);
rsb_init();
-
- /* Set "power disable control" bit */
- axp_setbits(0x32, BIT(7));
+ axp_power_off();
break;
default:
break;
}
- udelay(1000);
- ERROR("PSCI: Cannot turn off system, halting.\n");
- wfi();
- panic();
}
diff --git a/plat/allwinner/sun50i_h6/platform.mk b/plat/allwinner/sun50i_h6/platform.mk
index 5c21ead..4ecc57c 100644
--- a/plat/allwinner/sun50i_h6/platform.mk
+++ b/plat/allwinner/sun50i_h6/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -7,4 +7,5 @@
# The differences between the platform are covered by the include files.
include plat/allwinner/common/allwinner-common.mk
-PLAT_BL_COMMON_SOURCES += drivers/mentor/i2c/mi2cv.c
+BL31_SOURCES += drivers/allwinner/axp/axp805.c \
+ drivers/mentor/i2c/mi2cv.c
diff --git a/plat/allwinner/sun50i_h6/sunxi_power.c b/plat/allwinner/sun50i_h6/sunxi_power.c
index 5b5bad1..443015b 100644
--- a/plat/allwinner/sun50i_h6/sunxi_power.c
+++ b/plat/allwinner/sun50i_h6/sunxi_power.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2018, Icenowy Zheng <icenowy@aosc.io>
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -10,6 +10,7 @@
#include <arch_helpers.h>
#include <common/debug.h>
+#include <drivers/allwinner/axp.h>
#include <drivers/delay_timer.h>
#include <drivers/mentor/mi2cv.h>
#include <lib/mmio.h>
@@ -19,53 +20,51 @@
#include <sunxi_private.h>
#define AXP805_ADDR 0x36
-#define AXP805_ID 0x03
-enum pmic_type {
- NO_PMIC,
+static enum pmic_type {
+ UNKNOWN,
AXP805,
-};
+} pmic;
-enum pmic_type pmic;
-
-int axp_i2c_read(uint8_t chip, uint8_t reg, uint8_t *val)
+int axp_read(uint8_t reg)
{
+ uint8_t val;
int ret;
- ret = i2c_write(chip, 0, 0, ®, 1);
- if (ret)
+ ret = i2c_write(AXP805_ADDR, 0, 0, ®, 1);
+ if (ret == 0)
+ ret = i2c_read(AXP805_ADDR, 0, 0, &val, 1);
+ if (ret) {
+ ERROR("PMIC: Cannot read AXP805 register %02x\n", reg);
return ret;
+ }
- return i2c_read(chip, 0, 0, val, 1);
+ return val;
}
-int axp_i2c_write(uint8_t chip, uint8_t reg, uint8_t val)
+int axp_write(uint8_t reg, uint8_t val)
{
- return i2c_write(chip, reg, 1, &val, 1);
+ int ret;
+
+ ret = i2c_write(AXP805_ADDR, reg, 1, &val, 1);
+ if (ret)
+ ERROR("PMIC: Cannot write AXP805 register %02x\n", reg);
+
+ return ret;
}
static int axp805_probe(void)
{
int ret;
- uint8_t val;
- ret = axp_i2c_write(AXP805_ADDR, 0xff, 0x0);
- if (ret) {
- ERROR("PMIC: Cannot put AXP805 to master mode.\n");
- return -EPERM;
- }
-
- ret = axp_i2c_read(AXP805_ADDR, AXP805_ID, &val);
+ /* Switch the AXP805 to master/single-PMIC mode. */
+ ret = axp_write(0xff, 0x0);
+ if (ret)
+ return ret;
- if (!ret && ((val & 0xcf) == 0x40))
- NOTICE("PMIC: AXP805 detected\n");
- else if (ret) {
- ERROR("PMIC: Cannot communicate with AXP805.\n");
- return -EPERM;
- } else {
- ERROR("PMIC: Non-AXP805 chip attached at AXP805's address.\n");
- return -EINVAL;
- }
+ ret = axp_check_id();
+ if (ret)
+ return ret;
return 0;
}
@@ -74,41 +73,36 @@
{
int ret;
+ INFO("PMIC: Probing AXP805 on I2C\n");
+
- sunxi_init_platform_r_twi(SUNXI_SOC_H6, false);
+ ret = sunxi_init_platform_r_twi(SUNXI_SOC_H6, false);
+ if (ret)
+ return ret;
+
/* initialise mi2cv driver */
i2c_init((void *)SUNXI_R_I2C_BASE);
- NOTICE("PMIC: Probing AXP805\n");
- pmic = AXP805;
-
ret = axp805_probe();
if (ret)
- pmic = NO_PMIC;
- else
- pmic = AXP805;
+ return ret;
+
+ pmic = AXP805;
+ axp_setup_regulators(fdt);
return 0;
}
-void __dead2 sunxi_power_down(void)
+void sunxi_power_down(void)
{
- uint8_t val;
-
switch (pmic) {
case AXP805:
/* Re-initialise after rich OS might have used it. */
sunxi_init_platform_r_twi(SUNXI_SOC_H6, false);
/* initialise mi2cv driver */
i2c_init((void *)SUNXI_R_I2C_BASE);
- axp_i2c_read(AXP805_ADDR, 0x32, &val);
- axp_i2c_write(AXP805_ADDR, 0x32, val | 0x80);
+ axp_power_off();
break;
default:
break;
}
-
- udelay(1000);
- ERROR("PSCI: Cannot communicate with PMIC, halting\n");
- wfi();
- panic();
}
diff --git a/plat/arm/common/arm_gicv3.c b/plat/arm/common/arm_gicv3.c
index cfc5359..4a3a22e 100644
--- a/plat/arm/common/arm_gicv3.c
+++ b/plat/arm/common/arm_gicv3.c
@@ -44,12 +44,11 @@
/*
* We save and restore the GICv3 context on system suspend. Allocate the
- * data in the designated EL3 Secure carve-out memory. The `volatile`
- * is used to prevent the compiler from removing the gicv3 contexts even
- * though the DEFINE_LOAD_SYM_ADDR creates a dummy reference to it.
+ * data in the designated EL3 Secure carve-out memory. The `used` attribute
+ * is used to prevent the compiler from removing the gicv3 contexts.
*/
-static volatile gicv3_redist_ctx_t rdist_ctx __section("arm_el3_tzc_dram");
-static volatile gicv3_dist_ctx_t dist_ctx __section("arm_el3_tzc_dram");
+static gicv3_redist_ctx_t rdist_ctx __section("arm_el3_tzc_dram") __used;
+static gicv3_dist_ctx_t dist_ctx __section("arm_el3_tzc_dram") __used;
/* Define accessor function to get reference to the GICv3 context */
DEFINE_LOAD_SYM_ADDR(rdist_ctx)
diff --git a/plat/intel/soc/common/aarch64/plat_helpers.S b/plat/intel/soc/common/aarch64/plat_helpers.S
index 00fe2d9..27b538a 100644
--- a/plat/intel/soc/common/aarch64/plat_helpers.S
+++ b/plat/intel/soc/common/aarch64/plat_helpers.S
@@ -8,6 +8,7 @@
#include <asm_macros.S>
#include <cpu_macros.S>
#include <platform_def.h>
+#include <el3_common_macros.S>
.globl plat_secondary_cold_boot_setup
.globl platform_is_primary_cpu
@@ -17,6 +18,7 @@
.globl plat_crash_console_putc
.globl plat_crash_console_flush
.globl platform_mem_init
+ .globl plat_secondary_cpus_bl31_entry
.globl plat_get_my_entrypoint
@@ -33,7 +35,6 @@
/* Wait until the it gets reset signal from rstmgr gets populated */
poll_mailbox:
wfi
-
mov_imm x0, PLAT_SEC_ENTRY
ldr x1, [x0]
mov_imm x2, PLAT_CPUID_RELEASE
@@ -114,3 +115,14 @@
mov x0, #0
ret
endfunc platform_mem_init
+
+func plat_secondary_cpus_bl31_entry
+ el3_entrypoint_common \
+ _init_sctlr=0 \
+ _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
+ _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
+ _init_memory=1 \
+ _init_c_runtime=1 \
+ _exception_vectors=runtime_exceptions \
+ _pie_fixup_size=BL31_LIMIT - BL31_BASE
+endfunc plat_secondary_cpus_bl31_entry
diff --git a/plat/intel/soc/common/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h
index e57aafb..d6014d3 100644
--- a/plat/intel/soc/common/include/platform_def.h
+++ b/plat/intel/soc/common/include/platform_def.h
@@ -16,8 +16,8 @@
#define PLAT_SOCFPGA_STRATIX10 1
#define PLAT_SOCFPGA_AGILEX 2
-#define PLAT_CPUID_RELEASE 0xffe1b000
-#define PLAT_SEC_ENTRY 0xffe1b008
+/* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */
+#define PLAT_CPU_RELEASE_ADDR 0xffd12210
/* Define next boot image name and offset */
#define PLAT_NS_IMAGE_OFFSET 0x50000
@@ -106,19 +106,24 @@
*/
-#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
+#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
-#define BL1_RO_BASE (0xffe00000)
-#define BL1_RO_LIMIT (0xffe0f000)
-#define BL1_RW_BASE (0xffe10000)
-#define BL1_RW_LIMIT (0xffe1ffff)
-#define BL1_RW_SIZE (0x14000)
+#define BL1_RO_BASE (0xffe00000)
+#define BL1_RO_LIMIT (0xffe0f000)
+#define BL1_RW_BASE (0xffe10000)
+#define BL1_RW_LIMIT (0xffe1ffff)
+#define BL1_RW_SIZE (0x14000)
-#define BL2_BASE (0xffe00000)
-#define BL2_LIMIT (0xffe1b000)
+#define BL2_BASE (0xffe00000)
+#define BL2_LIMIT (0xffe1b000)
-#define BL31_BASE (0xffe1c000)
-#define BL31_LIMIT (0xffe3bfff)
+#define BL31_BASE (0x1000)
+#define BL31_LIMIT (0x81000)
+
+#define BL_DATA_LIMIT PLAT_HANDOFF_OFFSET
+
+#define PLAT_CPUID_RELEASE (BL_DATA_LIMIT - 16)
+#define PLAT_SEC_ENTRY (BL_DATA_LIMIT - 8)
/*******************************************************************************
* Platform specific page table and MMU setup constants
@@ -194,5 +199,16 @@
#define MAX_IO_DEVICES 4
#define MAX_IO_BLOCK_DEVICES 2
+#ifndef __ASSEMBLER__
+struct socfpga_bl31_params {
+ param_header_t h;
+ image_info_t *bl31_image_info;
+ entry_point_info_t *bl32_ep_info;
+ image_info_t *bl32_image_info;
+ entry_point_info_t *bl33_ep_info;
+ image_info_t *bl33_image_info;
+};
+#endif
+
#endif /* PLATFORM_DEF_H */
diff --git a/plat/intel/soc/common/include/socfpga_private.h b/plat/intel/soc/common/include/socfpga_private.h
index 3754844..ca38f62 100644
--- a/plat/intel/soc/common/include/socfpga_private.h
+++ b/plat/intel/soc/common/include/socfpga_private.h
@@ -61,5 +61,6 @@
unsigned long socfpga_get_ns_image_entrypoint(void);
+void plat_secondary_cpus_bl31_entry(void);
#endif /* SOCFPGA_PRIVATE_H */
diff --git a/plat/intel/soc/common/socfpga_psci.c b/plat/intel/soc/common/socfpga_psci.c
index e298361..65a4b09 100644
--- a/plat/intel/soc/common/socfpga_psci.c
+++ b/plat/intel/soc/common/socfpga_psci.c
@@ -15,8 +15,6 @@
#include "socfpga_plat_def.h"
-uintptr_t *socfpga_sec_entry = (uintptr_t *) PLAT_SEC_ENTRY;
-uintptr_t *cpuid_release = (uintptr_t *) PLAT_CPUID_RELEASE;
/*******************************************************************************
* plat handler called when a CPU is about to enter standby.
@@ -45,7 +43,7 @@
if (cpu_id == -1)
return PSCI_E_INTERN_FAIL;
- *cpuid_release = cpu_id;
+ mmio_write_64(PLAT_CPUID_RELEASE, cpu_id);
/* release core reset */
mmio_setbits_32(SOCFPGA_RSTMGR_MPUMODRST_OFST, 1 << cpu_id);
@@ -183,8 +181,8 @@
const struct plat_psci_ops **psci_ops)
{
/* Save warm boot entrypoint.*/
- *socfpga_sec_entry = sec_entrypoint;
-
+ mmio_write_64(PLAT_SEC_ENTRY, sec_entrypoint);
*psci_ops = &socfpga_psci_pm_ops;
+
return 0;
}
diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c
index a133f82..29bd176 100644
--- a/plat/intel/soc/stratix10/bl31_plat_setup.c
+++ b/plat/intel/soc/stratix10/bl31_plat_setup.c
@@ -53,23 +53,33 @@
void *from_bl2 = (void *) arg0;
bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
-
assert(params_from_bl2 != NULL);
- assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
- assert(params_from_bl2->h.version >= VERSION_2);
/*
* Copy BL32 (if populated by BL31) and BL33 entry point information.
* They are stored in Secure RAM, in BL31's address space.
*/
+ if (params_from_bl2->h.type == PARAM_BL_PARAMS &&
+ params_from_bl2->h.version >= VERSION_2) {
+
- bl_params_node_t *bl_params = params_from_bl2->head;
+ bl_params_node_t *bl_params = params_from_bl2->head;
- while (bl_params) {
- if (bl_params->image_id == BL33_IMAGE_ID)
- bl33_image_ep_info = *bl_params->ep_info;
+ while (bl_params) {
+ if (bl_params->image_id == BL33_IMAGE_ID)
+ bl33_image_ep_info = *bl_params->ep_info;
- bl_params = bl_params->next_params_info;
+ bl_params = bl_params->next_params_info;
+ }
+ } else {
+ struct socfpga_bl31_params *arg_from_bl2 =
+ (struct socfpga_bl31_params *) from_bl2;
+
+ assert(arg_from_bl2->h.type == PARAM_BL31);
+ assert(arg_from_bl2->h.version >= VERSION_1);
+
+ bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
+ bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
}
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
}
@@ -100,6 +110,10 @@
gicv2_distif_init();
gicv2_pcpu_distif_init();
gicv2_cpuif_enable();
+
+ /* Signal secondary CPUs to jump to BL31 (BL2 = U-boot SPL) */
+ mmio_write_64(PLAT_CPU_RELEASE_ADDR,
+ (uint64_t)plat_secondary_cpus_bl31_entry);
}
const mmap_region_t plat_stratix10_mmap[] = {
diff --git a/plat/intel/soc/stratix10/plat_psci.c b/plat/intel/soc/stratix10/plat_psci.c
deleted file mode 100644
index 73389c9..0000000
--- a/plat/intel/soc/stratix10/plat_psci.c
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch_helpers.h>
-#include <assert.h>
-#include <common/debug.h>
-#include <errno.h>
-#include <lib/mmio.h>
-#include <drivers/arm/gic_common.h>
-#include <drivers/arm/gicv2.h>
-#include <plat/common/platform.h>
-#include <lib/psci/psci.h>
-
-#include "platform_def.h"
-#include "s10_reset_manager.h"
-#include "socfpga_mailbox.h"
-
-#define S10_RSTMGR_OFST 0xffd11000
-#define S10_RSTMGR_MPUMODRST_OFST 0x20
-
-uintptr_t *stratix10_sec_entry = (uintptr_t *) PLAT_SEC_ENTRY;
-uintptr_t *cpuid_release = (uintptr_t *) PLAT_CPUID_RELEASE;
-
-/*******************************************************************************
- * plat handler called when a CPU is about to enter standby.
- ******************************************************************************/
-void plat_cpu_standby(plat_local_state_t cpu_state)
-{
- /*
- * Enter standby state
- * dsb is good practice before using wfi to enter low power states
- */
- VERBOSE("%s: cpu_state: 0x%x\n", __func__, cpu_state);
- dsb();
- wfi();
-}
-
-/*******************************************************************************
- * plat handler called when a power domain is about to be turned on. The
- * mpidr determines the CPU to be turned on.
- ******************************************************************************/
-int plat_pwr_domain_on(u_register_t mpidr)
-{
- unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr);
-
- VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr);
-
- if (cpu_id == -1)
- return PSCI_E_INTERN_FAIL;
-
- *cpuid_release = cpu_id;
-
- /* release core reset */
- mmio_setbits_32(S10_RSTMGR_OFST + S10_RSTMGR_MPUMODRST_OFST,
- 1 << cpu_id);
- return PSCI_E_SUCCESS;
-}
-
-/*******************************************************************************
- * plat handler called when a power domain is about to be turned off. The
- * target_state encodes the power state that each level should transition to.
- ******************************************************************************/
-void plat_pwr_domain_off(const psci_power_state_t *target_state)
-{
- unsigned int cpu_id = plat_my_core_pos();
-
- for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
- VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
- __func__, i, target_state->pwr_domain_state[i]);
-
- /* TODO: Prevent interrupts from spuriously waking up this cpu */
- /* gicv2_cpuif_disable(); */
-
- /* assert core reset */
- mmio_setbits_32(S10_RSTMGR_OFST + S10_RSTMGR_MPUMODRST_OFST,
- 1 << cpu_id);
-}
-
-/*******************************************************************************
- * plat handler called when a power domain is about to be suspended. The
- * target_state encodes the power state that each level should transition to.
- ******************************************************************************/
-void plat_pwr_domain_suspend(const psci_power_state_t *target_state)
-{
- unsigned int cpu_id = plat_my_core_pos();
-
- for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
- VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
- __func__, i, target_state->pwr_domain_state[i]);
- /* assert core reset */
- mmio_setbits_32(S10_RSTMGR_OFST + S10_RSTMGR_MPUMODRST_OFST,
- 1 << cpu_id);
-
-}
-
-/*******************************************************************************
- * plat handler called when a power domain has just been powered on after
- * being turned off earlier. The target_state encodes the low power state that
- * each level has woken up from.
- ******************************************************************************/
-void plat_pwr_domain_on_finish(const psci_power_state_t *target_state)
-{
- for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
- VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
- __func__, i, target_state->pwr_domain_state[i]);
-
- /* Program the gic per-cpu distributor or re-distributor interface */
- gicv2_pcpu_distif_init();
- gicv2_set_pe_target_mask(plat_my_core_pos());
-
- /* Enable the gic cpu interface */
- gicv2_cpuif_enable();
-}
-
-/*******************************************************************************
- * plat handler called when a power domain has just been powered on after
- * having been suspended earlier. The target_state encodes the low power state
- * that each level has woken up from.
- * TODO: At the moment we reuse the on finisher and reinitialize the secure
- * context. Need to implement a separate suspend finisher.
- ******************************************************************************/
-void plat_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
-{
- unsigned int cpu_id = plat_my_core_pos();
-
- for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
- VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
- __func__, i, target_state->pwr_domain_state[i]);
-
- /* release core reset */
- mmio_clrbits_32(S10_RSTMGR_OFST + S10_RSTMGR_MPUMODRST_OFST,
- 1 << cpu_id);
-}
-
-/*******************************************************************************
- * plat handlers to shutdown/reboot the system
- ******************************************************************************/
-static void __dead2 plat_system_off(void)
-{
- wfi();
- ERROR("System Off: operation not handled.\n");
- panic();
-}
-
-static void __dead2 plat_system_reset(void)
-{
- INFO("assert Peripheral from Reset\r\n");
-
- deassert_peripheral_reset();
- mailbox_reset_cold();
-
- while (1)
- wfi();
-}
-
-int plat_validate_power_state(unsigned int power_state,
- psci_power_state_t *req_state)
-{
- VERBOSE("%s: power_state: 0x%x\n", __func__, power_state);
-
- return PSCI_E_SUCCESS;
-}
-
-int plat_validate_ns_entrypoint(unsigned long ns_entrypoint)
-{
- VERBOSE("%s: ns_entrypoint: 0x%lx\n", __func__, ns_entrypoint);
- return PSCI_E_SUCCESS;
-}
-
-void plat_get_sys_suspend_power_state(psci_power_state_t *req_state)
-{
- req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE;
- req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE;
-}
-
-/*******************************************************************************
- * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
- * platform layer will take care of registering the handlers with PSCI.
- ******************************************************************************/
-const plat_psci_ops_t plat_psci_pm_ops = {
- .cpu_standby = plat_cpu_standby,
- .pwr_domain_on = plat_pwr_domain_on,
- .pwr_domain_off = plat_pwr_domain_off,
- .pwr_domain_suspend = plat_pwr_domain_suspend,
- .pwr_domain_on_finish = plat_pwr_domain_on_finish,
- .pwr_domain_suspend_finish = plat_pwr_domain_suspend_finish,
- .system_off = plat_system_off,
- .system_reset = plat_system_reset,
- .validate_power_state = plat_validate_power_state,
- .validate_ns_entrypoint = plat_validate_ns_entrypoint,
- .get_sys_suspend_power_state = plat_get_sys_suspend_power_state
-};
-
-/*******************************************************************************
- * Export the platform specific power ops.
- ******************************************************************************/
-int plat_setup_psci_ops(uintptr_t sec_entrypoint,
- const struct plat_psci_ops **psci_ops)
-{
- /* Save warm boot entrypoint.*/
- *stratix10_sec_entry = sec_entrypoint;
-
- *psci_ops = &plat_psci_pm_ops;
- return 0;
-}
diff --git a/plat/intel/soc/stratix10/plat_sip_svc.c b/plat/intel/soc/stratix10/plat_sip_svc.c
deleted file mode 100644
index 23a009d..0000000
--- a/plat/intel/soc/stratix10/plat_sip_svc.c
+++ /dev/null
@@ -1,378 +0,0 @@
-/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <common/debug.h>
-#include <common/runtime_svc.h>
-#include <lib/mmio.h>
-#include <socfpga_mailbox.h>
-#include <tools_share/uuid.h>
-
-/* Number of SiP Calls implemented */
-#define SIP_NUM_CALLS 0x3
-
-/* Total buffer the driver can hold */
-#define FPGA_CONFIG_BUFFER_SIZE 4
-
-int current_block;
-int current_buffer;
-int current_id = 1;
-int max_blocks;
-uint32_t bytes_per_block;
-uint32_t blocks_submitted;
-uint32_t blocks_completed;
-
-struct fpga_config_info {
- uint32_t addr;
- int size;
- int size_written;
- uint32_t write_requested;
- int subblocks_sent;
- int block_number;
-};
-
-/* SiP Service UUID */
-DEFINE_SVC_UUID2(intl_svc_uid,
- 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a,
- 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81);
-
-uint64_t plat_sip_handler(uint32_t smc_fid,
- uint64_t x1,
- uint64_t x2,
- uint64_t x3,
- uint64_t x4,
- void *cookie,
- void *handle,
- uint64_t flags)
-{
- ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
- SMC_RET1(handle, SMC_UNK);
-}
-
-struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE];
-
-static void intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer)
-{
- uint32_t args[3];
-
- while (max_blocks > 0 && buffer->size > buffer->size_written) {
- if (buffer->size - buffer->size_written <=
- bytes_per_block) {
- args[0] = (1<<8);
- args[1] = buffer->addr + buffer->size_written;
- args[2] = buffer->size - buffer->size_written;
- buffer->size_written +=
- buffer->size - buffer->size_written;
- buffer->subblocks_sent++;
- mailbox_send_cmd_async(0x4,
- MBOX_RECONFIG_DATA,
- args, 3, 0);
- current_buffer++;
- current_buffer %= FPGA_CONFIG_BUFFER_SIZE;
- } else {
- args[0] = (1<<8);
- args[1] = buffer->addr + buffer->size_written;
- args[2] = bytes_per_block;
- buffer->size_written += bytes_per_block;
- mailbox_send_cmd_async(0x4,
- MBOX_RECONFIG_DATA,
- args, 3, 0);
- buffer->subblocks_sent++;
- }
- max_blocks--;
- }
-}
-
-static int intel_fpga_sdm_write_all(void)
-{
- int i;
-
- for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++)
- intel_fpga_sdm_write_buffer(
- &fpga_config_buffers[current_buffer]);
-
- return 0;
-}
-
-uint32_t intel_mailbox_fpga_config_isdone(void)
-{
- uint32_t args[2];
- uint32_t response[6];
- int status;
-
- status = mailbox_send_cmd(1, MBOX_RECONFIG_STATUS, args, 0, 0,
- response);
-
- if (status < 0)
- return INTEL_SIP_SMC_STATUS_ERROR;
-
- if (response[RECONFIG_STATUS_STATE] &&
- response[RECONFIG_STATUS_STATE] != MBOX_CFGSTAT_STATE_CONFIG)
- return INTEL_SIP_SMC_STATUS_ERROR;
-
- if (!(response[RECONFIG_STATUS_PIN_STATUS] & PIN_STATUS_NSTATUS))
- return INTEL_SIP_SMC_STATUS_ERROR;
-
- if (response[RECONFIG_STATUS_SOFTFUNC_STATUS] &
- SOFTFUNC_STATUS_SEU_ERROR)
- return INTEL_SIP_SMC_STATUS_ERROR;
-
- if ((response[RECONFIG_STATUS_SOFTFUNC_STATUS] &
- SOFTFUNC_STATUS_CONF_DONE) &&
- (response[RECONFIG_STATUS_SOFTFUNC_STATUS] &
- SOFTFUNC_STATUS_INIT_DONE))
- return INTEL_SIP_SMC_STATUS_OK;
-
- return INTEL_SIP_SMC_STATUS_ERROR;
-}
-
-static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed)
-{
- int i;
-
- for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
- if (fpga_config_buffers[i].block_number == current_block) {
- fpga_config_buffers[i].subblocks_sent--;
- if (fpga_config_buffers[i].subblocks_sent == 0
- && fpga_config_buffers[i].size <=
- fpga_config_buffers[i].size_written) {
- fpga_config_buffers[i].write_requested = 0;
- current_block++;
- *buffer_addr_completed =
- fpga_config_buffers[i].addr;
- return 0;
- }
- }
- }
-
- return -1;
-}
-
-unsigned int address_in_ddr(uint32_t *addr)
-{
- if (((unsigned long long)addr > DRAM_BASE) &&
- ((unsigned long long)addr < DRAM_BASE + DRAM_SIZE))
- return 0;
-
- return -1;
-}
-
-int intel_fpga_config_completed_write(uint32_t *completed_addr,
- uint32_t *count)
-{
- uint32_t status = INTEL_SIP_SMC_STATUS_OK;
- *count = 0;
- int resp_len = 0;
- uint32_t resp[5];
- int all_completed = 1;
- int count_check = 0;
-
- if (address_in_ddr(completed_addr) != 0 || address_in_ddr(count) != 0)
- return INTEL_SIP_SMC_STATUS_ERROR;
-
- for (count_check = 0; count_check < 3; count_check++)
- if (address_in_ddr(&completed_addr[*count + count_check]) != 0)
- return INTEL_SIP_SMC_STATUS_ERROR;
-
- resp_len = mailbox_read_response(0x4, resp);
-
- while (resp_len >= 0 && *count < 3) {
- max_blocks++;
- if (mark_last_buffer_xfer_completed(
- &completed_addr[*count]) == 0)
- *count = *count + 1;
- else
- break;
- resp_len = mailbox_read_response(0x4, resp);
- }
-
- if (*count <= 0) {
- if (resp_len != MBOX_NO_RESPONSE &&
- resp_len != MBOX_TIMEOUT && resp_len != 0) {
- return INTEL_SIP_SMC_STATUS_ERROR;
- }
-
- *count = 0;
- }
-
- intel_fpga_sdm_write_all();
-
- if (*count > 0)
- status = INTEL_SIP_SMC_STATUS_OK;
- else if (*count == 0)
- status = INTEL_SIP_SMC_STATUS_BUSY;
-
- for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
- if (fpga_config_buffers[i].write_requested != 0) {
- all_completed = 0;
- break;
- }
- }
-
- if (all_completed == 1)
- return INTEL_SIP_SMC_STATUS_OK;
-
- return status;
-}
-
-int intel_fpga_config_start(uint32_t config_type)
-{
- uint32_t response[3];
- int status = 0;
-
- status = mailbox_send_cmd(2, MBOX_RECONFIG, 0, 0, 0,
- response);
-
- if (status < 0)
- return status;
-
- max_blocks = response[0];
- bytes_per_block = response[1];
-
- for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
- fpga_config_buffers[i].size = 0;
- fpga_config_buffers[i].size_written = 0;
- fpga_config_buffers[i].addr = 0;
- fpga_config_buffers[i].write_requested = 0;
- fpga_config_buffers[i].block_number = 0;
- fpga_config_buffers[i].subblocks_sent = 0;
- }
-
- blocks_submitted = 0;
- current_block = 0;
- current_buffer = 0;
-
- return 0;
-}
-
-
-uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size)
-{
- int i = 0;
- uint32_t status = INTEL_SIP_SMC_STATUS_OK;
-
- if (mem < DRAM_BASE || mem > DRAM_BASE + DRAM_SIZE)
- status = INTEL_SIP_SMC_STATUS_REJECTED;
-
- if (mem + size > DRAM_BASE + DRAM_SIZE)
- status = INTEL_SIP_SMC_STATUS_REJECTED;
-
- for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
- if (!fpga_config_buffers[i].write_requested) {
- fpga_config_buffers[i].addr = mem;
- fpga_config_buffers[i].size = size;
- fpga_config_buffers[i].size_written = 0;
- fpga_config_buffers[i].write_requested = 1;
- fpga_config_buffers[i].block_number =
- blocks_submitted++;
- fpga_config_buffers[i].subblocks_sent = 0;
- break;
- }
- }
-
-
- if (i == FPGA_CONFIG_BUFFER_SIZE) {
- status = INTEL_SIP_SMC_STATUS_REJECTED;
- return status;
- } else if (i == FPGA_CONFIG_BUFFER_SIZE - 1) {
- status = INTEL_SIP_SMC_STATUS_BUSY;
- }
-
- intel_fpga_sdm_write_all();
-
- return status;
-}
-
-/*
- * This function is responsible for handling all SiP calls from the NS world
- */
-
-uintptr_t sip_smc_handler(uint32_t smc_fid,
- u_register_t x1,
- u_register_t x2,
- u_register_t x3,
- u_register_t x4,
- void *cookie,
- void *handle,
- u_register_t flags)
-{
- uint32_t status = INTEL_SIP_SMC_STATUS_OK;
- uint32_t completed_addr[3];
- uint32_t count = 0;
-
- switch (smc_fid) {
- case SIP_SVC_UID:
- /* Return UID to the caller */
- SMC_UUID_RET(handle, intl_svc_uid);
- break;
- case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE:
- status = intel_mailbox_fpga_config_isdone();
- SMC_RET4(handle, status, 0, 0, 0);
- break;
- case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM:
- SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
- INTEL_SIP_SMC_FPGA_CONFIG_ADDR,
- INTEL_SIP_SMC_FPGA_CONFIG_SIZE -
- INTEL_SIP_SMC_FPGA_CONFIG_ADDR);
- break;
- case INTEL_SIP_SMC_FPGA_CONFIG_START:
- status = intel_fpga_config_start(x1);
- SMC_RET4(handle, status, 0, 0, 0);
- break;
- case INTEL_SIP_SMC_FPGA_CONFIG_WRITE:
- status = intel_fpga_config_write(x1, x2);
- SMC_RET4(handle, status, 0, 0, 0);
- break;
- case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE:
- status = intel_fpga_config_completed_write(completed_addr,
- &count);
- switch (count) {
- case 1:
- SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
- completed_addr[0], 0, 0);
- break;
- case 2:
- SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
- completed_addr[0],
- completed_addr[1], 0);
- break;
- case 3:
- SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
- completed_addr[0],
- completed_addr[1],
- completed_addr[2]);
- break;
- case 0:
- SMC_RET4(handle, status, 0, 0, 0);
- break;
- default:
- SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR);
- }
- break;
-
- default:
- return plat_sip_handler(smc_fid, x1, x2, x3, x4,
- cookie, handle, flags);
- }
-}
-
-DECLARE_RT_SVC(
- s10_sip_svc,
- OEN_SIP_START,
- OEN_SIP_END,
- SMC_TYPE_FAST,
- NULL,
- sip_smc_handler
-);
-
-DECLARE_RT_SVC(
- s10_sip_svc_std,
- OEN_SIP_START,
- OEN_SIP_END,
- SMC_TYPE_YIELD,
- NULL,
- sip_smc_handler
-);
diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h
index 1a9ba0a..67f5abb 100644
--- a/plat/nvidia/tegra/include/t194/tegra_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_def.h
@@ -10,6 +10,12 @@
#include <lib/utils_def.h>
/*******************************************************************************
+ * Chip specific page table and MMU setup constants
+ ******************************************************************************/
+#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 40)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 40)
+
+/*******************************************************************************
* These values are used by the PSCI implementation during the `CPU_SUSPEND`
* and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state'
* parameter.
diff --git a/plat/nvidia/tegra/include/t194/tegra_mc_def.h b/plat/nvidia/tegra/include/t194/tegra_mc_def.h
new file mode 100644
index 0000000..e0444c1
--- /dev/null
+++ b/plat/nvidia/tegra/include/t194/tegra_mc_def.h
@@ -0,0 +1,650 @@
+/*
+ * Copyright (c) 2019, NVIDIA Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __TEGRA_MC_DEF_H__
+#define __TEGRA_MC_DEF_H__
+
+/*******************************************************************************
+ * Memory Controller Order_id registers
+ ******************************************************************************/
+#define MC_CLIENT_ORDER_ID_9 U(0x2a24)
+#define MC_CLIENT_ORDER_ID_9_RESET_VAL 0x00000000U
+#define MC_CLIENT_ORDER_ID_9_XUSB_HOSTW_MASK (0x3U << 12)
+#define MC_CLIENT_ORDER_ID_9_XUSB_HOSTW_ORDER_ID (3U << 12)
+
+#define MC_CLIENT_ORDER_ID_27 U(0x2a6c)
+#define MC_CLIENT_ORDER_ID_27_RESET_VAL 0x00000000U
+#define MC_CLIENT_ORDER_ID_27_PCIE0W_MASK (0x3U << 4)
+#define MC_CLIENT_ORDER_ID_27_PCIE0W_ORDER_ID (1U << 4)
+
+#define MC_CLIENT_ORDER_ID_28 U(0x2a70)
+#define MC_CLIENT_ORDER_ID_28_RESET_VAL 0x00000000U
+#define MC_CLIENT_ORDER_ID_28_PCIE4W_MASK (0x3U << 4)
+#define MC_CLIENT_ORDER_ID_28_PCIE4W_ORDER_ID (3U << 4)
+#define MC_CLIENT_ORDER_ID_28_PCIE5W_MASK (0x3U << 12)
+#define MC_CLIENT_ORDER_ID_28_PCIE5W_ORDER_ID (2U << 12)
+
+#define mc_client_order_id(id, client) \
+ (~MC_CLIENT_ORDER_ID_##id##_##client##_MASK | \
+ MC_CLIENT_ORDER_ID_##id##_##client##_ORDER_ID)
+
+/*******************************************************************************
+ * Memory Controller's VC ID configuration registers
+ ******************************************************************************/
+#define VC_NISO 0U
+#define VC_SISO 1U
+#define VC_ISO 2U
+
+#define MC_HUB_PC_VC_ID_0 U(0x2a78)
+#define MC_HUB_PC_VC_ID_0_RESET_VAL 0x00020100U
+#define MC_HUB_PC_VC_ID_0_APB_VC_ID_MASK (0x3U << 8)
+#define MC_HUB_PC_VC_ID_0_APB_VC_ID (VC_NISO << 8)
+
+#define MC_HUB_PC_VC_ID_2 U(0x2a80)
+#define MC_HUB_PC_VC_ID_2_RESET_VAL 0x10001000U
+#define MC_HUB_PC_VC_ID_2_SD_VC_ID_MASK (0x3U << 28)
+#define MC_HUB_PC_VC_ID_2_SD_VC_ID (VC_NISO << 28)
+
+#define MC_HUB_PC_VC_ID_4 U(0x2a88)
+#define MC_HUB_PC_VC_ID_4_RESET_VAL 0x10020011U
+#define MC_HUB_PC_VC_ID_4_NIC_VC_ID_MASK (0x3U << 28)
+#define MC_HUB_PC_VC_ID_4_NIC_VC_ID (VC_NISO << 28)
+
+#define mc_hub_vc_id(id, client) \
+ (~MC_HUB_PC_VC_ID_##id##_##client##_VC_ID_MASK | \
+ MC_HUB_PC_VC_ID_##id##_##client##_VC_ID)
+
+/*******************************************************************************
+ * Memory Controller's PCFIFO client configuration registers
+ ******************************************************************************/
+#define MC_PCFIFO_CLIENT_CONFIG0 0xdd0U
+
+#define MC_PCFIFO_CLIENT_CONFIG1 0xdd4U
+#define MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL 0x20200000U
+#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_UNORDERED (0U << 17)
+#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_MASK (1U << 17)
+#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_UNORDERED (0U << 21)
+#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_MASK (1U << 21)
+#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_UNORDERED (0U << 29)
+#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_ORDERED (1U << 29)
+#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_MASK (1U << 29)
+
+#define MC_PCFIFO_CLIENT_CONFIG2 0xdd8U
+#define MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL 0x00002800U
+#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_UNORDERED (0U << 11)
+#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_MASK (1U << 11)
+#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_UNORDERED (0U << 13)
+#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_ORDERED (1U << 13)
+#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_MASK (1U << 13)
+#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_TSECSWR_UNORDERED (0U << 21)
+#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_TSECSWR_MASK (1U << 21)
+
+#define MC_PCFIFO_CLIENT_CONFIG3 0xddcU
+#define MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL 0x08000080U
+#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWA_UNORDERED (0U << 4)
+#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWA_MASK (1U << 4)
+#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCW_UNORDERED (0U << 6)
+#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCW_MASK (1U << 6)
+#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_UNORDERED (0U << 7)
+#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_MASK (1U << 7)
+#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_VICSWR_UNORDERED (0U << 13)
+#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_VICSWR_MASK (1U << 13)
+#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_APEW_UNORDERED (0U << 27)
+#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_APEW_MASK (1U << 27)
+
+#define MC_PCFIFO_CLIENT_CONFIG4 0xde0U
+#define MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL 0x5552a022U
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_UNORDERED (0U << 1)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_MASK (1U << 1)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_UNORDERED (0U << 5)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_MASK (1U << 5)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_TSECSWRB_UNORDERED (0U << 7)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_TSECSWRB_MASK (1U << 7)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_UNORDERED (0U << 13)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_MASK (1U << 13)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_ORDERED (1U << 15)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_MASK (1U << 15)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_UNORDERED (0U << 17)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_MASK (1U << 17)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPW_UNORDERED (0U << 20)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPW_MASK (1U << 20)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_UNORDERED (0U << 22)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_MASK (1U << 22)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONW_UNORDERED (0U << 24)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONW_MASK (1U << 24)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_UNORDERED (0U << 26)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_MASK (1U << 26)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEW_UNORDERED (0U << 28)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEW_MASK (1U << 28)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_UNORDERED (0U << 30)
+#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_MASK (1U << 30)
+
+#define MC_PCFIFO_CLIENT_CONFIG5 0xbf4U
+#define MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL 0x20000001U
+#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_UNORDERED (0U << 0)
+#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_MASK (1U << 0)
+#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_VIFALW_UNORDERED (0U << 30)
+#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_VIFALW_MASK (1U << 30)
+
+#define MC_PCFIFO_CLIENT_CONFIG6 0xb90U
+#define MC_PCFIFO_CLIENT_CONFIG6_RESET_VAL 0xaa280000U
+#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_RCEW_UNORDERED (0U << 19)
+#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_RCEW_MASK (1U << 19)
+#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_RCEDMAW_UNORDERED (0U << 21)
+#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_RCEDMAW_MASK (1U << 21)
+#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE0W_UNORDERED (0U << 25)
+#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE0W_MASK (1U << 25)
+#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE1W_ORDERED (1U << 27)
+#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE1W_MASK (1U << 27)
+#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE2W_ORDERED (1U << 29)
+#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE2W_MASK (1U << 29)
+#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE3W_ORDERED (1U << 31)
+#define MC_PCFIFO_CLIENT_CONFIG6_PCFIFO_PCIE3W_MASK (1U << 31)
+
+#define MC_PCFIFO_CLIENT_CONFIG7 0xaccU
+#define MC_PCFIFO_CLIENT_CONFIG7_RESET_VAL 0x0000000aU
+#define MC_PCFIFO_CLIENT_CONFIG7_PCFIFO_PCIE4W_UNORDERED (0U << 1)
+#define MC_PCFIFO_CLIENT_CONFIG7_PCFIFO_PCIE4W_MASK (1U << 1)
+#define MC_PCFIFO_CLIENT_CONFIG7_PCFIFO_PCIE5W_UNORDERED (0U << 3)
+#define MC_PCFIFO_CLIENT_CONFIG7_PCFIFO_PCIE5W_MASK (1U << 3)
+
+/*******************************************************************************
+ * StreamID to indicate no SMMU translations (requests to be steered on the
+ * SMMU bypass path)
+ ******************************************************************************/
+#define MC_STREAM_ID_MAX 0x7FU
+
+/*******************************************************************************
+ * Stream ID Override Config registers
+ ******************************************************************************/
+#define MC_STREAMID_OVERRIDE_CFG_PVA1RDA 0x660U
+#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD 0xe0U
+#define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR 0x3f8U
+#define MC_STREAMID_OVERRIDE_CFG_PVA0RDA1 0x758U
+#define MC_STREAMID_OVERRIDE_CFG_PVA0RDC 0x640U
+#define MC_STREAMID_OVERRIDE_CFG_DLA0RDA 0x5f0U
+#define MC_STREAMID_OVERRIDE_CFG_BPMPR 0x498U
+#define MC_STREAMID_OVERRIDE_CFG_APEDMAR 0x4f8U
+#define MC_STREAMID_OVERRIDE_CFG_AXISR 0x460U
+#define MC_STREAMID_OVERRIDE_CFG_TSECSRD 0x2a0U
+#define MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB 0x5f8U
+#define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1 0x788U
+#define MC_STREAMID_OVERRIDE_CFG_MPCOREW 0x1c8U
+#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD1 0x780U
+#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR 0x250U
+#define MC_STREAMID_OVERRIDE_CFG_MIU1R 0x540U
+#define MC_STREAMID_OVERRIDE_CFG_MIU0R 0x530U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE1W 0x6d8U
+#define MC_STREAMID_OVERRIDE_CFG_PVA1WRA 0x678U
+#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW 0x258U
+#define MC_STREAMID_OVERRIDE_CFG_AXIAPW 0x418U
+#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB 0x338U
+#define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1e8U
+#define MC_STREAMID_OVERRIDE_CFG_DLA0WRA 0x600U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE3R 0x6f0U
+#define MC_STREAMID_OVERRIDE_CFG_MIU3W 0x588U
+#define MC_STREAMID_OVERRIDE_CFG_SCEDMAR 0x4e8U
+#define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR 0xb0U
+#define MC_STREAMID_OVERRIDE_CFG_SDMMCWA 0x320U
+#define MC_STREAMID_OVERRIDE_CFG_MIU2R 0x570U
+#define MC_STREAMID_OVERRIDE_CFG_APEDMAW 0x500U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE2AW 0x6e8U
+#define MC_STREAMID_OVERRIDE_CFG_SESWR 0x408U
+#define MC_STREAMID_OVERRIDE_CFG_PVA1RDB1 0x770U
+#define MC_STREAMID_OVERRIDE_CFG_AXISW 0x468U
+#define MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB 0x618U
+#define MC_STREAMID_OVERRIDE_CFG_AONDMAW 0x4d0U
+#define MC_STREAMID_OVERRIDE_CFG_TSECSWRB 0x438U
+#define MC_STREAMID_OVERRIDE_CFG_ISPWB 0x238U
+#define MC_STREAMID_OVERRIDE_CFG_HDAR 0xa8U
+#define MC_STREAMID_OVERRIDE_CFG_SDMMCRA 0x300U
+#define MC_STREAMID_OVERRIDE_CFG_ETRW 0x428U
+#define MC_STREAMID_OVERRIDE_CFG_RCEDMAW 0x6a8U
+#define MC_STREAMID_OVERRIDE_CFG_TSECSWR 0x2a8U
+#define MC_STREAMID_OVERRIDE_CFG_ETRR 0x420U
+#define MC_STREAMID_OVERRIDE_CFG_SDMMCR 0x310U
+#define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD 0x3f0U
+#define MC_STREAMID_OVERRIDE_CFG_AONDMAR 0x4c8U
+#define MC_STREAMID_OVERRIDE_CFG_SCER 0x4d8U
+#define MC_STREAMID_OVERRIDE_CFG_MIU5W 0x7e8U
+#define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD 0x6b0U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE4R 0x700U
+#define MC_STREAMID_OVERRIDE_CFG_ISPWA 0x230U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE0W 0x6c8U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE5R1 0x778U
+#define MC_STREAMID_OVERRIDE_CFG_DLA1RDA 0x610U
+#define MC_STREAMID_OVERRIDE_CFG_VICSWR 0x368U
+#define MC_STREAMID_OVERRIDE_CFG_SESRD 0x400U
+#define MC_STREAMID_OVERRIDE_CFG_SDMMCW 0x330U
+#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB 0x318U
+#define MC_STREAMID_OVERRIDE_CFG_ISPFALW 0x720U
+#define MC_STREAMID_OVERRIDE_CFG_EQOSW 0x478U
+#define MC_STREAMID_OVERRIDE_CFG_RCEDMAR 0x6a0U
+#define MC_STREAMID_OVERRIDE_CFG_RCER 0x690U
+#define MC_STREAMID_OVERRIDE_CFG_NVDECSWR 0x3c8U
+#define MC_STREAMID_OVERRIDE_CFG_UFSHCR 0x480U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE4W 0x708U
+#define MC_STREAMID_OVERRIDE_CFG_VICSRD 0x360U
+#define MC_STREAMID_OVERRIDE_CFG_APER 0x3d0U
+#define MC_STREAMID_OVERRIDE_CFG_MIU7R 0x8U
+#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD 0x7c8U
+#define MC_STREAMID_OVERRIDE_CFG_MIU7W 0x10U
+#define MC_STREAMID_OVERRIDE_CFG_PVA1RDA1 0x768U
+#define MC_STREAMID_OVERRIDE_CFG_PVA1WRC 0x688U
+#define MC_STREAMID_OVERRIDE_CFG_AONW 0x4c0U
+#define MC_STREAMID_OVERRIDE_CFG_MIU4W 0x598U
+#define MC_STREAMID_OVERRIDE_CFG_HDAW 0x1a8U
+#define MC_STREAMID_OVERRIDE_CFG_BPMPW 0x4a0U
+#define MC_STREAMID_OVERRIDE_CFG_DLA1WRA 0x620U
+#define MC_STREAMID_OVERRIDE_CFG_DLA0RDA1 0x748U
+#define MC_STREAMID_OVERRIDE_CFG_MIU1W 0x548U
+#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1 0x508U
+#define MC_STREAMID_OVERRIDE_CFG_VICSRD1 0x510U
+#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW 0x4b0U
+#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SWR 0x7d8U
+#define MC_STREAMID_OVERRIDE_CFG_PVA0WRC 0x658U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE5R 0x710U
+#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR 0x260U
+#define MC_STREAMID_OVERRIDE_CFG_UFSHCW 0x488U
+#define MC_STREAMID_OVERRIDE_CFG_PVA1WRB 0x680U
+#define MC_STREAMID_OVERRIDE_CFG_PVA0WRB 0x650U
+#define MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB 0x628U
+#define MC_STREAMID_OVERRIDE_CFG_NVENC1SWR 0x6b8U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE0R 0x6c0U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE3W 0x6f8U
+#define MC_STREAMID_OVERRIDE_CFG_PVA0RDA 0x630U
+#define MC_STREAMID_OVERRIDE_CFG_MIU6W 0x7f8U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE1R 0x6d0U
+#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD1 0x7d0U
+#define MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB 0x608U
+#define MC_STREAMID_OVERRIDE_CFG_PVA1RDC 0x670U
+#define MC_STREAMID_OVERRIDE_CFG_MIU0W 0x538U
+#define MC_STREAMID_OVERRIDE_CFG_MIU2W 0x578U
+#define MC_STREAMID_OVERRIDE_CFG_MPCORER 0x138U
+#define MC_STREAMID_OVERRIDE_CFG_AXIAPR 0x410U
+#define MC_STREAMID_OVERRIDE_CFG_AONR 0x4b8U
+#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR 0x4a8U
+#define MC_STREAMID_OVERRIDE_CFG_PVA0RDB 0x638U
+#define MC_STREAMID_OVERRIDE_CFG_VIFALW 0x5e8U
+#define MC_STREAMID_OVERRIDE_CFG_MIU6R 0x7f0U
+#define MC_STREAMID_OVERRIDE_CFG_EQOSR 0x470U
+#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD 0x3c0U
+#define MC_STREAMID_OVERRIDE_CFG_TSECSRDB 0x430U
+#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 0x518U
+#define MC_STREAMID_OVERRIDE_CFG_PVA0RDB1 0x760U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE0R1 0x798U
+#define MC_STREAMID_OVERRIDE_CFG_SCEDMAW 0x4f0U
+#define MC_STREAMID_OVERRIDE_CFG_APEW 0x3d8U
+#define MC_STREAMID_OVERRIDE_CFG_MIU5R 0x7e0U
+#define MC_STREAMID_OVERRIDE_CFG_DLA1RDA1 0x750U
+#define MC_STREAMID_OVERRIDE_CFG_PVA0WRA 0x648U
+#define MC_STREAMID_OVERRIDE_CFG_ISPFALR 0x228U
+#define MC_STREAMID_OVERRIDE_CFG_PTCR 0x0U
+#define MC_STREAMID_OVERRIDE_CFG_MIU4R 0x590U
+#define MC_STREAMID_OVERRIDE_CFG_ISPRA 0x220U
+#define MC_STREAMID_OVERRIDE_CFG_VIFALR 0x5e0U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE2AR 0x6e0U
+#define MC_STREAMID_OVERRIDE_CFG_RCEW 0x698U
+#define MC_STREAMID_OVERRIDE_CFG_ISPRA1 0x790U
+#define MC_STREAMID_OVERRIDE_CFG_SCEW 0x4e0U
+#define MC_STREAMID_OVERRIDE_CFG_MIU3R 0x580U
+#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW 0x268U
+#define MC_STREAMID_OVERRIDE_CFG_SATAR 0xf8U
+#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR 0x490U
+#define MC_STREAMID_OVERRIDE_CFG_PVA1RDB 0x668U
+#define MC_STREAMID_OVERRIDE_CFG_VIW 0x390U
+#define MC_STREAMID_OVERRIDE_CFG_NVENCSWR 0x158U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE5W 0x718U
+
+/*******************************************************************************
+ * Macro to calculate Security cfg register addr from StreamID Override register
+ ******************************************************************************/
+#define MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(addr) ((addr) + (uint32_t)sizeof(uint32_t))
+
+#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_SO_DEV (0U << 4)
+#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_SO_DEV (1U << 4)
+#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SO_DEV (2U << 4)
+#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_SO_DEV (3U << 4)
+
+#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_NORMAL (0U << 8)
+#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_NORMAL (1U << 8)
+#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_NORMAL (2U << 8)
+#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_NORMAL (3U << 8)
+
+#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_ZERO (0U << 12)
+#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_CLIENT_AXI_ID (1U << 12)
+
+/*******************************************************************************
+ * Memory Controller transaction override config registers
+ ******************************************************************************/
+#define MC_TXN_OVERRIDE_CONFIG_HDAR 0x10a8U
+#define MC_TXN_OVERRIDE_CONFIG_DLA1WRA 0x1624U
+#define MC_TXN_OVERRIDE_CONFIG_PCIE1W 0x16dcU
+#define MC_TXN_OVERRIDE_CONFIG_PVA0RDC 0x1644U
+#define MC_TXN_OVERRIDE_CONFIG_PTCR 0x1000U
+#define MC_TXN_OVERRIDE_CONFIG_EQOSW 0x1478U
+#define MC_TXN_OVERRIDE_CONFIG_MPCOREW 0x11c8U
+#define MC_TXN_OVERRIDE_CONFIG_DLA1FALWRB 0x162cU
+#define MC_TXN_OVERRIDE_CONFIG_AXISR 0x1460U
+#define MC_TXN_OVERRIDE_CONFIG_PVA0WRB 0x1654U
+#define MC_TXN_OVERRIDE_CONFIG_MIU6R 0x17f4U
+#define MC_TXN_OVERRIDE_CONFIG_MIU5R 0x17e4U
+#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD1 0x1784U
+#define MC_TXN_OVERRIDE_CONFIG_PCIE0R 0x16c4U
+#define MC_TXN_OVERRIDE_CONFIG_EQOSR 0x1470U
+#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD 0x10e0U
+#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD1 0x178cU
+#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB1 0x1774U
+#define MC_TXN_OVERRIDE_CONFIG_NVENC1SWR 0x16bcU
+#define MC_TXN_OVERRIDE_CONFIG_VICSRD1 0x1510U
+#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR 0x14a8U
+#define MC_TXN_OVERRIDE_CONFIG_VIW 0x1390U
+#define MC_TXN_OVERRIDE_CONFIG_PCIE5R 0x1714U
+#define MC_TXN_OVERRIDE_CONFIG_AXISW 0x1468U
+#define MC_TXN_OVERRIDE_CONFIG_MIU6W 0x17fcU
+#define MC_TXN_OVERRIDE_CONFIG_UFSHCR 0x1480U
+#define MC_TXN_OVERRIDE_CONFIG_PCIE0R1 0x179cU
+#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB1 0x1764U
+#define MC_TXN_OVERRIDE_CONFIG_TSECSWR 0x12a8U
+#define MC_TXN_OVERRIDE_CONFIG_MIU7R 0x1008U
+#define MC_TXN_OVERRIDE_CONFIG_SATAR 0x10f8U
+#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW 0x1258U
+#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA 0x15f4U
+#define MC_TXN_OVERRIDE_CONFIG_TSECSWRB 0x1438U
+#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SWR 0x17dcU
+#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA1 0x176cU
+#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB 0x166cU
+#define MC_TXN_OVERRIDE_CONFIG_AONDMAW 0x14d0U
+#define MC_TXN_OVERRIDE_CONFIG_AONW 0x14c0U
+#define MC_TXN_OVERRIDE_CONFIG_ETRR 0x1420U
+#define MC_TXN_OVERRIDE_CONFIG_PCIE2AW 0x16ecU
+#define MC_TXN_OVERRIDE_CONFIG_PCIE1R 0x16d4U
+#define MC_TXN_OVERRIDE_CONFIG_PVA1RDC 0x1674U
+#define MC_TXN_OVERRIDE_CONFIG_PVA0WRA 0x164cU
+#define MC_TXN_OVERRIDE_CONFIG_TSECSRDB 0x1430U
+#define MC_TXN_OVERRIDE_CONFIG_MIU1W 0x1548U
+#define MC_TXN_OVERRIDE_CONFIG_PCIE0W 0x16ccU
+#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD 0x17ccU
+#define MC_TXN_OVERRIDE_CONFIG_MIU7W 0x1010U
+#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1 0x1518U
+#define MC_TXN_OVERRIDE_CONFIG_MIU3R 0x1580U
+#define MC_TXN_OVERRIDE_CONFIG_MIU3W 0x158cU
+#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR 0x1250U
+#define MC_TXN_OVERRIDE_CONFIG_SESRD 0x1400U
+#define MC_TXN_OVERRIDE_CONFIG_SCER 0x14d8U
+#define MC_TXN_OVERRIDE_CONFIG_MPCORER 0x1138U
+#define MC_TXN_OVERRIDE_CONFIG_SDMMCWA 0x1320U
+#define MC_TXN_OVERRIDE_CONFIG_HDAW 0x11a8U
+#define MC_TXN_OVERRIDE_CONFIG_NVDECSWR 0x13c8U
+#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA 0x1634U
+#define MC_TXN_OVERRIDE_CONFIG_AONDMAR 0x14c8U
+#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB 0x1338U
+#define MC_TXN_OVERRIDE_CONFIG_ISPFALR 0x1228U
+#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA1 0x175cU
+#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD 0x16b4U
+#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1 0x1508U
+#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA 0x1664U
+#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA1 0x174cU
+#define MC_TXN_OVERRIDE_CONFIG_ISPWB 0x1238U
+#define MC_TXN_OVERRIDE_CONFIG_APEW 0x13d8U
+#define MC_TXN_OVERRIDE_CONFIG_AXIAPR 0x1410U
+#define MC_TXN_OVERRIDE_CONFIG_PCIE2AR 0x16e4U
+#define MC_TXN_OVERRIDE_CONFIG_ISPFALW 0x1724U
+#define MC_TXN_OVERRIDE_CONFIG_SDMMCR 0x1310U
+#define MC_TXN_OVERRIDE_CONFIG_MIU2W 0x1578U
+#define MC_TXN_OVERRIDE_CONFIG_RCER 0x1694U
+#define MC_TXN_OVERRIDE_CONFIG_PCIE4W 0x170cU
+#define MC_TXN_OVERRIDE_CONFIG_BPMPW 0x14a0U
+#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR 0x1490U
+#define MC_TXN_OVERRIDE_CONFIG_ISPRA 0x1220U
+#define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR 0x13f8U
+#define MC_TXN_OVERRIDE_CONFIG_VICSRD 0x1360U
+#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD1 0x17d4U
+#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA 0x1614U
+#define MC_TXN_OVERRIDE_CONFIG_SCEDMAW 0x14f0U
+#define MC_TXN_OVERRIDE_CONFIG_SDMMCW 0x1330U
+#define MC_TXN_OVERRIDE_CONFIG_DLA1FALRDB 0x161cU
+#define MC_TXN_OVERRIDE_CONFIG_APEDMAR 0x14f8U
+#define MC_TXN_OVERRIDE_CONFIG_RCEW 0x169cU
+#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB 0x1318U
+#define MC_TXN_OVERRIDE_CONFIG_DLA0WRA 0x1604U
+#define MC_TXN_OVERRIDE_CONFIG_VIFALR 0x15e4U
+#define MC_TXN_OVERRIDE_CONFIG_PCIE3R 0x16f4U
+#define MC_TXN_OVERRIDE_CONFIG_MIU1R 0x1540U
+#define MC_TXN_OVERRIDE_CONFIG_PCIE5W 0x171cU
+#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR 0x1260U
+#define MC_TXN_OVERRIDE_CONFIG_MIU0W 0x1538U
+#define MC_TXN_OVERRIDE_CONFIG_DLA0FALWRB 0x160cU
+#define MC_TXN_OVERRIDE_CONFIG_VIFALW 0x15ecU
+#define MC_TXN_OVERRIDE_CONFIG_DLA0FALRDB 0x15fcU
+#define MC_TXN_OVERRIDE_CONFIG_PCIE3W 0x16fcU
+#define MC_TXN_OVERRIDE_CONFIG_MIU0R 0x1530U
+#define MC_TXN_OVERRIDE_CONFIG_PVA0WRC 0x165cU
+#define MC_TXN_OVERRIDE_CONFIG_SCEDMAR 0x14e8U
+#define MC_TXN_OVERRIDE_CONFIG_APEDMAW 0x1500U
+#define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR 0x10b0U
+#define MC_TXN_OVERRIDE_CONFIG_SESWR 0x1408U
+#define MC_TXN_OVERRIDE_CONFIG_AXIAPW 0x1418U
+#define MC_TXN_OVERRIDE_CONFIG_MIU4R 0x1594U
+#define MC_TXN_OVERRIDE_CONFIG_MIU4W 0x159cU
+#define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD 0x13f0U
+#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD 0x13c0U
+#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW 0x14b0U
+#define MC_TXN_OVERRIDE_CONFIG_APER 0x13d0U
+#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA1 0x1754U
+#define MC_TXN_OVERRIDE_CONFIG_PVA1WRB 0x1684U
+#define MC_TXN_OVERRIDE_CONFIG_ISPWA 0x1230U
+#define MC_TXN_OVERRIDE_CONFIG_PVA1WRC 0x168cU
+#define MC_TXN_OVERRIDE_CONFIG_RCEDMAR 0x16a4U
+#define MC_TXN_OVERRIDE_CONFIG_ISPRA1 0x1794U
+#define MC_TXN_OVERRIDE_CONFIG_AONR 0x14b8U
+#define MC_TXN_OVERRIDE_CONFIG_RCEDMAW 0x16acU
+#define MC_TXN_OVERRIDE_CONFIG_UFSHCW 0x1488U
+#define MC_TXN_OVERRIDE_CONFIG_ETRW 0x1428U
+#define MC_TXN_OVERRIDE_CONFIG_SATAW 0x11e8U
+#define MC_TXN_OVERRIDE_CONFIG_VICSWR 0x1368U
+#define MC_TXN_OVERRIDE_CONFIG_NVENCSWR 0x1158U
+#define MC_TXN_OVERRIDE_CONFIG_PCIE5R1 0x177cU
+#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB 0x163cU
+#define MC_TXN_OVERRIDE_CONFIG_SDMMCRA 0x1300U
+#define MC_TXN_OVERRIDE_CONFIG_PVA1WRA 0x167cU
+#define MC_TXN_OVERRIDE_CONFIG_MIU5W 0x17ecU
+#define MC_TXN_OVERRIDE_CONFIG_BPMPR 0x1498U
+#define MC_TXN_OVERRIDE_CONFIG_MIU2R 0x1570U
+#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW 0x1268U
+#define MC_TXN_OVERRIDE_CONFIG_TSECSRD 0x12a0U
+#define MC_TXN_OVERRIDE_CONFIG_PCIE4R 0x1704U
+#define MC_TXN_OVERRIDE_CONFIG_SCEW 0x14e0U
+
+#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID (1U << 0)
+#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV (2U << 4)
+#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT (1U << 12)
+
+/*******************************************************************************
+ * Non-SO_DEV transactions override values for CGID_TAG bitfield for the
+ * MC_TXN_OVERRIDE_CONFIG_{module} registers
+ ******************************************************************************/
+#define MC_TXN_OVERRIDE_CGID_TAG_DEFAULT 0U
+#define MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID 1U
+#define MC_TXN_OVERRIDE_CGID_TAG_ZERO 2U
+#define MC_TXN_OVERRIDE_CGID_TAG_ADR 3U
+#define MC_TXN_OVERRIDE_CGID_TAG_MASK 3ULL
+
+/*******************************************************************************
+ * Memory Controller Reset Control registers
+ ******************************************************************************/
+#define MC_CLIENT_HOTRESET_CTRL0 0x200U
+#define MC_CLIENT_HOTRESET_CTRL0_RESET_VAL 0U
+#define MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB (1U << 0)
+#define MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB (1U << 6)
+#define MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB (1U << 7)
+#define MC_CLIENT_HOTRESET_CTRL0_ISP2_FLUSH_ENB (1U << 8)
+#define MC_CLIENT_HOTRESET_CTRL0_MPCORE_FLUSH_ENB (1U << 9)
+#define MC_CLIENT_HOTRESET_CTRL0_NVENC_FLUSH_ENB (1U << 11)
+#define MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB (1U << 15)
+#define MC_CLIENT_HOTRESET_CTRL0_VI_FLUSH_ENB (1U << 17)
+#define MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB (1U << 18)
+#define MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB (1U << 19)
+#define MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB (1U << 20)
+#define MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB (1U << 22)
+#define MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB (1U << 29)
+#define MC_CLIENT_HOTRESET_CTRL0_SDMMC2A_FLUSH_ENB (1U << 30)
+#define MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB (1U << 31)
+#define MC_CLIENT_HOTRESET_STATUS0 0x204U
+#define MC_CLIENT_HOTRESET_CTRL1 0x970U
+#define MC_CLIENT_HOTRESET_CTRL1_RESET_VAL 0U
+#define MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB (1U << 0)
+#define MC_CLIENT_HOTRESET_CTRL1_GPU_FLUSH_ENB (1U << 2)
+#define MC_CLIENT_HOTRESET_CTRL1_NVDEC_FLUSH_ENB (1U << 5)
+#define MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB (1U << 6)
+#define MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB (1U << 7)
+#define MC_CLIENT_HOTRESET_CTRL1_NVJPG_FLUSH_ENB (1U << 8)
+#define MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB (1U << 12)
+#define MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB (1U << 13)
+#define MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB (1U << 17)
+#define MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB (1U << 18)
+#define MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB (1U << 19)
+#define MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB (1U << 20)
+#define MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB (1U << 21)
+#define MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB (1U << 22)
+#define MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB (1U << 23)
+#define MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB (1U << 26)
+#define MC_CLIENT_HOTRESET_CTRL1_RCE_FLUSH_ENB (1U << 31)
+#define MC_CLIENT_HOTRESET_STATUS1 0x974U
+#define MC_CLIENT_HOTRESET_CTRL2 0x97cU
+#define MC_CLIENT_HOTRESET_CTRL2_RESET_VAL 0U
+#define MC_CLIENT_HOTRESET_CTRL2_RCEDMA_FLUSH_ENB (1U << 0)
+#define MC_CLIENT_HOTRESET_CTRL2_PCIE_FLUSH_ENB (1U << 2)
+#define MC_CLIENT_HOTRESET_CTRL2_PCIE5A_FLUSH_ENB (1U << 4)
+#define MC_CLIENT_HOTRESET_CTRL2_AONDMA_FLUSH_ENB (1U << 9)
+#define MC_CLIENT_HOTRESET_CTRL2_BPMPDMA_FLUSH_ENB (1U << 10)
+#define MC_CLIENT_HOTRESET_CTRL2_SCEDMA_FLUSH_ENB (1U << 11)
+#define MC_CLIENT_HOTRESET_CTRL2_APEDMA_FLUSH_ENB (1U << 14)
+#define MC_CLIENT_HOTRESET_CTRL2_PCIE3A_FLUSH_ENB (1U << 16)
+#define MC_CLIENT_HOTRESET_CTRL2_PCIE3_FLUSH_ENB (1U << 17)
+#define MC_CLIENT_HOTRESET_CTRL2_PCIE0A_FLUSH_ENB (1U << 22)
+#define MC_CLIENT_HOTRESET_CTRL2_PCIE0A2_FLUSH_ENB (1U << 23)
+#define MC_CLIENT_HOTRESET_CTRL2_PCIE4A_FLUSH_ENB (1U << 25)
+#define MC_CLIENT_HOTRESET_STATUS2 0x1898U
+
+/*******************************************************************************
+ * Tegra TSA Controller constants
+ ******************************************************************************/
+#define TEGRA_TSA_BASE U(0x02000000)
+
+#define TSA_CONFIG_STATIC0_CSR_RESET_R 0x20000000U
+#define TSA_CONFIG_STATIC0_CSW_RESET_W 0x20001000U
+#define TSA_CONFIG_STATIC0_CSW_RESET_SO_DEV 0x20001000U
+
+#define TSA_CONFIG_STATIC0_CSW_PCIE1W 0x1004U
+#define TSA_CONFIG_STATIC0_CSW_PCIE2AW 0x1008U
+#define TSA_CONFIG_STATIC0_CSW_PCIE3W 0x100cU
+#define TSA_CONFIG_STATIC0_CSW_PCIE4W 0x1028U
+#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x2004U
+#define TSA_CONFIG_STATIC0_CSR_SATAR 0x2010U
+#define TSA_CONFIG_STATIC0_CSW_SATAW 0x2014U
+#define TSA_CONFIG_STATIC0_CSW_PCIE0W 0x2020U
+#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x202cU
+#define TSA_CONFIG_STATIC0_CSW_NVENC1SWR 0x3004U
+#define TSA_CONFIG_STATIC0_CSW_NVENCSWR 0x3010U
+#define TSA_CONFIG_STATIC0_CSW_NVDEC1SWR 0x4004U
+#define TSA_CONFIG_STATIC0_CSR_ISPFALR 0x4010U
+#define TSA_CONFIG_STATIC0_CSW_ISPWA 0x4014U
+#define TSA_CONFIG_STATIC0_CSW_ISPWB 0x4018U
+#define TSA_CONFIG_STATIC0_CSW_ISPFALW 0x401cU
+#define TSA_CONFIG_STATIC0_CSW_NVDECSWR 0x5004U
+#define TSA_CONFIG_STATIC0_CSR_EQOSR 0x5010U
+#define TSA_CONFIG_STATIC0_CSW_EQOSW 0x5014U
+#define TSA_CONFIG_STATIC0_CSR_SDMMCRAB 0x5020U
+#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x5024U
+#define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x6004U
+#define TSA_CONFIG_STATIC0_CSR_SDMMCR 0x6010U
+#define TSA_CONFIG_STATIC0_CSR_SDMMCRA 0x6014U
+#define TSA_CONFIG_STATIC0_CSW_SDMMCW 0x6018U
+#define TSA_CONFIG_STATIC0_CSW_SDMMCWA 0x601cU
+#define TSA_CONFIG_STATIC0_CSR_RCER 0x6030U
+#define TSA_CONFIG_STATIC0_CSR_RCEDMAR 0x6034U
+#define TSA_CONFIG_STATIC0_CSW_RCEW 0x6038U
+#define TSA_CONFIG_STATIC0_CSW_RCEDMAW 0x603cU
+#define TSA_CONFIG_STATIC0_CSR_SCER 0x6050U
+#define TSA_CONFIG_STATIC0_CSR_SCEDMAR 0x6054U
+#define TSA_CONFIG_STATIC0_CSW_SCEW 0x6058U
+#define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0x605cU
+#define TSA_CONFIG_STATIC0_CSR_AXIAPR 0x7004U
+#define TSA_CONFIG_STATIC0_CSR_ETRR 0x7008U
+#define TSA_CONFIG_STATIC0_CSR_HOST1XDMAR 0x700cU
+#define TSA_CONFIG_STATIC0_CSW_AXIAPW 0x7010U
+#define TSA_CONFIG_STATIC0_CSW_ETRW 0x7014U
+#define TSA_CONFIG_STATIC0_CSR_NVJPGSRD 0x8004U
+#define TSA_CONFIG_STATIC0_CSW_NVJPGSWR 0x8008U
+#define TSA_CONFIG_STATIC0_CSR_AXISR 0x8014U
+#define TSA_CONFIG_STATIC0_CSW_AXISW 0x8018U
+#define TSA_CONFIG_STATIC0_CSR_BPMPR 0x9004U
+#define TSA_CONFIG_STATIC0_CSR_BPMPDMAR 0x9008U
+#define TSA_CONFIG_STATIC0_CSW_BPMPW 0x900cU
+#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0x9010U
+#define TSA_CONFIG_STATIC0_CSR_SESRD 0x9024U
+#define TSA_CONFIG_STATIC0_CSR_TSECSRD 0x9028U
+#define TSA_CONFIG_STATIC0_CSR_TSECSRDB 0x902cU
+#define TSA_CONFIG_STATIC0_CSW_SESWR 0x9030U
+#define TSA_CONFIG_STATIC0_CSW_TSECSWR 0x9034U
+#define TSA_CONFIG_STATIC0_CSW_TSECSWRB 0x9038U
+#define TSA_CONFIG_STATIC0_CSW_PCIE5W 0xb004U
+#define TSA_CONFIG_STATIC0_CSW_VICSWR 0xc004U
+#define TSA_CONFIG_STATIC0_CSR_APER 0xd004U
+#define TSA_CONFIG_STATIC0_CSR_APEDMAR 0xd008U
+#define TSA_CONFIG_STATIC0_CSW_APEW 0xd00cU
+#define TSA_CONFIG_STATIC0_CSW_APEDMAW 0xd010U
+#define TSA_CONFIG_STATIC0_CSR_HDAR 0xf004U
+#define TSA_CONFIG_STATIC0_CSW_HDAW 0xf008U
+#define TSA_CONFIG_STATIC0_CSR_NVDISPLAYR 0xf014U
+#define TSA_CONFIG_STATIC0_CSR_VIFALR 0x10004U
+#define TSA_CONFIG_STATIC0_CSW_VIW 0x10008U
+#define TSA_CONFIG_STATIC0_CSW_VIFALW 0x1000cU
+#define TSA_CONFIG_STATIC0_CSR_AONR 0x12004U
+#define TSA_CONFIG_STATIC0_CSR_AONDMAR 0x12008U
+#define TSA_CONFIG_STATIC0_CSW_AONW 0x1200cU
+#define TSA_CONFIG_STATIC0_CSW_AONDMAW 0x12010U
+#define TSA_CONFIG_STATIC0_CSR_PCIE1R 0x14004U
+#define TSA_CONFIG_STATIC0_CSR_PCIE2AR 0x14008U
+#define TSA_CONFIG_STATIC0_CSR_PCIE3R 0x1400cU
+#define TSA_CONFIG_STATIC0_CSR_PCIE4R 0x14028U
+#define TSA_CONFIG_STATIC0_CSR_XUSB_DEVR 0x15004U
+#define TSA_CONFIG_STATIC0_CSR_XUSB_HOSTR 0x15010U
+#define TSA_CONFIG_STATIC0_CSR_UFSHCR 0x16004U
+#define TSA_CONFIG_STATIC0_CSW_DLA1WRA 0x18004U
+#define TSA_CONFIG_STATIC0_CSR_DLA1FALRDB 0x18010U
+#define TSA_CONFIG_STATIC0_CSW_DLA1FALWRB 0x18014U
+#define TSA_CONFIG_STATIC0_CSW_DLA0WRA 0x19004U
+#define TSA_CONFIG_STATIC0_CSR_DLA0FALRDB 0x19010U
+#define TSA_CONFIG_STATIC0_CSW_DLA0FALWRB 0x19014U
+#define TSA_CONFIG_STATIC0_CSR_PVA1RDC 0x1a004U
+#define TSA_CONFIG_STATIC0_CSW_PVA1WRC 0x1a008U
+#define TSA_CONFIG_STATIC0_CSW_PVA1WRA 0x1a014U
+#define TSA_CONFIG_STATIC0_CSW_PVA1WRB 0x1a020U
+#define TSA_CONFIG_STATIC0_CSW_PVA0WRB 0x1b004U
+#define TSA_CONFIG_STATIC0_CSR_PVA0RDC 0x1b010U
+#define TSA_CONFIG_STATIC0_CSW_PVA0WRC 0x1b014U
+#define TSA_CONFIG_STATIC0_CSW_PVA0WRA 0x1b020U
+#define TSA_CONFIG_STATIC0_CSR_NVENC1SRD 0x1d004U
+#define TSA_CONFIG_STATIC0_CSR_NVENCSRD 0x1d010U
+#define TSA_CONFIG_STATIC0_CSR_NVDEC1SRD 0x1e004U
+#define TSA_CONFIG_STATIC0_CSR_ISPRA 0x1e010U
+#define TSA_CONFIG_STATIC0_CSR_NVDECSRD 0x1f004U
+#define TSA_CONFIG_STATIC0_CSR_PCIE0R 0x21004U
+#define TSA_CONFIG_STATIC0_CSR_PCIE5R 0x23004U
+#define TSA_CONFIG_STATIC0_CSR_VICSRD 0x24004U
+#define TSA_CONFIG_STATIC0_CSR_DLA1RDA 0x26004U
+#define TSA_CONFIG_STATIC0_CSR_DLA0RDA 0x27004U
+#define TSA_CONFIG_STATIC0_CSR_PVA1RDA 0x28004U
+#define TSA_CONFIG_STATIC0_CSR_PVA1RDB 0x28010U
+#define TSA_CONFIG_STATIC0_CSR_PVA0RDB 0x29004U
+#define TSA_CONFIG_STATIC0_CSR_PVA0RDA 0x29010U
+
+#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (ULL(0x3) << 11)
+#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (ULL(0) << 11)
+
+#endif /* __TEGRA_MC_DEF_H__ */
diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
index 948fade..1188a3b 100644
--- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
@@ -66,10 +66,10 @@
<< TEGRA194_WAKE_TIME_SHIFT;
/*
- * Clean percpu_data[cpu] to DRAM. This needs to be done to ensure that
- * the correct value is read in tegra_soc_pwr_domain_suspend(), which
- * is called with caches disabled. It is possible to read a stale value
- * from DRAM in that function, because the L2 cache is not flushed
+ * Clean t19x_percpu_data[cpu] to DRAM. This needs to be done to ensure
+ * that the correct value is read in tegra_soc_pwr_domain_suspend(),
+ * which is called with caches disabled. It is possible to read a stale
+ * value from DRAM in that function, because the L2 cache is not flushed
* unless the cluster is entering CC6/CC7.
*/
clean_dcache_range((uint64_t)&t19x_percpu_data[cpu],
@@ -125,7 +125,7 @@
val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ?
(uint32_t)TEGRA_NVG_CORE_C6 : (uint32_t)TEGRA_NVG_CORE_C7;
ret = mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, (uint64_t)val,
- percpu_data[cpu].wake_time, 0);
+ t19x_percpu_data[cpu].wake_time, 0);
assert(ret == 0);
} else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
diff --git a/plat/nvidia/tegra/soc/t194/plat_smmu.c b/plat/nvidia/tegra/soc/t194/plat_smmu.c
index 1696d59..640ef4d 100644
--- a/plat/nvidia/tegra/soc/t194/plat_smmu.c
+++ b/plat/nvidia/tegra/soc/t194/plat_smmu.c
@@ -270,143 +270,8 @@
mc_make_sid_override_cfg(MIU2W),
mc_make_sid_override_cfg(MIU3R),
mc_make_sid_override_cfg(MIU3W),
- smmu_make_gnsr0_nsec_cfg(CR0),
- smmu_make_gnsr0_sec_cfg(IDR0),
- smmu_make_gnsr0_sec_cfg(IDR1),
- smmu_make_gnsr0_sec_cfg(IDR2),
- smmu_make_gnsr0_nsec_cfg(GFSR),
- smmu_make_gnsr0_nsec_cfg(GFSYNR0),
- smmu_make_gnsr0_nsec_cfg(GFSYNR1),
- smmu_make_gnsr0_nsec_cfg(TLBGSTATUS),
- smmu_make_gnsr0_nsec_cfg(PIDR2),
- smmu_make_smrg_group(0),
- smmu_make_smrg_group(1),
- smmu_make_smrg_group(2),
- smmu_make_smrg_group(3),
- smmu_make_smrg_group(4),
- smmu_make_smrg_group(5),
- smmu_make_smrg_group(6),
- smmu_make_smrg_group(7),
- smmu_make_smrg_group(8),
- smmu_make_smrg_group(9),
- smmu_make_smrg_group(10),
- smmu_make_smrg_group(11),
- smmu_make_smrg_group(12),
- smmu_make_smrg_group(13),
- smmu_make_smrg_group(14),
- smmu_make_smrg_group(15),
- smmu_make_smrg_group(16),
- smmu_make_smrg_group(17),
- smmu_make_smrg_group(18),
- smmu_make_smrg_group(19),
- smmu_make_smrg_group(20),
- smmu_make_smrg_group(21),
- smmu_make_smrg_group(22),
- smmu_make_smrg_group(23),
- smmu_make_smrg_group(24),
- smmu_make_smrg_group(25),
- smmu_make_smrg_group(26),
- smmu_make_smrg_group(27),
- smmu_make_smrg_group(28),
- smmu_make_smrg_group(29),
- smmu_make_smrg_group(30),
- smmu_make_smrg_group(31),
- smmu_make_smrg_group(32),
- smmu_make_smrg_group(33),
- smmu_make_smrg_group(34),
- smmu_make_smrg_group(35),
- smmu_make_smrg_group(36),
- smmu_make_smrg_group(37),
- smmu_make_smrg_group(38),
- smmu_make_smrg_group(39),
- smmu_make_smrg_group(40),
- smmu_make_smrg_group(41),
- smmu_make_smrg_group(42),
- smmu_make_smrg_group(43),
- smmu_make_smrg_group(44),
- smmu_make_smrg_group(45),
- smmu_make_smrg_group(46),
- smmu_make_smrg_group(47),
- smmu_make_smrg_group(48),
- smmu_make_smrg_group(49),
- smmu_make_smrg_group(50),
- smmu_make_smrg_group(51),
- smmu_make_smrg_group(52),
- smmu_make_smrg_group(53),
- smmu_make_smrg_group(54),
- smmu_make_smrg_group(55),
- smmu_make_smrg_group(56),
- smmu_make_smrg_group(57),
- smmu_make_smrg_group(58),
- smmu_make_smrg_group(59),
- smmu_make_smrg_group(60),
- smmu_make_smrg_group(61),
- smmu_make_smrg_group(62),
- smmu_make_smrg_group(63),
- smmu_make_cb_group(0),
- smmu_make_cb_group(1),
- smmu_make_cb_group(2),
- smmu_make_cb_group(3),
- smmu_make_cb_group(4),
- smmu_make_cb_group(5),
- smmu_make_cb_group(6),
- smmu_make_cb_group(7),
- smmu_make_cb_group(8),
- smmu_make_cb_group(9),
- smmu_make_cb_group(10),
- smmu_make_cb_group(11),
- smmu_make_cb_group(12),
- smmu_make_cb_group(13),
- smmu_make_cb_group(14),
- smmu_make_cb_group(15),
- smmu_make_cb_group(16),
- smmu_make_cb_group(17),
- smmu_make_cb_group(18),
- smmu_make_cb_group(19),
- smmu_make_cb_group(20),
- smmu_make_cb_group(21),
- smmu_make_cb_group(22),
- smmu_make_cb_group(23),
- smmu_make_cb_group(24),
- smmu_make_cb_group(25),
- smmu_make_cb_group(26),
- smmu_make_cb_group(27),
- smmu_make_cb_group(28),
- smmu_make_cb_group(29),
- smmu_make_cb_group(30),
- smmu_make_cb_group(31),
- smmu_make_cb_group(32),
- smmu_make_cb_group(33),
- smmu_make_cb_group(34),
- smmu_make_cb_group(35),
- smmu_make_cb_group(36),
- smmu_make_cb_group(37),
- smmu_make_cb_group(38),
- smmu_make_cb_group(39),
- smmu_make_cb_group(40),
- smmu_make_cb_group(41),
- smmu_make_cb_group(42),
- smmu_make_cb_group(43),
- smmu_make_cb_group(44),
- smmu_make_cb_group(45),
- smmu_make_cb_group(46),
- smmu_make_cb_group(47),
- smmu_make_cb_group(48),
- smmu_make_cb_group(49),
- smmu_make_cb_group(50),
- smmu_make_cb_group(51),
- smmu_make_cb_group(52),
- smmu_make_cb_group(53),
- smmu_make_cb_group(54),
- smmu_make_cb_group(55),
- smmu_make_cb_group(56),
- smmu_make_cb_group(57),
- smmu_make_cb_group(58),
- smmu_make_cb_group(59),
- smmu_make_cb_group(60),
- smmu_make_cb_group(61),
- smmu_make_cb_group(62),
- smmu_make_cb_group(63),
+ smmu_make_cfg(TEGRA_SMMU0_BASE),
+ smmu_make_cfg(TEGRA_SMMU2_BASE),
smmu_bypass_cfg, /* TBU settings */
_END_OF_TABLE_,
};
diff --git a/plat/nvidia/tegra/soc/t194/plat_trampoline.S b/plat/nvidia/tegra/soc/t194/plat_trampoline.S
index 33c7e6f..696a577 100644
--- a/plat/nvidia/tegra/soc/t194/plat_trampoline.S
+++ b/plat/nvidia/tegra/soc/t194/plat_trampoline.S
@@ -12,7 +12,7 @@
#define TEGRA194_STATE_SYSTEM_SUSPEND 0x5C7
#define TEGRA194_STATE_SYSTEM_RESUME 0x600D
-#define TEGRA194_SMMU_CTX_SIZE 0x490
+#define TEGRA194_SMMU_CTX_SIZE 0x80B
.align 4
.globl tegra194_cpu_reset_handler
diff --git a/plat/rockchip/px30/drivers/pmu/pmu.c b/plat/rockchip/px30/drivers/pmu/pmu.c
index 0a2515d..5f4e64f 100644
--- a/plat/rockchip/px30/drivers/pmu/pmu.c
+++ b/plat/rockchip/px30/drivers/pmu/pmu.c
@@ -22,6 +22,7 @@
#include <plat_private.h>
#include <pmu.h>
#include <px30_def.h>
+#include <secure.h>
#include <soc.h>
DEFINE_BAKERY_LOCK(rockchip_pd_lock);
diff --git a/plat/rockchip/px30/drivers/secure/secure.c b/plat/rockchip/px30/drivers/secure/secure.c
new file mode 100644
index 0000000..144f945
--- /dev/null
+++ b/plat/rockchip/px30/drivers/secure/secure.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <ddr_parameter.h>
+#include <plat_private.h>
+#include <secure.h>
+#include <px30_def.h>
+
+/**
+ * There are 8 regions for DDR security control
+ * @rgn - the DDR regions 0 ~ 7 which are can be configured.
+ * @st - start address to set as secure
+ * @sz - length of area to set as secure
+ * The internal unit is megabytes, so memory areas need to be aligned
+ * to megabyte borders.
+ */
+static void secure_ddr_region(uint32_t rgn,
+ uintptr_t st, size_t sz)
+{
+ uintptr_t ed = st + sz;
+ uintptr_t st_mb, ed_mb;
+ uint32_t val;
+
+ assert(rgn <= 7);
+ assert(st < ed);
+
+ /* check aligned 1MB */
+ assert(st % SIZE_M(1) == 0);
+ assert(ed % SIZE_M(1) == 0);
+
+ st_mb = st / SIZE_M(1);
+ ed_mb = ed / SIZE_M(1);
+
+ /* map top and base */
+ mmio_write_32(FIREWALL_DDR_BASE +
+ FIREWALL_DDR_FW_DDR_RGN(rgn),
+ RG_MAP_SECURE(ed_mb, st_mb));
+
+ /* enable secure */
+ val = mmio_read_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_CON_REG);
+ val |= BIT(rgn);
+ mmio_write_32(FIREWALL_DDR_BASE +
+ FIREWALL_DDR_FW_DDR_CON_REG, val);
+}
+
+void secure_timer_init(void)
+{
+ mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG,
+ TIMER_DIS);
+
+ mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT0, 0xffffffff);
+ mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT1, 0xffffffff);
+
+ /* auto reload & enable the timer */
+ mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG,
+ TIMER_EN | TIMER_FMODE);
+}
+
+void sgrf_init(void)
+{
+#ifdef PLAT_RK_SECURE_DDR_MINILOADER
+ uint32_t i;
+ struct param_ddr_usage usg;
+
+ /* general secure regions */
+ usg = ddr_region_usage_parse(DDR_PARAM_BASE,
+ PLAT_MAX_DDR_CAPACITY_MB);
+
+ /* region-0 for TF-A, region-1 for optional OP-TEE */
+ assert(usg.s_nr < 7);
+
+ for (i = 0; i < usg.s_nr; i++)
+ secure_ddr_region(7 - i, usg.s_top[i], usg.s_base[i]);
+#endif
+
+ /* secure the trustzone ram */
+ secure_ddr_region(0, TZRAM_BASE, TZRAM_SIZE);
+
+ /* set all slave ip into no-secure, except stimer */
+ mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), SGRF_SLV_S_ALL_NS);
+ mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SLV_S_ALL_NS);
+ mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SLV_S_ALL_NS);
+ mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SLV_S_ALL_NS);
+ mmio_write_32(SGRF_BASE + SGRF_SOC_CON(8), 0x00030000);
+
+ /* set master crypto to no-secure, dcf to secure */
+ mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), 0x000f0003);
+
+ /* set DMAC into no-secure */
+ mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(0), DMA_IRQ_BOOT_NS);
+ mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(1), DMA_PERI_CH_NS_15_0);
+ mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(2), DMA_PERI_CH_NS_19_16);
+ mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(3), DMA_MANAGER_BOOT_NS);
+
+ /* soft reset dma before use */
+ mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_REQ);
+ udelay(5);
+ mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_RLS);
+}
diff --git a/plat/rockchip/px30/drivers/secure/secure.h b/plat/rockchip/px30/drivers/secure/secure.h
new file mode 100644
index 0000000..498027d
--- /dev/null
+++ b/plat/rockchip/px30/drivers/secure/secure.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SECURE_H
+#define SECURE_H
+
+/***************************************************************************
+ * SGRF
+ ***************************************************************************/
+#define SGRF_SOC_CON(i) ((i) * 0x4)
+#define SGRF_DMAC_CON(i) (0x30 + (i) * 0x4)
+
+#define SGRF_MST_S_ALL_NS 0xffffffff
+#define SGRF_SLV_S_ALL_NS 0xffff0000
+#define DMA_IRQ_BOOT_NS 0xffffffff
+#define DMA_PERI_CH_NS_15_0 0xffffffff
+#define DMA_PERI_CH_NS_19_16 0x000f000f
+#define DMA_MANAGER_BOOT_NS 0x00010001
+#define DMA_SOFTRST_REQ BITS_WITH_WMASK(1, 0x1, 12)
+#define DMA_SOFTRST_RLS BITS_WITH_WMASK(0, 0x1, 12)
+
+/***************************************************************************
+ * DDR FIREWALL
+ ***************************************************************************/
+#define FIREWALL_DDR_FW_DDR_RGN(i) ((i) * 0x4)
+#define FIREWALL_DDR_FW_DDR_MST(i) (0x20 + (i) * 0x4)
+#define FIREWALL_DDR_FW_DDR_CON_REG 0x40
+#define FIREWALL_DDR_FW_DDR_RGN_NUM 8
+#define FIREWALL_DDR_FW_DDR_MST_NUM 6
+
+#define PLAT_MAX_DDR_CAPACITY_MB 4096
+#define RG_MAP_SECURE(top, base) ((((top) - 1) << 16) | (base))
+
+/**************************************************
+ * secure timer
+ **************************************************/
+
+/* chanal0~5 */
+#define STIMER_CHN_BASE(n) (STIME_BASE + 0x20 * (n))
+
+#define TIMER_LOAD_COUNT0 0x0
+#define TIMER_LOAD_COUNT1 0x4
+
+#define TIMER_CUR_VALUE0 0x8
+#define TIMER_CUR_VALUE1 0xc
+
+#define TIMER_CONTROL_REG 0x10
+#define TIMER_INTSTATUS 0x18
+
+#define TIMER_DIS 0x0
+#define TIMER_EN 0x1
+
+#define TIMER_FMODE (0x0 << 1)
+#define TIMER_RMODE (0x1 << 1)
+
+#define TIMER_LOAD_COUNT0_MSK (0xffffffff)
+#define TIMER_LOAD_COUNT1_MSK (0xffffffff00000000)
+
+void secure_timer_init(void);
+void sgrf_init(void);
+
+#endif /* SECURE_H */
diff --git a/plat/rockchip/px30/drivers/soc/soc.c b/plat/rockchip/px30/drivers/soc/soc.c
index e00561d..200563d 100644
--- a/plat/rockchip/px30/drivers/soc/soc.c
+++ b/plat/rockchip/px30/drivers/soc/soc.c
@@ -12,10 +12,10 @@
#include <drivers/delay_timer.h>
#include <lib/mmio.h>
-#include <ddr_parameter.h>
#include <platform_def.h>
#include <pmu.h>
#include <px30_def.h>
+#include <secure.h>
#include <soc.h>
#include <rockchip_sip_svc.h>
@@ -83,65 +83,6 @@
0xffff0000);
}
-void secure_timer_init(void)
-{
- mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG,
- TIMER_DIS);
-
- mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT0, 0xffffffff);
- mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT1, 0xffffffff);
-
- /* auto reload & enable the timer */
- mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG,
- TIMER_EN | TIMER_FMODE);
-}
-
-static void sgrf_init(void)
-{
- uint32_t i, val;
- struct param_ddr_usage usg;
-
- /* general secure regions */
- usg = ddr_region_usage_parse(DDR_PARAM_BASE,
- PLAT_MAX_DDR_CAPACITY_MB);
- for (i = 0; i < usg.s_nr; i++) {
- /* enable secure */
- val = mmio_read_32(FIREWALL_DDR_BASE +
- FIREWALL_DDR_FW_DDR_CON_REG);
- val |= BIT(7 - i);
- mmio_write_32(FIREWALL_DDR_BASE +
- FIREWALL_DDR_FW_DDR_CON_REG, val);
- /* map top and base */
- mmio_write_32(FIREWALL_DDR_BASE +
- FIREWALL_DDR_FW_DDR_RGN(7 - i),
- RG_MAP_SECURE(usg.s_top[i], usg.s_base[i]));
- }
-
- /* set ddr rgn0_top and rga0_top as 0 */
- mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_RGN(0), 0x0);
-
- /* set all slave ip into no-secure, except stimer */
- mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), SGRF_SLV_S_ALL_NS);
- mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SLV_S_ALL_NS);
- mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SLV_S_ALL_NS);
- mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SLV_S_ALL_NS);
- mmio_write_32(SGRF_BASE + SGRF_SOC_CON(8), 0x00030000);
-
- /* set master crypto to no-secure, dcf to secure */
- mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), 0x000f0003);
-
- /* set DMAC into no-secure */
- mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(0), DMA_IRQ_BOOT_NS);
- mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(1), DMA_PERI_CH_NS_15_0);
- mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(2), DMA_PERI_CH_NS_19_16);
- mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(3), DMA_MANAGER_BOOT_NS);
-
- /* soft reset dma before use */
- mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_REQ);
- udelay(5);
- mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_RLS);
-}
-
static void soc_reset_config_all(void)
{
uint32_t tmp;
diff --git a/plat/rockchip/px30/drivers/soc/soc.h b/plat/rockchip/px30/drivers/soc/soc.h
index 69f2de4..648d18b 100644
--- a/plat/rockchip/px30/drivers/soc/soc.h
+++ b/plat/rockchip/px30/drivers/soc/soc.h
@@ -29,21 +29,6 @@
};
/***************************************************************************
- * SGRF
- ***************************************************************************/
-#define SGRF_SOC_CON(i) ((i) * 0x4)
-#define SGRF_DMAC_CON(i) (0x30 + (i) * 0x4)
-
-#define SGRF_MST_S_ALL_NS 0xffffffff
-#define SGRF_SLV_S_ALL_NS 0xffff0000
-#define DMA_IRQ_BOOT_NS 0xffffffff
-#define DMA_PERI_CH_NS_15_0 0xffffffff
-#define DMA_PERI_CH_NS_19_16 0x000f000f
-#define DMA_MANAGER_BOOT_NS 0x00010001
-#define DMA_SOFTRST_REQ BITS_WITH_WMASK(1, 0x1, 12)
-#define DMA_SOFTRST_RLS BITS_WITH_WMASK(0, 0x1, 12)
-
-/***************************************************************************
* GRF
***************************************************************************/
#define GRF_SOC_CON(i) (0x0400 + (i) * 4)
@@ -61,18 +46,6 @@
#define GRF_SOC_CON2_NSWDT_RST_EN 12
/***************************************************************************
- * DDR FIREWALL
- ***************************************************************************/
-#define FIREWALL_DDR_FW_DDR_RGN(i) ((i) * 0x4)
-#define FIREWALL_DDR_FW_DDR_MST(i) (0x20 + (i) * 0x4)
-#define FIREWALL_DDR_FW_DDR_CON_REG 0x40
-#define FIREWALL_DDR_FW_DDR_RGN_NUM 8
-#define FIREWALL_DDR_FW_DDR_MST_NUM 6
-
-#define PLAT_MAX_DDR_CAPACITY_MB 4096
-#define RG_MAP_SECURE(top, base) ((((top) - 1) << 16) | (base))
-
-/***************************************************************************
* cru
***************************************************************************/
#define CRU_MODE 0xa0
@@ -136,37 +109,10 @@
#define GPIO_INT_STATUS 0x40
#define GPIO_NUMS 4
-/**************************************************
- * secure timer
- **************************************************/
-
-/* chanal0~5 */
-#define STIMER_CHN_BASE(n) (STIME_BASE + 0x20 * (n))
-
-#define TIMER_LOAD_COUNT0 0x0
-#define TIMER_LOAD_COUNT1 0x4
-
-#define TIMER_CUR_VALUE0 0x8
-#define TIMER_CUR_VALUE1 0xc
-
-#define TIMER_CONTROL_REG 0x10
-#define TIMER_INTSTATUS 0x18
-
-#define TIMER_DIS 0x0
-#define TIMER_EN 0x1
-
-#define TIMER_FMODE (0x0 << 1)
-#define TIMER_RMODE (0x1 << 1)
-
-#define TIMER_LOAD_COUNT0_MSK (0xffffffff)
-#define TIMER_LOAD_COUNT1_MSK (0xffffffff00000000)
-
void clk_gate_con_save(uint32_t *clkgt_save);
void clk_gate_con_restore(uint32_t *clkgt_save);
void clk_gate_con_disable(void);
-void secure_timer_init(void);
-void secure_timer_disable(void);
void px30_soc_reset_config(void);
#endif /* __SOC_H__ */
diff --git a/plat/rockchip/px30/include/platform_def.h b/plat/rockchip/px30/include/platform_def.h
index 9dccab8..2f4f672 100644
--- a/plat/rockchip/px30/include/platform_def.h
+++ b/plat/rockchip/px30/include/platform_def.h
@@ -69,9 +69,9 @@
/*******************************************************************************
* Platform memory map related constants
******************************************************************************/
-/* TF text, ro, rw, Size: 512KB */
+/* TF text, ro, rw, Size: 1MB */
#define TZRAM_BASE (0x0)
-#define TZRAM_SIZE (0x80000)
+#define TZRAM_SIZE (0x100000)
/*******************************************************************************
* BL31 specific defines.
diff --git a/plat/rockchip/px30/platform.mk b/plat/rockchip/px30/platform.mk
index ee85cd3..87cf187 100644
--- a/plat/rockchip/px30/platform.mk
+++ b/plat/rockchip/px30/platform.mk
@@ -20,6 +20,7 @@
-I${RK_PLAT_COMMON}/pmusram \
-I${RK_PLAT_SOC}/ \
-I${RK_PLAT_SOC}/drivers/pmu/ \
+ -I${RK_PLAT_SOC}/drivers/secure/ \
-I${RK_PLAT_SOC}/drivers/soc/ \
-I${RK_PLAT_SOC}/include/
@@ -45,16 +46,20 @@
${RK_PLAT_COMMON}/aarch64/plat_helpers.S \
${RK_PLAT_COMMON}/aarch64/platform_common.c \
${RK_PLAT_COMMON}/bl31_plat_setup.c \
- ${RK_PLAT_COMMON}/drivers/parameter/ddr_parameter.c \
${RK_PLAT_COMMON}/params_setup.c \
${RK_PLAT_COMMON}/pmusram/cpus_on_fixed_addr.S \
${RK_PLAT_COMMON}/plat_pm.c \
${RK_PLAT_COMMON}/plat_topology.c \
${RK_PLAT_COMMON}/rockchip_sip_svc.c \
${RK_PLAT_SOC}/drivers/pmu/pmu.c \
+ ${RK_PLAT_SOC}/drivers/secure/secure.c \
${RK_PLAT_SOC}/drivers/soc/soc.c \
${RK_PLAT_SOC}/plat_sip_calls.c
+ifdef PLAT_RK_SECURE_DDR_MINILOADER
+BL31_SOURCES += ${RK_PLAT_COMMON}/drivers/parameter/ddr_parameter.c
+endif
+
ENABLE_PLAT_COMPAT := 0
MULTI_CONSOLE_API := 1
diff --git a/plat/rockchip/px30/px30_def.h b/plat/rockchip/px30/px30_def.h
index 283b606..efe789e 100644
--- a/plat/rockchip/px30/px30_def.h
+++ b/plat/rockchip/px30/px30_def.h
@@ -11,6 +11,7 @@
#define MINOR_VERSION (0)
#define SIZE_K(n) ((n) * 1024)
+#define SIZE_M(n) ((n) * 1024 * 1024)
#define WITH_16BITS_WMSK(bits) (0xffff0000 | (bits))
diff --git a/plat/rockchip/rk3288/drivers/secure/secure.c b/plat/rockchip/rk3288/drivers/secure/secure.c
index 68994e4..25e1cca 100644
--- a/plat/rockchip/rk3288/drivers/secure/secure.c
+++ b/plat/rockchip/rk3288/drivers/secure/secure.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -38,15 +38,18 @@
* SGRF_SOC_CON21 - end address of the RGN_7 + RGN_X control
*
* @rgn - the DDR regions 0 ~ 7 which are can be configured.
- * The @st and @ed indicate the start and end addresses for which to set
- * the security, and the unit is byte. When the st_mb == 0, ed_mb == 0, the
+ * @st - start address to set as secure
+ * @sz - length of area to set as secure
+ * The @st_mb and @ed_mb indicate the start and end addresses for which to set
+ * the security, and the unit is megabyte. When the st_mb == 0, ed_mb == 0, the
* address range 0x0 ~ 0xfffff is secure.
*
* For example, if we would like to set the range [0, 32MB) is security via
* DDR_RGN0, then rgn == 0, st_mb == 0, ed_mb == 31.
*/
-static void sgrf_ddr_rgn_config(uint32_t rgn, uintptr_t st, uintptr_t ed)
+static void sgrf_ddr_rgn_config(uint32_t rgn, uintptr_t st, size_t sz)
{
+ uintptr_t ed = st + sz;
uintptr_t st_mb, ed_mb;
assert(rgn <= 7);
diff --git a/plat/rockchip/rk3328/drivers/soc/soc.c b/plat/rockchip/rk3328/drivers/soc/soc.c
index 59d8572..306308f 100644
--- a/plat/rockchip/rk3328/drivers/soc/soc.c
+++ b/plat/rockchip/rk3328/drivers/soc/soc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -97,6 +97,7 @@
void sgrf_init(void)
{
+#ifdef PLAT_RK_SECURE_DDR_MINILOADER
uint32_t i, val;
struct param_ddr_usage usg;
@@ -115,6 +116,7 @@
FIREWALL_DDR_FW_DDR_RGN(7 - i),
RG_MAP_SECURE(usg.s_top[i], usg.s_base[i]));
}
+#endif
/* set ddr rgn0_top and rga0_top as 0 */
mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_RGN(0), 0x0);
diff --git a/plat/rockchip/rk3328/include/platform_def.h b/plat/rockchip/rk3328/include/platform_def.h
index baac12d..e9eb3fa 100644
--- a/plat/rockchip/rk3328/include/platform_def.h
+++ b/plat/rockchip/rk3328/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -66,9 +66,9 @@
/*******************************************************************************
* Platform memory map related constants
******************************************************************************/
-/* TF text, ro, rw, Size: 512KB */
+/* TF text, ro, rw, Size: 1MB */
#define TZRAM_BASE (0x0)
-#define TZRAM_SIZE (0x80000)
+#define TZRAM_SIZE (0x100000)
/*******************************************************************************
* BL31 specific defines.
diff --git a/plat/rockchip/rk3328/platform.mk b/plat/rockchip/rk3328/platform.mk
index 0da4f2d..0c5cfae 100644
--- a/plat/rockchip/rk3328/platform.mk
+++ b/plat/rockchip/rk3328/platform.mk
@@ -42,7 +42,6 @@
drivers/delay_timer/generic_delay_timer.c \
lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
- ${RK_PLAT_COMMON}/drivers/parameter/ddr_parameter.c \
${RK_PLAT_COMMON}/aarch64/plat_helpers.S \
${RK_PLAT_COMMON}/params_setup.c \
${RK_PLAT_COMMON}/bl31_plat_setup.c \
@@ -53,6 +52,10 @@
${RK_PLAT_SOC}/drivers/pmu/pmu.c \
${RK_PLAT_SOC}/drivers/soc/soc.c
+ifdef PLAT_RK_SECURE_DDR_MINILOADER
+BL31_SOURCES += ${RK_PLAT_COMMON}/drivers/parameter/ddr_parameter.c
+endif
+
include lib/coreboot/coreboot.mk
include lib/libfdt/libfdt.mk
diff --git a/plat/rockchip/rk3368/include/platform_def.h b/plat/rockchip/rk3368/include/platform_def.h
index 9334a83..2abd56b 100644
--- a/plat/rockchip/rk3368/include/platform_def.h
+++ b/plat/rockchip/rk3368/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -67,9 +67,9 @@
/*******************************************************************************
* Platform memory map related constants
******************************************************************************/
-/* TF text, ro, rw, Size: 512KB */
+/* TF text, ro, rw, Size: 1MB */
#define TZRAM_BASE (0x0)
-#define TZRAM_SIZE (0x80000)
+#define TZRAM_SIZE (0x100000)
/*******************************************************************************
* BL31 specific defines.
diff --git a/plat/rockchip/rk3399/drivers/dp/cdn_dp.c b/plat/rockchip/rk3399/drivers/dp/cdn_dp.c
index aa71fde..a8773f4 100644
--- a/plat/rockchip/rk3399/drivers/dp/cdn_dp.c
+++ b/plat/rockchip/rk3399/drivers/dp/cdn_dp.c
@@ -18,7 +18,7 @@
".global hdcp_handler\n"
".balign 4\n"
"hdcp_handler:\n"
- ".incbin \"" __XSTRING(HDCPFW) "\"\n"
+ ".incbin \"" HDCPFW "\"\n"
".type hdcp_handler, %function\n"
".size hdcp_handler, .- hdcp_handler\n"
".popsection\n"
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c
index 30941fd..faee678 100644
--- a/plat/rockchip/rk3399/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c
@@ -400,6 +400,25 @@
clk_gate_con_restore();
}
+void pmu_power_domains_on(void)
+{
+ clk_gate_con_disable();
+ pmu_set_power_domain(PD_VDU, pmu_pd_on);
+ pmu_set_power_domain(PD_VCODEC, pmu_pd_on);
+ pmu_set_power_domain(PD_RGA, pmu_pd_on);
+ pmu_set_power_domain(PD_IEP, pmu_pd_on);
+ pmu_set_power_domain(PD_EDP, pmu_pd_on);
+ pmu_set_power_domain(PD_GMAC, pmu_pd_on);
+ pmu_set_power_domain(PD_SDIOAUDIO, pmu_pd_on);
+ pmu_set_power_domain(PD_HDCP, pmu_pd_on);
+ pmu_set_power_domain(PD_ISP1, pmu_pd_on);
+ pmu_set_power_domain(PD_ISP0, pmu_pd_on);
+ pmu_set_power_domain(PD_VO, pmu_pd_on);
+ pmu_set_power_domain(PD_TCPD1, pmu_pd_on);
+ pmu_set_power_domain(PD_TCPD0, pmu_pd_on);
+ pmu_set_power_domain(PD_GPU, pmu_pd_on);
+}
+
void rk3399_flush_l2_b(void)
{
uint32_t wait_cnt = 0;
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.h b/plat/rockchip/rk3399/drivers/pmu/pmu.h
index 74db82f..bb7de50 100644
--- a/plat/rockchip/rk3399/drivers/pmu/pmu.h
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.h
@@ -136,5 +136,6 @@
extern uint32_t clst_warmboot_data[PLATFORM_CLUSTER_COUNT];
extern void sram_func_set_ddrctl_pll(uint32_t pll_src);
+void pmu_power_domains_on(void);
#endif /* PMU_H */
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu_fw.c b/plat/rockchip/rk3399/drivers/pmu/pmu_fw.c
index a09ad21..25596b1 100644
--- a/plat/rockchip/rk3399/drivers/pmu/pmu_fw.c
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu_fw.c
@@ -5,20 +5,18 @@
*/
/* convoluted way to make sure that the define is pasted just the right way */
-#define _INCBIN(file, sym, sec) \
+#define INCBIN(file, sym, sec) \
__asm__( \
- ".section " #sec "\n" \
- ".global " #sym "\n" \
- ".type " #sym ", %object\n" \
+ ".section " sec "\n" \
+ ".global " sym "\n" \
+ ".type " sym ", %object\n" \
".align 4\n" \
- #sym ":\n" \
- ".incbin \"" #file "\"\n" \
- ".size " #sym ", .-" #sym "\n" \
- ".global " #sym "_end\n" \
- #sym "_end:\n" \
+ sym ":\n" \
+ ".incbin \"" file "\"\n" \
+ ".size " sym ", .-" sym "\n" \
+ ".global " sym "_end\n" \
+ sym "_end:\n" \
)
-#define INCBIN(file, sym, sec) _INCBIN(file, sym, sec)
-
-INCBIN(RK3399M0FW, rk3399m0_bin, ".sram.incbin");
-INCBIN(RK3399M0PMUFW, rk3399m0pmu_bin, ".pmusram.incbin");
+INCBIN(RK3399M0FW, "rk3399m0_bin", ".sram.incbin");
+INCBIN(RK3399M0PMUFW, "rk3399m0pmu_bin", ".pmusram.incbin");
diff --git a/plat/rockchip/rk3399/drivers/secure/secure.c b/plat/rockchip/rk3399/drivers/secure/secure.c
index 8286f17..13c83ca 100644
--- a/plat/rockchip/rk3399/drivers/secure/secure.c
+++ b/plat/rockchip/rk3399/drivers/secure/secure.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -45,6 +45,8 @@
* bypass, 1: enable bypass
*
* @rgn - the DDR regions 0 ~ 7 which are can be configured.
+ * @st - start address to set as secure
+ * @sz - length of area to set as secure
* The @st_mb and @ed_mb indicate the start and end addresses for which to set
* the security, and the unit is megabyte. When the st_mb == 0, ed_mb == 0, the
* address range 0x0 ~ 0xfffff is secure.
@@ -53,8 +55,9 @@
* DDR_RGN0, then rgn == 0, st_mb == 0, ed_mb == 31.
*/
static void sgrf_ddr_rgn_config(uint32_t rgn,
- uintptr_t st, uintptr_t ed)
+ uintptr_t st, size_t sz)
{
+ uintptr_t ed = st + sz;
uintptr_t st_mb, ed_mb;
assert(rgn <= 7);
diff --git a/plat/rockchip/rk3399/drivers/soc/soc.c b/plat/rockchip/rk3399/drivers/soc/soc.c
index c877dbd..98b5ad6 100644
--- a/plat/rockchip/rk3399/drivers/soc/soc.c
+++ b/plat/rockchip/rk3399/drivers/soc/soc.c
@@ -17,6 +17,7 @@
#include <dram.h>
#include <m0_ctl.h>
#include <plat_private.h>
+#include <pmu.h>
#include <rk3399_def.h>
#include <secure.h>
#include <soc.h>
@@ -327,6 +328,7 @@
void __dead2 soc_global_soft_reset(void)
{
+ pmu_power_domains_on();
set_pll_slow_mode(VPLL_ID);
set_pll_slow_mode(NPLL_ID);
set_pll_slow_mode(GPLL_ID);
diff --git a/plat/rockchip/rk3399/plat_sip_calls.c b/plat/rockchip/rk3399/plat_sip_calls.c
index c2cc5b1..ce8476c 100644
--- a/plat/rockchip/rk3399/plat_sip_calls.c
+++ b/plat/rockchip/rk3399/plat_sip_calls.c
@@ -56,17 +56,21 @@
void *handle,
u_register_t flags)
{
+#ifdef PLAT_RK_DP_HDCP
uint64_t x5, x6;
+#endif
switch (smc_fid) {
case RK_SIP_DDR_CFG:
SMC_RET1(handle, ddr_smc_handler(x1, x2, x3, x4));
+#ifdef PLAT_RK_DP_HDCP
case RK_SIP_HDCP_CONTROL:
SMC_RET1(handle, dp_hdcp_ctrl(x1));
case RK_SIP_HDCP_KEY_DATA64:
x5 = read_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X5);
x6 = read_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X6);
SMC_RET1(handle, dp_hdcp_store_key(x1, x2, x3, x4, x5, x6));
+#endif
default:
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
SMC_RET1(handle, SMC_UNK);
diff --git a/plat/rockchip/rk3399/platform.mk b/plat/rockchip/rk3399/platform.mk
index cfc48e8..5a23d3c 100644
--- a/plat/rockchip/rk3399/platform.mk
+++ b/plat/rockchip/rk3399/platform.mk
@@ -56,7 +56,6 @@
${RK_PLAT_COMMON}/aarch64/platform_common.c \
${RK_PLAT_COMMON}/rockchip_sip_svc.c \
${RK_PLAT_SOC}/plat_sip_calls.c \
- ${RK_PLAT_SOC}/drivers/dp/cdn_dp.c \
${RK_PLAT_SOC}/drivers/gpio/rk3399_gpio.c \
${RK_PLAT_SOC}/drivers/pmu/pmu.c \
${RK_PLAT_SOC}/drivers/pmu/pmu_fw.c \
@@ -82,22 +81,26 @@
BUILD_M0 := ${BUILD_PLAT}/m0
RK3399M0FW=${BUILD_M0}/${PLAT_M0}.bin
-$(eval $(call add_define,RK3399M0FW))
+$(eval $(call add_define_val,RK3399M0FW,\"$(RK3399M0FW)\"))
RK3399M0PMUFW=${BUILD_M0}/${PLAT_M0}pmu.bin
-$(eval $(call add_define,RK3399M0PMUFW))
+$(eval $(call add_define_val,RK3399M0PMUFW,\"$(RK3399M0PMUFW)\"))
+
+ifdef PLAT_RK_DP_HDCP
+BL31_SOURCES += ${RK_PLAT_SOC}/drivers/dp/cdn_dp.c
HDCPFW=${RK_PLAT_SOC}/drivers/dp/hdcp.bin
-$(eval $(call add_define,HDCPFW))
+$(eval $(call add_define_val,HDCPFW,\"$(HDCPFW)\"))
+
+${BUILD_PLAT}/bl31/cdn_dp.o: CCACHE_EXTRAFILES=$(HDCPFW)
+${RK_PLAT_SOC}/drivers/dp/cdn_dp.c: $(HDCPFW)
+endif
# CCACHE_EXTRAFILES is needed because ccache doesn't handle .incbin
export CCACHE_EXTRAFILES
${BUILD_PLAT}/bl31/pmu_fw.o: CCACHE_EXTRAFILES=$(RK3399M0FW):$(RK3399M0PMUFW)
${RK_PLAT_SOC}/drivers/pmu/pmu_fw.c: $(RK3399M0FW)
-${BUILD_PLAT}/bl31/cdn_dp.o: CCACHE_EXTRAFILES=$(HDCPFW)
-${RK_PLAT_SOC}/drivers/dp/cdn_dp.c: $(HDCPFW)
-
$(eval $(call MAKE_PREREQ_DIR,${BUILD_M0},${BUILD_PLAT}))
.PHONY: $(RK3399M0FW)
$(RK3399M0FW): | ${BUILD_M0}