tree 84232188f673bdfe5de3d66acb9cde74d195cee2
parent 6ed3bf61eb9bf3adb58ee6de6832faf6823b6aad
author Boyan Karatotev <boyan.karatotev@arm.com> 1702396741 +0000
committer Boyan Karatotev <boyan.karatotev@arm.com> 1708954885 +0000

feat(tc): introduce an FPGA subvariant and TC3 CPUs

TC is getting an FPGA port alongside the FVP. It is meant to be
identical, but the core configurations on TC2 differ (there are 14 in an
odd arrangement).

Introduce these differences and gate them behind a new TARGET_FLAVOUR
flag which defaults to FVP for compatibility.

While updating CPUs, it's a good time to do TC3 too. It has different
cores in a different configuration again, so it needs different capacity
values. Those have been derived using GeekBench 6.0 ST on the FPGA.

Finally GPU and DPU power domains are 1 above the CPUs so make that
relative.

In the end, the big/mid/little configurations are:
 * TC2 FVP:  1/3/4
 * TC2 FPGA: 2/3/5/4 (the 3 is a big "min" core)
 * TC3 both: 2/4/2 (with new capacities)

Co-developed-by: Tintu Thomas <tintu.thomas@arm.com>
Co-developed-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I3c3a10d6727f5010fd9026a404df27e9262dff6b