Merge changes from topic "sm_bk/errata_refactor" into integration
* changes:
refactor(cpus): convert the Cortex-A57 to use cpu helpers
refactor(cpus): convert the Cortex-A57 to use the errata framework
refactor(cpus): reorder Cortex-A57 errata by ascending order
refactor(cpus): add Cortex-A57 errata framework information
refactor(cpus): convert the Cortex-A53 to use cpu helpers
refactor(cpus): convert the Cortex-A53 to use the errata framework
refactor(cpus): reorder Cortex-A53 errata by ascending order
diff --git a/Makefile b/Makefile
index 0c35120..8e2fd81 100644
--- a/Makefile
+++ b/Makefile
@@ -768,8 +768,8 @@
ifeq (${AARCH32_SP_MAKE},)
$(error Error: No bl32/${AARCH32_SP}/${AARCH32_SP}.mk located)
endif
- $(info Including ${AARCH32_SP_MAKE})
- include ${AARCH32_SP_MAKE}
+ $(info Including ${AARCH32_SP_MAKE})
+ include ${AARCH32_SP_MAKE}
endif
endif #(ARCH=aarch32)
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index bc37c94..951f023 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -437,6 +437,7 @@
#define ID_AA64PFR1_EL1_SME_SHIFT U(24)
#define ID_AA64PFR1_EL1_SME_MASK ULL(0xf)
+#define ID_AA64PFR1_EL1_SME_WIDTH U(4)
#define ID_AA64PFR1_EL1_SME_NOT_SUPPORTED ULL(0x0)
#define ID_AA64PFR1_EL1_SME_SUPPORTED ULL(0x1)
#define ID_AA64PFR1_EL1_SME2_SUPPORTED ULL(0x2)
diff --git a/lib/cpus/aarch64/cortex_gelas.S b/lib/cpus/aarch64/cortex_gelas.S
index e0d20a9..dc704f2 100644
--- a/lib/cpus/aarch64/cortex_gelas.S
+++ b/lib/cpus/aarch64/cortex_gelas.S
@@ -34,13 +34,20 @@
* ----------------------------------------------------
*/
func cortex_gelas_core_pwr_dwn
+#if ENABLE_SME_FOR_NS
/* ---------------------------------------------------
- * Disable SME
+ * Disable SME if enabled and supported
* ---------------------------------------------------
*/
+ mrs x0, ID_AA64PFR1_EL1
+ ubfx x0, x0, #ID_AA64PFR1_EL1_SME_SHIFT, \
+ #ID_AA64PFR1_EL1_SME_WIDTH
+ cmp x0, #ID_AA64PFR1_EL1_SME_NOT_SUPPORTED
+ b.eq 1f
msr CORTEX_GELAS_SVCRSM, xzr
msr CORTEX_GELAS_SVCRZA, xzr
-
+1:
+#endif
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------------
diff --git a/plat/arm/board/a5ds/platform.mk b/plat/arm/board/a5ds/platform.mk
index 6fcf080..3ed7a63 100644
--- a/plat/arm/board/a5ds/platform.mk
+++ b/plat/arm/board/a5ds/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2019-2021, Arm Limited. All rights reserved.
+# Copyright (c) 2019-2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -98,6 +98,10 @@
NEED_BL32 := yes
+ifeq (${AARCH32_SP},none)
+ $(error Variable AARCH32_SP has to be set for AArch32)
+endif
+
MULTI_CONSOLE_API := 1
ARM_DISABLE_TRUSTED_WDOG := 1
diff --git a/plat/arm/board/corstone700/platform.mk b/plat/arm/board/corstone700/platform.mk
index 75833f6..d6d3bef 100644
--- a/plat/arm/board/corstone700/platform.mk
+++ b/plat/arm/board/corstone700/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2019-2022, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2019-2023, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -25,6 +25,10 @@
NEED_BL32 := yes
+ifeq (${AARCH32_SP},none)
+ $(error Variable AARCH32_SP has to be set for AArch32)
+endif
+
# Include GICv2 driver files
include drivers/arm/gic/v2/gicv2.mk
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 6ac4e09..9104838 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -407,10 +407,6 @@
PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c
endif
-ifeq (${ARCH},aarch32)
- NEED_BL32 := yes
-endif
-
# Enable the dynamic translation tables library.
ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),)
ifeq (${ARCH},aarch32)
diff --git a/plat/arm/board/fvp_ve/platform.mk b/plat/arm/board/fvp_ve/platform.mk
index f7eace8..79cf356 100644
--- a/plat/arm/board/fvp_ve/platform.mk
+++ b/plat/arm/board/fvp_ve/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2019-2021, Arm Limited. All rights reserved.
+# Copyright (c) 2019-2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -96,6 +96,10 @@
NEED_BL32 := yes
+ifeq (${AARCH32_SP},none)
+ $(error Variable AARCH32_SP has to be set for AArch32)
+endif
+
# Modification of arm_common.mk
# Process ARM_DISABLE_TRUSTED_WDOG flag
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index 4914553..41d1b66 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -6,6 +6,12 @@
include common/fdt_wrappers.mk
+ifeq (${ARCH},aarch32)
+ ifeq (${AARCH32_SP},none)
+ $(error Variable AARCH32_SP has to be set for AArch32)
+ endif
+endif
+
ifeq (${ARCH}, aarch64)
# On ARM standard platorms, the TSP can execute from Trusted SRAM, Trusted
# DRAM (if available) or the TZC secured area of DRAM.
diff --git a/plat/imx/imx7/common/imx7.mk b/plat/imx/imx7/common/imx7.mk
index f4f5bfc..156c55d 100644
--- a/plat/imx/imx7/common/imx7.mk
+++ b/plat/imx/imx7/common/imx7.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -110,3 +110,7 @@
ifeq (${ARCH},aarch64)
$(error Error: AArch64 not supported on i.mx7)
endif
+
+ifeq (${AARCH32_SP}, none)
+ $(error Variable AARCH32_SP has to be set for AArch32)
+endif
diff --git a/plat/nuvoton/npcm845x/npcm845x_bl31_setup.c b/plat/nuvoton/npcm845x/npcm845x_bl31_setup.c
index 26ddb4b..08448db 100644
--- a/plat/nuvoton/npcm845x/npcm845x_bl31_setup.c
+++ b/plat/nuvoton/npcm845x/npcm845x_bl31_setup.c
@@ -47,27 +47,12 @@
BL31_END - BL31_START, \
MT_MEMORY | MT_RW | EL3_PAS)
-#if RECLAIM_INIT_CODE
-IMPORT_SYM(unsigned long, __INIT_CODE_START__, BL_INIT_CODE_BASE);
-IMPORT_SYM(unsigned long, __INIT_CODE_END__, BL_CODE_END_UNALIGNED);
-
-#define BL_INIT_CODE_END ((BL_CODE_END_UNALIGNED + PAGE_SIZE - 1) & \
- ~(PAGE_SIZE - 1))
-
-#define MAP_BL_INIT_CODE MAP_REGION_FLAT( \
- BL_INIT_CODE_BASE, \
- BL_INIT_CODE_END - \
- BL_INIT_CODE_BASE, \
- MT_CODE | MT_SECURE)
-#endif /* RECLAIM_INIT_CODE */
-
#if SEPARATE_NOBITS_REGION
#define MAP_BL31_NOBITS MAP_REGION_FLAT( \
BL31_NOBITS_BASE, \
BL31_NOBITS_LIMIT - \
BL31_NOBITS_BASE, \
MT_MEMORY | MT_RW | EL3_PAS)
-
#endif /* SEPARATE_NOBITS_REGION */
/******************************************************************************
@@ -324,9 +309,6 @@
{
const mmap_region_t bl_regions[] = {
MAP_BL31_TOTAL,
-#if RECLAIM_INIT_CODE
- MAP_BL_INIT_CODE,
-#endif /* RECLAIM_INIT_CODE */
#if SEPARATE_NOBITS_REGION
MAP_BL31_NOBITS,
#endif /* SEPARATE_NOBITS_REGION */
diff --git a/plat/nuvoton/npcm845x/platform.mk b/plat/nuvoton/npcm845x/platform.mk
index f38ae29..7fbf11e 100644
--- a/plat/nuvoton/npcm845x/platform.mk
+++ b/plat/nuvoton/npcm845x/platform.mk
@@ -9,7 +9,7 @@
# This is a debug flag for bring-up. It allows reducing CPU numbers
# SECONDARY_BRINGUP := 1
RESET_TO_BL31 := 1
-PMD_SPM_AT_SEL2 := 0
+SPMD_SPM_AT_SEL2 := 0
#temporary until the RAM size is reduced
USE_COHERENT_MEM := 1
@@ -21,29 +21,12 @@
# Trusted DRAM (if available) or the TZC secured area of DRAM.
# TZC secured DRAM is the default.
-ARM_TSP_RAM_LOCATION ?= dram
-
-ifeq (${ARM_TSP_RAM_LOCATION}, tsram)
-ARM_TSP_RAM_LOCATION_ID = ARM_TRUSTED_SRAM_ID
-else ifeq (${ARM_TSP_RAM_LOCATION}, tdram)
-ARM_TSP_RAM_LOCATION_ID = ARM_TRUSTED_DRAM_ID
-else ifeq (${ARM_TSP_RAM_LOCATION}, dram)
-ARM_TSP_RAM_LOCATION_ID = ARM_DRAM_ID
-else
-$(error "Unsupported ARM_TSP_RAM_LOCATION value")
-endif
-
-# Process flags
# Process ARM_BL31_IN_DRAM flag
ARM_BL31_IN_DRAM := 0
$(eval $(call assert_boolean,ARM_BL31_IN_DRAM))
$(eval $(call add_define,ARM_BL31_IN_DRAM))
-else
-ARM_TSP_RAM_LOCATION_ID = ARM_TRUSTED_SRAM_ID
endif
-$(eval $(call add_define,ARM_TSP_RAM_LOCATION_ID))
-
# For the original power-state parameter format, the State-ID can be encoded
# according to the recommended encoding or zero. This flag determines which
# State-ID encoding to be parsed.
@@ -370,12 +353,6 @@
include ${IMG_PARSER_LIB_MK}
endif
-ifeq (${RECLAIM_INIT_CODE}, 1)
-ifeq (${ARM_XLAT_TABLES_LIB_V1}, 1)
-$(error "To reclaim init code xlat tables v2 must be used")
-endif
-endif
-
ifeq (${MEASURED_BOOT},1)
MEASURED_BOOT_MK := drivers/measured_boot/measured_boot.mk
$(info Including ${MEASURED_BOOT_MK})
@@ -392,6 +369,3 @@
DEBUG_CONSOLE ?= 0
$(eval $(call add_define,DEBUG_CONSOLE))
-
-$(eval $(call add_define,ARM_TSP_RAM_LOCATION_ID))
-
diff --git a/plat/qti/msm8916/platform.mk b/plat/qti/msm8916/platform.mk
index 4f4dcb4..c71ad94 100644
--- a/plat/qti/msm8916/platform.mk
+++ b/plat/qti/msm8916/platform.mk
@@ -75,11 +75,14 @@
PRELOADED_BL33_BASE ?= 0x8f600000
ifeq (${ARCH},aarch64)
-BL32_BASE ?= BL31_LIMIT
-$(eval $(call add_define,BL31_BASE))
+ BL32_BASE ?= BL31_LIMIT
+ $(eval $(call add_define,BL31_BASE))
else
-# There is no BL31 on aarch32, so reuse its location for BL32
-BL32_BASE ?= $(BL31_BASE)
+ ifeq (${AARCH32_SP},none)
+ $(error Variable AARCH32_SP has to be set for AArch32)
+ endif
+ # There is no BL31 on aarch32, so reuse its location for BL32
+ BL32_BASE ?= $(BL31_BASE)
endif
$(eval $(call add_define,BL32_BASE))
diff --git a/plat/rockchip/rk3288/platform.mk b/plat/rockchip/rk3288/platform.mk
index b8dd195..e6f78cf 100644
--- a/plat/rockchip/rk3288/platform.mk
+++ b/plat/rockchip/rk3288/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -67,3 +67,7 @@
ENABLE_SVE_FOR_NS := 0
WORKAROUND_CVE_2017_5715 := 0
+
+ifeq (${AARCH32_SP}, none)
+ $(error Variable AARCH32_SP has to be set for AArch32)
+endif