diff --git a/plat/nvidia/tegra/soc/t186/drivers/se/se.c b/plat/nvidia/tegra/soc/t186/drivers/se/se.c
index dfb9de8..25f8cd0 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/se/se.c
+++ b/plat/nvidia/tegra/soc/t186/drivers/se/se.c
@@ -12,7 +12,6 @@
 #include <bpmp_ipc.h>
 #include <pmc.h>
 #include <security_engine.h>
-#include <tegra186_private.h>
 #include <tegra_private.h>
 
 #include "se_private.h"
diff --git a/plat/nvidia/tegra/soc/t186/plat_memctrl.c b/plat/nvidia/tegra/soc/t186/plat_memctrl.c
index 09377bb..7ff7e77 100644
--- a/plat/nvidia/tegra/soc/t186/plat_memctrl.c
+++ b/plat/nvidia/tegra/soc/t186/plat_memctrl.c
@@ -10,8 +10,8 @@
 
 #include <mce.h>
 #include <memctrl_v2.h>
-#include <tegra_mc_def.h>
 #include <tegra186_private.h>
+#include <tegra_mc_def.h>
 #include <tegra_platform.h>
 #include <tegra_private.h>
 
@@ -711,13 +711,6 @@
 void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes)
 {
 	uint32_t val;
-	uint64_t src_base_tzdram;
-	const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
-	uint64_t src_len_in_bytes = BL31_END - BL31_START;
-
-	/* base address of BL3-1 source in TZDRAM */
-	src_base_tzdram = params_from_bl2->tzdram_base +
-	      tegra186_get_cpu_reset_handler_size();
 
 	/*
 	 * Setup the Memory controller to allow only secure accesses to
@@ -747,15 +740,6 @@
 	mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_TZDRAM_ADDR_HI, val);
 
 	/*
-	 * save tzdram_addr_lo and ATF-size, this would be used in SC7-RF to
-	 * generate SHA256.
-	 */
-	mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV68_LO,
-			(uint32_t)src_base_tzdram);
-	mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV0_HI,
-			(uint32_t)src_len_in_bytes);
-
-	/*
 	 * MCE propagates the security configuration values across the
 	 * CCPLEX.
 	 */
diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
index 4316c98..6f58427 100644
--- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
@@ -134,8 +134,7 @@
 		mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_BOOTP_FCFG, val);
 
 		/* save MC context to TZDRAM */
-		mc_ctx_base = params_from_bl2->tzdram_base +
-				tegra186_get_mc_ctx_offset();
+		mc_ctx_base = params_from_bl2->tzdram_base;
 		tegra_mc_save_context((uintptr_t)mc_ctx_base);
 
 		/* Prepare for system suspend */
@@ -286,7 +285,7 @@
 
 	if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
 		val = params_from_bl2->tzdram_base +
-		      tegra186_get_cpu_reset_handler_size();
+			tegra186_get_mc_ctx_size();
 
 		/* Initialise communication channel with BPMP */
 		assert(tegra_bpmp_ipc_init() == 0);
@@ -313,10 +312,19 @@
 		 * BL3-1 over to TZDRAM.
 		 */
 		val = params_from_bl2->tzdram_base +
-			tegra186_get_cpu_reset_handler_size();
+			tegra186_get_mc_ctx_size();
 		memcpy16((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE,
 			 (uintptr_t)BL31_END - (uintptr_t)BL31_BASE);
 
+		/*
+		 * Save code base and size; this would be used by SC7-RF to
+		 * verify binary
+		 */
+		mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV68_LO,
+				(uint32_t)val);
+		mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV0_HI,
+				(uint32_t)src_len_in_bytes);
+
 		ret = tegra_bpmp_ipc_disable_clock(TEGRA186_CLK_SE);
 		if (ret != 0) {
 			ERROR("Failed to disable clock\n");
diff --git a/plat/nvidia/tegra/soc/t186/plat_secondary.c b/plat/nvidia/tegra/soc/t186/plat_secondary.c
index 8417374..fbb550a 100644
--- a/plat/nvidia/tegra/soc/t186/plat_secondary.c
+++ b/plat/nvidia/tegra/soc/t186/plat_secondary.c
@@ -12,7 +12,6 @@
 #include <lib/mmio.h>
 
 #include <mce.h>
-#include <tegra186_private.h>
 #include <tegra_def.h>
 #include <tegra_private.h>
 
@@ -21,33 +20,18 @@
 
 #define CPU_RESET_MODE_AA64		1U
 
-extern void memcpy16(void *dest, const void *src, unsigned int length);
-
 /*******************************************************************************
  * Setup secondary CPU vectors
  ******************************************************************************/
 void plat_secondary_setup(void)
 {
 	uint32_t addr_low, addr_high;
-	const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
-	uint64_t cpu_reset_handler_base, cpu_reset_handler_size;
 
 	INFO("Setting up secondary CPU boot\n");
 
-	/*
-	 * The BL31 code resides in the TZSRAM which loses state
-	 * when we enter System Suspend. Copy the wakeup trampoline
-	 * code to TZDRAM to help us exit from System Suspend.
-	 */
-	cpu_reset_handler_base = tegra186_get_cpu_reset_handler_base();
-	cpu_reset_handler_size = tegra186_get_cpu_reset_handler_size();
-	(void)memcpy16((void *)(uintptr_t)params_from_bl2->tzdram_base,
-			(const void *)(uintptr_t)cpu_reset_handler_base,
-			cpu_reset_handler_size);
-
 	/* TZDRAM base will be used as the "resume" address */
-	addr_low = (uint32_t)params_from_bl2->tzdram_base | CPU_RESET_MODE_AA64;
-	addr_high = (uint32_t)((params_from_bl2->tzdram_base >> 32U) & 0x7ffU);
+	addr_low = (uintptr_t)&tegra_secure_entrypoint | CPU_RESET_MODE_AA64;
+	addr_high = (uintptr_t)(((uintptr_t)&tegra_secure_entrypoint >> 32U) & 0x7ffU);
 
 	/* save reset vector to be used during SYSTEM_SUSPEND exit */
 	mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO,
diff --git a/plat/nvidia/tegra/soc/t186/plat_trampoline.S b/plat/nvidia/tegra/soc/t186/plat_trampoline.S
index adb39f5..2fc2046 100644
--- a/plat/nvidia/tegra/soc/t186/plat_trampoline.S
+++ b/plat/nvidia/tegra/soc/t186/plat_trampoline.S
@@ -14,93 +14,28 @@
 
 #define TEGRA186_MC_CTX_SIZE		0x93
 
-	.globl	tegra186_cpu_reset_handler
-
-/* CPU reset handler routine */
-func tegra186_cpu_reset_handler _align=4
-	/* prepare to relocate to TZSRAM */
-	mov	x0, #BL31_BASE
-	adr	x1, __tegra186_cpu_reset_handler_end
-	adr	x2, __tegra186_cpu_reset_handler_data
-	ldr	x2, [x2, #8]
-
-	/* memcpy16 */
-m_loop16:
-	cmp	x2, #16
-	b.lt	m_loop1
-	ldp	x3, x4, [x1], #16
-	stp	x3, x4, [x0], #16
-	sub	x2, x2, #16
-	b	m_loop16
-	/* copy byte per byte */
-m_loop1:
-	cbz	x2, boot_cpu
-	ldrb	w3, [x1], #1
-	strb	w3, [x0], #1
-	subs	x2, x2, #1
-	b.ne	m_loop1
-
-boot_cpu:
-	adr	x0, __tegra186_cpu_reset_handler_data
-	ldr	x0, [x0]
-	br	x0
-endfunc tegra186_cpu_reset_handler
+	.globl tegra186_get_mc_ctx_size
 
 	/*
-	 * Tegra186 reset data (offset 0x0 - 0x430)
+	 * Tegra186 reset data (offset 0x0 - 0x420)
 	 *
-	 * 0x000: secure world's entrypoint
-	 * 0x008: BL31 size (RO + RW)
-	 * 0x00C: MC context start
-	 * 0x42C: MC context end
+	 * 0x000: MC context start
+	 * 0x420: MC context end
 	 */
 
 	.align 4
-	.type	__tegra186_cpu_reset_handler_data, %object
-	.globl	__tegra186_cpu_reset_handler_data
-__tegra186_cpu_reset_handler_data:
-	.quad	tegra_secure_entrypoint
-	.quad	__BL31_END__ - BL31_BASE
-
-	.globl	__tegra186_system_suspend_state
-__tegra186_system_suspend_state:
-	.quad	0
-
-	.align 4
-	.globl	__tegra186_mc_context
 __tegra186_mc_context:
 	.rept	TEGRA186_MC_CTX_SIZE
 	.quad	0
 	.endr
-	.size	__tegra186_cpu_reset_handler_data, \
-		. - __tegra186_cpu_reset_handler_data
 
 	.align 4
-	.globl	__tegra186_cpu_reset_handler_end
-__tegra186_cpu_reset_handler_end:
-
-	.globl tegra186_get_cpu_reset_handler_size
-	.globl tegra186_get_cpu_reset_handler_base
-	.globl tegra186_get_mc_ctx_offset
-
-/* return size of the CPU reset handler */
-func tegra186_get_cpu_reset_handler_size
-	adr	x0, __tegra186_cpu_reset_handler_end
-	adr	x1, tegra186_cpu_reset_handler
-	sub	x0, x0, x1
-	ret
-endfunc tegra186_get_cpu_reset_handler_size
-
-/* return the start address of the CPU reset handler */
-func tegra186_get_cpu_reset_handler_base
-	adr	x0, tegra186_cpu_reset_handler
-	ret
-endfunc tegra186_get_cpu_reset_handler_base
+__tegra186_mc_context_end:
 
 /* return the size of the MC context */
-func tegra186_get_mc_ctx_offset
-	adr	x0, __tegra186_mc_context
-	adr	x1, tegra186_cpu_reset_handler
+func tegra186_get_mc_ctx_size
+	adr	x0, __tegra186_mc_context_end
+	adr	x1, __tegra186_mc_context
 	sub	x0, x0, x1
 	ret
-endfunc tegra186_get_mc_ctx_offset
+endfunc tegra186_get_mc_ctx_size