Tegra186: system resume from TZSRAM memory
TZSRAM loses power during System suspend, so the entire contents
are copied to TZDRAM before Sysem Suspend entry. The warmboot code
verifies and restores the contents to TZSRAM during System Resume.
This patch removes the code that sets up CPU vector to point to
TZSRAM during System Resume as a result. The trampoline code can
also be completely removed as a result.
Change-Id: I2830eb1db16efef3dfd96c4e3afc41a307588ca1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/plat/nvidia/tegra/soc/t186/plat_secondary.c b/plat/nvidia/tegra/soc/t186/plat_secondary.c
index 8417374..fbb550a 100644
--- a/plat/nvidia/tegra/soc/t186/plat_secondary.c
+++ b/plat/nvidia/tegra/soc/t186/plat_secondary.c
@@ -12,7 +12,6 @@
#include <lib/mmio.h>
#include <mce.h>
-#include <tegra186_private.h>
#include <tegra_def.h>
#include <tegra_private.h>
@@ -21,33 +20,18 @@
#define CPU_RESET_MODE_AA64 1U
-extern void memcpy16(void *dest, const void *src, unsigned int length);
-
/*******************************************************************************
* Setup secondary CPU vectors
******************************************************************************/
void plat_secondary_setup(void)
{
uint32_t addr_low, addr_high;
- const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
- uint64_t cpu_reset_handler_base, cpu_reset_handler_size;
INFO("Setting up secondary CPU boot\n");
- /*
- * The BL31 code resides in the TZSRAM which loses state
- * when we enter System Suspend. Copy the wakeup trampoline
- * code to TZDRAM to help us exit from System Suspend.
- */
- cpu_reset_handler_base = tegra186_get_cpu_reset_handler_base();
- cpu_reset_handler_size = tegra186_get_cpu_reset_handler_size();
- (void)memcpy16((void *)(uintptr_t)params_from_bl2->tzdram_base,
- (const void *)(uintptr_t)cpu_reset_handler_base,
- cpu_reset_handler_size);
-
/* TZDRAM base will be used as the "resume" address */
- addr_low = (uint32_t)params_from_bl2->tzdram_base | CPU_RESET_MODE_AA64;
- addr_high = (uint32_t)((params_from_bl2->tzdram_base >> 32U) & 0x7ffU);
+ addr_low = (uintptr_t)&tegra_secure_entrypoint | CPU_RESET_MODE_AA64;
+ addr_high = (uintptr_t)(((uintptr_t)&tegra_secure_entrypoint >> 32U) & 0x7ffU);
/* save reset vector to be used during SYSTEM_SUSPEND exit */
mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO,