refactor(neoverse-rd): clean-up nrd_plat_arm_def1.h file

As the last step of refactoring the platform support of the first
generation of reference design platforms (A75/N1/V1), clean-up the
platform port definitions listed in the nrd_plat_arm_def1.h file.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I73a9b94f1db22192398ea8211109d2e4aaf965e1
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_def1.h
index c890b10..74835f6 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_def1.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_def1.h
@@ -16,6 +16,15 @@
  * CSS memory map related defines
  ******************************************************************************/
 
+/* On-Chip ROM */
+#define NRD_CSS_TRUSTED_ROM_BASE	UL(0x00000000)
+#define NRD_CSS_TRUSTED_ROM_SIZE	UL(0x00080000)	/* 512KB */
+
+/* On-Chip RAM */
+#define	NRD_CSS_TRUSTED_SRAM_SIZE	UL(0x00080000)	/* 512KB */
+#define NRD_CSS_NONTRUSTED_SRAM_BASE	UL(0x06000000)
+#define NRD_CSS_NONTRUSTED_SRAM_SIZE	UL(0x00080000)	/* 512KB */
+
 /* PL011 UART */
 #define NRD_CSS_SEC_UART_BASE		UL(0x2A410000)
 #define NRD_CSS_UART_SIZE		UL(0x10000)
@@ -27,4 +36,8 @@
 /* Secure Watchdog */
 #define NRD_CSS_WDOG_BASE		UL(0x2A480000)
 
+/* DRAM2 */
+#define NRD_CSS_DRAM2_BASE		ULL(0x8080000000)
+#define NRD_CSS_DRAM2_SIZE		ULL(0x180000000)
+
 #endif /* NRD_CSS_DEF1_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h
index 0ee8220..70a7d49 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h
@@ -16,6 +16,14 @@
  * BL sizes
  ******************************************************************************/
 
+#define NRD_CSS_BL1_RW_SIZE		UL(64 * 1024)	/* 64KB */
+
+#if TRUSTED_BOARD_BOOT
+# define NRD_CSS_BL2_SIZE		UL(0x28000)
+#else
+# define NRD_CSS_BL2_SIZE		UL(0x14000)
+#endif
+
 /*
  * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
  * calculated using the current BL31 PROGBITS debug size plus the sizes of BL2
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h
index 0827f98..bca095c 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h
@@ -56,15 +56,15 @@
 # if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)
 #  define PLAT_ARM_MMAP_ENTRIES		(10 + ((NRD_CHIP_COUNT - 1) * 3))
 #  define MAX_XLAT_TABLES		(11 + ((NRD_CHIP_COUNT - 1) * 3))
-#  define PLAT_SP_IMAGE_MMAP_REGIONS	(12)
-#  define PLAT_SP_IMAGE_MAX_XLAT_TABLES	(14)
+#  define PLAT_SP_IMAGE_MMAP_REGIONS	U(12)
+#  define PLAT_SP_IMAGE_MAX_XLAT_TABLES	U(14)
 # else
 #  define PLAT_ARM_MMAP_ENTRIES		(5 + ((NRD_CHIP_COUNT - 1) * 3))
 #  define MAX_XLAT_TABLES		(6 + ((NRD_CHIP_COUNT - 1) * 3))
 # endif
 #elif defined(IMAGE_BL32)
-# define PLAT_ARM_MMAP_ENTRIES		(8)
-# define MAX_XLAT_TABLES		(5)
+# define PLAT_ARM_MMAP_ENTRIES		U(8)
+# define MAX_XLAT_TABLES		U(5)
 #elif defined(IMAGE_BL2)
 # define PLAT_ARM_MMAP_ENTRIES		(11 + (NRD_CHIP_COUNT - 1))
 
@@ -76,11 +76,11 @@
  */
 # define MAX_XLAT_TABLES		(11  + ((NRD_CHIP_COUNT - 1) * 2))
 #elif !USE_ROMLIB
-# define PLAT_ARM_MMAP_ENTRIES		(11)
-# define MAX_XLAT_TABLES		(7)
+# define PLAT_ARM_MMAP_ENTRIES		U(11)
+# define MAX_XLAT_TABLES		U(7)
 #else
-# define PLAT_ARM_MMAP_ENTRIES		(12)
-# define MAX_XLAT_TABLES		(6)
+# define PLAT_ARM_MMAP_ENTRIES		U(12)
+# define MAX_XLAT_TABLES		U(6)
 #endif
 
 /*******************************************************************************
@@ -89,26 +89,26 @@
 
 #if defined(IMAGE_BL1)
 # if TRUSTED_BOARD_BOOT
-#  define PLATFORM_STACK_SIZE		(0x1000)
+#  define PLATFORM_STACK_SIZE		U(0x1000)
 # else
-#  define PLATFORM_STACK_SIZE		(0x440)
+#  define PLATFORM_STACK_SIZE		U(0x440)
 # endif
 #elif defined(IMAGE_BL2)
 # if TRUSTED_BOARD_BOOT
-#  define PLATFORM_STACK_SIZE		(0x1000)
+#  define PLATFORM_STACK_SIZE		U(0x1000)
 # else
-#  define PLATFORM_STACK_SIZE		(0x400)
+#  define PLATFORM_STACK_SIZE		U(0x400)
 # endif
 #elif defined(IMAGE_BL2U)
-# define PLATFORM_STACK_SIZE		(0x400)
+# define PLATFORM_STACK_SIZE		U(0x400)
 #elif defined(IMAGE_BL31)
 # if SPM_MM
-#  define PLATFORM_STACK_SIZE		(0x500)
+#  define PLATFORM_STACK_SIZE		U(0x500)
 # else
-#  define PLATFORM_STACK_SIZE		(0x400)
+#  define PLATFORM_STACK_SIZE		U(0x400)
 # endif
 #elif defined(IMAGE_BL32)
-# define PLATFORM_STACK_SIZE		(0x440)
+# define PLATFORM_STACK_SIZE		U(0x440)
 #endif
 
 #if (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP))
@@ -124,15 +124,16 @@
  * BL sizes
  ******************************************************************************/
 
-#define PLAT_ARM_MAX_BL1_RW_SIZE	(64 * 1024)	/* 64 KB */
 #if USE_ROMLIB
-#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	(0x1000)
-#define PLAT_ARM_MAX_ROMLIB_RO_SIZE	(0xe000)
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	U(0x1000)
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE	U(0xe000)
 #else
-#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	(0)
-#define PLAT_ARM_MAX_ROMLIB_RO_SIZE	(0)
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	U(0)
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE	U(0)
 #endif
 
+#define PLAT_ARM_MAX_BL1_RW_SIZE	NRD_CSS_BL1_RW_SIZE
+
 /*
  * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
  * little space for growth. Additional 8KiB space is added per chip in
@@ -140,13 +141,8 @@
  * peripheral access which lies in >4TB address space.
  *
  */
-#if TRUSTED_BOARD_BOOT
-# define PLAT_ARM_MAX_BL2_SIZE		(0x28000 + ((NRD_CHIP_COUNT - 1) * \
-							0x2000))
-#else
-# define PLAT_ARM_MAX_BL2_SIZE		(0x14000 + ((NRD_CHIP_COUNT - 1) * \
-							0x2000))
-#endif
+#define PLAT_ARM_MAX_BL2_SIZE		(NRD_CSS_BL2_SIZE +		\
+						((NRD_CHIP_COUNT - 1) * 0x2000))
 
 #define PLAT_ARM_MAX_BL31_SIZE		(NRD_CSS_BL31_SIZE +		\
 						PLAT_ARM_MAX_BL2_SIZE +	\
@@ -156,16 +152,16 @@
  * ROM, SRAM and DRAM config
  ******************************************************************************/
 
-#define PLAT_ARM_TRUSTED_SRAM_SIZE	(0x00080000)	/* 512 KB */
+#define PLAT_ARM_TRUSTED_SRAM_SIZE	NRD_CSS_TRUSTED_SRAM_SIZE
 
-#define PLAT_ARM_TRUSTED_ROM_BASE	(0x0)
-#define PLAT_ARM_TRUSTED_ROM_SIZE	(0x00080000)	/* 512KB */
+#define PLAT_ARM_TRUSTED_ROM_BASE	NRD_CSS_TRUSTED_ROM_BASE
+#define PLAT_ARM_TRUSTED_ROM_SIZE	NRD_CSS_TRUSTED_ROM_SIZE
 
-#define PLAT_ARM_NSRAM_BASE		(0x06000000)
-#define PLAT_ARM_NSRAM_SIZE		(0x00080000)	/* 512KB */
+#define PLAT_ARM_NSRAM_BASE		NRD_CSS_NONTRUSTED_SRAM_BASE
+#define PLAT_ARM_NSRAM_SIZE		NRD_CSS_NONTRUSTED_SRAM_SIZE
 
-#define PLAT_ARM_DRAM2_BASE		ULL(0x8080000000)
-#define PLAT_ARM_DRAM2_SIZE		ULL(0x180000000)
+#define PLAT_ARM_DRAM2_BASE		NRD_CSS_DRAM2_BASE
+#define PLAT_ARM_DRAM2_SIZE		NRD_CSS_DRAM2_SIZE
 
 /*******************************************************************************
  * Console config
@@ -204,8 +200,8 @@
 #define PLAT_ARM_MEM_PROT_ADDR		(V2M_FLASH0_BASE + \
 					 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
 /* IO storage framework */
-#define MAX_IO_DEVICES			(3)
-#define MAX_IO_HANDLES			(4)
+#define MAX_IO_DEVICES			U(3)
+#define MAX_IO_HANDLES			U(4)
 
 /*******************************************************************************
  * SCMI config
@@ -229,16 +225,16 @@
 
 #define PLAT_ARM_G1S_IRQ_PROPS(grp)	CSS_G1S_IRQ_PROPS(grp)
 #define PLAT_ARM_G0_IRQ_PROPS(grp)	ARM_G0_IRQ_PROPS(grp)
-#define PLAT_SP_PRI			(0x10)
+#define PLAT_SP_PRI			U(0x10)
 
 /*******************************************************************************
  * Platform type identification macro
  ******************************************************************************/
 
 /* Platform ID related accessors */
-#define BOARD_CSS_PLAT_ID_REG_ID_MASK		0x0f
-#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT		0x0
-#define BOARD_CSS_PLAT_TYPE_EMULATOR		0x02
+#define BOARD_CSS_PLAT_ID_REG_ID_MASK		U(0x0f)
+#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT		U(0x0)
+#define BOARD_CSS_PLAT_TYPE_EMULATOR		U(0x02)
 
 #ifndef __ASSEMBLER__
 #define BOARD_CSS_GET_PLAT_TYPE(addr)					\
@@ -247,6 +243,7 @@
 #endif /* __ASSEMBLER__ */
 
 /* Platform ID address */
-#define BOARD_CSS_PLAT_ID_REG_ADDR		UL(0x7ffe00e0)
+#define BOARD_CSS_PLAT_ID_REG_ADDR		NRD_ROS_PLATFORM_BASE +	\
+						UL(0x00fe00e0)
 
 #endif /* NRD_PLAT_ARM_DEF1_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_def1.h
index 4e5c4cc..b86ab21 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_def1.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_def1.h
@@ -28,4 +28,8 @@
 #define NRD_ROS_NOR2_FLASH_BASE		UL(0x10000000)
 #define NRD_ROS_NOR2_FLASH_SIZE		UL(0x04000000)
 
+/* RoS Platform */
+#define NRD_ROS_PLATFORM_BASE		UL(0x7F000000)
+#define NRD_ROS_PLATFORM_SIZE		UL(0x20000000)
+
 #endif /* NRD_ROS_DEF1_H */