diff --git a/plat/nvidia/tegra/include/t194/tegra_mc_def.h b/plat/nvidia/tegra/include/t194/tegra_mc_def.h
index 6911ba1..34bdd75 100644
--- a/plat/nvidia/tegra/include/t194/tegra_mc_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_mc_def.h
@@ -660,6 +660,10 @@
 #define TSA_CONFIG_CSW_SO_DEV_HUBID_MASK			(ULL(0x3) << 15)
 #define TSA_CONFIG_CSW_SO_DEV_HUB2				(ULL(2) << 15)
 
+#define REORDER_DEPTH_LIMIT					16
+#define TSA_CONFIG_CSW_REORDER_DEPTH_LIMIT_MASK			(ULL(0x7FF) << 21)
+#define reorder_depth_limit(limit)				(ULL(limit) << 21)
+
 #define tsa_read_32(client) \
 		mmio_read_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client)
 
@@ -670,4 +674,12 @@
 		TSA_CONFIG_CSW_SO_DEV_HUB2)); \
 	}
 
+#define mc_set_tsa_depth_limit(limit, client) \
+	{ \
+		uint32_t val = mmio_read_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client); \
+		mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \
+		((val & ~TSA_CONFIG_CSW_REORDER_DEPTH_LIMIT_MASK) | \
+		reorder_depth_limit(limit))); \
+	}
+
 #endif /* TEGRA_MC_DEF_H */
diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c
index 78e6527..3ec07f2 100644
--- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c
+++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c
@@ -384,6 +384,18 @@
 	reg_val = tsa_read_32(XUSB_HOSTW);
 	mc_set_tsa_hub2(reg_val, XUSB_HOSTW);
 
+	/*
+	 * Hw Bug: 200385660, 200394107
+	 * PCIE datapath hangs when there are more than 28 outstanding
+	 * requests on data backbone for x1 controller. This is seen
+	 * on third party PCIE IP, C1 - PCIE1W, C2 - PCIE2AW and C3 - PCIE3W.
+	 *
+	 * Setting Reorder depth limit, 16 which is < 28.
+	 */
+	mc_set_tsa_depth_limit(REORDER_DEPTH_LIMIT, PCIE1W);
+	mc_set_tsa_depth_limit(REORDER_DEPTH_LIMIT, PCIE2AW);
+	mc_set_tsa_depth_limit(REORDER_DEPTH_LIMIT, PCIE3W);
+
 	/* Ordered MC Clients on Xavier are EQOS, SATA, XUSB, PCIe1 and PCIe3
 	 * ISO clients(DISP, VI, EQOS) should never snoop caches and
 	 *     don't need ROC/PCFIFO ordering.