Optimize barrier usage during Cortex-A57 power down
This the patch replaces the DSB SY with DSB ISH
after disabling L2 prefetches during the Cortex-A57
power down sequence.
Change-Id: I048d12d830c1b974b161224eff079fb9f8ecf52d
diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S
index e777497..c2e11bd 100644
--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S
@@ -57,7 +57,7 @@
bic x0, x0, x1
msr CPUECTLR_EL1, x0
isb
- dsb sy
+ dsb ish
ret
/* ---------------------------------------------