commit 1604fa0dfdbe4d67612e92e22c4c71e1bfd4b24a
author Soby Mathew <soby.mathew@arm.com> Mon Sep 22 12:15:26 2014 +0100
committer Soby Mathew <soby.mathew@arm.com> Wed Oct 29 17:38:56 2014 +0000
tree 8fd89f21b24dfb9a0b6c00c0aa137547d50cfcd5
parent c088433267a0f97a363160b357a718692a90537f

Optimize barrier usage during Cortex-A57 power down

This the patch replaces the DSB SY with DSB ISH
after disabling L2 prefetches during the Cortex-A57
power down sequence.

Change-Id: I048d12d830c1b974b161224eff079fb9f8ecf52d

lib/cpus/aarch64/cortex_a57.S

diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S
index e777497..c2e11bd 100644
--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S
@@ -57,7 +57,7 @@
 	bic	x0, x0, x1
 	msr	CPUECTLR_EL1, x0
 	isb
-	dsb	sy
+	dsb	ish
 	ret
 
 	/* ---------------------------------------------