tree 3dc42777bab82b26acfd73953b1af80f0b7110cf
parent be6fe2f7002b2f07da82353aaf815736d2a7f346
parent 88309be146ead951009514cc83ff6c84b84123da
author Manish V Badarkhe <manish.badarkhe@arm.com> 1709027998 +0100
committer TrustedFirmware Code Review <review@review.trustedfirmware.org> 1709027998 +0100

Merge changes I1415e402,Ia92cc693,I7a42f72e,I6e75659e,I4c6136c5, ... into integration

* changes:
  refactor(tc): correlate secure world addresses with platform_def
  feat(tc): add memory node in the device tree
  feat(tc): pass the DTB address to BL33 in R0
  feat(tc): add arm_ffa node in dts
  chore(tc): add dummy entropy to speed up the Linux boot
  feat(tc): choose the DPU address and irq based on the target
  feat(tc): add SCMI power domain and IOMMU toggles
  refactor(tc): move the FVP RoS to a separate file
  feat(tc): factor in FVP/FPGA differences
  feat(tc): introduce an FPGA subvariant and TC3 CPUs
  feat(tc): add TC3 platform definitions
  refactor(tc): sanitise the device tree
  feat(tc): add PMU entry
  feat(tc): allow booting from DRAM
  chore(tc): remove unused hdlcd
  feat(tc): add firmware update secure partition
  feat(tc): add spmc manifest with trusty sp
  refactor(tc): unify all the spmc manifests
  feat(arm): add trusty_sp_fw_config build option
  fix(tc): do not enable MPMM and Aux AMU counters always
  fix(tc): correct interrupts
  feat(tc): interrupt numbers for `smmu_700`
  feat(tc): enable gpu/dpu scmi power domain and also gpu perf domain