Merge "fix(tc): retain NS timer frame ID for TC2 as 0" into integration
diff --git a/.editorconfig b/.editorconfig
index 12f786d..1b29c88 100644
--- a/.editorconfig
+++ b/.editorconfig
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -70,3 +70,6 @@
# [PEP8] Maximum Line Length
# "Limit all lines to a maximum of 79 characters."
max_line_length = 79
+
+[.git/COMMIT_EDITMSG]
+max_line_length = 72
diff --git a/Makefile b/Makefile
index ea4966d..4f3f261 100644
--- a/Makefile
+++ b/Makefile
@@ -597,19 +597,11 @@
################################################################################
# FEAT_RME
ifeq (${ENABLE_RME},1)
- # RME doesn't support BRBE
- ENABLE_BRBE_FOR_NS := 0
-
# RME doesn't support PIE
ifneq (${ENABLE_PIE},0)
$(error ENABLE_RME does not support PIE)
endif
- # RME doesn't support BRBE
- ifneq (${ENABLE_BRBE_FOR_NS},0)
- $(error ENABLE_RME does not support BRBE.)
- endif
-
# RME requires AARCH64
ifneq (${ARCH},aarch64)
$(error ENABLE_RME requires AArch64)
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S
index e47b082..7423805 100644
--- a/bl31/aarch64/runtime_exceptions.S
+++ b/bl31/aarch64/runtime_exceptions.S
@@ -229,7 +229,6 @@
save_x30
apply_at_speculative_wa
sync_and_handle_pending_serror
- unmask_async_ea
handle_sync_exception
end_vector_entry sync_exception_aarch64
@@ -237,7 +236,6 @@
save_x30
apply_at_speculative_wa
sync_and_handle_pending_serror
- unmask_async_ea
b handle_interrupt_exception
end_vector_entry irq_aarch64
@@ -245,7 +243,6 @@
save_x30
apply_at_speculative_wa
sync_and_handle_pending_serror
- unmask_async_ea
b handle_interrupt_exception
end_vector_entry fiq_aarch64
@@ -258,7 +255,6 @@
save_x30
apply_at_speculative_wa
sync_and_handle_pending_serror
- unmask_async_ea
b handle_lower_el_async_ea
#else
b report_unhandled_exception
@@ -279,7 +275,6 @@
save_x30
apply_at_speculative_wa
sync_and_handle_pending_serror
- unmask_async_ea
handle_sync_exception
end_vector_entry sync_exception_aarch32
@@ -287,7 +282,6 @@
save_x30
apply_at_speculative_wa
sync_and_handle_pending_serror
- unmask_async_ea
b handle_interrupt_exception
end_vector_entry irq_aarch32
@@ -295,7 +289,6 @@
save_x30
apply_at_speculative_wa
sync_and_handle_pending_serror
- unmask_async_ea
b handle_interrupt_exception
end_vector_entry fiq_aarch32
@@ -308,7 +301,6 @@
save_x30
apply_at_speculative_wa
sync_and_handle_pending_serror
- unmask_async_ea
b handle_lower_el_async_ea
#else
b report_unhandled_exception
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 4d08a7f..03526a6 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -49,12 +49,14 @@
:|G|: `laurenw-arm`_
:|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
:|G|: `madhukar-Arm`_
-:|M|: Raghu Krishnamurthy <raghu.ncstate@icloud.com>
+:|M|: Raghu Krishnamurthy <raghuoss@raghushome.com>
:|G|: `raghuncstate`_
:|M|: Manish Badarkhe <manish.badarkhe@arm.com>
:|G|: `ManishVB-Arm`_
:|M|: Yann Gautier <yann.gautier@st.com>
:|G|: `Yann-lms`_
+:|M|: Govindraj Raja <govindraj.raja@arm.com>
+:|G|: `govindraj-arm`_
LTS Maintainers
---------------
@@ -1016,7 +1018,7 @@
:|G|: `sandrine-bailleux-arm`_
:|M|: Joanna Farley <joanna.farley@arm.com>
:|G|: `joannafarley-arm`_
-:|M|: Raghu Krishnamurthy <raghu.ncstate@icloud.com>
+:|M|: Raghu Krishnamurthy <raghuoss@raghushome.com>
:|G|: `raghuncstate`_
:|M|: Varun Wadekar <vwadekar@nvidia.com>
:|G|: `vwadekar`_
@@ -1055,6 +1057,7 @@
.. _divin-raj: https://github.com/divin-raj
.. _etienne-lms: https://github.com/etienne-lms
.. _glneo: https://github.com/glneo
+.. _govindraj-arm: https://github.com/govindraj-arm
.. _gprocopciucnxp: https://github.com/gprocopciucnxp
.. _grandpaul: https://github.com/grandpaul
.. _harrisonmutai-arm: https://github.com/harrisonmutai-arm
diff --git a/fdts/stm32mp25-bl2.dtsi b/fdts/stm32mp25-bl2.dtsi
index e250e3f..e6662d0 100644
--- a/fdts/stm32mp25-bl2.dtsi
+++ b/fdts/stm32mp25-bl2.dtsi
@@ -31,6 +31,7 @@
bl32_extra2_uuid = "8ea87bb1-cfa2-3f4d-85fd-e7bba50220d9";
bl33_uuid = "d6d0eea7-fcea-d54b-9782-9934f234b6e4";
hw_cfg_uuid = "08b8f1d9-c9cf-9349-a962-6fbc6b7265cc";
+ soc_fw_cfg_uuid = "9979814b-0376-fb46-8c8e-8d267f7859e0";
tos_fw_cfg_uuid = "26257c1a-dbc6-7f47-8d96-c4c4b0248021";
nt_fw_cfg_uuid = "28da9815-93e8-7e44-ac66-1aaf801550f9";
};
diff --git a/fdts/stm32mp25-bl31.dtsi b/fdts/stm32mp25-bl31.dtsi
new file mode 100644
index 0000000..fa63f63
--- /dev/null
+++ b/fdts/stm32mp25-bl31.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright (C) 2024, STMicroelectronics - All Rights Reserved
+ */
+
+/ {
+ soc@0 {
+ rifsc@42080000 {
+ /delete-node/ mmc@48220000;
+ /delete-node/ mmc@48230000;
+ };
+ };
+};
diff --git a/fdts/stm32mp25-fw-config.dtsi b/fdts/stm32mp25-fw-config.dtsi
index 102980d..2f83f24 100644
--- a/fdts/stm32mp25-fw-config.dtsi
+++ b/fdts/stm32mp25-fw-config.dtsi
@@ -31,6 +31,10 @@
id = <BL31_IMAGE_ID>;
};
+ soc_fw-config {
+ id = <SOC_FW_CONFIG_ID>;
+ };
+
tos_fw {
id = <BL32_IMAGE_ID>;
};
diff --git a/fdts/stm32mp257f-ev1-ca35tdcid-fw-config.dtsi b/fdts/stm32mp257f-ev1-ca35tdcid-fw-config.dtsi
index e41c6b9..5bfcf8d 100644
--- a/fdts/stm32mp257f-ev1-ca35tdcid-fw-config.dtsi
+++ b/fdts/stm32mp257f-ev1-ca35tdcid-fw-config.dtsi
@@ -11,6 +11,10 @@
/ {
dtb-registry {
+ soc_fw-config {
+ load-address = <0x0 0x81ff0000>;
+ max-size = <0x10000>;
+ };
tos_fw {
load-address = <0x0 0x82000000>;
max-size = <0x2000000>;
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 8145616..6a19822 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -633,6 +633,8 @@
/* MDCR_EL3 definitions */
#define MDCR_EBWE_BIT (ULL(1) << 43)
+#define MDCR_E3BREC (ULL(1) << 38)
+#define MDCR_E3BREW (ULL(1) << 37)
#define MDCR_EnPMSN_BIT (ULL(1) << 36)
#define MDCR_MPMX_BIT (ULL(1) << 35)
#define MDCR_MCCD_BIT (ULL(1) << 34)
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index 60c5a0c..1666e3b 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S
@@ -59,24 +59,18 @@
* zero here but are updated ahead of transitioning to a lower EL in the
* function cm_init_context_common().
*
- * SCR_EL3.SIF: Set to one to disable instruction fetches from
- * Non-secure memory.
- *
- * SCR_EL3.EA: Set to one to route External Aborts and SError Interrupts
- * to EL3 when executing at any EL.
- *
* SCR_EL3.EEL2: Set to one if S-EL2 is present and enabled.
*
* NOTE: Modifying EEL2 bit along with EA bit ensures that we mitigate
* against ERRATA_V2_3099206.
* ---------------------------------------------------------------------
*/
- mov_imm x0, (SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT)
+ mov_imm x0, SCR_RESET_VAL
#if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2
- mrs x1, id_aa64pfr0_el1
- and x1, x1, #(ID_AA64PFR0_SEL2_MASK << ID_AA64PFR0_SEL2_SHIFT)
- cbz x1, 1f
- orr x0, x0, #SCR_EEL2_BIT
+ mrs x1, id_aa64pfr0_el1
+ and x1, x1, #(ID_AA64PFR0_SEL2_MASK << ID_AA64PFR0_SEL2_SHIFT)
+ cbz x1, 1f
+ orr x0, x0, #SCR_EEL2_BIT
#endif
1:
msr scr_el3, x0
@@ -84,22 +78,11 @@
/* ---------------------------------------------------------------------
* Initialise MDCR_EL3, setting all fields rather than relying on hw.
* Some fields are architecturally UNKNOWN on reset.
- *
- * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug.
- * Debug exceptions, other than Breakpoint Instruction exceptions, are
- * disabled from all ELs in Secure state.
*/
- mov_imm x0, (MDCR_EL3_RESET_VAL | MDCR_SDD_BIT)
+ mov_imm x0, MDCR_EL3_RESET_VAL
msr mdcr_el3, x0
/* ---------------------------------------------------------------------
- * Enable External Aborts and SError Interrupts now that the exception
- * vectors have been setup.
- * ---------------------------------------------------------------------
- */
- msr daifclr, #DAIF_ABT_BIT
-
- /* ---------------------------------------------------------------------
* Initialise CPTR_EL3, setting all fields rather than relying on hw.
* All fields are architecturally UNKNOWN on reset.
* ---------------------------------------------------------------------
@@ -107,28 +90,6 @@
mov_imm x0, CPTR_EL3_RESET_VAL
msr cptr_el3, x0
- /*
- * If Data Independent Timing (DIT) functionality is implemented,
- * always enable DIT in EL3.
- * First assert that the FEAT_DIT build flag matches the feature id
- * register value for DIT.
- */
-#if ENABLE_FEAT_DIT
-#if ENABLE_ASSERTIONS || ENABLE_FEAT_DIT > 1
- mrs x0, id_aa64pfr0_el1
- ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH
-#if ENABLE_FEAT_DIT > 1
- cbz x0, 1f
-#else
- cmp x0, #DIT_IMPLEMENTED
- ASM_ASSERT(eq)
-#endif
-
-#endif /* ENABLE_ASSERTIONS */
- mov x0, #DIT_BIT
- msr DIT, x0
-1:
-#endif
.endm
/* -----------------------------------------------------------------------------
@@ -270,6 +231,12 @@
el3_arch_init_common
+ /* ---------------------------------------------------------------------
+ * Set the el3 execution context(i.e. root_context).
+ * ---------------------------------------------------------------------
+ */
+ setup_el3_execution_context
+
.if \_secondary_cold_boot
/* -------------------------------------------------------------
* Check if this is a primary or secondary CPU cold boot.
@@ -460,4 +427,68 @@
end:
.endm
+/*-----------------------------------------------------------------------------
+ * Helper macro to configure EL3 registers we care about, while executing
+ * at EL3/Root world. Root world has its own execution environment and
+ * needs to have its settings configured to be independent of other worlds.
+ * -----------------------------------------------------------------------------
+ */
+ .macro setup_el3_execution_context
+
+ /* ---------------------------------------------------------------------
+ * The following registers need to be part of separate root context
+ * as their values are of importance during EL3 execution.
+ * Hence these registers are overwritten to their intital values,
+ * irrespective of whichever world they return from to ensure EL3 has a
+ * consistent execution context throughout the lifetime of TF-A.
+ *
+ * DAIF.A: Enable External Aborts and SError Interrupts at EL3.
+ *
+ * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug.
+ * Debug exceptions, other than Breakpoint Instruction exceptions, are
+ * disabled from all ELs in Secure state.
+ *
+ * SCR_EL3.EA: Set to one to enable SError interrupts at EL3.
+ *
+ * SCR_EL3.SIF: Set to one to disable instruction fetches from
+ * Non-secure memory.
+ *
+ * PMCR_EL0.DP: Set to one so that the cycle counter,
+ * PMCCNTR_EL0 does not count when event counting is prohibited.
+ * Necessary on PMUv3 <= p7 where MDCR_EL3.{SCCD,MCCD} are not
+ * available.
+ *
+ * PSTATE.DIT: Set to one to enable the Data Independent Timing (DIT)
+ * functionality, if implemented in EL3.
+ * ---------------------------------------------------------------------
+ */
+ msr daifclr, #DAIF_ABT_BIT
+
+ mrs x15, mdcr_el3
+ orr x15, x15, #MDCR_SDD_BIT
+ msr mdcr_el3, x15
+
+ mrs x15, scr_el3
+ orr x15, x15, #SCR_EA_BIT
+ orr x15, x15, #SCR_SIF_BIT
+ msr scr_el3, x15
+
+ mrs x15, pmcr_el0
+ orr x15, x15, #PMCR_EL0_DP_BIT
+ msr pmcr_el0, x15
+
+#if ENABLE_FEAT_DIT
+#if ENABLE_FEAT_DIT > 1
+ mrs x15, id_aa64pfr0_el1
+ ubfx x15, x15, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH
+ cbz x15, 1f
+#endif
+ mov x15, #DIT_BIT
+ msr DIT, x15
+ 1:
+#endif
+
+ isb
+ .endm
+
#endif /* EL3_COMMON_MACROS_S */
diff --git a/include/drivers/cadence/cdns_sdmmc.h b/include/drivers/cadence/cdns_sdmmc.h
index 8bf3b78..4be7414 100644
--- a/include/drivers/cadence/cdns_sdmmc.h
+++ b/include/drivers/cadence/cdns_sdmmc.h
@@ -281,7 +281,6 @@
(SDMMC_CDN_##_reg))
/* MMC Peripheral Definition */
-#define SOCFPGA_MMC_BLOCK_SIZE U(8192)
#define SOCFPGA_MMC_BLOCK_MASK (SOCFPGA_MMC_BLOCK_SIZE - U(1))
#define SOCFPGA_MMC_BOOT_CLK_RATE (400 * 1000)
#define MMC_RESPONSE_NONE 0
diff --git a/include/lib/cpus/aarch64/cortex_arcadia.h b/include/lib/cpus/aarch64/cortex_arcadia.h
new file mode 100644
index 0000000..8b74de2
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_arcadia.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_ARCADIA_H
+#define CORTEX_ARCADIA_H
+
+#define CORTEX_ARCADIA_MIDR U(0x410FD8F0)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_ARCADIA_CPUECTLR_EL1 S3_0_C15_C1_4
+#define CORTEX_ARCADIA_CPUECTLR_EL1_EXTLLC_BIT U(0)
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_ARCADIA_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CORTEX_ARCADIA_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+
+#endif /* CORTEX_ARCADIA_H */
diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S
index 98294b9..5e92934 100644
--- a/include/lib/cpus/aarch64/cpu_macros.S
+++ b/include/lib/cpus/aarch64/cpu_macros.S
@@ -433,7 +433,7 @@
*
* _get_rev:
* Optional parameter that determines whether to insert a call to the CPU revision fetching
- * procedure. Stores the result of this in the temporary register x10.
+ * procedure. Stores the result of this in the temporary register x10 to allow for chaining
*
* clobbers: x0-x10 (PCS compliant)
*/
diff --git a/include/lib/el3_runtime/cpu_data.h b/include/lib/el3_runtime/cpu_data.h
index 2c7b619..8b54806 100644
--- a/include/lib/el3_runtime/cpu_data.h
+++ b/include/lib/el3_runtime/cpu_data.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -59,8 +59,19 @@
#define CPU_DATA_CRASH_BUF_END CPU_DATA_CRASH_BUF_OFFSET
#endif
+/* buffer space for EHF data is sizeof(pe_exc_data_t) */
+#define CPU_DATA_EHF_DATA_SIZE 8
+#define CPU_DATA_EHF_DATA_BUF_OFFSET CPU_DATA_CRASH_BUF_END
+
+#if defined(IMAGE_BL31) && EL3_EXCEPTION_HANDLING
+#define CPU_DATA_EHF_DATA_BUF_END (CPU_DATA_EHF_DATA_BUF_OFFSET + \
+ CPU_DATA_EHF_DATA_SIZE)
+#else
+#define CPU_DATA_EHF_DATA_BUF_END CPU_DATA_EHF_DATA_BUF_OFFSET
+#endif /* EL3_EXCEPTION_HANDLING */
+
/* cpu_data size is the data size rounded up to the platform cache line size */
-#define CPU_DATA_SIZE (((CPU_DATA_CRASH_BUF_END + \
+#define CPU_DATA_SIZE (((CPU_DATA_EHF_DATA_BUF_END + \
CACHE_WRITEBACK_GRANULE - 1) / \
CACHE_WRITEBACK_GRANULE) * \
CACHE_WRITEBACK_GRANULE)
@@ -68,7 +79,7 @@
#if ENABLE_RUNTIME_INSTRUMENTATION
/* Temporary space to store PMF timestamps from assembly code */
#define CPU_DATA_PMF_TS_COUNT 1
-#define CPU_DATA_PMF_TS0_OFFSET CPU_DATA_CRASH_BUF_END
+#define CPU_DATA_PMF_TS0_OFFSET CPU_DATA_EHF_DATA_BUF_END
#define CPU_DATA_PMF_TS0_IDX 0
#endif
@@ -159,6 +170,12 @@
assert_cpu_data_crash_stack_offset_mismatch);
#endif
+#if defined(IMAGE_BL31) && EL3_EXCEPTION_HANDLING
+CASSERT(CPU_DATA_EHF_DATA_BUF_OFFSET == __builtin_offsetof
+ (cpu_data_t, ehf_data),
+ assert_cpu_data_ehf_stack_offset_mismatch);
+#endif
+
CASSERT(CPU_DATA_SIZE == sizeof(cpu_data_t),
assert_cpu_data_size_mismatch);
diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S
index 374cc5d..fecb56f 100644
--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S
@@ -57,7 +57,7 @@
msr osdlr_el1, x0
isb
- apply_erratum cortex_a57, ERRATUM(817169), ERRATA_A57_817169
+ apply_erratum cortex_a57, ERRATUM(817169), ERRATA_A57_817169, NO_GET_CPU_REV
dsb sy
ret
diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S
index 4c33dda..b9f6081 100644
--- a/lib/cpus/aarch64/cortex_a710.S
+++ b/lib/cpus/aarch64/cortex_a710.S
@@ -216,7 +216,7 @@
* ----------------------------------------------------
*/
func cortex_a710_core_pwr_dwn
- apply_erratum cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768
+ apply_erratum cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768, NO_GET_CPU_REV
apply_erratum cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219, NO_GET_CPU_REV
/* ---------------------------------------------------
diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S
index 97e036e..017086a 100644
--- a/lib/cpus/aarch64/cortex_a76.S
+++ b/lib/cpus/aarch64/cortex_a76.S
@@ -505,7 +505,7 @@
*/
sysreg_bit_set CORTEX_A76_CPUPWRCTLR_EL1, CORTEX_A76_CORE_PWRDN_EN_MASK
- apply_erratum cortex_a76, ERRATUM(2743102), ERRATA_A76_2743102
+ apply_erratum cortex_a76, ERRATUM(2743102), ERRATA_A76_2743102, NO_GET_CPU_REV
isb
ret
diff --git a/lib/cpus/aarch64/cortex_a77.S b/lib/cpus/aarch64/cortex_a77.S
index d1fc41a..f53b646 100644
--- a/lib/cpus/aarch64/cortex_a77.S
+++ b/lib/cpus/aarch64/cortex_a77.S
@@ -161,7 +161,7 @@
sysreg_bit_set CORTEX_A77_CPUPWRCTLR_EL1, \
CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- apply_erratum cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100
+ apply_erratum cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100, NO_GET_CPU_REV
isb
ret
diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S
index 5a63e78..1de570a 100644
--- a/lib/cpus/aarch64/cortex_a78.S
+++ b/lib/cpus/aarch64/cortex_a78.S
@@ -192,7 +192,7 @@
func cortex_a78_core_pwr_dwn
sysreg_bit_set CORTEX_A78_CPUPWRCTLR_EL1, CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
- apply_erratum cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019
+ apply_erratum cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019, NO_GET_CPU_REV
isb
ret
diff --git a/lib/cpus/aarch64/cortex_a78c.S b/lib/cpus/aarch64/cortex_a78c.S
index 97d5743..260cc73 100644
--- a/lib/cpus/aarch64/cortex_a78c.S
+++ b/lib/cpus/aarch64/cortex_a78c.S
@@ -132,7 +132,7 @@
*/
sysreg_bit_set CORTEX_A78C_CPUPWRCTLR_EL1, CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
- apply_erratum cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121
+ apply_erratum cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121, NO_GET_CPU_REV
isb
ret
diff --git a/lib/cpus/aarch64/cortex_arcadia.S b/lib/cpus/aarch64/cortex_arcadia.S
new file mode 100644
index 0000000..c97d87d
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_arcadia.S
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_arcadia.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Cortex-ARCADIA must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Cortex-ARCADIA supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+cpu_reset_func_start cortex_arcadia
+ /* Disable speculative loads */
+ msr SSBS, xzr
+cpu_reset_func_end cortex_arcadia
+
+ /* ----------------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ----------------------------------------------------
+ */
+func cortex_arcadia_core_pwr_dwn
+ /* ---------------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------------
+ */
+ sysreg_bit_set CORTEX_ARCADIA_CPUPWRCTLR_EL1, CORTEX_ARCADIA_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ isb
+ ret
+endfunc cortex_arcadia_core_pwr_dwn
+
+ /* ---------------------------------------------
+ * This function provides Cortex-Arcadia specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ascii and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.cortex_arcadia_regs, "aS"
+cortex_arcadia_regs: /* The ascii list of register names to be reported */
+ .asciz "cpuectlr_el1", ""
+
+func cortex_arcadia_cpu_reg_dump
+ adr x6, cortex_arcadia_regs
+ mrs x8, CORTEX_ARCADIA_CPUECTLR_EL1
+ ret
+endfunc cortex_arcadia_cpu_reg_dump
+
+declare_cpu_ops cortex_arcadia, CORTEX_ARCADIA_MIDR, \
+ cortex_arcadia_reset_func, \
+ cortex_arcadia_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S
index ab0b19d..ac60903 100644
--- a/lib/cpus/aarch64/cortex_x2.S
+++ b/lib/cpus/aarch64/cortex_x2.S
@@ -126,10 +126,10 @@
check_erratum_ls cortex_x2, ERRATUM(2742423), CPU_REV(2, 1)
-workaround_reset_start cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515
+workaround_runtime_start cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515
/* dsb before isb of power down sequence */
dsb sy
-workaround_reset_end cortex_x2, ERRATUM(2768515)
+workaround_runtime_end cortex_x2, ERRATUM(2768515)
check_erratum_ls cortex_x2, ERRATUM(2768515), CPU_REV(2, 1)
@@ -172,12 +172,7 @@
*/
sysreg_bit_set CORTEX_X2_CPUPWRCTLR_EL1, CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
-#if ERRATA_X2_2768515
- mov x15, x30
- bl cpu_get_rev_var
- bl erratum_cortex_x2_2768515_wa
- mov x30, x15
-#endif /* ERRATA_X2_2768515 */
+ apply_erratum cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515, NO_GET_CPU_REV
isb
ret
endfunc cortex_x2_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S
index 248f107..a81c4cf 100644
--- a/lib/cpus/aarch64/cortex_x3.S
+++ b/lib/cpus/aarch64/cortex_x3.S
@@ -114,13 +114,13 @@
* ----------------------------------------------------
*/
func cortex_x3_core_pwr_dwn
- apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909
+ apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909, NO_GET_CPU_REV
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
sysreg_bit_set CORTEX_X3_CPUPWRCTLR_EL1, CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- apply_erratum cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088
+ apply_erratum cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088, NO_GET_CPU_REV
isb
ret
endfunc cortex_x3_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_x4.S b/lib/cpus/aarch64/cortex_x4.S
index 8820de5..320fd90 100644
--- a/lib/cpus/aarch64/cortex_x4.S
+++ b/lib/cpus/aarch64/cortex_x4.S
@@ -111,7 +111,7 @@
*/
sysreg_bit_set CORTEX_X4_CPUPWRCTLR_EL1, CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- apply_erratum cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089
+ apply_erratum cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089, NO_GET_CPU_REV
isb
ret
diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S
index 50e1ae3..f727226 100644
--- a/lib/cpus/aarch64/neoverse_n1.S
+++ b/lib/cpus/aarch64/neoverse_n1.S
@@ -236,7 +236,7 @@
*/
sysreg_bit_set NEOVERSE_N1_CPUPWRCTLR_EL1, NEOVERSE_N1_CORE_PWRDN_EN_MASK
- apply_erratum neoverse_n1, ERRATUM(2743102), ERRATA_N1_2743102
+ apply_erratum neoverse_n1, ERRATUM(2743102), ERRATA_N1_2743102, NO_GET_CPU_REV
isb
ret
diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S
index 7d7cc44..d2237f1 100644
--- a/lib/cpus/aarch64/neoverse_n2.S
+++ b/lib/cpus/aarch64/neoverse_n2.S
@@ -265,8 +265,7 @@
cpu_reset_func_end neoverse_n2
func neoverse_n2_core_pwr_dwn
-
- apply_erratum neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478
+ apply_erratum neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478, NO_GET_CPU_REV
apply_erratum neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639, NO_GET_CPU_REV
/* ---------------------------------------------------
@@ -276,7 +275,7 @@
*/
sysreg_bit_set NEOVERSE_N2_CPUPWRCTLR_EL1, NEOVERSE_N2_CORE_PWRDN_EN_BIT
- apply_erratum neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089
+ apply_erratum neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089, NO_GET_CPU_REV
isb
ret
diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S
index 89299b7..1ec3e94 100644
--- a/lib/cpus/aarch64/neoverse_v1.S
+++ b/lib/cpus/aarch64/neoverse_v1.S
@@ -253,7 +253,7 @@
* ---------------------------------------------
*/
sysreg_bit_set NEOVERSE_V1_CPUPWRCTLR_EL1, NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- apply_erratum neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093
+ apply_erratum neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093, NO_GET_CPU_REV
isb
ret
diff --git a/lib/cpus/aarch64/neoverse_v2.S b/lib/cpus/aarch64/neoverse_v2.S
index d8c32a4..ca66f8d 100644
--- a/lib/cpus/aarch64/neoverse_v2.S
+++ b/lib/cpus/aarch64/neoverse_v2.S
@@ -100,7 +100,7 @@
* ---------------------------------------------------
*/
sysreg_bit_set NEOVERSE_V2_CPUPWRCTLR_EL1, NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372
+ apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372, NO_GET_CPU_REV
isb
ret
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index ab9d4b6..a353a87 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -400,9 +400,6 @@
/* PMUv3 is presumed to be always present */
mrs x9, pmcr_el0
str x9, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0]
- /* Disable cycle counter when event counting is prohibited */
- orr x9, x9, #PMCR_EL0_DP_BIT
- msr pmcr_el0, x9
isb
#if CTX_INCLUDE_PAUTH_REGS
/* ----------------------------------------------------------
@@ -444,12 +441,7 @@
*/
func prepare_el3_entry
save_gp_pmcr_pauth_regs
- enable_serror_at_el3
- /*
- * Set the PSTATE bits not described in the Aarch64.TakeException
- * pseudocode to their default values.
- */
- set_unset_pstate_bits
+ setup_el3_execution_context
ret
endfunc prepare_el3_entry
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 7c84e0e..003cb25 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -775,13 +775,6 @@
*/
trf_enable(ctx);
}
-
- if (is_feat_brbe_supported()) {
- /*
- * Enable FEAT_BRBE for Non-Secure and prohibit for Secure state.
- */
- brbe_enable(ctx);
- }
#endif /* IMAGE_BL31 */
}
@@ -807,6 +800,10 @@
debugv8p9_extended_bp_wp_enable(ctx);
}
+ if (is_feat_brbe_supported()) {
+ brbe_enable(ctx);
+ }
+
pmuv3_enable(ctx);
#endif /* IMAGE_BL31 */
}
diff --git a/lib/extensions/brbe/brbe.c b/lib/extensions/brbe/brbe.c
index dde0266..fef6647 100644
--- a/lib/extensions/brbe/brbe.c
+++ b/lib/extensions/brbe/brbe.c
@@ -16,11 +16,13 @@
/*
* MDCR_EL3.SBRBE = 0b01
- *
* Allows BRBE usage in non-secure world and prohibited in
* secure world.
+ *
+ * MDCR_EL3.{E3BREW, E3BREC} = 0b00
+ * Branch recording at EL3 is disabled
*/
- mdcr_el3_val &= ~(MDCR_SBRBE_MASK << MDCR_SBRBE_SHIFT);
+ mdcr_el3_val &= ~((MDCR_SBRBE_MASK << MDCR_SBRBE_SHIFT) | MDCR_E3BREW | MDCR_E3BREC);
mdcr_el3_val |= (0x1UL << MDCR_SBRBE_SHIFT);
write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
}
diff --git a/lib/psci/aarch64/psci_helpers.S b/lib/psci/aarch64/psci_helpers.S
index 3b77ab2..cca08c1 100644
--- a/lib/psci/aarch64/psci_helpers.S
+++ b/lib/psci/aarch64/psci_helpers.S
@@ -1,11 +1,12 @@
/*
- * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <asm_macros.S>
#include <assert_macros.S>
+#include <cpu_macros.S>
#include <lib/psci/psci.h>
#include <platform_def.h>
@@ -124,9 +125,8 @@
* -----------------------------------------------------------------------
*/
func psci_power_down_wfi
-#if ERRATA_A510_2684597
- bl apply_cpu_pwr_dwn_errata
-#endif
+ apply_erratum cortex_a510, ERRATUM(2684597), ERRATA_A510_2684597
+
dsb sy // ensure write buffer empty
1:
wfi
diff --git a/lib/psci/aarch64/runtime_errata.S b/lib/psci/aarch64/runtime_errata.S
deleted file mode 100644
index 89e3e12..0000000
--- a/lib/psci/aarch64/runtime_errata.S
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <asm_macros.S>
-#include <cortex_a510.h>
-#include <cpu_macros.S>
-
-/*
- * void apply_cpu_pwr_dwn_errata(void);
- *
- * This function applies various CPU errata during power down.
- */
- .globl apply_cpu_pwr_dwn_errata
-func apply_cpu_pwr_dwn_errata
- mov x19, x30
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_A510_2684597
- bl erratum_cortex_a510_2684597_wa
-#endif
-
- ret x19
-endfunc apply_cpu_pwr_dwn_errata
diff --git a/lib/psci/psci_lib.mk b/lib/psci/psci_lib.mk
index c71580f..527ad3a 100644
--- a/lib/psci/psci_lib.mk
+++ b/lib/psci/psci_lib.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -21,8 +21,7 @@
lib/psci/${ARCH}/psci_helpers.S
ifeq (${ARCH}, aarch64)
-PSCI_LIB_SOURCES += lib/el3_runtime/aarch64/context.S \
- lib/psci/aarch64/runtime_errata.S
+PSCI_LIB_SOURCES += lib/el3_runtime/aarch64/context.S
endif
ifeq (${USE_COHERENT_MEM}, 1)
diff --git a/plat/allwinner/sun50i_a64/platform.mk b/plat/allwinner/sun50i_a64/platform.mk
index e3c7c52..cced7f0 100644
--- a/plat/allwinner/sun50i_a64/platform.mk
+++ b/plat/allwinner/sun50i_a64/platform.mk
@@ -4,6 +4,10 @@
# SPDX-License-Identifier: BSD-3-Clause
#
+# To report supported idle states
+# this has to be defined before allwinner-common.mk
+SUNXI_AMEND_DTB := 1
+
# The differences between the platform are covered by the include files.
include plat/allwinner/common/allwinner-common.mk
diff --git a/plat/allwinner/sun50i_a64/platform_defaults.mk b/plat/allwinner/sun50i_a64/platform_defaults.mk
new file mode 100644
index 0000000..5b61029
--- /dev/null
+++ b/plat/allwinner/sun50i_a64/platform_defaults.mk
@@ -0,0 +1,9 @@
+#
+# Copyright (c) 2024, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# LTO has to be enabled on this platform due to memory constraints
+ENABLE_LTO := 1
+
diff --git a/plat/amd/versal2/aarch64/common.c b/plat/amd/versal2/aarch64/common.c
index 3ab3dca..5fce01e 100644
--- a/plat/amd/versal2/aarch64/common.c
+++ b/plat/amd/versal2/aarch64/common.c
@@ -31,7 +31,7 @@
MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(IPI_BASE, IPI_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
-#if defined(TRANSFER_LIST)
+#if TRANSFER_LIST
MAP_REGION_FLAT(FW_HANDOFF_BASE, FW_HANDOFF_BASE + FW_HANDOFF_SIZE,
MT_MEMORY | MT_RW | MT_NS),
#endif
diff --git a/plat/amd/versal2/bl31_setup.c b/plat/amd/versal2/bl31_setup.c
index 6c8cf5a..64c356a 100644
--- a/plat/amd/versal2/bl31_setup.c
+++ b/plat/amd/versal2/bl31_setup.c
@@ -27,6 +27,7 @@
#include <plat_fdt.h>
#include <plat_private.h>
#include <plat_startup.h>
+#include <plat_xfer_list.h>
#include <pm_api_sys.h>
#include <pm_client.h>
@@ -80,6 +81,7 @@
(void)arg2;
(void)arg3;
uint32_t uart_clock;
+ int32_t rc;
board_detection();
@@ -145,7 +147,12 @@
SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
- bl31_set_default_config();
+
+ rc = transfer_list_populate_ep_info(&bl32_image_ep_info, &bl33_image_ep_info);
+ if (rc == TL_OPS_NON || rc == TL_OPS_CUS) {
+ NOTICE("BL31: TL not found, using default config\n");
+ bl31_set_default_config();
+ }
long rev_var = cpu_get_rev_var();
@@ -241,10 +248,6 @@
void bl31_plat_arch_setup(void)
{
const mmap_region_t bl_regions[] = {
-#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE))
- MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE,
- MT_MEMORY | MT_RW | MT_NS),
-#endif
MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
MT_MEMORY | MT_RW | MT_SECURE),
MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
diff --git a/plat/amd/versal2/include/platform_def.h b/plat/amd/versal2/include/platform_def.h
index 090fe46..42c9b08 100644
--- a/plat/amd/versal2/include/platform_def.h
+++ b/plat/amd/versal2/include/platform_def.h
@@ -91,7 +91,7 @@
#define PLAT_OCM_BASE U(0xBBF00000)
#define PLAT_OCM_LIMIT U(0xBC000000)
-#if defined(TRANSFER_LIST)
+#if TRANSFER_LIST
/*
* FIXME: This address should come from firmware before TF-A
* Having this to make sure the transfer list functionality works
diff --git a/plat/amd/versal2/platform.mk b/plat/amd/versal2/platform.mk
index e2112e0..3114976 100644
--- a/plat/amd/versal2/platform.mk
+++ b/plat/amd/versal2/platform.mk
@@ -6,6 +6,9 @@
PLAT_PATH := plat/amd/versal2
+override NEED_BL1 := no
+override NEED_BL2 := no
+
# A78 Erratum for SoC
ERRATA_A78_AE_1941500 := 1
ERRATA_A78_AE_1951502 := 1
@@ -28,6 +31,10 @@
override CTX_INCLUDE_AARCH32_REGS := 0
+# Platform to support Dynamic XLAT Table by default
+override PLAT_XLAT_TABLES_DYNAMIC := 1
+$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
+
ifdef MEM_BASE
$(eval $(call add_define,MEM_BASE))
@@ -144,3 +151,9 @@
CORTEX_A78_AE_H_INC := 1
$(eval $(call add_define, CORTEX_A78_AE_H_INC))
endif
+
+# Enable Handoff protocol using transfer lists
+TRANSFER_LIST := 1
+
+include lib/transfer_list/transfer_list.mk
+BL31_SOURCES += plat/xilinx/common/plat_xfer_list.c
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 33e1feb..1ec1943 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -211,10 +211,11 @@
#Build AArch64-only CPUs with no FVP model yet.
ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1)
- FVP_CPU_LIBS += lib/cpus/aarch64/neoverse_n3.S \
+ FVP_CPU_LIBS += lib/cpus/aarch64/neoverse_n3.S \
lib/cpus/aarch64/cortex_gelas.S \
lib/cpus/aarch64/nevis.S \
- lib/cpus/aarch64/travis.S
+ lib/cpus/aarch64/travis.S \
+ lib/cpus/aarch64/cortex_arcadia.S
endif
else
diff --git a/plat/intel/soc/agilex/bl31_plat_setup.c b/plat/intel/soc/agilex/bl31_plat_setup.c
index 6e45158..4c10e7b 100644
--- a/plat/intel/soc/agilex/bl31_plat_setup.c
+++ b/plat/intel/soc/agilex/bl31_plat_setup.c
@@ -1,6 +1,7 @@
/*
* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,12 +14,16 @@
#include <drivers/ti/uart/uart_16550.h>
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables.h>
+#include <plat/common/platform.h>
#include "ccu/ncore_ccu.h"
#include "socfpga_mailbox.h"
#include "socfpga_private.h"
#include "socfpga_sip_svc.h"
+/* Get non-secure SPSR for BL33. Zephyr and Linux */
+uint32_t arm_get_spsr_for_bl33_entry(void);
+
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
@@ -59,9 +64,7 @@
u_register_t arg2, u_register_t arg3)
{
static console_t console;
-
mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY);
-
console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK,
PLAT_BAUDRATE, &console);
/*
@@ -69,6 +72,33 @@
*/
void *from_bl2 = (void *) arg0;
+#if RESET_TO_BL31
+ /* There are no parameters from BL2 if BL31 is a reset vector */
+ assert(from_bl2 == NULL);
+ void *plat_params_from_bl2 = (void *) arg3;
+
+ assert(plat_params_from_bl2 == NULL);
+
+ /* Populate entry point information for BL33 */
+ SET_PARAM_HEAD(&bl33_image_ep_info,
+ PARAM_EP,
+ VERSION_1,
+ 0);
+
+# if ARM_LINUX_KERNEL_AS_BL33
+ /*
+ * According to the file ``Documentation/arm64/booting.txt`` of the
+ * Linux kernel tree, Linux expects the physical address of the device
+ * tree blob (DTB) in x0, while x1-x3 are reserved for future use and
+ * must be 0.
+ */
+ bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE;
+ bl33_image_ep_info.args.arg1 = 0U;
+ bl33_image_ep_info.args.arg2 = 0U;
+ bl33_image_ep_info.args.arg3 = 0U;
+# endif
+
+#else /* RESET_TO_BL31 */
bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
assert(params_from_bl2 != NULL);
@@ -76,28 +106,38 @@
* Copy BL32 (if populated by BL31) and BL33 entry point information.
* They are stored in Secure RAM, in BL31's address space.
*/
-
if (params_from_bl2->h.type == PARAM_BL_PARAMS &&
params_from_bl2->h.version >= VERSION_2) {
-
bl_params_node_t *bl_params = params_from_bl2->head;
-
while (bl_params) {
if (bl_params->image_id == BL33_IMAGE_ID)
bl33_image_ep_info = *bl_params->ep_info;
-
bl_params = bl_params->next_params_info;
}
} else {
struct socfpga_bl31_params *arg_from_bl2 =
(struct socfpga_bl31_params *) from_bl2;
-
assert(arg_from_bl2->h.type == PARAM_BL31);
assert(arg_from_bl2->h.version >= VERSION_1);
-
bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
}
+
+ bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE;
+ bl33_image_ep_info.args.arg1 = 0U;
+ bl33_image_ep_info.args.arg2 = 0U;
+ bl33_image_ep_info.args.arg3 = 0U;
+#endif
+
+ /*
+ * Tell BL31 where the non-trusted software image
+ * is located and the entry state information
+ */
+# if ARM_LINUX_KERNEL_AS_BL33
+ bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
+ bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
+#endif
+
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
}
@@ -172,8 +212,34 @@
#endif
{0}
};
-
setup_page_tables(bl_regions, plat_agilex_mmap);
enable_mmu_el3(0);
}
+/* Get non-secure image entrypoint for BL33. Zephyr and Linux */
+uintptr_t plat_get_ns_image_entrypoint(void)
+{
+#ifdef PRELOADED_BL33_BASE
+ return PRELOADED_BL33_BASE;
+#else
+ return PLAT_NS_IMAGE_OFFSET;
+#endif
+}
+
+/* Get non-secure SPSR for BL33. Zephyr and Linux */
+uint32_t arm_get_spsr_for_bl33_entry(void)
+{
+ unsigned int mode;
+ uint32_t spsr;
+
+ /* Figure out what mode we enter the non-secure world in */
+ mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
+
+ /*
+ * TODO: Consider the possibility of specifying the SPSR in
+ * the FIP ToC and allowing the platform to have a say as
+ * well.
+ */
+ spsr = SPSR_64((uint64_t)mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
+ return spsr;
+}
diff --git a/plat/intel/soc/agilex/include/socfpga_plat_def.h b/plat/intel/soc/agilex/include/socfpga_plat_def.h
index 4e3397f..72ffbe2 100644
--- a/plat/intel/soc/agilex/include/socfpga_plat_def.h
+++ b/plat/intel/soc/agilex/include/socfpga_plat_def.h
@@ -16,6 +16,11 @@
/* Platform Setting */
#define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX
#define BOOT_SOURCE BOOT_SOURCE_SDMMC
+/* 1 = Flush cache, 0 = No cache flush.
+ * Default for Agilex is No cache flush.
+ * For Agilex FP8, set to Flush cache.
+ */
+#define CACHE_FLUSH 0
#define PLAT_PRIMARY_CPU 0
#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
@@ -29,6 +34,13 @@
#define CAD_QSPIDATA_OFST 0xff900000
#define CAD_QSPI_OFFSET 0xff8d2000
+/* SDMMC Setting */
+# if ARM_LINUX_KERNEL_AS_BL33
+#define SOCFPGA_MMC_BLOCK_SIZE U(32768)
+# else
+#define SOCFPGA_MMC_BLOCK_SIZE U(8192)
+# endif
+
/* Register Mapping */
#define SOCFPGA_CCU_NOC_REG_BASE 0xf7000000
#define SOCFPGA_F2SDRAMMGR_REG_BASE U(0xf8024000)
diff --git a/plat/intel/soc/agilex5/include/agilex5_cache.h b/plat/intel/soc/agilex5/include/agilex5_cache.h
index 095d99e..f7801b9 100644
--- a/plat/intel/soc/agilex5/include/agilex5_cache.h
+++ b/plat/intel/soc/agilex5/include/agilex5_cache.h
@@ -8,5 +8,6 @@
#define AGX5_CACHE_H
void invalidate_dcache_all(void);
+void invalidate_cache_low_el(void);
#endif /* AGX5_CACHE_H */
diff --git a/plat/intel/soc/agilex5/include/socfpga_plat_def.h b/plat/intel/soc/agilex5/include/socfpga_plat_def.h
index 5789261..ab6e2bc 100644
--- a/plat/intel/soc/agilex5/include/socfpga_plat_def.h
+++ b/plat/intel/soc/agilex5/include/socfpga_plat_def.h
@@ -17,6 +17,10 @@
/* Platform Setting */
#define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX5
#define BOOT_SOURCE BOOT_SOURCE_SDMMC
+/* 1 = Flush cache, 0 = No cache flush.
+ * Default for Agilex5 is Cache flush.
+ */
+#define CACHE_FLUSH 1
#define MMC_DEVICE_TYPE 1 /* MMC = 0, SD = 1 */
#define XLAT_TABLES_V2 U(1)
#define PLAT_PRIMARY_CPU_A55 0x000
@@ -41,6 +45,13 @@
#define CAD_QSPIDATA_OFST 0x10900000
#define CAD_QSPI_OFFSET 0x108d2000
+/* SDMMC Setting */
+# if ARM_LINUX_KERNEL_AS_BL33
+#define SOCFPGA_MMC_BLOCK_SIZE U(32768)
+# else
+#define SOCFPGA_MMC_BLOCK_SIZE U(8192)
+# endif
+
/* Register Mapping */
#define SOCFPGA_CCU_NOC_REG_BASE 0x1c000000
#define SOCFPGA_F2SDRAMMGR_REG_BASE 0x18001000
diff --git a/plat/intel/soc/agilex5/soc/agilex5_cache.S b/plat/intel/soc/agilex5/soc/agilex5_cache.S
index a174386..52ed5d3 100644
--- a/plat/intel/soc/agilex5/soc/agilex5_cache.S
+++ b/plat/intel/soc/agilex5/soc/agilex5_cache.S
@@ -9,6 +9,21 @@
#include <plat_macros.S>
.globl invalidate_dcache_all
+ .globl invalidate_cache_low_el
+ /* --------------------------------------------------------
+ * Invalidate for NS EL2 and EL1
+ * --------------------------------------------------------
+ */
+func invalidate_cache_low_el
+ mrs x0,SCR_EL3
+ orr x1,x0,#SCR_NS_BIT
+ msr SCR_EL3, x1
+ isb
+ tlbi ALLE2
+ dsb sy
+ tlbi ALLE1
+ dsb sy
+endfunc invalidate_cache_low_el
.pushsection .text.asm_dcache_level, "ax"
func asm_dcache_level
diff --git a/plat/intel/soc/common/aarch64/plat_helpers.S b/plat/intel/soc/common/aarch64/plat_helpers.S
index cbd0121..9a17587 100644
--- a/plat/intel/soc/common/aarch64/plat_helpers.S
+++ b/plat/intel/soc/common/aarch64/plat_helpers.S
@@ -1,5 +1,7 @@
/*
* Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/intel/soc/common/drivers/ccu/ncore_ccu.c b/plat/intel/soc/common/drivers/ccu/ncore_ccu.c
index ca76b6a..931ffcf 100644
--- a/plat/intel/soc/common/drivers/ccu/ncore_ccu.c
+++ b/plat/intel/soc/common/drivers/ccu/ncore_ccu.c
@@ -1,10 +1,12 @@
/*
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <common/debug.h>
+#include <drivers/delay_timer.h>
#include <errno.h>
#include <lib/mmio.h>
#include <platform_def.h>
@@ -16,7 +18,24 @@
uint32_t poll_active_bit(uint32_t dir);
-#define SMMU_DMI 1
+#define SMMU_DMI 1
+#define CCU_DMI0_DMIUSMCMCR SOCFPGA_CCU_NOC_REG_BASE + 0x7340
+#define CCU_DMI0_DMIUSMCMAR SOCFPGA_CCU_NOC_REG_BASE + 0x7344
+#define CCU_DMI0_DMIUSMCMCR_MNTOP GENMASK(3, 0)
+#define MAX_DISTRIBUTED_MEM_INTERFACE 2
+#define FLUSH_ALL_ENTRIES 0x4
+#define CCU_DMI0_DMIUSMCMCR_ARRAY_ID GENMASK(21, 16)
+#define ARRAY_ID_TAG 0x0
+#define ARRAY_ID_DATA 0x1
+#define CACHE_OPERATION_DONE BIT(0)
+#define TIMEOUT_200MS 200
+
+#define __bf_shf(x) (__builtin_ffsll(x) - 1)
+
+#define FIELD_PREP(_mask, _val) \
+ ({ \
+ ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \
+ })
#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
ncore_ccu_reg_t ncore_ccu_modules[] = {
@@ -632,3 +651,61 @@
mmio_write_32(SOCFPGA_SYSMGR(TSN_TBU_STREAM_CTRL_REG_3_TSN1), ENABLE_STREAMID);
mmio_write_32(SOCFPGA_SYSMGR(TSN_TBU_STREAM_CTRL_REG_3_TSN2), ENABLE_STREAMID);
}
+
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+/* TODO: Temp added this here*/
+static int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match, uint32_t delay_ms)
+{
+ int time_out = delay_ms;
+
+ while (time_out-- > 0) {
+
+ if ((mmio_read_32(addr) & mask) == match) {
+ return 0;
+ }
+ udelay(1000);
+ }
+
+ return -ETIMEDOUT;
+}
+
+int flush_l3_dcache(void)
+{
+ int i;
+ int ret = 0;
+
+ /* Flushing all entries in CCU system memory cache */
+ for (i = 0; i < MAX_DISTRIBUTED_MEM_INTERFACE; i++) {
+ mmio_write_32(FIELD_PREP(CCU_DMI0_DMIUSMCMCR_MNTOP, FLUSH_ALL_ENTRIES) |
+ FIELD_PREP(CCU_DMI0_DMIUSMCMCR_ARRAY_ID, ARRAY_ID_TAG),
+ (uintptr_t)(CCU_DMI0_DMIUSMCMCR + (i * 0x1000)));
+
+ /* Wait for cache maintenance operation done */
+ ret = poll_idle_status((CCU_DMI0_DMIUSMCMAR +
+ (i * 0x1000)), CACHE_OPERATION_DONE,
+ CACHE_OPERATION_DONE, TIMEOUT_200MS);
+
+ if (ret != 0) {
+ VERBOSE("%s: Timeout while waiting for flushing tag in DMI%d done\n",
+ __func__, i);
+ return ret;
+ }
+
+ mmio_write_32(FIELD_PREP(CCU_DMI0_DMIUSMCMCR_MNTOP, FLUSH_ALL_ENTRIES) |
+ FIELD_PREP(CCU_DMI0_DMIUSMCMCR_ARRAY_ID, ARRAY_ID_DATA),
+ (uintptr_t)(CCU_DMI0_DMIUSMCMCR + (i * 0x1000)));
+
+ /* Wait for cache maintenance operation done */
+ ret = poll_idle_status((CCU_DMI0_DMIUSMCMAR +
+ (i * 0x1000)), CACHE_OPERATION_DONE,
+ CACHE_OPERATION_DONE, TIMEOUT_200MS);
+
+ if (ret != 0) {
+ VERBOSE("%s: Timeout while waiting for flushing data in DMI%d done\n",
+ __func__, i);
+ }
+ }
+
+ return ret;
+}
+#endif
diff --git a/plat/intel/soc/common/drivers/ccu/ncore_ccu.h b/plat/intel/soc/common/drivers/ccu/ncore_ccu.h
index e00c4b7..a89c098 100644
--- a/plat/intel/soc/common/drivers/ccu/ncore_ccu.h
+++ b/plat/intel/soc/common/drivers/ccu/ncore_ccu.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -452,5 +453,6 @@
uint32_t init_ncore_ccu(void);
void ncore_enable_ocram_firewall(void);
void setup_smmu_stream_id(void);
+int flush_l3_dcache(void);
#endif
diff --git a/plat/intel/soc/common/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h
index 1946898..0788ab8 100644
--- a/plat/intel/soc/common/include/platform_def.h
+++ b/plat/intel/soc/common/include/platform_def.h
@@ -1,6 +1,7 @@
/*
* Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -31,7 +32,6 @@
/* Define next boot image name and offset */
/* Get non-secure image entrypoint for BL33. Zephyr and Linux */
#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
-
#ifndef PRELOADED_BL33_BASE
#define PLAT_NS_IMAGE_OFFSET 0x80200000
#else
@@ -40,7 +40,12 @@
#define PLAT_HANDOFF_OFFSET 0x0003F000
#else
+/* Legacy Products. Please refactor with Agilex5 */
+#ifndef PRELOADED_BL33_BASE
#define PLAT_NS_IMAGE_OFFSET 0x10000000
+#else
+#define PLAT_NS_IMAGE_OFFSET PRELOADED_BL33_BASE
+#endif
#define PLAT_HANDOFF_OFFSET 0xFFE3F000
#endif
@@ -48,6 +53,7 @@
#define PLAT_NAND_DATA_BASE (0x0200000)
#define PLAT_SDMMC_DATA_BASE (0x0)
+
/*******************************************************************************
* Platform binary types for linking
******************************************************************************/
diff --git a/plat/intel/soc/common/include/socfpga_private.h b/plat/intel/soc/common/include/socfpga_private.h
index 041c282..a0d4180 100644
--- a/plat/intel/soc/common/include/socfpga_private.h
+++ b/plat/intel/soc/common/include/socfpga_private.h
@@ -1,5 +1,6 @@
/*
- * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
+ * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/intel/soc/common/socfpga_psci.c b/plat/intel/soc/common/socfpga_psci.c
index 623843e..8dc39e2 100644
--- a/plat/intel/soc/common/socfpga_psci.c
+++ b/plat/intel/soc/common/socfpga_psci.c
@@ -17,8 +17,13 @@
#include <lib/mmio.h>
#include <lib/psci/psci.h>
#include <plat/common/platform.h>
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+#include "agilex5_cache.h"
+#endif
+#include "ccu/ncore_ccu.h"
#include "socfpga_mailbox.h"
#include "socfpga_plat_def.h"
+#include "socfpga_private.h"
#include "socfpga_reset_manager.h"
#include "socfpga_sip_svc.h"
#include "socfpga_system_manager.h"
@@ -190,6 +195,14 @@
if (intel_rsu_update_address) {
mailbox_rsu_update(addr_buf);
} else {
+#if CACHE_FLUSH
+ /* ATF Flush and Invalidate Cache */
+ dcsw_op_all(DCCISW);
+ invalidate_cache_low_el();
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ flush_l3_dcache();
+#endif
+#endif
mailbox_reset_cold();
}
diff --git a/plat/intel/soc/common/socfpga_storage.c b/plat/intel/soc/common/socfpga_storage.c
index d250d9e..7679f59 100644
--- a/plat/intel/soc/common/socfpga_storage.c
+++ b/plat/intel/soc/common/socfpga_storage.c
@@ -1,6 +1,7 @@
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,16 +22,21 @@
#include <drivers/partition/partition.h>
#include <lib/mmio.h>
#include <tools_share/firmware_image_package.h>
-
#include "drivers/sdmmc/sdmmc.h"
#include "socfpga_private.h"
#include "socfpga_ros.h"
#define PLAT_FIP_BASE (0)
+# if ARM_LINUX_KERNEL_AS_BL33
+#define PLAT_FIP_MAX_SIZE (0x8000000)
+#define PLAT_MMC_DATA_BASE (0x10000000)
+#define PLAT_MMC_DATA_SIZE (0x100000)
+# else
#define PLAT_FIP_MAX_SIZE (0x1000000)
#define PLAT_MMC_DATA_BASE (0xffe3c000)
#define PLAT_MMC_DATA_SIZE (0x2000)
+# endif
static const io_dev_connector_t *fip_dev_con;
static const io_dev_connector_t *boot_dev_con;
diff --git a/plat/intel/soc/n5x/include/socfpga_plat_def.h b/plat/intel/soc/n5x/include/socfpga_plat_def.h
index 1b662ad..c5e66c7 100644
--- a/plat/intel/soc/n5x/include/socfpga_plat_def.h
+++ b/plat/intel/soc/n5x/include/socfpga_plat_def.h
@@ -29,6 +29,13 @@
#define CAD_QSPIDATA_OFST 0xff900000
#define CAD_QSPI_OFFSET 0xff8d2000
+/* SDMMC Setting */
+# if ARM_LINUX_KERNEL_AS_BL33
+#define SOCFPGA_MMC_BLOCK_SIZE U(32768)
+# else
+#define SOCFPGA_MMC_BLOCK_SIZE U(8192)
+# endif
+
/* Register Mapping */
#define SOCFPGA_CCU_NOC_REG_BASE U(0xf7000000)
#define SOCFPGA_F2SDRAMMGR_REG_BASE U(0xf8024000)
diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
index d4c7dab..cd4c163 100644
--- a/plat/intel/soc/stratix10/include/socfpga_plat_def.h
+++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
@@ -28,6 +28,13 @@
#define CAD_QSPIDATA_OFST 0xff900000
#define CAD_QSPI_OFFSET 0xff8d2000
+/* SDMMC Setting */
+# if ARM_LINUX_KERNEL_AS_BL33
+#define SOCFPGA_MMC_BLOCK_SIZE U(32768)
+# else
+#define SOCFPGA_MMC_BLOCK_SIZE U(8192)
+# endif
+
/* Register Mapping */
#define SOCFPGA_CCU_NOC_REG_BASE 0xf7000000
#define SOCFPGA_F2SDRAMMGR_REG_BASE U(0xf8024000)
diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk
index afcf514..0a33c3d 100644
--- a/plat/intel/soc/stratix10/platform.mk
+++ b/plat/intel/soc/stratix10/platform.mk
@@ -1,6 +1,7 @@
#
# Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
-# Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
+# Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+# Copyright (c) 2024, Altera Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -26,6 +27,7 @@
lib/xlat_tables/xlat_tables_common.c \
plat/intel/soc/common/aarch64/platform_common.c \
plat/intel/soc/common/aarch64/plat_helpers.S \
+ plat/intel/soc/common/drivers/ccu/ncore_ccu.c \
plat/intel/soc/common/socfpga_delay_timer.c \
plat/intel/soc/common/soc/socfpga_firewall.c
diff --git a/plat/st/common/stm32mp_fconf_io.c b/plat/st/common/stm32mp_fconf_io.c
index 1aecece..644275e 100644
--- a/plat/st/common/stm32mp_fconf_io.c
+++ b/plat/st/common/stm32mp_fconf_io.c
@@ -77,7 +77,7 @@
#define DEFAULT_UUID_NUMBER U(7)
#ifdef __aarch64__
-#define BL31_UUID_NUMBER U(1)
+#define BL31_UUID_NUMBER U(2)
#else
#define BL31_UUID_NUMBER U(0)
#endif
@@ -115,6 +115,7 @@
{FW_CONFIG_ID, "fw_cfg_uuid"},
#ifdef __aarch64__
{BL31_IMAGE_ID, "bl31_uuid"},
+ {SOC_FW_CONFIG_ID, "soc_fw_cfg_uuid"},
#endif
{BL32_IMAGE_ID, "bl32_uuid"},
{BL32_EXTRA1_IMAGE_ID, "bl32_extra1_uuid"},
diff --git a/plat/st/stm32mp2/bl2_plat_setup.c b/plat/st/stm32mp2/bl2_plat_setup.c
index 345850b..2fabc41 100644
--- a/plat/st/stm32mp2/bl2_plat_setup.c
+++ b/plat/st/stm32mp2/bl2_plat_setup.c
@@ -280,6 +280,7 @@
unsigned int i;
const unsigned int image_ids[] = {
BL31_IMAGE_ID,
+ SOC_FW_CONFIG_ID,
BL32_IMAGE_ID,
BL33_IMAGE_ID,
HW_CONFIG_ID,
@@ -345,6 +346,7 @@
break;
case HW_CONFIG_ID:
+ case SOC_FW_CONFIG_ID:
break;
default:
diff --git a/plat/st/stm32mp2/bl31_plat_setup.c b/plat/st/stm32mp2/bl31_plat_setup.c
index dbf1371..586bfe8 100644
--- a/plat/st/stm32mp2/bl31_plat_setup.c
+++ b/plat/st/stm32mp2/bl31_plat_setup.c
@@ -8,12 +8,16 @@
#include <stdint.h>
#include <common/bl_common.h>
+#include <drivers/generic_delay_timer.h>
#include <drivers/st/stm32_console.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
#include <platform_def.h>
+static entry_point_info_t bl32_image_ep_info;
+static entry_point_info_t bl33_image_ep_info;
+
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
@@ -31,6 +35,12 @@
BL_CODE_END - BL_CODE_BASE,
MT_CODE | MT_SECURE);
+ /*
+ * Map soc_fw_config device tree with secure property, i.e. default region.
+ * DDR region definitions will be finalized at BL32 level.
+ */
+ mmap_add_region(arg1, arg1, STM32MP_SOC_FW_CONFIG_MAX_SIZE, MT_RO_DATA | MT_SECURE);
+
#if USE_COHERENT_MEM
/* Map coherent memory */
mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
@@ -40,6 +50,20 @@
configure_mmu();
+ ret = dt_open_and_check(arg1);
+ if (ret < 0) {
+ EARLY_ERROR("%s: failed to open DT (%d)\n", __func__, ret);
+ panic();
+ }
+
+ ret = stm32mp2_clk_init();
+ if (ret < 0) {
+ EARLY_ERROR("%s: failed init clocks (%d)\n", __func__, ret);
+ panic();
+ }
+
+ (void)stm32mp_uart_console_setup();
+
/*
* Map upper SYSRAM where bl_params_t are stored in BL2
*/
@@ -60,6 +84,31 @@
bl_params_node_t *bl_params = params_from_bl2->head;
while (bl_params != NULL) {
+ /*
+ * Copy BL33 entry point information.
+ * They are stored in Secure RAM, in BL2's address space.
+ */
+ if (bl_params->image_id == BL33_IMAGE_ID) {
+ bl33_image_ep_info = *bl_params->ep_info;
+ /*
+ * Check if hw_configuration is given to BL32 and
+ * share it to BL33
+ */
+ if (arg2 != 0U) {
+ bl33_image_ep_info.args.arg0 = 0U;
+ bl33_image_ep_info.args.arg1 = 0U;
+ bl33_image_ep_info.args.arg2 = arg2;
+ }
+ }
+
+ if (bl_params->image_id == BL32_IMAGE_ID) {
+ bl32_image_ep_info = *bl_params->ep_info;
+
+ if (arg2 != 0U) {
+ bl32_image_ep_info.args.arg3 = arg2;
+ }
+ }
+
bl_params = bl_params->next_params_info;
}
@@ -73,6 +122,9 @@
void bl31_plat_arch_setup(void)
{
+ generic_delay_timer_init();
+
+ stm32mp_gic_init();
}
void bl31_platform_setup(void)
@@ -81,5 +133,27 @@
entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
{
- return NULL;
+ entry_point_info_t *next_image_info = NULL;
+
+ assert(sec_state_is_valid(type));
+
+ switch (type) {
+ case NON_SECURE:
+ next_image_info = &bl33_image_ep_info;
+ break;
+
+ case SECURE:
+ next_image_info = &bl32_image_ep_info;
+ break;
+
+ default:
+ break;
+ }
+
+ /* None of the next images on ST platforms can have 0x0 as the entrypoint */
+ if ((next_image_info == NULL) || (next_image_info->pc == 0UL)) {
+ return NULL;
+ }
+
+ return next_image_info;
}
diff --git a/plat/st/stm32mp2/plat_bl2_mem_params_desc.c b/plat/st/stm32mp2/plat_bl2_mem_params_desc.c
index ecad0b4..2513180 100644
--- a/plat/st/stm32mp2/plat_bl2_mem_params_desc.c
+++ b/plat/st/stm32mp2/plat_bl2_mem_params_desc.c
@@ -70,6 +70,21 @@
.next_handoff_image_id = BL32_IMAGE_ID,
},
+ /* Fill SoC FW config related information */
+ {
+ .image_id = SOC_FW_CONFIG_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
+ VERSION_2, entry_point_info_t,
+ SECURE | NON_EXECUTABLE),
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+ VERSION_2, image_info_t,
+ IMAGE_ATTRIB_SKIP_LOADING),
+
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+
/* Fill BL32 related information */
{
.image_id = BL32_IMAGE_ID,
diff --git a/plat/st/stm32mp2/platform.mk b/plat/st/stm32mp2/platform.mk
index c12e512..df1cacd 100644
--- a/plat/st/stm32mp2/platform.mk
+++ b/plat/st/stm32mp2/platform.mk
@@ -48,6 +48,8 @@
# Device tree
BL2_DTSI := stm32mp25-bl2.dtsi
FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME)))
+BL31_DTSI := stm32mp25-bl31.dtsi
+FDT_SOURCES += $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl31.dts,$(DTB_FILE_NAME)))
# Macros and rules to build TF binary
STM32_TF_STM32 := $(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME)))
@@ -56,6 +58,7 @@
STM32MP_FW_CONFIG_NAME := $(patsubst %.dtb,%-fw-config.dtb,$(DTB_FILE_NAME))
STM32MP_FW_CONFIG := ${BUILD_PLAT}/fdts/$(STM32MP_FW_CONFIG_NAME)
+STM32MP_SOC_FW_CONFIG := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl31.dtb,$(DTB_FILE_NAME)))
ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1)
STM32MP_DDR_FW_PATH ?= drivers/st/ddr/phy/firmware/bin/stm32mp2
STM32MP_DDR_FW_NAME := ${DDR_TYPE}_pmu_train.bin
@@ -64,6 +67,8 @@
FDT_SOURCES += $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(STM32MP_FW_CONFIG_NAME)))
# Add the FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_FW_CONFIG},--fw-config))
+# Add the SOC_FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_IMG,STM32MP_SOC_FW_CONFIG,--soc-fw-config))
ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1)
# Add the FW_DDR to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_IMG,STM32MP_DDR_FW,--ddr-fw))
@@ -198,4 +203,11 @@
false; \
fi
+# Create DTB file for BL31
+${BUILD_PLAT}/fdts/%-bl31.dts: fdts/%.dts fdts/${BL31_DTSI} | $$(@D)/
+ @echo '#include "$(patsubst fdts/%,%,$<)"' > $@
+ @echo '#include "${BL31_DTSI}"' >> $@
+
+${BUILD_PLAT}/fdts/%-bl31.dtb: ${BUILD_PLAT}/fdts/%-bl31.dts
+
include plat/st/common/common_rules.mk
diff --git a/plat/st/stm32mp2/stm32mp2_def.h b/plat/st/stm32mp2/stm32mp2_def.h
index 73116db..b441502 100644
--- a/plat/st/stm32mp2/stm32mp2_def.h
+++ b/plat/st/stm32mp2/stm32mp2_def.h
@@ -138,7 +138,11 @@
* MAX_MMAP_REGIONS is usually:
* BL stm32mp2_mmap size + mmap regions in *_plat_arch_setup
*/
+#if defined(IMAGE_BL31)
+#define MAX_MMAP_REGIONS 7
+#else
#define MAX_MMAP_REGIONS 6
+#endif
/* DTB initialization value */
#define STM32MP_BL2_DTB_SIZE U(0x00006000) /* 24 KB for DTB */
@@ -166,6 +170,7 @@
#define STM32MP_HW_CONFIG_BASE (STM32MP_BL33_BASE + \
STM32MP_BL33_MAX_SIZE)
#define STM32MP_HW_CONFIG_MAX_SIZE U(0x40000)
+#define STM32MP_SOC_FW_CONFIG_MAX_SIZE U(0x10000) /* 64kB for BL31 DT */
/*******************************************************************************
* STM32MP2 device/io map related constants (used for MMU)
diff --git a/plat/st/stm32mp2/stm32mp2_private.c b/plat/st/stm32mp2/stm32mp2_private.c
index 7ad974f..5be4c5a 100644
--- a/plat/st/stm32mp2/stm32mp2_private.c
+++ b/plat/st/stm32mp2/stm32mp2_private.c
@@ -117,6 +117,33 @@
return CK_BUS_GPIOA + (bank - GPIO_BANK_A);
}
+#if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2)
+/*
+ * UART Management
+ */
+static const uintptr_t stm32mp2_uart_addresses[STM32MP_NB_OF_UART] = {
+ USART1_BASE,
+ USART2_BASE,
+ USART3_BASE,
+ UART4_BASE,
+ UART5_BASE,
+ USART6_BASE,
+ UART7_BASE,
+ UART8_BASE,
+ UART9_BASE,
+};
+
+uintptr_t get_uart_address(uint32_t instance_nb)
+{
+ if ((instance_nb == 0U) ||
+ (instance_nb > STM32MP_NB_OF_UART)) {
+ return 0U;
+ }
+
+ return stm32mp2_uart_addresses[instance_nb - 1U];
+}
+#endif
+
uint32_t stm32mp_get_chip_version(void)
{
static uint32_t rev;
diff --git a/plat/xilinx/common/include/plat_xfer_list.h b/plat/xilinx/common/include/plat_xfer_list.h
new file mode 100644
index 0000000..cc79a2c
--- /dev/null
+++ b/plat/xilinx/common/include/plat_xfer_list.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_XFER_LIST_H
+#define PLAT_XFER_LIST_H
+
+#include <lib/transfer_list.h>
+
+int32_t transfer_list_populate_ep_info(entry_point_info_t *bl32,
+ entry_point_info_t *bl33);
+
+#endif /* PLAT_XFER_LIST_H */
diff --git a/plat/xilinx/common/plat_xfer_list.c b/plat/xilinx/common/plat_xfer_list.c
new file mode 100644
index 0000000..eae7ce4
--- /dev/null
+++ b/plat/xilinx/common/plat_xfer_list.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <stddef.h>
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <lib/transfer_list.h>
+
+/*
+ * FIXME: This address should come from firmware before TF-A runs
+ * Having this to make sure the transfer list functionality works
+ */
+#define FW_HANDOFF_BASE U(0x1200000)
+#define FW_HANDOFF_SIZE U(0x600000)
+
+static struct transfer_list_header *tl_hdr;
+
+int32_t transfer_list_populate_ep_info(entry_point_info_t *bl32,
+ entry_point_info_t *bl33)
+{
+ struct transfer_list_entry *te = NULL;
+ struct entry_point_info *ep;
+ int32_t ret;
+
+ tl_hdr = (struct transfer_list_header *)FW_HANDOFF_BASE;
+ ret = transfer_list_check_header(tl_hdr);
+ if ((ret == TL_OPS_ALL) || (ret == TL_OPS_RO)) {
+ transfer_list_dump(tl_hdr);
+ while ((te = transfer_list_next(tl_hdr, te)) != NULL) {
+ ep = transfer_list_entry_data(te);
+ if (te->tag_id == TL_TAG_EXEC_EP_INFO64) {
+ switch (GET_SECURITY_STATE(ep->h.attr)) {
+ case NON_SECURE:
+ *bl33 = *ep;
+ continue;
+ case SECURE:
+ *bl32 = *ep;
+ continue;
+ default:
+ ERROR("Unrecognized Image Security State %lu\n",
+ GET_SECURITY_STATE(ep->h.attr));
+ ret = TL_OPS_NON;
+ }
+ }
+ }
+ }
+ return ret;
+}