diff --git a/.checkpatch.conf b/.checkpatch.conf
index 2a53961..8b6c70e 100644
--- a/.checkpatch.conf
+++ b/.checkpatch.conf
@@ -43,10 +43,6 @@
 # Commit messages might contain a Gerrit Change-Id.
 --ignore GERRIT_CHANGE_ID
 
-# Do not check the format of commit messages, as Github's merge commits do not
-# observe it.
---ignore GIT_COMMIT_ID
-
 # FILE_PATH_CHANGES reports this kind of message:
 # "added, moved or deleted file(s), does MAINTAINERS need updating?"
 # We do not use this MAINTAINERS file process in TF.
diff --git a/docs/change-log.rst b/docs/change-log.rst
index 71f24fd..4ef3ac1 100644
--- a/docs/change-log.rst
+++ b/docs/change-log.rst
@@ -1626,7 +1626,7 @@
    -  `Power Domain Topology Design`_
 
 -  Applied the new image terminology to the code base and documentation, as
-   described on the `TF-A wiki on GitHub`_.
+   described in the `image terminology document`_.
 
 -  The build system has been reworked to improve readability and facilitate
    adding future extensions.
@@ -2420,7 +2420,7 @@
 
 --------------
 
-*Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.*
 
 .. _SDEI Specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
 .. _PSCI Integration Guide: ./getting_started/psci-lib-integration-guide.rst
@@ -2431,7 +2431,7 @@
 .. _Firmware Design: ./design/firmware-design.rst
 .. _TF-A Reset Design: ./design/reset-design.rst
 .. _Power Domain Topology Design: ./design/psci-pd-tree.rst
-.. _TF-A wiki on GitHub: https://github.com/ARM-software/arm-trusted-firmware/wiki/ARM-Trusted-Firmware-Image-Terminology
+.. _image terminology document: ./getting_started/image-terminology.rst
 .. _Authentication Framework: ./design/auth-framework.rst
 .. _OP-TEE Dispatcher: ./spd/optee-dispatcher.rst
 .. _tf-issue#501: https://github.com/ARM-software/tf-issues/issues/501
diff --git a/docs/components/firmware-update.rst b/docs/components/firmware-update.rst
index d6bb6ce..30bdc24 100644
--- a/docs/components/firmware-update.rst
+++ b/docs/components/firmware-update.rst
@@ -392,11 +392,11 @@
 
 --------------
 
-*Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved.*
 
 .. _Trusted Board Boot: ../design/trusted-board-boot.rst
 .. _Porting Guide: ../getting_started/porting-guide.rst
-.. _here: https://github.com/ARM-software/arm-trusted-firmware/wiki/ARM-Trusted-Firmware-Image-Terminology
+.. _here: ../getting_started/image-terminology.rst
 .. _Authentication Framework Design: ../design/auth-framework.rst
 .. _Universally Unique Identifier: https://tools.ietf.org/rfc/rfc4122.txt
 
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 6b524c2..d3fe89d 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -226,6 +226,35 @@
 -  ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76
    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
 
+For Neoverse N1, the following errata build flags are defined :
+
+-  ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1
+   CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU.
+
+-  ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1
+   CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
+
+-  ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1
+   CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
+
+-  ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1
+   CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
+
+-  ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1
+   CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
+
+-  ``ERRATA_N1_1257314``: This applies errata 1257314 workaround to Neoverse-N1
+   CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
+
+-  ``ERRATA_N1_1262606``: This applies errata 1262606 workaround to Neoverse-N1
+   CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
+
+-  ``ERRATA_N1_1262888``: This applies errata 1262888 workaround to Neoverse-N1
+   CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
+
+-  ``ERRATA_N1_1275112``: This applies errata 1275112 workaround to Neoverse-N1
+   CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
+
 -  ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1
    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
 
diff --git a/docs/plat/fvp_ve.rst b/docs/plat/fvp_ve.rst
index 5253863..6abf9e5 100644
--- a/docs/plat/fvp_ve.rst
+++ b/docs/plat/fvp_ve.rst
@@ -1,12 +1,11 @@
 Arm Versatile Express
 =====================
 
-Versatile Express (VE) family development platform provides an
-ultra fast environment for prototyping arm-v7 System-on-Chip designs.
-VE Fixed Virtual Platforms (FVP) are simulations of Versatile Express boards.
-The platform in arm-trusted-firmware has been verified with Arm Cortex-A5
-and Cortex-A7 VE FVP's. This platform is tested on and only expected to work
-with single core models.
+Versatile Express (VE) family development platform provides an ultra fast
+environment for prototyping Armv7 System-on-Chip designs. VE Fixed Virtual
+Platforms (FVP) are simulations of Versatile Express boards. The platform in
+Trusted Firmware-A has been verified with Arm Cortex-A5 and Cortex-A7 VE FVP's.
+This platform is tested on and only expected to work with single core models.
 
 Boot Sequence
 -------------
@@ -20,7 +19,7 @@
 ~~~~~~~~~~~~~~
 -  `U-boot <https://git.linaro.org/landing-teams/working/arm/u-boot.git>`__
 
--  `arm-trusted-firmware <https://github.com/ARM-software/arm-trusted-firmware>`__
+-  `Trusted Firmware-A <https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git>`__
 
 Build Procedure
 ~~~~~~~~~~~~~~~
@@ -71,7 +70,7 @@
 ~~~~~~~~~~~~~
 
 The following model parameters should be used to boot Linux using the build of
-arm-trusted-firmware-a made using the above make commands:
+Trusted Firmware-A made using the above make commands:
 
   .. code:: shell
 
diff --git a/docs/process/platform-compatibility-policy.rst b/docs/process/platform-compatibility-policy.rst
index 1c80eb5..a11ba38 100644
--- a/docs/process/platform-compatibility-policy.rst
+++ b/docs/process/platform-compatibility-policy.rst
@@ -20,18 +20,19 @@
 the contributor of the change is expected to make good effort to migrate the
 upstream platforms to the new interface.
 
-The `Release information`_ documents the deprecated interfaces and the intended
-release after which it will be removed. When an interface is deprecated, the
-page must be updated to indicate the release after which the interface will be
-removed. This must be at least 1 full release cycle in future. For non-trivial
-interface changes, a `tf-issue`_ should be posted to notify platforms that they
-should migrate away from the deprecated interfaces. Platforms are expected to
-migrate before the removal of the deprecated interface.
+The deprecated interfaces are listed inside `Release information`_ as well as
+the release after which each one will be removed. When an interface is
+deprecated, the page must be updated to indicate the release after which the
+interface will be removed. This must be at least 1 full release cycle in future.
+For non-trivial interface changes, an email should be sent out to the `TF-A
+public mailing list`_ to notify platforms that they should migrate away from the
+deprecated interfaces. Platforms are expected to migrate before the removal of
+the deprecated interface.
 
 --------------
 
-*Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.*
 
 .. _Porting Guide: ../getting_started/porting-guide.rst
-.. _Release information: https://github.com/ARM-software/arm-trusted-firmware/wiki/TF-A-Release-information#removal-of-deprecated-interfaces
-.. _tf-issue: https://github.com/ARM-software/tf-issues/issues
+.. _Release information: ./release-information.rst#removal-of-deprecated-interfaces
+.. _TF-A public mailing list: https://lists.trustedfirmware.org/mailman/listinfo/tf-a
diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h
index b66aeb8..f90aa2e 100644
--- a/include/lib/cpus/aarch64/neoverse_n1.h
+++ b/include/lib/cpus/aarch64/neoverse_n1.h
@@ -30,13 +30,29 @@
  ******************************************************************************/
 #define NEOVERSE_N1_CPUECTLR_EL1	S3_0_C15_C1_4
 
+#define NEOVERSE_N1_WS_THR_L2_MASK	(ULL(3) << 24)
+#define NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT	(ULL(1) << 51)
+
 /*******************************************************************************
  * CPU Auxiliary Control register specific definitions.
  ******************************************************************************/
+#define NEOVERSE_N1_CPUACTLR_EL1	S3_0_C15_C1_0
+
+#define NEOVERSE_N1_CPUACTLR_EL1_BIT_6	(ULL(1) << 6)
+#define NEOVERSE_N1_CPUACTLR_EL1_BIT_13	(ULL(1) << 13)
+
 #define NEOVERSE_N1_CPUACTLR2_EL1	S3_0_C15_C1_1
 
+#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_0		(ULL(1) << 0)
 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2		(ULL(1) << 2)
+#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_11	(ULL(1) << 11)
+#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_15	(ULL(1) << 15)
 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16	(ULL(1) << 16)
+#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59	(ULL(1) << 59)
+
+#define NEOVERSE_N1_CPUACTLR3_EL1	S3_0_C15_C1_2
+
+#define NEOVERSE_N1_CPUACTLR3_EL1_BIT_10	(ULL(1) << 10)
 
 /* Instruction patching registers */
 #define CPUPSELR_EL3	S3_6_C15_C8_0
diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S
index 8afc4a2..b143a2e 100644
--- a/lib/cpus/aarch64/neoverse_n1.S
+++ b/lib/cpus/aarch64/neoverse_n1.S
@@ -43,7 +43,6 @@
 	msr	CPUPMR_EL3, x0
 	ldr	x0, =0x800200071
 	msr	CPUPCR_EL3, x0
-	isb
 1:
 	ret	x17
 endfunc errata_n1_1043202_wa
@@ -69,13 +68,247 @@
 
 	/* Disable speculative loads */
 	msr	SSBS, xzr
-	isb
 
 1:
 	ret
 endfunc neoverse_n1_disable_speculative_loads
 
 /* --------------------------------------------------
+ * Errata Workaround for Neoverse N1 Errata #1073348
+ * This applies to revision r0p0 and r1p0 of Neoverse N1.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_n1_1073348_wa
+	/* Compare x0 against revision r1p0 */
+	mov	x17, x30
+	bl	check_errata_1073348
+	cbz	x0, 1f
+	mrs	x1, NEOVERSE_N1_CPUACTLR_EL1
+	orr	x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6
+	msr	NEOVERSE_N1_CPUACTLR_EL1, x1
+1:
+	ret	x17
+endfunc errata_n1_1073348_wa
+
+func check_errata_1073348
+	/* Applies to r0p0 and r1p0 */
+	mov	x1, #0x10
+	b	cpu_rev_var_ls
+endfunc check_errata_1073348
+
+/* --------------------------------------------------
+ * Errata Workaround for Neoverse N1 Errata #1130799
+ * This applies to revision <=r2p0 of Neoverse N1.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_n1_1130799_wa
+	/* Compare x0 against revision r2p0 */
+	mov	x17, x30
+	bl	check_errata_1130799
+	cbz	x0, 1f
+	mrs	x1, NEOVERSE_N1_CPUACTLR2_EL1
+	orr	x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59
+	msr	NEOVERSE_N1_CPUACTLR2_EL1, x1
+1:
+	ret	x17
+endfunc errata_n1_1130799_wa
+
+func check_errata_1130799
+	/* Applies to <=r2p0 */
+	mov	x1, #0x20
+	b	cpu_rev_var_ls
+endfunc check_errata_1130799
+
+/* --------------------------------------------------
+ * Errata Workaround for Neoverse N1 Errata #1165347
+ * This applies to revision <=r2p0 of Neoverse N1.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_n1_1165347_wa
+	/* Compare x0 against revision r2p0 */
+	mov	x17, x30
+	bl	check_errata_1165347
+	cbz	x0, 1f
+	mrs	x1, NEOVERSE_N1_CPUACTLR2_EL1
+	orr	x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0
+	orr	x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15
+	msr	NEOVERSE_N1_CPUACTLR2_EL1, x1
+1:
+	ret	x17
+endfunc errata_n1_1165347_wa
+
+func check_errata_1165347
+	/* Applies to <=r2p0 */
+	mov	x1, #0x20
+	b	cpu_rev_var_ls
+endfunc check_errata_1165347
+
+/* --------------------------------------------------
+ * Errata Workaround for Neoverse N1 Errata #1207823
+ * This applies to revision <=r2p0 of Neoverse N1.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_n1_1207823_wa
+	/* Compare x0 against revision r2p0 */
+	mov	x17, x30
+	bl	check_errata_1207823
+	cbz	x0, 1f
+	mrs	x1, NEOVERSE_N1_CPUACTLR2_EL1
+	orr	x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11
+	msr	NEOVERSE_N1_CPUACTLR2_EL1, x1
+1:
+	ret	x17
+endfunc errata_n1_1207823_wa
+
+func check_errata_1207823
+	/* Applies to <=r2p0 */
+	mov	x1, #0x20
+	b	cpu_rev_var_ls
+endfunc check_errata_1207823
+
+/* --------------------------------------------------
+ * Errata Workaround for Neoverse N1 Errata #1220197
+ * This applies to revision <=r2p0 of Neoverse N1.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_n1_1220197_wa
+	/* Compare x0 against revision r2p0 */
+	mov	x17, x30
+	bl	check_errata_1220197
+	cbz	x0, 1f
+	mrs	x1, NEOVERSE_N1_CPUECTLR_EL1
+	orr	x1, x1, NEOVERSE_N1_WS_THR_L2_MASK
+	msr	NEOVERSE_N1_CPUECTLR_EL1, x1
+1:
+	ret	x17
+endfunc errata_n1_1220197_wa
+
+func check_errata_1220197
+	/* Applies to <=r2p0 */
+	mov	x1, #0x20
+	b	cpu_rev_var_ls
+endfunc check_errata_1220197
+
+/* --------------------------------------------------
+ * Errata Workaround for Neoverse N1 Errata #1257314
+ * This applies to revision <=r3p0 of Neoverse N1.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_n1_1257314_wa
+	/* Compare x0 against revision r3p0 */
+	mov	x17, x30
+	bl	check_errata_1257314
+	cbz	x0, 1f
+	mrs	x1, NEOVERSE_N1_CPUACTLR3_EL1
+	orr	x1, x1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10
+	msr	NEOVERSE_N1_CPUACTLR3_EL1, x1
+1:
+	ret	x17
+endfunc errata_n1_1257314_wa
+
+func check_errata_1257314
+	/* Applies to <=r3p0 */
+	mov	x1, #0x30
+	b	cpu_rev_var_ls
+endfunc check_errata_1257314
+
+/* --------------------------------------------------
+ * Errata Workaround for Neoverse N1 Errata #1262606
+ * This applies to revision <=r3p0 of Neoverse N1.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_n1_1262606_wa
+	/* Compare x0 against revision r3p0 */
+	mov	x17, x30
+	bl	check_errata_1262606
+	cbz	x0, 1f
+	mrs	x1, NEOVERSE_N1_CPUACTLR_EL1
+	orr	x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
+	msr	NEOVERSE_N1_CPUACTLR_EL1, x1
+1:
+	ret	x17
+endfunc errata_n1_1262606_wa
+
+func check_errata_1262606
+	/* Applies to <=r3p0 */
+	mov	x1, #0x30
+	b	cpu_rev_var_ls
+endfunc check_errata_1262606
+
+/* --------------------------------------------------
+ * Errata Workaround for Neoverse N1 Errata #1262888
+ * This applies to revision <=r3p0 of Neoverse N1.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_n1_1262888_wa
+	/* Compare x0 against revision r3p0 */
+	mov	x17, x30
+	bl	check_errata_1262888
+	cbz	x0, 1f
+	mrs	x1, NEOVERSE_N1_CPUECTLR_EL1
+	orr	x1, x1, NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT
+	msr	NEOVERSE_N1_CPUECTLR_EL1, x1
+1:
+	ret	x17
+endfunc errata_n1_1262888_wa
+
+func check_errata_1262888
+	/* Applies to <=r3p0 */
+	mov	x1, #0x30
+	b	cpu_rev_var_ls
+endfunc check_errata_1262888
+
+/* --------------------------------------------------
+ * Errata Workaround for Neoverse N1 Errata #1275112
+ * This applies to revision <=r3p0 of Neoverse N1.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_n1_1275112_wa
+	/* Compare x0 against revision r3p0 */
+	mov	x17, x30
+	bl	check_errata_1275112
+	cbz	x0, 1f
+	mrs	x1, NEOVERSE_N1_CPUACTLR_EL1
+	orr	x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
+	msr	NEOVERSE_N1_CPUACTLR_EL1, x1
+1:
+	ret	x17
+endfunc errata_n1_1275112_wa
+
+func check_errata_1275112
+	/* Applies to <=r3p0 */
+	mov	x1, #0x30
+	b	cpu_rev_var_ls
+endfunc check_errata_1275112
+
+/* --------------------------------------------------
  * Errata Workaround for Neoverse N1 Erratum 1315703.
  * This applies to revision <= r3p0 of Neoverse N1.
  * Inputs:
@@ -92,7 +325,6 @@
 	mrs	x0, NEOVERSE_N1_CPUACTLR2_EL1
 	orr	x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_16
 	msr	NEOVERSE_N1_CPUACTLR2_EL1, x0
-	isb
 
 1:
 	ret	x17
@@ -123,6 +355,51 @@
 	bl	errata_n1_1043202_wa
 #endif
 
+#if ERRATA_N1_1073348
+	mov	x0, x18
+	bl	errata_n1_1073348_wa
+#endif
+
+#if ERRATA_N1_1130799
+	mov	x0, x18
+	bl	errata_n1_1130799_wa
+#endif
+
+#if ERRATA_N1_1165347
+	mov	x0, x18
+	bl	errata_n1_1165347_wa
+#endif
+
+#if ERRATA_N1_1207823
+	mov	x0, x18
+	bl	errata_n1_1207823_wa
+#endif
+
+#if ERRATA_N1_1220197
+	mov	x0, x18
+	bl	errata_n1_1220197_wa
+#endif
+
+#if ERRATA_N1_1257314
+	mov	x0, x18
+	bl	errata_n1_1257314_wa
+#endif
+
+#if ERRATA_N1_1262606
+	mov	x0, x18
+	bl	errata_n1_1262606_wa
+#endif
+
+#if ERRATA_N1_1262888
+	mov	x0, x18
+	bl	errata_n1_1262888_wa
+#endif
+
+#if ERRATA_N1_1275112
+	mov	x0, x18
+	bl	errata_n1_1275112_wa
+#endif
+
 #if ERRATA_N1_1315703
 	mov	x0, x18
 	bl	errata_n1_1315703_wa
@@ -133,24 +410,22 @@
 	mrs	x0, actlr_el3
 	orr	x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT
 	msr	actlr_el3, x0
-	isb
 
 	/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
 	mrs	x0, actlr_el2
 	orr	x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT
 	msr	actlr_el2, x0
-	isb
 
 	/* Enable group0 counters */
 	mov	x0, #NEOVERSE_N1_AMU_GROUP0_MASK
 	msr	CPUAMCNTENSET_EL0, x0
-	isb
 #endif
 
 #if ERRATA_DSU_936184
 	bl	errata_dsu_936184_wa
 #endif
 
+	isb
 	ret	x19
 endfunc neoverse_n1_reset_func
 
@@ -185,6 +460,15 @@
 	 * checking functions of each errata.
 	 */
 	report_errata ERRATA_N1_1043202, neoverse_n1, 1043202
+	report_errata ERRATA_N1_1073348, neoverse_n1, 1073348
+	report_errata ERRATA_N1_1130799, neoverse_n1, 1130799
+	report_errata ERRATA_N1_1165347, neoverse_n1, 1165347
+	report_errata ERRATA_N1_1207823, neoverse_n1, 1207823
+	report_errata ERRATA_N1_1220197, neoverse_n1, 1220197
+	report_errata ERRATA_N1_1257314, neoverse_n1, 1257314
+	report_errata ERRATA_N1_1262606, neoverse_n1, 1262606
+	report_errata ERRATA_N1_1262888, neoverse_n1, 1262888
+	report_errata ERRATA_N1_1275112, neoverse_n1, 1275112
 	report_errata ERRATA_N1_1315703, neoverse_n1, 1315703
 	report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184
 
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index db45375..2604023 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -238,6 +238,42 @@
 # only to r0p0 and r1p0 of the Neoverse N1 cpu.
 ERRATA_N1_1043202	?=1
 
+# Flag to apply erratum 1073348 workaround during reset. This erratum applies
+# only to revision r0p0 and r1p0 of the Neoverse N1 cpu.
+ERRATA_N1_1073348	?=0
+
+# Flag to apply erratum 1130799 workaround during reset. This erratum applies
+# only to revision <= r2p0 of the Neoverse N1 cpu.
+ERRATA_N1_1130799	?=0
+
+# Flag to apply erratum 1165347 workaround during reset. This erratum applies
+# only to revision <= r2p0 of the Neoverse N1 cpu.
+ERRATA_N1_1165347	?=0
+
+# Flag to apply erratum 1207823 workaround during reset. This erratum applies
+# only to revision <= r2p0 of the Neoverse N1 cpu.
+ERRATA_N1_1207823	?=0
+
+# Flag to apply erratum 1220197 workaround during reset. This erratum applies
+# only to revision <= r2p0 of the Neoverse N1 cpu.
+ERRATA_N1_1220197	?=0
+
+# Flag to apply erratum 1257314 workaround during reset. This erratum applies
+# only to revision <= r3p0 of the Neoverse N1 cpu.
+ERRATA_N1_1257314	?=0
+
+# Flag to apply erratum 1262606 workaround during reset. This erratum applies
+# only to revision <= r3p0 of the Neoverse N1 cpu.
+ERRATA_N1_1262606	?=0
+
+# Flag to apply erratum 1262888 workaround during reset. This erratum applies
+# only to revision <= r3p0 of the Neoverse N1 cpu.
+ERRATA_N1_1262888	?=0
+
+# Flag to apply erratum 1275112 workaround during reset. This erratum applies
+# only to revision <= r3p0 of the Neoverse N1 cpu.
+ERRATA_N1_1275112	?=0
+
 # Flag to apply erratum 1315703 workaround during reset. This erratum applies
 # to revisions before r3p1 of the Neoverse N1 cpu.
 ERRATA_N1_1315703	?=1
@@ -431,6 +467,42 @@
 $(eval $(call assert_boolean,ERRATA_N1_1043202))
 $(eval $(call add_define,ERRATA_N1_1043202))
 
+# Process ERRATA_N1_1073348 flag
+$(eval $(call assert_boolean,ERRATA_N1_1073348))
+$(eval $(call add_define,ERRATA_N1_1073348))
+
+# Process ERRATA_N1_1130799 flag
+$(eval $(call assert_boolean,ERRATA_N1_1130799))
+$(eval $(call add_define,ERRATA_N1_1130799))
+
+# Process ERRATA_N1_1165347 flag
+$(eval $(call assert_boolean,ERRATA_N1_1165347))
+$(eval $(call add_define,ERRATA_N1_1165347))
+
+# Process ERRATA_N1_1207823 flag
+$(eval $(call assert_boolean,ERRATA_N1_1207823))
+$(eval $(call add_define,ERRATA_N1_1207823))
+
+# Process ERRATA_N1_1220197 flag
+$(eval $(call assert_boolean,ERRATA_N1_1220197))
+$(eval $(call add_define,ERRATA_N1_1220197))
+
+# Process ERRATA_N1_1257314 flag
+$(eval $(call assert_boolean,ERRATA_N1_1257314))
+$(eval $(call add_define,ERRATA_N1_1257314))
+
+# Process ERRATA_N1_1262606 flag
+$(eval $(call assert_boolean,ERRATA_N1_1262606))
+$(eval $(call add_define,ERRATA_N1_1262606))
+
+# Process ERRATA_N1_1262888 flag
+$(eval $(call assert_boolean,ERRATA_N1_1262888))
+$(eval $(call add_define,ERRATA_N1_1262888))
+
+# Process ERRATA_N1_1275112 flag
+$(eval $(call assert_boolean,ERRATA_N1_1275112))
+$(eval $(call add_define,ERRATA_N1_1275112))
+
 # Process ERRATA_N1_1315703 flag
 $(eval $(call assert_boolean,ERRATA_N1_1315703))
 $(eval $(call add_define,ERRATA_N1_1315703))
diff --git a/plat/rpi3/rpi3_stack_protector.c b/plat/rpi3/rpi3_stack_protector.c
index 815f731..6f49f61 100644
--- a/plat/rpi3/rpi3_stack_protector.c
+++ b/plat/rpi3/rpi3_stack_protector.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,6 +7,7 @@
 #include <stdint.h>
 
 #include <lib/utils.h>
+#include <lib/utils_def.h>
 
 #include "rpi3_private.h"
 
diff --git a/plat/socionext/uniphier/platform.mk b/plat/socionext/uniphier/platform.mk
index 94c4405..d974584 100644
--- a/plat/socionext/uniphier/platform.mk
+++ b/plat/socionext/uniphier/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -27,8 +27,9 @@
 PLAT_INCLUDES		:=	-I$(PLAT_PATH)/include
 
 # common sources for BL2, BL31 (and BL32 if SPD=tspd)
-PLAT_BL_COMMON_SOURCES	+=	drivers/console/aarch64/console.S	\
+PLAT_BL_COMMON_SOURCES	+=	plat/common/aarch64/crash_console_helpers.S \
 				$(PLAT_PATH)/uniphier_console.S		\
+				$(PLAT_PATH)/uniphier_console_setup.c	\
 				$(PLAT_PATH)/uniphier_helpers.S		\
 				$(PLAT_PATH)/uniphier_soc_info.c	\
 				$(PLAT_PATH)/uniphier_xlat_setup.c	\
diff --git a/plat/socionext/uniphier/uniphier_bl31_setup.c b/plat/socionext/uniphier/uniphier_bl31_setup.c
index ce32d89..bf78a14 100644
--- a/plat/socionext/uniphier/uniphier_bl31_setup.c
+++ b/plat/socionext/uniphier/uniphier_bl31_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -84,11 +84,3 @@
 	uniphier_mmap_setup(BL31_BASE, BL31_SIZE, NULL);
 	enable_mmu_el3(0);
 }
-
-void bl31_plat_runtime_setup(void)
-{
-	/* Suppress any runtime logs unless DEBUG is defined */
-#if !DEBUG
-	console_uninit();
-#endif
-}
diff --git a/plat/socionext/uniphier/uniphier_console.S b/plat/socionext/uniphier/uniphier_console.S
index 03aff48..2c8dc8f 100644
--- a/plat/socionext/uniphier/uniphier_console.S
+++ b/plat/socionext/uniphier/uniphier_console.S
@@ -1,81 +1,23 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <asm_macros.S>
+#include <drivers/console.h>
 
-#define UNIPHIER_UART_BASE	0x54006800
-#define UNIPHIER_UART_END	0x54006c00
-#define UNIPHIER_UART_OFFSET	0x100
-
-#define UNIPHIER_UART_RX	0x00	/* In:  Receive buffer */
-#define UNIPHIER_UART_TX	0x00	/* Out: Transmit buffer */
-
-#define UNIPHIER_UART_FCR	0x0c	/* Char/FIFO Control Register */
-#define   UNIPHIER_UART_FCR_ENABLE_FIFO	0x01	/* Enable the FIFO */
-
-#define UNIPHIER_UART_LCR_MCR	0x10	/* Line/Modem Control Register */
-#define   UNIPHIER_UART_LCR_WLEN8	0x03	/* Wordlength: 8 bits */
-#define UNIPHIER_UART_LSR	0x14	/* Line Status Register */
-#define   UNIPHIER_UART_LSR_TEMT_BIT	6	/* Transmitter empty */
-#define   UNIPHIER_UART_LSR_THRE_BIT	5	/* Transmit-hold-register empty */
-#define   UNIPHIER_UART_LSR_DR_BIT	0	/* Receiver data ready */
-#define UNIPHIER_UART_DLR	0x24	/* Divisor Latch Register */
+#include "uniphier_console.h"
 
 /*
- * Uncomment for debug
- */
-/* #define UNIPHIER_UART_INIT_DIVISOR */
-#define UNIPHIER_UART_DEFAULT_BASE	(UNIPHIER_UART_BASE)
-#define UNIPHIER_UART_CLK_RATE		58820000
-#define UNIPHIER_UART_DEFAULT_BAUDRATE	115200
-
-/*
- * In: x0 - console base address
- *     w1 - uart clock in Hz
- *     w2 - baud rate
- * Out: return 1 on success, or 0 on error
- */
-	.globl	console_core_init
-func console_core_init
-	cbz	x0, 1f
-#ifdef UNIPHIER_UART_INIT_DIVISOR
-	cbz	w1, 1f
-	cbz	w2, 1f
-	/* divisor = uart_clock / (16 * baud_rate) */
-	udiv	w2, w1, w2
-	lsr	w2, w2, #4
-#endif
-	/* Make sure the transmitter is empty before the divisor set/change */
-0:	ldr	w1, [x0, #UNIPHIER_UART_LSR]
-	tbz	w1, #UNIPHIER_UART_LSR_TEMT_BIT, 0b
-#ifdef UNIPHIER_UART_INIT_DIVISOR
-	str	w2, [x0, #UNIPHIER_UART_DLR]
-#endif
-	mov	w2, #UNIPHIER_UART_FCR_ENABLE_FIFO
-	str	w2, [x0, #UNIPHIER_UART_FCR]
-
-	mov	w2, #(UNIPHIER_UART_LCR_WLEN8 << 8)
-	str	w2, [x0, #UNIPHIER_UART_LCR_MCR]
-
-	mov	w0, #1
-	ret
-1:	mov	w0, #0
-	ret
-endfunc console_core_init
-
-/*
  * In: w0 - character to be printed
- *     x1 - console base address
- * Out: return the character written, or -1 on error
+ *     x1 - pointer to console structure
+ * Out: return the character written (always succeeds)
  * Clobber: x2
  */
-	.globl	console_core_putc
-func console_core_putc
-	/* Error out if the console is not initialized */
-	cbz	x1, 2f
+	.globl	uniphier_console_putc
+func uniphier_console_putc
+	ldr	x1, [x1, #CONSOLE_T_DRVDATA]
 
 	/* Wait until the transmitter FIFO gets empty */
 0:	ldr	w2, [x1, #UNIPHIER_UART_LSR]
@@ -86,43 +28,40 @@
 1:	str	w2, [x1, #UNIPHIER_UART_TX]
 
 	cmp	w2, #'\n'
-	b.ne	3f
+	b.ne	2f
 	mov	w2, #'\r'	/* Append '\r' to '\n' */
 	b	1b
-2:	mov	w0, #-1
-3:	ret
-endfunc console_core_putc
+2:	ret
+endfunc uniphier_console_putc
 
 /*
- * In: x0 - console base address
- * Out: return the character read
+ * In: x0 - pointer to console structure
+ * Out: return the character read, or ERROR_NO_PENDING_CHAR if no character
+	is available
  * Clobber: x1
  */
-	.globl	console_core_getc
-func console_core_getc
-	/* Error out if the console is not initialized */
-	cbz	x0, 1f
+	.globl	uniphier_console_getc
+func uniphier_console_getc
+	ldr	x0, [x0, #CONSOLE_T_DRVDATA]
 
-	/* Wait while the receiver FIFO is empty */
-0:	ldr	w1, [x0, #UNIPHIER_UART_LSR]
-	tbz	w1, #UNIPHIER_UART_LSR_DR_BIT, 0b
+	ldr	w1, [x0, #UNIPHIER_UART_LSR]
+	tbz	w1, #UNIPHIER_UART_LSR_DR_BIT, 0f
 
 	ldr	w0, [x0, #UNIPHIER_UART_RX]
-
 	ret
-1:	mov	w0, #-1
+
+0:	mov	w0, #ERROR_NO_PENDING_CHAR
 	ret
-endfunc console_core_getc
+endfunc uniphier_console_getc
 
 /*
- * In:  x0 - console base address
- * Out: return 0, or -1 on error
+ * In: x0 - pointer to console structure
+ * Out: return 0 (always succeeds)
  * Clobber: x1
  */
-	.global console_core_flush
-func console_core_flush
-	/* Error out if the console is not initialized */
-	cbz	x0, 1f
+	.global uniphier_console_flush
+func uniphier_console_flush
+	ldr	x0, [x0, #CONSOLE_T_DRVDATA]
 
 	/* wait until the transmitter gets empty */
 0:	ldr	w1, [x0, #UNIPHIER_UART_LSR]
@@ -130,83 +69,4 @@
 
 	mov	w0, #0
 	ret
-1:	mov	w0, #-1
-	ret
-endfunc console_core_flush
-
-/* find initialized UART port */
-.macro uniphier_console_get_base base, tmpx, tmpw
-	ldr	\base, =UNIPHIER_UART_BASE
-0000:	ldr	\tmpw, [\base, #UNIPHIER_UART_DLR]
-	mvn	\tmpw, \tmpw
-	uxth	\tmpw, \tmpw
-	cbnz	\tmpw, 0001f
-	add	\base, \base, #UNIPHIER_UART_OFFSET
-	ldr	\tmpx, =UNIPHIER_UART_END
-	cmp	\base, \tmpx
-	b.lo	0000b
-	mov	\base, #0
-0001:
-.endm
-
-/*
- * int plat_crash_console_init(void)
- * Clobber: x0-x2
- */
-	.globl	plat_crash_console_init
-func plat_crash_console_init
-#ifdef UNIPHIER_UART_INIT_DIVISOR
-	ldr	x0, =UNIPHIER_UART_DEFAULT_BASE
-	ldr	x1, =UNIPHIER_UART_CLK_RATE
-	ldr	x2, =UNIPHIER_UART_DEFAULT_BAUDRATE
-	b	console_core_init
-#else
-	ret
-#endif
-endfunc plat_crash_console_init
-
-/*
- * int plat_crash_console_putc(int c)
- * Clobber: x1, x2
- */
-	.globl	plat_crash_console_putc
-func plat_crash_console_putc
-#ifdef UNIPHIER_UART_INIT_DIVISOR
-	ldr	x1, =UNIPHIER_UART_DEFAULT_BASE
-#else
-	uniphier_console_get_base x1, x2, w2
-#endif
-	b	console_core_putc
-endfunc plat_crash_console_putc
-
-/*
- * int plat_crash_console_flush(void)
- * Clobber: x0, x1
- */
-	.global plat_crash_console_flush
-func plat_crash_console_flush
-#ifdef UNIPHIER_UART_INIT_DIVISOR
-	ldr	x0, =UNIPHIER_UART_DEFAULT_BASE
-#else
-	uniphier_console_get_base x0, x1, w1
-#endif
-	b	console_core_flush
-endfunc plat_crash_console_flush
-
-/*
- * void uniphier_console_setup(void)
- * Clobber: x0-x2
- */
-	.globl	uniphier_console_setup
-func uniphier_console_setup
-#ifdef UNIPHIER_UART_INIT_DIVISOR
-	ldr	x0, =UNIPHIER_UART_DEFAULT_BASE
-	ldr	w1, =UNIPHIER_UART_CLK_RATE
-	ldr	w2, =UNIPHIER_UART_DEFAULT_BAUDRATE
-#else
-	uniphier_console_get_base x0, x1, w1
-	mov	w1, #0
-	mov	w2, #0
-#endif
-	b	console_init
-endfunc uniphier_console_setup
+endfunc uniphier_console_flush
diff --git a/plat/socionext/uniphier/uniphier_console.h b/plat/socionext/uniphier/uniphier_console.h
new file mode 100644
index 0000000..e35fc88
--- /dev/null
+++ b/plat/socionext/uniphier/uniphier_console.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef UNIPHIER_CONSOLE_H
+#define UNIPHIER_CONSOLE_H
+
+#define UNIPHIER_UART_RX	0x00	/* In:  Receive buffer */
+#define UNIPHIER_UART_TX	0x00	/* Out: Transmit buffer */
+
+#define UNIPHIER_UART_FCR	0x0c	/* Char/FIFO Control Register */
+#define   UNIPHIER_UART_FCR_ENABLE_FIFO	0x01	/* Enable the FIFO */
+
+#define UNIPHIER_UART_LCR_MCR	0x10	/* Line/Modem Control Register */
+#define   UNIPHIER_UART_LCR_WLEN8	0x03	/* Wordlength: 8 bits */
+#define UNIPHIER_UART_LSR	0x14	/* Line Status Register */
+#define   UNIPHIER_UART_LSR_TEMT	0x40	/* Transmitter empty */
+#define   UNIPHIER_UART_LSR_TEMT_BIT	6	/* Transmitter empty */
+#define   UNIPHIER_UART_LSR_THRE_BIT	5	/* Transmit-hold-register empty */
+#define   UNIPHIER_UART_LSR_DR_BIT	0	/* Receiver data ready */
+#define UNIPHIER_UART_DLR	0x24	/* Divisor Latch Register */
+
+#endif /* UNIPHIER_CONSOLE_H */
diff --git a/plat/socionext/uniphier/uniphier_console_setup.c b/plat/socionext/uniphier/uniphier_console_setup.c
new file mode 100644
index 0000000..8185ec5
--- /dev/null
+++ b/plat/socionext/uniphier/uniphier_console_setup.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2019, Socionext Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/console.h>
+#include <errno.h>
+#include <lib/mmio.h>
+#include <plat/common/platform.h>
+
+#include "uniphier.h"
+#include "uniphier_console.h"
+
+#define UNIPHIER_UART_BASE	0x54006800
+#define UNIPHIER_UART_END	0x54006c00
+#define UNIPHIER_UART_OFFSET	0x100
+
+struct uniphier_console {
+	struct console console;
+	uintptr_t base;
+};
+
+/* These callbacks are implemented in assembly to use crash_console_helpers.S */
+int uniphier_console_putc(int character, struct console *console);
+int uniphier_console_getc(struct console *console);
+int uniphier_console_flush(struct console *console);
+
+static struct uniphier_console uniphier_console = {
+	.console = {
+		.flags = CONSOLE_FLAG_BOOT |
+#if DEBUG
+			 CONSOLE_FLAG_RUNTIME |
+#endif
+			 CONSOLE_FLAG_CRASH,
+		.putc = uniphier_console_putc,
+		.getc = uniphier_console_getc,
+		.flush = uniphier_console_flush,
+	},
+};
+
+/*
+ * There are 4 UART ports available on this platform. By default, we want to
+ * use the same one as used in the previous firmware stage.
+ */
+static uintptr_t uniphier_console_get_base(void)
+{
+	uintptr_t base = UNIPHIER_UART_BASE;
+	uint32_t div;
+
+	while (base < UNIPHIER_UART_END) {
+		div = mmio_read_32(base + UNIPHIER_UART_DLR);
+		if (div)
+			return base;
+		base += UNIPHIER_UART_OFFSET;
+	}
+
+	return 0;
+}
+
+static void uniphier_console_init(uintptr_t base)
+{
+	mmio_write_32(base + UNIPHIER_UART_FCR, UNIPHIER_UART_FCR_ENABLE_FIFO);
+	mmio_write_32(base + UNIPHIER_UART_LCR_MCR,
+		      UNIPHIER_UART_LCR_WLEN8 << 8);
+}
+
+void uniphier_console_setup(void)
+{
+	uintptr_t base;
+
+	base = uniphier_console_get_base();
+	if (!base)
+		plat_error_handler(-EINVAL);
+
+	uniphier_console.base = base;
+	console_register(&uniphier_console.console);
+
+	/*
+	 * The hardware might be still printing characters queued up in the
+	 * previous firmware stage. Make sure the transmitter is empty before
+	 * any initialization. Otherwise, the console might get corrupted.
+	 */
+	console_flush();
+
+	uniphier_console_init(base);
+}
diff --git a/plat/ti/k3/common/plat_common.mk b/plat/ti/k3/common/plat_common.mk
index f154a96..20a94ef 100644
--- a/plat/ti/k3/common/plat_common.mk
+++ b/plat/ti/k3/common/plat_common.mk
@@ -25,6 +25,9 @@
 # A72 Erratum for SoC
 ERRATA_A72_859971	:=	1
 
+CRASH_REPORTING		:= 1
+HANDLE_EA_EL3_FIRST	:= 1
+
 # Split out RO data into a non-executable section
 SEPARATE_CODE_AND_RODATA :=    1
 
diff --git a/tools/fiptool/Makefile.msvc b/tools/fiptool/Makefile.msvc
new file mode 100644
index 0000000..58dbb89
--- /dev/null
+++ b/tools/fiptool/Makefile.msvc
@@ -0,0 +1,30 @@
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+CC = cl.exe
+LD = link.exe
+
+FIPTOOL = fiptool.exe
+OBJECTS = fiptool.obj tbbr_config.obj win_posix.obj
+
+INC = -I. -I..\..\include\tools_share
+CFLAGS = $(CFLAGS) /nologo /Za /Zi /c /O2 /MT
+
+all: $(FIPTOOL)
+
+$(FIPTOOL): $(OBJECTS)
+	$(LD) /INCREMENTAL:NO /debug /nodefaultlib:libc.lib /out:$@ $(LIBS) $**
+
+.PHONY: clean realclean
+
+clean:
+	del /f /q $(OBJECTS) > nul
+
+realclean:
+	del /f /q $(OBJECTS) $(FIPTOOL) > nul
+
+.c.obj:
+	$(CC) -c $(CFLAGS) $(INC) $< -Fo$@