Merge "docs: fix rendering for code blocks in SPM" into integration
diff --git a/.readthedocs.yaml b/.readthedocs.yaml
index 450d6be..6207066 100644
--- a/.readthedocs.yaml
+++ b/.readthedocs.yaml
@@ -17,10 +17,10 @@
- plantuml
jobs:
post_create_environment:
- - pip install poetry
+ - pip install poetry=="1.3.2"
- poetry config virtualenvs.create false
post_install:
- - poetry install --with docs
+ - poetry install --with doc
sphinx:
configuration: docs/conf.py
diff --git a/Makefile b/Makefile
index 892c2c9..2c5748f 100644
--- a/Makefile
+++ b/Makefile
@@ -8,7 +8,7 @@
# Trusted Firmware Version
#
VERSION_MAJOR := 2
-VERSION_MINOR := 8
+VERSION_MINOR := 9
VERSION := ${VERSION_MAJOR}.${VERSION_MINOR}
# Default goal is build all images
@@ -414,6 +414,10 @@
WARNINGS += -Wunused-but-set-variable -Wmaybe-uninitialized \
-Wpacked-bitfield-compat -Wshift-overflow=2 \
-Wlogical-op
+
+# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105523
+TF_CFLAGS += $(call cc_option, --param=min-pagesize=0)
+
else
# using clang
WARNINGS += -Wshift-overflow -Wshift-sign-overflow \
@@ -790,17 +794,23 @@
$(error "BL2_IN_XIP_MEM is only supported when RESET_TO_BL2 is enabled")
endif
-# For RAS_EXTENSION, require that EAs are handled in EL3 first
+# RAS_EXTENSION is deprecated, provide alternate build options
ifeq ($(RAS_EXTENSION),1)
+ $(error "RAS_EXTENSION is now deprecated, please use ENABLE_FEAT_RAS and RAS_FFH_SUPPORT instead")
+endif
+# RAS firmware first handling requires that EAs are handled in EL3 first
+ifeq ($(RAS_FFH_SUPPORT),1)
+ ifneq ($(ENABLE_FEAT_RAS),1)
+ $(error For RAS_FFH_SUPPORT, ENABLE_FEAT_RAS must also be 1)
+ endif
ifneq ($(HANDLE_EA_EL3_FIRST_NS),1)
- $(error For RAS_EXTENSION, HANDLE_EA_EL3_FIRST_NS must also be 1)
+ $(error For RAS_FFH_SUPPORT, HANDLE_EA_EL3_FIRST_NS must also be 1)
endif
endif
-
-# When FAULT_INJECTION_SUPPORT is used, require that RAS_EXTENSION is enabled
+# When FAULT_INJECTION_SUPPORT is used, require that FEAT_RAS is enabled
ifeq ($(FAULT_INJECTION_SUPPORT),1)
- ifneq ($(RAS_EXTENSION),1)
- $(error For FAULT_INJECTION_SUPPORT, RAS_EXTENSION must also be 1)
+ ifeq ($(ENABLE_FEAT_RAS),0)
+ $(error For FAULT_INJECTION_SUPPORT, ENABLE_FEAT_RAS must not be 0)
endif
endif
@@ -912,11 +922,20 @@
endif
endif
+ifneq (${ENABLE_SME_FOR_NS},0)
+ ifeq (${ENABLE_SVE_FOR_NS},0)
+ $(error "ENABLE_SME_FOR_NS requires ENABLE_SVE_FOR_NS")
+ endif
+endif
+
# Secure SME/SVE requires the non-secure component as well
ifeq (${ENABLE_SME_FOR_SWD},1)
ifeq (${ENABLE_SME_FOR_NS},0)
$(error "ENABLE_SME_FOR_SWD requires ENABLE_SME_FOR_NS")
endif
+ ifeq (${ENABLE_SVE_FOR_SWD},0)
+ $(error "ENABLE_SME_FOR_SWD requires ENABLE_SVE_FOR_SWD")
+ endif
endif
ifeq (${ENABLE_SVE_FOR_SWD},1)
ifeq (${ENABLE_SVE_FOR_NS},0)
@@ -1058,6 +1077,7 @@
# Variables for use with PRINT_MEMORY_MAP
PRINT_MEMORY_MAP_PATH ?= tools/memory
PRINT_MEMORY_MAP ?= ${PRINT_MEMORY_MAP_PATH}/print_memory_map.py
+INVERTED_MEMMAP ?= 0
# Variables for use with documentation build using Sphinx tool
DOCS_PATH ?= docs
@@ -1163,7 +1183,10 @@
SIMICS_BUILD \
FEATURE_DETECTION \
TRNG_SUPPORT \
+ ERRATA_ABI_SUPPORT \
+ ERRATA_NON_ARM_INTERCONNECT \
CONDITIONAL_CMO \
+ RAS_FFH_SUPPORT \
)))
$(eval $(call assert_numerics,\
@@ -1182,6 +1205,7 @@
ENABLE_FEAT_AMU \
ENABLE_FEAT_AMUv1p1 \
ENABLE_FEAT_CSV2_2 \
+ ENABLE_FEAT_RAS \
ENABLE_FEAT_DIT \
ENABLE_FEAT_ECV \
ENABLE_FEAT_FGT \
@@ -1208,10 +1232,10 @@
FW_ENC_STATUS \
NR_OF_FW_BANKS \
NR_OF_IMAGES_IN_FW_BANK \
- RAS_EXTENSION \
TWED_DELAY \
ENABLE_FEAT_TWED \
SVE_VECTOR_LEN \
+ IMPDEF_SYSREG_TRAP \
)))
ifdef KEY_SIZE
@@ -1280,7 +1304,8 @@
PROGRAMMABLE_RESET_ADDRESS \
PSCI_EXTENDED_STATE_ID \
PSCI_OS_INIT_MODE \
- RAS_EXTENSION \
+ ENABLE_FEAT_RAS \
+ RAS_FFH_SUPPORT \
RESET_TO_BL31 \
SEPARATE_CODE_AND_RODATA \
SEPARATE_BL2_NOLOAD_REGION \
@@ -1294,6 +1319,8 @@
TRUSTED_BOARD_BOOT \
CRYPTO_SUPPORT \
TRNG_SUPPORT \
+ ERRATA_ABI_SUPPORT \
+ ERRATA_NON_ARM_INTERCONNECT \
USE_COHERENT_MEM \
USE_DEBUGFS \
ARM_IO_IN_DTB \
@@ -1343,6 +1370,7 @@
TWED_DELAY \
ENABLE_FEAT_TWED \
CONDITIONAL_CMO \
+ IMPDEF_SYSREG_TRAP \
)))
ifeq (${SANITIZE_UB},trap)
diff --git a/bl1/aarch64/bl1_exceptions.S b/bl1/aarch64/bl1_exceptions.S
index c54219f..eaaf59a 100644
--- a/bl1/aarch64/bl1_exceptions.S
+++ b/bl1/aarch64/bl1_exceptions.S
@@ -218,9 +218,7 @@
smc_handler:
/* -----------------------------------------------------
* Save x0-x29 and ARMv8.3-PAuth (if enabled) registers.
- * If Secure Cycle Counter is not disabled in MDCR_EL3
- * when ARMv8.5-PMU is implemented, save PMCR_EL0 and
- * disable Cycle Counter.
+ * Save PMCR_EL0 and disable Cycle Counter.
* TODO: Revisit to store only SMCCC specified registers.
* -----------------------------------------------------
*/
diff --git a/bl31/aarch64/ea_delegate.S b/bl31/aarch64/ea_delegate.S
index 9419476..dd6b4dc 100644
--- a/bl31/aarch64/ea_delegate.S
+++ b/bl31/aarch64/ea_delegate.S
@@ -81,9 +81,7 @@
1:
/*
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
- * If Secure Cycle Counter is not disabled in MDCR_EL3 when
- * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
- * Also set the PSTATE to a known state.
+ * Also save PMCR_EL0 and set the PSTATE to a known state.
*/
bl prepare_el3_entry
@@ -123,9 +121,7 @@
/*
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
- * If Secure Cycle Counter is not disabled in MDCR_EL3 when
- * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
- * Also set the PSTATE to a known state.
+ * Also save PMCR_EL0 and set the PSTATE to a known state.
*/
bl prepare_el3_entry
@@ -153,7 +149,7 @@
* x1: EA syndrome
*/
func delegate_sync_ea
-#if RAS_EXTENSION
+#if RAS_FFH_SUPPORT
/*
* Check for Uncontainable error type. If so, route to the platform
* fatal error handler rather than the generic EA one.
@@ -183,7 +179,7 @@
* x1: EA syndrome
*/
func delegate_async_ea
-#if RAS_EXTENSION
+#if RAS_FFH_SUPPORT
/* Check Exception Class to ensure SError, as this function should
* only be invoked for SError. If that is not the case, which implies
* either an HW error or programming error, panic.
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S
index 2fa9f06..8bcf94e 100644
--- a/bl31/aarch64/runtime_exceptions.S
+++ b/bl31/aarch64/runtime_exceptions.S
@@ -50,16 +50,16 @@
/*
* Macro that prepares entry to EL3 upon taking an exception.
*
- * With RAS_EXTENSION, this macro synchronizes pending errors with an ESB
- * instruction. When an error is thus synchronized, the handling is
+ * With RAS_FFH_SUPPORT, this macro synchronizes pending errors with an
+ * ESB instruction. When an error is thus synchronized, the handling is
* delegated to platform EA handler.
*
- * Without RAS_EXTENSION, this macro synchronizes pending errors using
+ * Without RAS_FFH_SUPPORT, this macro synchronizes pending errors using
* a DSB, unmasks Asynchronous External Aborts and saves X30 before
* setting the flag CTX_IS_IN_EL3.
*/
.macro check_and_unmask_ea
-#if RAS_EXTENSION
+#if RAS_FFH_SUPPORT
/* Synchronize pending External Aborts */
esb
@@ -72,9 +72,7 @@
/*
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
- * If Secure Cycle Counter is not disabled in MDCR_EL3 when
- * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
- * Also set the PSTATE to a known state.
+ * Also save PMCR_EL0 and set the PSTATE to a known state.
*/
bl prepare_el3_entry
@@ -164,9 +162,7 @@
/*
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
- * If Secure Cycle Counter is not disabled in MDCR_EL3 when
- * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
- * Also set the PSTATE to a known state.
+ * Also save PMCR_EL0 and set the PSTATE to a known state.
*/
bl prepare_el3_entry
@@ -307,7 +303,7 @@
end_vector_entry fiq_sp_elx
vector_entry serror_sp_elx
-#if !RAS_EXTENSION
+#if !RAS_FFH_SUPPORT
/*
* This will trigger if the exception was taken due to SError in EL3 or
* because of pending asynchronous external aborts from lower EL that got
@@ -359,7 +355,7 @@
vector_entry serror_aarch64
save_x30
apply_at_speculative_wa
-#if RAS_EXTENSION
+#if RAS_FFH_SUPPORT
msr daifclr, #DAIF_ABT_BIT
#else
check_and_unmask_ea
@@ -402,7 +398,7 @@
vector_entry serror_aarch32
save_x30
apply_at_speculative_wa
-#if RAS_EXTENSION
+#if RAS_FFH_SUPPORT
msr daifclr, #DAIF_ABT_BIT
#else
check_and_unmask_ea
@@ -440,9 +436,7 @@
/*
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
- * If Secure Cycle Counter is not disabled in MDCR_EL3 when
- * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
- * Also set the PSTATE to a known state.
+ * Also save PMCR_EL0 and set the PSTATE to a known state.
*/
bl prepare_el3_entry
diff --git a/bl31/bl31.mk b/bl31/bl31.mk
index 9b5cf55..d7c9a52 100644
--- a/bl31/bl31.mk
+++ b/bl31/bl31.mk
@@ -91,6 +91,10 @@
BL31_SOURCES += lib/extensions/spe/spe.c
endif
+ifeq (${ERRATA_ABI_SUPPORT},1)
+BL31_SOURCES += services/std_svc/errata_abi/errata_abi_main.c
+endif
+
ifneq (${ENABLE_FEAT_AMU},0)
BL31_SOURCES += ${AMU_SOURCES}
endif
@@ -101,12 +105,10 @@
ifneq (${ENABLE_SME_FOR_NS},0)
BL31_SOURCES += lib/extensions/sme/sme.c
-BL31_SOURCES += lib/extensions/sve/sve.c
-else
+endif
ifneq (${ENABLE_SVE_FOR_NS},0)
BL31_SOURCES += lib/extensions/sve/sve.c
endif
-endif
ifneq (${ENABLE_MPAM_FOR_LOWER_ELS},0)
BL31_SOURCES += lib/extensions/mpam/mpam.c
diff --git a/bl31/bl31_traps.c b/bl31/bl31_traps.c
index b12185d..2cfe14a 100644
--- a/bl31/bl31_traps.c
+++ b/bl31/bl31_traps.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2023, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -11,13 +12,19 @@
int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx)
{
- switch (esr_el3 & ISS_SYSREG_OPCODE_MASK) {
+ uint64_t __unused opcode = esr_el3 & ISS_SYSREG_OPCODE_MASK;
+
#if ENABLE_FEAT_RNG_TRAP
- case ISS_SYSREG_OPCODE_RNDR:
- case ISS_SYSREG_OPCODE_RNDRRS:
+ if ((opcode == ISS_SYSREG_OPCODE_RNDR) || (opcode == ISS_SYSREG_OPCODE_RNDRRS)) {
return plat_handle_rng_trap(esr_el3, ctx);
+ }
#endif
- default:
- return TRAP_RET_UNHANDLED;
+
+#if IMPDEF_SYSREG_TRAP
+ if ((opcode & ISS_SYSREG_OPCODE_IMPDEF) == ISS_SYSREG_OPCODE_IMPDEF) {
+ return plat_handle_impdef_trap(esr_el3, ctx);
}
+#endif
+
+ return TRAP_RET_UNHANDLED;
}
diff --git a/bl32/sp_min/sp_min.mk b/bl32/sp_min/sp_min.mk
index fb0161c..ec75d88 100644
--- a/bl32/sp_min/sp_min.mk
+++ b/bl32/sp_min/sp_min.mk
@@ -46,6 +46,10 @@
services/std_svc/trng/trng_entropy_pool.c
endif
+ifeq (${ERRATA_ABI_SUPPORT}, 1)
+BL32_SOURCES += services/std_svc/errata_abi/errata_abi_main.c
+endif
+
ifneq (${ENABLE_SYS_REG_TRACE_FOR_NS},0)
BL32_SOURCES += lib/extensions/sys_reg_trace/aarch32/sys_reg_trace.c
endif
diff --git a/changelog.yaml b/changelog.yaml
index 6dbb9b2..0c4644d 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -165,11 +165,15 @@
- plat/arm
subsections:
+ - title: A5DS
+ scope: a5ds
+
- title: CSS
scope: css
deprecated:
- plat/arm/css
+ - plat/css
- title: FPGA
scope: fpga
@@ -208,6 +212,9 @@
scope: rd
subsections:
+ - title: RD-N1 Edge
+ scope: rdn1edge
+
- title: RD-N2
scope: rdn2
@@ -224,6 +231,9 @@
- title: TC
scope: tc
+ deprecated:
+ - plat/tc
+
subsections:
- title: TC0
scope: tc0
@@ -335,6 +345,9 @@
- title: Tegra 194
scope: tegra194
+ - title: Tegra 210
+ scope: tegra210
+
- title: NXP
scope: nxp
@@ -383,6 +396,9 @@
deprecated:
- plat/imx/imx8m/imx8mq
+ - title: i.MX 8
+ scope: imx8
+
- title: Layerscape
scope: layerscape
@@ -465,6 +481,10 @@
deprecated:
- plat/qemu
+ subsections:
+ - title: SBSA
+ scope: qemu-sbsa
+
- title: QTI
scope: qti
@@ -640,6 +660,9 @@
- title: RMMD
scope: rmmd
+ - title: RMM
+ scope: rmm
+
- title: SPM
scope: spm
@@ -662,6 +685,9 @@
- title: TRNG
scope: trng
+ - title: ERRATA_ABI
+ scope: errata_abi
+
- title: Libraries
subsections:
@@ -808,6 +834,9 @@
- title: GUID Partition Tables Support
scope: guid-partition
+ deprecated:
+ - partition
+
- title: SCMI
scope: scmi
@@ -877,6 +906,9 @@
deprecated:
- drivers/tzc380
+ - title: SBSA
+ scope: sbsa
+
- title: Marvell
scope: marvell-drivers
@@ -1172,6 +1204,9 @@
- title: PIE
scope: pie
+ - title: PIE/POR
+ scope: pie/por
+
- title: Security
scope: security
@@ -1242,6 +1277,9 @@
- title: Git Hooks
scope: hooks
+ deprecated:
+ - git-hooks
+
- title: Tools
subsections:
diff --git a/common/feat_detect.c b/common/feat_detect.c
index eb4db95..50b74d0 100644
--- a/common/feat_detect.c
+++ b/common/feat_detect.c
@@ -60,16 +60,6 @@
}
}
-/*******************************************************************************
- * Feature : FEAT_RAS (Reliability, Availability, and Serviceability Extension)
- ******************************************************************************/
-static void read_feat_ras(void)
-{
-#if (RAS_EXTENSION == FEAT_STATE_ALWAYS)
- feat_detect_panic(is_armv8_2_feat_ras_present(), "RAS");
-#endif
-}
-
/************************************************
* Feature : FEAT_PAUTH (Pointer Authentication)
***********************************************/
@@ -160,9 +150,9 @@
check_feature(ENABLE_FEAT_VHE, read_feat_vhe_id_field(), "VHE", 1, 1);
/* v8.2 features */
- read_feat_ras();
check_feature(ENABLE_SVE_FOR_NS, read_feat_sve_id_field(),
"SVE", 1, 1);
+ check_feature(ENABLE_FEAT_RAS, read_feat_ras_id_field(), "RAS", 1, 2);
/* v8.3 features */
read_feat_pauth();
diff --git a/docs/about/features.rst b/docs/about/features.rst
index cb8b552..4a2c77e 100644
--- a/docs/about/features.rst
+++ b/docs/about/features.rst
@@ -22,8 +22,8 @@
Cache Coherent Network (CCN), Network Interconnect (NIC) and TrustZone
Controller (TZC).
-- A generic |SCMI| driver to interface with conforming power controllers, for
- example the Arm System Control Processor (SCP).
+- Secure Monitor library code such as world switching, EL2/EL1 context
+ management and interrupt routing.
- SMC (Secure Monitor Call) handling, conforming to the `SMC Calling
Convention`_ using an EL3 runtime services framework.
@@ -34,14 +34,22 @@
is also suitable for integration with other AArch32 EL3 Runtime Software,
for example an AArch32 Secure OS.
+- A generic |SCMI| driver to interface with conforming power controllers, for
+ example the Arm System Control Processor (SCP).
+
- A minimal AArch32 Secure Payload (*SP_MIN*) to demonstrate |PSCI| library
integration with AArch32 EL3 Runtime Software.
-- Secure Monitor library code such as world switching, EL1 context management
- and interrupt routing.
- When a Secure-EL1 Payload (SP) is present, for example a Secure OS, the
- AArch64 EL3 Runtime Software must be integrated with a Secure Payload
- Dispatcher (SPD) component to customize the interaction with the SP.
+- Secure partition manager dispatcher(SPMD) with following two configurations:
+
+ - S-EL2 SPMC implementation, widely compliant with FF-A v1.1 EAC0 and initial
+ support of FF-A v1.2.
+
+ - EL3 SPMC implementation, compliant with a subset of FF-A v1.1 EAC0.
+
+- Support for Arm CCA based on FEAT_RME which supports authenticated boot and
+ execution of RMM with the necessary routing of RMI commands as specified in
+ RMM Beta 0 Specification.
- A Test SP and SPD to demonstrate AArch64 Secure Monitor functionality and SP
interaction with PSCI.
@@ -50,12 +58,20 @@
`Trusty Secure OS`_ and `ProvenCore Secure OS`_.
- A Trusted Board Boot implementation, conforming to all mandatory TBBR
- requirements. This includes image authentication, Firmware Update (or
- recovery mode), and packaging of the various firmware images into a
+ requirements. This includes image authentication, Firmware recovery,
+ Firmware encryption and packaging of the various firmware images into a
Firmware Image Package (FIP).
-- Pre-integration of TBB with the Arm CryptoCell product, to take advantage of
- its hardware Root of Trust and crypto acceleration services.
+- Measured boot support with PoC to showcase its interaction with firmware TPM
+ (fTPM) service implemneted on top of OP-TEE.
+
+- Support for Dynamic Root of Trust for Measurement (DRTM).
+
+- Following firmware update mechanisms available:
+
+ - PSA Firmware Update (PSA FWU)
+
+ - TBBR Firmware Update (TBBR FWU)
- Reliability, Availability, and Serviceability (RAS) functionality, including
@@ -81,6 +97,8 @@
secure system processor, or where a non-TF-A ROM expects BL2 to be loaded
at EL3.
+- Support for Errata management firmware interface.
+
- Support for the GCC, LLVM and Arm Compiler 6 toolchains.
- Support for combining several libraries into a "romlib" image that may be
@@ -88,27 +106,13 @@
in ROM but is accessed through a jump-table that may be stored
in read-write memory, allowing for the library code to be patched.
-- Support for the Secure Partition Manager Dispatcher (SPMD) component as a
- new standard service.
-
-- Support for ARMv8.3 pointer authentication in the normal and secure worlds.
- The use of pointer authentication in the normal world is enabled whenever
- architectural support is available, without the need for additional build
- flags.
-
-- Position-Independent Executable (PIE) support. Currently for BL2, BL31, and
- TSP, with further support to be added in a future release.
+- Position-Independent Executable (PIE) support.
Still to come
-------------
- Support for additional platforms.
-- Refinements to Position Independent Executable (PIE) support.
-
-- Continued support for the FF-A v1.0 (formally known as SPCI) specification, to enable the
- use of secure partition management in the secure world.
-
- Documentation enhancements.
- Ongoing support for new architectural features, CPUs and System IP.
@@ -125,4 +129,4 @@
--------------
-*Copyright (c) 2019-2021, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2023, Arm Limited. All rights reserved.*
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 02dae05..0287d6c 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -50,6 +50,8 @@
:|G|: `raghuncstate`_
:|M|: Manish Badarkhe <manish.badarkhe@arm.com>
:|G|: `ManishVB-Arm`_
+:|M|: Yann Gautier <yann.gautier@st.com>
+:|G|: `Yann-lms`_
LTS Maintainers
---------------
diff --git a/docs/about/release-information.rst b/docs/about/release-information.rst
index cd52460..0768e1f 100644
--- a/docs/about/release-information.rst
+++ b/docs/about/release-information.rst
@@ -52,7 +52,9 @@
+-----------------+---------------------------+------------------------------+
| v2.8 | 5th week of Nov '22 | 3rd week of Nov '22 |
+-----------------+---------------------------+------------------------------+
-| v2.9 | 1st week of May '23 | 3rd week of Apr '23 |
+| v2.9 | 4th week of May '23 | 2nd week of May '23 |
++-----------------+---------------------------+------------------------------+
+| v3.0 | 2nd week of Nov '23 | 2nd week of Oct '23 |
+-----------------+---------------------------+------------------------------+
Removal of Deprecated Interfaces
@@ -67,7 +69,7 @@
| | Date | after | |
| | | Release | |
+================================+=============+=========+=========================================================+
-| plat_convert_pk() function | Nov'22 | 2.9 | Platform conversion to manage specific PK hash |
+| None at this time | | | |
+--------------------------------+-------------+---------+---------------------------------------------------------+
Removal of Deprecated Drivers
@@ -82,8 +84,6 @@
| | Date | after | |
| | | Release | |
+================================+=============+=========+=========================================================+
-| io_dummy driver | Nov'22 | 2.9 | No more used by any upstream platform |
-+--------------------------------+-------------+---------+---------------------------------------------------------+
| CryptoCell-712 | 2.9 | 3.0 | No longer maintained. |
+--------------------------------+-------------+---------+---------------------------------------------------------+
| CryptoCell-713 | 2.9 | 3.0 | No longer maintained. |
diff --git a/docs/change-log.md b/docs/change-log.md
index bb05afb..b660c73 100644
--- a/docs/change-log.md
+++ b/docs/change-log.md
@@ -3,6 +3,1024 @@
This document contains a summary of the new features, changes, fixes and known
issues in each release of Trusted Firmware-A.
+## [2.9.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.8.0..refs/tags/v2.9.0) (2023-05-16)
+
+### ⚠ BREAKING CHANGES
+
+- **Libraries**
+
+ - **EL3 Runtime**
+
+ - **RAS**
+
+ - The previous RAS_EXTENSION is now deprecated. The equivalent functionality can be achieved by the following 2 options:
+ - ENABLE_FEAT_RAS
+ - RAS_FFH_SUPPORT
+
+ **See:** replace RAS_EXTENSION with FEAT_RAS ([9202d51](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9202d51990c192e8bc041e6f53d5ce63ee908665))
+
+- **Drivers**
+
+ - **Authentication**
+
+ - unify REGISTER_CRYPTO_LIB
+
+ **See:** unify REGISTER_CRYPTO_LIB ([dee99f1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dee99f10b1dcea09091f4a1d53185153802dfb64))
+
+ - **Arm**
+
+ - **Ethos-N**
+
+ - The Linux Kernel NPU driver can no longer directly configure and boot the NPU in a TZMP1 build. The API version has therefore been given a major version bump with this change.
+
+ **See:** add protected NPU firmware setup ([6dcf3e7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6dcf3e774457cf00b91abda715adfbefce822877))
+
+ - Building the FIP when TZMP1 support is enabled in the NPU driver now requires a parameter to specify the NPU firmware file.
+
+ **See:** load NPU firmware at BL2 ([33bcaed](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/33bcaed1211ab27968433b546979687bc1182630))
+
+- **Build System**
+
+ - BL2_AT_EL3 renamed to RESET_TO_BL2 across the repository.
+
+ **See:** distinguish BL2 as TF-A entry point and BL2 running at EL3 ([42d4d3b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/42d4d3baacb3b11c68163ec85de1bf2e34e0c882))
+
+ - check boolean flags are not empty
+
+ **See:** check boolean flags are not empty ([1369fb8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1369fb82c8e809c1a59a0d99184dbfd2d0b81afa))
+
+ - All input and output linker section names have been prefixed with the period character, e.g. `cpu_ops` -> `.cpu_ops`.
+
+ **See:** always prefix section names with `.` ([da04341](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/da04341ed52d214139fe2d16667ef5b58c38e502))
+
+ - The `EXTRA_LINKERFILE` build system variable has been replaced with the `<IMAGE>_LINKER_SCRIPT_SOURCES` variable. See the commit message for more information.
+
+ **See:** permit multiple linker scripts ([a6ff006](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a6ff0067ab57d848d3fb28a3eb2b47e6cf2a6092))
+
+ - The `LINKERFILE`, `BL_LINKERFILE` and `<IMAGE_LINKERFILE>` build system variables have been renamed. See the commit message for more information.
+
+ **See:** clarify linker script generation ([8227493](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/82274936374bf630bf5256370e93a531fdda6372))
+
+### Resolved Issues
+
+- **Architecture**
+
+ - **CPU feature / ID register handling in general**
+
+ - context-switch: move FGT availability check to callers ([de8c489](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/de8c489247458c00f7b48301fb5c5273c7a628fc))
+ - make stub enable functions "static inline" ([d7f3ed3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d7f3ed3655b85223583d8c2d9e719f364266ef26))
+ - resolve build errors due to compiler optimization ([e8f0dd5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e8f0dd58da231b81ba0ce6f27aaf1e31b4d4c429))
+
+ - **Memory Partitioning and Monitoring (MPAM) Extension (FEAT_MPAM)**
+
+ - feat_detect: support major/minor ([1f8be7f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1f8be7fc66fb59b197dde3b4ea83314b1728c6b8))
+ - remove unwanted param for "endfunc" macro ([0e0bd25](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0e0bd250ef08ba70b34db9eb0cab0f6ef4d08edf))
+ - run-time checks for mpam save/restore routines ([ed80440](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ed804406bf2ee04bde1c17683cec6f679ea1e160))
+
+ - **Pointer Authentication Extension**
+
+ - make pauth_helpers linking generic ([90ce8b8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/90ce8b8718d079b9e906d06bdd6a72da6cc5b636))
+
+ - **Performance Monitors Extension (FEAT_PMUv3)**
+
+ - switch FVP PMUv3 SPIs to PPI ([d7c455d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d7c455d8cca85de4a520da33db6523c9c8a7ee38))
+ - unconditionally save PMCR_EL0 ([1d6d680](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1d6d6802dd547c8b378a9a47572ee72e68cceb3b))
+
+ - **Scalable Matrix Extension (FEAT_SME, FEAT_SME2)**
+
+ - disable SME for SPD=spmd ([2fd2fce](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2fd2fcedff0595a7050328fa60dc4850d6b424bf))
+
+ - **Statistical profiling Extension (FEAT_SPE)**
+
+ - drop SPE EL2 context switch code ([16e3ddb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/16e3ddba1f049106387dfe21989243d2fc4cf061))
+
+- **Platforms**
+
+ - **Allwinner**
+
+ - check RSB availability in DT on H6 ([658b315](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/658b3154d5b06a467b65cb79d31da751ffc6f5a4))
+
+ - **Arm**
+
+ - arm_rotpk_header undefined reference ([95302e4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/95302e4b234589e0487996a5c0f1e111c21ffedc))
+
+ - **A5DS**
+
+ - add default value for ARM_DISABLE_TRUSTED_WDOG ([115ab63](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/115ab63872ab36f8202f4c4aab093c4e9182d4e7))
+
+ - **CSS**
+
+ - fix invalid redistributor poweroff ([60719e4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/60719e4e0965aead49d927f12bf2a37bd2629012))
+
+ - **FPGA**
+
+ - include missing header file ([b7253a1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b7253a14cdc633a606472ec4e5aa4123158e2013))
+
+ - **FVP**
+
+ - correct ehf priority for SPM_MM ([fb2fd55](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fb2fd558d8102ad79e5970714e0afec31a6138d7))
+ - incorrect UUID name in FVP tb_fw_config ([7f2bf23](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7f2bf23dec6e6467704d7d71ec44bee030912987))
+ - unconditionally include lib/psa headers ([72db458](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/72db45852d84db6ade0da2a232a44df3e5228b6d))
+ - work around BL31 progbits exceeded ([138221c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/138221c2457b9d04101b84084c07d576b0eb5a51))
+ - work around DRTM_SUPPORT BL31 progbits exceeded ([7762e5d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7762e5d0ed5c28b0a77dc25cc566cf54a69af7e6))
+
+ - **Morello**
+
+ - add platform-specific power domain functions ([02a5bcb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/02a5bcb0bc3c8596894b6d0ec8c979b330db387a))
+
+ - **N1SDP**
+
+ - add platform-specific power domain functions ([5bdafc4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5bdafc4099b446609965f9132e6c52a7bdeb9ac8))
+
+ - **RD**
+
+ - **RD-N1 Edge**
+
+ - change variable type to fix gcc sign conversion error ([3a3e0e5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3a3e0e5371e99b3764fd8e8d98a447911f3bb915))
+
+ - **TC**
+
+ - increase TC_TZC_DRAM1_SIZE ([7e3f6a8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7e3f6a87d74efec780c0832c0535dd64ef830cfa))
+ - change the FIP offset to 8 KiB boundary ([d07b8aa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d07b8aac39abc3026233e316686f4643d076f8d6))
+ - change the properties of optee reserved memory ([2fff46c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2fff46c80fe4aa27cd55ad4bfbe43c3823095259))
+ - enable dynamic feature detection of FEAT_SVE for NormalWorld ([67265f2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/67265f2f6d7604147080033a1c99150e9a020f28))
+ - enable the execution of both platform tests ([657b90e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/657b90ea1aa2831a7feed31f07fc8e92213e6465))
+ - only suspend booting after running plat tests ([9b26655](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9b266556d308c0af6f932fedd1c41fbda05204aa))
+ - unify TC ROM start addresses ([f9e11c7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f9e11c724bb7c919dc9bd5dd8fca1e04140374d2))
+ - update the name of mbedtls config header ([d5fc899](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d5fc8992c7b63675b6fc4b2c00a1e1acfdaaeee2))
+
+ - **Broadcom**
+
+ - add braces around bodies of conditionals ([9f58bfb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9f58bfbbe90d2891c289cd27ab7d2ede8b5572d4))
+
+ - **Intel**
+
+ - add mailbox error return status for FCS_DECRYPTION ([76ed322](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/76ed32236aa396cb0e15eb049bea03710ca1992d))
+ - agilex bitstream pre-authenticate ([4b3d323](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4b3d323acdd21d8853e38e135bf990b3767ca354))
+ - fix Agilex and N5X clock manager to main PLL C0 ([5f06bff](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5f06bffa831638fd95d2160209000ef36d2a22ce))
+ - fix fcs_client crashed when increased param size ([c42402c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c42402cdf8a3dfc6f6e62a92b2898066e8cc46f6))
+ - fix pinmux handoff bug on Agilex ([e6c0389](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e6c038909193b83bc293de9b1eb65440e75f8c91))
+ - fix print out ERROR when encounter SEU_Err ([1a0bf6e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1a0bf6e1d8fe899359535c0a0a68c2be5e5acaf4))
+ - fix sp_timer0 is not disabled in firewall on Agilex ([8de7167](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8de7167eb661ff730a79bd2c6db15c22fdc62c8a))
+ - fix the pointer of block memory to fill in and bytes being set ([afe9fcc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/afe9fcc3d262ca279a747c8ab6fa8bacf79c76fb))
+ - flash dcache before mmio read ([731622f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/731622fe757ab2bcc0492ad27bafecf24206ddac))
+ - mailbox store QSPI ref clk in scratch reg ([7f9e9e4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7f9e9e4b40152c0cb52bcc53ac3d32fd1c978416))
+ - missing NCORE CCU snoop filter fix in BL2 ([b34a48c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b34a48c1ce0dd7e44eac4ceb0537b337857b057f))
+ - remove checking on TEMP and VOLT checking for HWMON ([68ac5fe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/68ac5fe14c0220673d7ee88a99b3d02be1fef530))
+ - update boot scratch to indicate to Uboot is PSCI ON ([7f7a16a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7f7a16a6c0a49af593fa080eb66f72a20bb07299))
+
+ - **NVIDIA**
+
+ - **Tegra**
+
+ - append major revision to the chip_id value ([33c4766](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/33c476601cf48a4b02259b8cb43819acd824804f))
+ - remove dependency on CPU registers to get boot parameters ([0b9f05f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0b9f05fcaea069bff6894d99ec5babc4be29ca67))
+
+ - **Tegra 210**
+
+ - support legacy SMC_ID 0xC2FEFE00 ([40a4e2d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/40a4e2d84c38ffae899eaa2c33c1e280312919cf))
+
+ - **NXP**
+
+ - **i.MX**
+
+ - **i.MX 8M**
+
+ - add ddr4 dvfs sw workaround for ERR050712 ([e00fe11](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e00fe11df3fee04c7f3137817294d464466dab22))
+ - backup mr12/14 value from lpddr4 chip ([a2655f4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a2655f48697416b8350ba5b3f7f44f1f0be79d4e))
+ - correct the rank info get fro mstr ([5277c09](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5277c09606450daaffa43f3cf15fcc427d7ba612))
+ - fix coverity out of bound access issue ([0331b1c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0331b1c6111d198195298a2885dbd93cac1ad26a))
+ - fix the current fsp init ([25c4323](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/25c43233e866326326f9f82bfae03357c396a99f))
+ - fix the dfiphymaster setting after dvfs ([ad0cbbf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ad0cbbf513dfabe51a401c06be504e57d6b143ca))
+ - fix the dram retention random hang on some imx8mq Rev2.0 ([4bf5019](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4bf5019228cf89e0cbc2cd03627f755d51e3e198))
+ - fix the rank to rank space issue ([3330084](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3330084979e4c1a39a92f0642000664c79a00dda))
+
+ - **i.MX 8Q**
+
+ - fix compilation with gcc >= 12.x ([e75a3b6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e75a3b6e89c4bce11d1885426f22262def9bd664))
+
+ - **Layerscape**
+
+ - fix errata a008850 ([c45791b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c45791b2f20909c9a9d2bae84dafc17f55892fc8))
+ - fix nv_storage assert checking ([5d599b7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5d599b71ea6e0020f4f9d0e7af303726483217bc))
+ - unlock write access SMMU_CBn_ACTLR ([0ca1d8f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0ca1d8fba3bee32242b123ae28ad5c83a657aa0d))
+
+ - **LX2**
+
+ - init global data before using it ([50aa0ea](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/50aa0ea7acd21e7e9920a91a14db14a9f8c63700))
+
+ - **LS1046A**
+
+ - 4 keys secureboot failure resolved ([c0c157a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c0c157a680fcb100afed3e1ea9d342deea72ea05))
+
+ - **QEMU**
+
+ - enable dynamic feature detection of FEAT_SVE for NormalWorld ([fc259b6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fc259b6c3a551efbc810c8e08e82b7b5378f57ba))
+
+ - **SBSA**
+
+ - enable FGT ([c598692](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c598692d0c6a79dd10c34d5a4a740c90261cfc65))
+ - enable SVE and SME ([9bff7ce](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9bff7ce37545162d417953ac36c6878216815b94))
+
+ - **QTI**
+
+ - **MSM8916**
+
+ - add timeout for crash console TX flush ([7e002c8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7e002c8a13172c44f55ab49062861479b6622884))
+ - drop unneeded initialization of CNTACR ([d833af3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d833af3ab50cd2cfecb8868c3d5340df1572f042))
+ - flush dcache after writing msm8916_entry_point ([01ba69c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/01ba69cd9b833047653186858a6929e6c9379989))
+ - print \r before \n on UART console ([3fb7e40](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3fb7e40a21b1570a8ce1cd1708134fa7a05d94fb))
+
+ - **Raspberry Pi**
+
+ - **Raspberry Pi 3**
+
+ - initialize SD card host controller ([bd96d53](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bd96d533dc28c4c938aa54905787688823cbccac))
+
+ - **Renesas**
+
+ - align incompatible function pointers ([90c4b3b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/90c4b3b62d5303c22fdc5f65f0db784de0f4ac95))
+
+ - **Rockchip**
+
+ - use semicolon instead of comma ([8557d49](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8557d491b6dbd6cbf27cc2ae6425f6cb29ca2c35))
+
+ - **ST**
+
+ - add U suffix for unsigned numbers ([9c1aa12](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9c1aa1253c9c77487b73d46a89941e81e80864eb))
+ - explicitly check operators precedence ([56048fe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/56048fe215997ab6788ebd251e8cde094392dfc7))
+ - include utils.h to solve compilation error ([377846b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/377846b65e8eb946a6560f1200ca4ca0e1eb8b99))
+ - make metadata_block_spec static ([d1d8a9b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d1d8a9bad0be53792e219625b0d327cc4855378f))
+ - rework secure-status check in fdt_get_status() ([0ebaf22](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0ebaf222899c1c33fe8bd0e69bd2c287ebe1154b))
+ - use Boolean type for tests ([45d2d49](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/45d2d495e77c9c8f3e80774e48a80e4882c8ac0d))
+ - use indices when counting GPIOs in DT ([e7d7544](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e7d75448b9e46dee22fe23b37c28a522b9ec3a6c))
+
+ - **STM32MP1**
+
+ - add const for strings in stm32mp_get_soc_name() ([d7f5bed](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d7f5bed90eaacee0a223bcf23438dfb76dee08e6))
+ - add missing platform.h include ([6e55f9e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6e55f9e2cde0426c39ccda87b00047f85d30f97d))
+ - always define PKA algos flags ([e0e2d64](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e0e2d64f47654e4d86d0e400977eab0e4a01523e))
+ - remove boolean check on PLAT_TBBR_IMG_DEF ([231a0ad](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/231a0adb6abc35c125d4177749af37042575eca2))
+ - rework DWL buffer cache invalidation ([127ed00](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/127ed0008e03abb98b5447cb80c5634dfa554e7d))
+
+ - **Texas Instruments**
+
+ - do not take system power reference in bl31_platform_setup() ([9977948](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9977948112d732935362a3fe8518e3b2e4b7f6b7))
+ - fix typo in boot authentication message name ([81f525e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/81f525ecc75a3d8b344a27881098fcaab65f2d8f))
+
+ - **Xilinx**
+
+ - fix misra defects ([964e559](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/964e55928c8f966633cc57e41987aa00890f5da7))
+ - handle CRC failure in IPI ([5e92be5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5e92be5121e8ecd81a0f89eaae0d1a7ac8f4bfd7))
+ - handle CRC failure in IPI callback ([6173d91](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6173d914d673249ec47c080909c31a1654545913))
+ - initialize values to device enum members ([5c62d59](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5c62d599274b5d9facd4996b50c1a1e153b247a4))
+ - remove asserts around arg0/arg1 ([8be2044](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8be20446706c6b2fe911804385f308817495d2d4))
+ - remove unnecessary condition ([c984123](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c984123669a7ba7b8d1dc168db8e130ee52bbb1e))
+ - remove unused mailbox macros ([15f49cb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/15f49cb49d7daf2cd771c80d3dd80ff15874b40b))
+ - resolve integer handling issue ([4e46db4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4e46db40fc86ddc0556c42ba01198d13002fcf14))
+ - use lib/smccc.h macros instead of trusty spd ([0ee07d7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0ee07d796cece8074eb296415c88872504dee682))
+
+ - **Versal**
+
+ - check smc_fid 23:16 bits ([4a50363](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4a50363aaeaa16edafcff17486006049b30e1e2f))
+ - fix incorrect regbase for PMC IPI ([c4185d5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c4185d5103080621393edb770a56aa274f9af1a7))
+ - initialize the variable with value 0 in pm code ([cd73d62](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cd73d62b0e0920ca4e6c4fea7ab65bcbd63e07de))
+ - print proper atf handoff source ([0fe002c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0fe002c9be899f005316ea196ad4c6b08815d482))
+ - replace FPD_MAINCCI* macros ([245d30e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/245d30efe617af68c674b411d63c680dca1c21dd))
+ - sync location based on IPI_ID macros ([92a43bd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/92a43bdf366502c6919bbd2c8e4f687c51d9738c))
+
+ - **Versal NET**
+
+ - fix irq for IPI0 ([95bbfbc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/95bbfbc6e0789cba871e2518dba76ff9bf712331))
+ - clear power down bit during wakeup ([5f0f7e4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5f0f7e47e05f98587d424c2162d1ce20af4f588d))
+ - clear power down interrupt status before enable ([2d056db](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2d056db4e4981e0f8a58de0d1e44e46058b308f4))
+ - correct aff level for cpu off ([6ada9dc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6ada9dc325aaa29e2f4c87575093401197856639))
+ - disable wakeup interrupt during client wakeup ([e663f09](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e663f09b3cc2a3c933191c110557c6ffe5db6d6c))
+ - enable wake interrupt during client suspend ([39fffe5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/39fffe552fb04028de750e6080d9a8ba46e89b8c))
+ - fix setting power down state ([1f79bdf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1f79bdfd9ae105135a0192017d6f9368045228e9))
+ - populate gic v3 rdist data statically ([355dc3d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/355dc3d4deacf73a3d354682bcda454e6d13ed66))
+ - resolve misra 10.6 warnings ([8c23775](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8c23775e88bfc4ffa2b0eaf815d4f79992d344e6))
+ - resolve misra rule 20.7 warnings ([21d1966](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/21d1966a23b57425a400730270c8694e37b1a85c))
+ - use spin_lock instead of bakery_lock ([0b3a2cf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0b3a2cf0226878ad7098cc6cd1a97ade74fd9c38))
+
+ - **ZynqMP**
+
+ - add bitmask for get_op_char API ([ad4b667](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ad4b667d3ba7ece4cf28106aef6f91259b5b06ee))
+ - check return status of pm_get_api_version ([c92ad36](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c92ad369ca3a548ecbf30add110b1561fe416c10))
+ - check smc_fid 23:16 bits ([09b342a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/09b342a9d3aa030bde6d52e39203b9b8c8e6b106))
+ - conditional reservation of memory in DTB ([c52a142](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c52a142b7ceb397b4d66cc90f2bc717acc7263cd))
+ - enable A53 workaround(errata 1530924) ([d8133d7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d8133d7785969b417cbace293db6393c55844fac))
+ - fix bl31_zynqmp_setup.c coding style ([26ef5c2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/26ef5c29c62def3a21591dd216180d86063acdb4))
+ - fix DT reserved allocated size ([2c03915](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2c03915322ede112030fcfb8097d4697b92fcc2f))
+ - fix xck24 silicon ID ([f156590](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f156590767d5f80e942fa3f88a9b6a94c13ceb55))
+ - initialize uint32 with value 0U in pm code ([e65584a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e65584a017fadf002d5bdd1e95527c48610a6963))
+ - move EM SMC range to SIP range ([acbae39](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/acbae3998bd829ae4b31ea9da59055e3624991a5))
+ - panic w/o handoff structure in !JTAG ([fbe4dbe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fbe4dbeec906038795f72d8f9284a812bd6a852d))
+ - remove redundant api_version check ([d0b58c8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d0b58c8a9bff3cabfdb59e052ab7eaecfe64b305))
+ - remove unused PLAT_NUM_POWER_DOMAINS ([72c3124](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/72c3124f584609275424bf52a20fd707d4f1af6a))
+ - separate EM from PM SMCs ([a911396](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a9113966c35af281e9c8972b1209646963ff55d0))
+ - update MAX_XLAT_TABLES for DDR memory range ([12446ce](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/12446ce89e351959aebb610eb2e35cdc7eb84d26))
+ - update the conflicting EEMI API IDs ([bcc1348](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bcc1348b6bb2fcd987c8f047fa9f526f32768258))
+ - with DEBUG=1 move bl31 to DDR range ([2537f07](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2537f0725ee7d8f46bef3e5b49134419b5c3367b))
+
+- **Bootloader Images**
+
+ - **BL31**
+
+ - avoid clearing of argument registers in RESET_TO_BL31 case ([3e14df6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3e14df6f63303adb134d525b373ec7f08c1b1dc6))
+
+ - **BL32**
+
+ - **TSP**
+
+ - loop / crash if mmap of region fails ([8c353e0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8c353e0058e95cfa20c9a760ebd0908a9a9aa1c1))
+ - use verbose for power logs ([3354915](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3354915fff2ad5f97551c22a44a90f4ff7b7cc9b))
+
+- **Services**
+
+ - **RME**
+
+ - update sample platform attestation token ([19c1dce](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/19c1dcef88cb837abe175b89739e75e27539a561))
+
+ - **TRP**
+
+ - preserve RMI SMC X4 when not used as return ([b96253d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b96253db08383c3edfb417c505c8da6f7b1dbe75))
+
+ - **RMMD**
+
+ - add missing padding to RMM Boot Manifest and initialize it ([dc0ca64](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dc0ca64e4b6c86090eee025293e7ae7f1fe1cf12))
+
+ - **SPM**
+
+ - **EL3 SPMC**
+
+ - fix coverity scan warnings ([1543d17](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1543d17b9876add1cb89c1f5ffe0e6a129f5809e))
+ - improve bound check for descriptor ([def7590](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/def7590b3e34ff69b297c239cb8948d0bdc9c691))
+ - report execution state in partition info get ([62cd8f3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/62cd8f3147ed7fb146168c59cab3ba0e006210ad))
+
+ - **SPMD**
+
+ - fix build error with spmd ([fd51b21](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fd51b21573ec2e0d815caecb89cc323aac0fca6d))
+
+- **Libraries**
+
+ - **CPU Support**
+
+ - do not put RAS check before using esb ([9ec2ca2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9ec2ca2d453176179f923d7e0fbaac05341ebdc6))
+ - use hint instruction for "tsb csync" ([7a181b7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7a181b7d046a710db5238fb37047816636d2bb8a))
+ - workaround for Cortex-A510 erratum 2684597 ([aea4ccf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/aea4ccf8d9f3eabbc931f0e82df65ffca28c25e5))
+ - workaround for Cortex-A710 erratum 2282622 ([89d85ad](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/89d85ad0aad4fef7f56a9e18968b49e2b843ca9d))
+ - workaround for Cortex-A710 erratum 2768515 ([b87b02c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b87b02cf1d93f2be2113192cd5f1927e33121a80))
+ - workaround for Cortex-A78 erratum 2742426 ([a63332c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a63332c517ac5699644d3e2fbf159d3e35c32549))
+ - workaround for Cortex-A78 erratum 2772019 ([b10afcc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b10afcce5ff1202e1cd922dbd3c1e5980b478429))
+ - workaround for Cortex-A78 erratum 2779479 ([7d1700c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7d1700c4d475358539c9a84cb325183c86a06f33))
+ - workaround for Cortex-A78C erratum 1827430 ([672eb21](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/672eb21e26a41657b8146372d4283e794b430c5f))
+ - workaround for Cortex-A78C erratum 1827440 ([b01a59e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b01a59eb2a0456ca3ae6b8d020068ba846f813d4))
+ - workaround for Cortex-A78C erratum 2772121 ([00230e3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/00230e37e3c21fed4a46eeb69dea9d808f8402b4))
+ - workaround for Cortex-A78C erratum 2779484 ([66bf3ba](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/66bf3ba482e46137e19f368f1386436a33eaba74))
+ - workaround for Cortex-X2 erratum 2282622 ([f9c6301](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f9c6301d743405bd91b9a1fe433ce14fa60a830f))
+ - workaround for Cortex-X2 erratum 2768515 ([1cfde82](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1cfde82227558a8cc1792c068bc7a7cdf8feab43))
+ - workaround for Cortex-X3 erratum 2615812 ([c7e698c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c7e698cfdedbe2b1c8212dd71477f289f7644953))
+ - workaround for Neoverse N2 erratum 2743089 ([1ee7c82](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1ee7c8232c153203d104f148a33e6f641d503f96))
+ - workaround for Neoverse V1 errata 2743233 ([f1c3eae](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f1c3eae9e091a63b42eebae8b03d4d470c9c3f75))
+ - workaround for Neoverse V1 errata 2779461 ([2757da0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2757da06149238041308060e5cb51f0870a02a15))
+ - workaround for Neoverse V1 erratum 2743093 ([31747f0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/31747f057b13b5934b607b7021139e58a55f7766))
+ - workaround platforms non-arm interconnect ([ab062f0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ab062f0510d42b2019667e3f4df82a1f57121412))
+
+ - **EL3 Runtime**
+
+ - allow SErrors when executing in EL3 ([1cbe42a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1cbe42a510812a4a4415a26ba46821cad1c04b68))
+ - do not save scr_el3 during EL3 entry ([e61713b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e61713b00715fc988a970687f9bf53418b81b0ca))
+ - restore SPSR/ELR/SCR after esb ([ff1d2ef](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ff1d2ef387f085fdada4a122284b3b044fdde09c))
+
+ - **RAS**
+
+ - do not put RAS check before esb macro ([7d5036b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7d5036b8ec911d83ede6eb73f1693b6f160d90ed))
+
+ - **FCONF**
+
+ - fix FCONF_ARM_IO_UUID_NUMBER value ([e208f32](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e208f3244b311a23b3e7fa1c03b3e98a6228714a))
+ - make struct fconf_populator static ([40e740d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/40e740dc14e807455d8db99dc758af355aa7fa8f))
+
+ - **OP-TEE**
+
+ - address late comments and fix bad rc ([8d7c80f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8d7c80fa4c5ab17e25d6d82ff0b1e67795e903fb))
+ - return UUID for image loading service ([85ab882](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/85ab88238183be1e27835e14e3588fb73e0f6aa7))
+
+ - **PSCI**
+
+ - do not panic on illegal MPIDR ([8a6d0d2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8a6d0d262ae03db0a0bedd047a2df6f95e8823f6))
+ - potential array overflow with cpu on ([6632741](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/66327414fb1e3248d443f4eb2835f437625fb92c))
+ - remove unreachable switch/case blocks ([ad27f4b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ad27f4b5d918bbd1feb9a2deed3cb0e2ae39616e))
+ - tighten psci_power_down_wfi behaviour ([695a48b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/695a48b5b4366d1005f8b9a0fc83726914668fb5))
+
+ - **GPT**
+
+ - fix compilation error for gpt_rme.c ([a0d5147](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a0d5147b8282374e107461421bb229272fde924b))
+
+ - **SMCCC**
+
+ - check smc_fid [23:17] bits ([f8a3579](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f8a35797b919d8ea041480bd5eb2a334e7056e0b))
+
+ - **C Standard Library**
+
+ - properly define SCHAR_MIN ([06c01b0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/06c01b085fb28fcfe26d747da2ba33415dbd52b9))
+ - remove __putchar alias ([28dc825](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/28dc82580e50961f9b76933b20d576a6afc5035c))
+
+ - **Context Management**
+
+ - enable SCXTNUM access ([01cf14d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/01cf14dd41cae9c68cb5e76a815747a0d2a19a4a))
+
+- **Drivers**
+
+ - **Authentication**
+
+ - avoid out-of-bounds read in auth_nvctr() ([abb8f93](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/abb8f936fd0ad085b1966bdc2cddf040ba3865e3))
+ - forbid junk after extensions ([fd37982](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fd37982a19a4a2911912ce321b9468993a0919ad))
+ - only accept v3 X.509 certificates ([e9e4a2a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e9e4a2a6fd33d8fc21b00cfc9816a3dd3fef47fe))
+ - properly validate X.509 extensions ([f5c5185](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f5c51855d36e399e6e22cc1eb94f6b58e51b3b6d))
+ - reject invalid padding in digests ([f47547b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f47547b35462571636a76b737602e827ae43bc24))
+ - reject junk after certificates ([ca34dbc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ca34dbc0cdb1c4e1ab62aa4dd195cf9389b9edb7))
+ - reject padding after BIT STRING in signatures ([a8c8c5e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a8c8c5ef2a8f5a27772eb708f2201429dd8d32b2))
+ - require at least one extension to be present ([72460f5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/72460f50e2437a85ce5229c430931aab8f4a0d5b))
+ - require bit strings to have no unused bits ([8816dbb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8816dbb3819e626d14e1bb9702f6446cb80e26f0))
+ - use NULL instead of 0 for pointer check ([654b65b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/654b65b36d60a9c08e1d0cd88b35cd7bc2c813af))
+
+ - **mbedTLS**
+
+ - fix mbedtls coverity issues ([a9edc32](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a9edc32c8964ffe047909b4847edd710b5879f35))
+
+ - **Console**
+
+ - correct scopes for console symbols ([03bd481](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/03bd48102b575a9c86eed73866a5f9cd4d03e2d5))
+ - fix crash on spin_unlock with cache disabled ([5fb6946](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5fb6946ad70f5c6e82502a704633bba1dd82e507))
+
+ - **I/O**
+
+ - compare function pointers with NULL ([06d223c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/06d223cb4f54543299b96d40a682e33f9147e192))
+
+ - **MMC**
+
+ - align part config type ([53cbc94](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/53cbc949670877d1b661782ab452f6fac2302ce3))
+ - do not modify r_data in mmc_send_cmd() ([bf78a65](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bf78a6504254be9bf2cee38828a72f84773d4aa7))
+ - explicitly check operators precedence ([14cda51](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/14cda5168de45bbbcce1a5152140111d4fc8fd21))
+ - remove redundant reset_to_idle call ([bc0a738](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bc0a73866f3e4f7138892b228eb592be118b40d2))
+
+ - **GUID Partition Tables Support**
+
+ - add missing curly braces ([1290662](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1290662034578b4e52443c79f34dfd7c284c0435))
+ - add U suffix for unsigned numbers ([d1c6c49](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d1c6c495541b6e387179f987acbef274a12c7535))
+
+ - **SCMI**
+
+ - change function prototype to fix gcc error ([f0f2c90](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f0f2c90365d933ee0a160b4bf5723fc303d9ab73))
+ - fix compilation error in scmi base ([7c38934](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7c3893423d6ba5088f92f4ebdb626285759a1bcd))
+
+ - **UFS**
+
+ - device present (DP) field is set to '1' ([83103d1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/83103d1264fe3cd7d54f3a89121d6889b4d33980))
+ - flush the entire PRDT ([83ef869](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/83ef8698f9d1477c892cad15b4e48574ed634903))
+ - only allow using one slot ([56db7b8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/56db7b8b08d5bb350a02e1f794dc6eb02827917f))
+ - poll UCRDY for all commands ([6e57b2f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6e57b2f00e36e63da765e3aa1650b03772999726))
+ - set the PRDT length field properly ([20fdbcf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/20fdbcf502bd457a4b74ffa9a610d573594f1f6c))
+
+ - **Arm**
+
+ - **Ethos-N**
+
+ - add workaround for erratum 2838783 ([5a89947](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5a89947ab3ef8541b7adb6058af9ef141073043d))
+
+ - **GIC**
+
+ - wrap cache enabled assert under plat_can_cmo ([78fbb0e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/78fbb0ec8372a638b2b2a0276776892141ff43f8))
+
+ - **GICv3**
+
+ - fixed bug in the initialization of GICv3 SGIs/(E)PPIs interrupt priorities ([5d68e89](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5d68e8913ea983b21eb4a1163e6215ff8f8e96e4))
+ - restore scr_el3 after changing it ([1d0d5e4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1d0d5e40206c693e24b0a4de7dbcfc4b79f3138e))
+ - workaround for NVIDIA erratum T241-FABRIC-4 ([a02a45d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a02a45dfef4b02fa363a5f843ba6a0aac52d181f))
+
+ - **RSS**
+
+ - do not consider MHU_ERR_ALREADY_INIT as error ([55a7aa9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/55a7aa9252acfc9712a914e74bcddefc3a8d6390))
+ - fix msg deserialization bugs in comms ([dda0528](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dda052851a78fad150b6565ea4bb75644bd37dce))
+ - remove null-terminator from RSS metadata ([85a14bc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/85a14bc0a9598668c4678f9eda2ba497acba5ced))
+
+ - **NXP**
+
+ - fix fspi coverity issue ([5199b3b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5199b3b93c6ada8dd830f625f77987d3474a6f98))
+ - fix sd secure boot failure ([236ca56](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/236ca5667e8ac82aa53d4e933a78e6ca1ebf456e))
+ - fix tzc380 memory regions config ([07d8e34](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/07d8e34fdd5a81b6fe5f805560be44c1063cea79))
+ - use semicolon instead of comma ([50b8ea1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/50b8ea115f117e17646d73fe7606bee14bd02630))
+
+ - **NXP Crypto**
+
+ - fix coverity issue ([e492299](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e49229911f4e08e317453883886a113f3332b776))
+ - fix secure boot assert inclusion ([334badb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/334badb50f3ad55762785a6ba0266c2eb4d93e8e))
+
+ - **DDR**
+
+ - add checking return value ([e83812f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e83812f11a2d725931de88308c5b520d88bcca86))
+ - apply Max CDD values for warm boot ([00bb8c3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/00bb8c37e0fe57ae2126857ce2d2700106a76884))
+ - fix coverity issue ([2d541cb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2d541cbcbe90217df107e1ac0c4adb76d647b283))
+ - fix underrun coverity issue ([87612ea](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/87612eaefff34548b72fed0d8c93dcf73f9b8c81))
+ - use CDDWW for write to read delay ([fa01056](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fa0105693c85eacf6eda22eca63f220d304f7768))
+
+ - **ST**
+
+ - **Clock**
+
+ - avoid arithmetics on pointers ([4198fa1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4198fa1db7297d8385bb6624d4bd475870e5bf12))
+ - give the size for parent_mp13 and dividers_mp13 tables ([ee21709](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ee21709e98a9e0f60a46d79caf5b702a0b7941cc))
+ - remove useless switch ([69a2e32](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/69a2e320b6798ce3cf5cb27bf70e3384cfac3ebb))
+ - use Boolean type for tests ([c3ae7da](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c3ae7da02dd8b358239dde47c3325e333af81056))
+
+ - **Crypto**
+
+ - move flag control into source code ([6a187a0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6a187a002ee72ef865222870b2ecf99cf4d4efb8))
+ - remove platdata functions ([6b3ca0a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6b3ca0a81723290e2d9b33c406c0e65c1870baa8))
+ - set get_plain_pk_from_asn1() static ([70a422b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/70a422ba83df3f572af1d2931e950feb78592ca3))
+
+ - **GPIO**
+
+ - define shift as uint32_t ([5d942ff](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5d942ff1964131bf33f445f66175fe8211c77e23))
+
+ - **SDMMC2**
+
+ - check transfer size before filling register ([029f81e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/029f81e04c0232843f3e546fa080778a1008a9c5))
+
+ - **ST PMIC**
+
+ - define pmic_regs table size ([3cebeec](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3cebeec2ae452d33ec0cea322f4ab18137e41631))
+ - enclose macro parameter in parentheses ([be7195d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/be7195d06cb7731fe0d906c6eabe6cb6f39f29b1))
+
+ - **Regulator**
+
+ - enclose macro parameters in parentheses ([91af163](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/91af163cbbfab936e70568998e8b9dcb10203b8e))
+ - explicitly check operators precedence ([68083e7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/68083e7ad5ded7adbeca147546bbda6c14cab049))
+ - rework for_each_*rdev macros ([6a3ffb5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6a3ffb53910f136d14ddad5042da01a03e5087c4))
+ - use Boolean type for tests ([9a00daf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9a00daf9dd0a25da45a43142ca27126e6e26a622))
+
+ - **USB**
+
+ - replace redundant checks with asserts ([02af589](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/02af589cfa8d8aefaffeef3390e3fb8fdf51978f))
+
+- **Style**
+
+ - correct some typos ([1b491ee](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1b491eead580d7849a45a38f2c6a935a5d8d1160))
+
+- **Miscellaneous**
+
+ - **AArch64**
+
+ - allow build with ARM_ARCH_MINOR=4 ([78f56ee](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/78f56ee71c9ffe7a6ee36268f0fe1f7ca7d01738))
+
+ - **FDT Wrappers**
+
+ - use correct prototypes ([e0c56fd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e0c56fd71fbd7e8ef307777db8940fb2cf3c9957))
+
+ - **FDTs**
+
+ - **STM32MP1**
+
+ - **STM32MP15**
+
+ - use /omit-if-no-ref/ for spi and i2c ([d480df2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d480df2116fc0d629d52f654bc218ee36251cb33))
+ - use interrupts-extended for i2c2 ([600c8f7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/600c8f7d953d466e0ec5fd04bd6ef2e44c9c9125))
+
+ - **PIE**
+
+ - pass `-fpie` to the preprocessor as well ([966660e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/966660ecd0c8a3d6e4d18a5352bb431e71a9a793))
+
+ - **UUID**
+
+ - add missing `#include` directives ([12562af](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/12562af369e897c67aa45bfeb97cd7bb5d500cf6))
+
+ - add missing click dependency ([ff12683](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ff12683e87e44ead813600fac5415e05e7f95700))
+ - add parenthesis for tests in MIN, MAX and CLAMP macros ([8406db1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8406db14fbba19c25d000eaeab538a0474795da1))
+ - increase BL32 limit ([c2a7612](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c2a76122c88e9ba5de493e1aa765ad170614a31d))
+ - remove old-style declarations ([f4b8470](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f4b8470feee4437fb3984baeee8c61ed91f63f51))
+ - remove useless "return" at void functions ([af4d8c6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/af4d8c6d505c001ee78ea9dd9d8dd76ba039af9b))
+ - unify fallthrough annotations ([e138400](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e138400d1c19a561eaf9f23b0cadc07226684561))
+
+- **Documentation**
+
+ - add a build.tools.python entry ([4052d95](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4052d9583c850feeb8add29734bda0ef0343c238))
+ - add few missed links for Security Advisories ([43f3a9c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/43f3a9c4d67da76a00f9050e7cfe1333da51ff92))
+ - add plantuml as a dependency ([65982a9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/65982a94ef113d5d652d8e1a521b219be75fca42))
+ - add readthedocs configuration file ([8a84776](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8a84776340bf4215d235b7b6dc09cf94aed8c6b3))
+ - deprecate plat_convert_pk() in v2.9 ([e0f58c7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e0f58c7fb685560933e3583cb1dfab8fb2963692))
+ - make required compiler version == rather than >= ([415195c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/415195c03e6e1b3a5335ee242ab4116d2d1ac0b1))
+ - python version must be string ([3aa919e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3aa919eb278e7e0b23742ea043d79e1b1f1d75c6))
+ - specify python version to 3.10 ([a7773c5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a7773c590d0319bdf3b4ddc67c7b22180020224b))
+
+- **Build System**
+
+ - add a default value for INVERTED_MEMMAP ([4d32f91](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4d32f9138d61719bbaab57fdd853877a7e06b1cd))
+ - allow lower address access with gcc-12 ([dea23e2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dea23e245fb890c6c06eff7d1aed8fffa981fc05))
+ - allow warnings when using lld ([ebac692](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ebac6922d1f6fc16c5d3953dfb512553001dcdd3))
+ - partially fix qemu aarch32 build ([c68736d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c68736dab5631af3d9a1d33cb911e90e67e8ee34))
+
+- **Tools**
+
+ - **NXP Tools**
+
+ - fix coverity issue ([4fa0f09](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4fa0f097399c7d396bc14a6692476ada6981c458))
+
+ - **Secure Partition Tool**
+
+ - add dependency to SP image ([4daeaf3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4daeaf341a347a60fd481fb4a1530f18f8e4c058))
+
+ - **Certificate Creation Tool**
+
+ - change WARN to VERBOSE ([76a85cf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/76a85cfa0ab5e7093ad18601b7e73a1e425d8025))
+
+- **Dependencies**
+
+ - add missing aeabi_memset.S ([bdedee5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bdedee5a0f156d05eb62c704e702bfd1c506dc5d))
+
+### New Features
+
+- **Architecture**
+
+ - **Extended Translation Control Register (FEAT_TCR2).**
+
+ - add FEAT_TCR2 to the changelog ([a366640](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a366640cf22d7d0e610564f81e189f6037ff9473))
+ - support FEAT_TCR2 ([d333160](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d3331603664ca7d4ab1510df09e722e6ffb1df29))
+
+ - **CPU feature / ID register handling in general**
+
+ - enable FEAT_SME for FEAT_STATE_CHECKED ([45007ac](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/45007acd46981b9f289f03b283eb53e7ba37bb67))
+ - enable FEAT_SVE for FEAT_STATE_CHECKED ([2b0bc4e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2b0bc4e028a75d75c6d6942ddd404ef331db29be))
+ - extend check_feature() to deal with min/max ([a4cccb4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a4cccb4f6cbbb35d12bd5f8779f3c6d8d762619c))
+
+ - **Guarded Control Stack (FEAT_GCS)**
+
+ - support guarded control stack ([688ab57](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/688ab57b9349adb19277d88f2469ceeadb8ba083))
+
+ - **Support for the `HCRX_EL2` register (FEAT_HCX)**
+
+ - initialize HCRX_EL2 to its default value ([ddb615b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ddb615b419074727ac0a1430cf0f88bd018ac8df))
+
+ - **Scalable Matrix Extension (FEAT_SME, FEAT_SME2)**
+
+ - enable SME2 functionality for NS world ([03d3c0d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/03d3c0d729e24713d657209bedf74d255550babb))
+
+- **Platforms**
+
+ - **Allwinner**
+
+ - add extra CPU control registers ([b15e2cd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b15e2cda14b3ffddebd8b40cc5c31c1c0e9cbf0d))
+ - add function to detect H616 die variant ([fbde260](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fbde260b11171f0f67afbc631e22fe26366ff448))
+ - add support for Allwinner T507 SoC ([018c1d8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/018c1d878fbfd696ebeda52b5188e4658b87bf75))
+
+ - **Arm**
+
+ - add ARM_ROTPK_LOCATION variant full key ([5f89928](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5f899286eac994b8337959ad924a43c1a4a543c9))
+ - carveout DRAM1 area for Event Log ([6b2e961](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6b2e961fb1428c3fe213c524164a00fcaee495c4))
+
+ - **FVP**
+
+ - add Event Log maximum size property in DT ([1cf3e2f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1cf3e2f0a8eb0d6324ce3db68dd5c78bdb690a8a))
+ - copy the Event Log to TZC secured DRAM area ([191aa5d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/191aa5d3fc793c5c4cd8960d1ef7b95010cc9d87))
+ - define ns memory in the SPMC manifest ([7f28179](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7f28179a46b40ede461326dd329eb832c0d72b0d))
+ - emulate trapped RNDR ([1ae7552](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1ae75529bc2e5a213c3e458898c219c34aa99f65))
+ - enable errata management interface ([d3bed15](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d3bed15851a1b35b2608f7275f1294c8d4f7aee7))
+ - enable FEAT_FGT by default ([15107da](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/15107daad6b83b4ee1edfebf420b6779a054318e))
+ - enable FEAT_HCX by default ([2e12418](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2e1241888ee82a5a9b3b30acd83a1f4ea6732f1b))
+ - enable support for PSCI OS-initiated mode ([e75cc24](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e75cc247c744d21e52f834a442bf1c26d0ab6161))
+ - increase BL1_RW and BL2 size ([dbb9c1f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dbb9c1f5b69134ca43c944d84b413331a64fba15))
+ - introduce PLATFORM_TEST_EA_FFH config ([fe38cc6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fe38cc68975b23084b4ba512254926941c865a07))
+ - introduce PLATFORM_TEST_RAS_FFH config ([5602ce1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5602ce1d8db3256a7766776cb908b1f716c2d463))
+ - update device tree with load addresses of TOS_FW config ([1779762](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/177976286e347acd905d8082f31c201b9900d28e))
+
+ - **Juno**
+
+ - support ARM_IO_IN_DTB option for Juno ([2fad320](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2fad320f5623edcdd23297ab57c4b9b0b0ef872c))
+
+ - **Morello**
+
+ - add GPU DT node ([cd94c3d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cd94c3d6ad5e738c2583486b7a973bd8e516089b))
+ - add support for HW_CONFIG ([be79071](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/be79071ef73b4b08cca310ec7e7d915faea8f036))
+ - implement methods to retrieve soc-id information ([cc266bc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cc266bcd8c0a1d839151b69436fdf2c1ad07b0a1))
+
+ - **RD**
+
+ - **RD-N2**
+
+ - add platform id value for rdn2 variant 3 ([028c619](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/028c6190d9f3d892a84b5b9cbfdbbab808a73acb))
+
+ - **TC**
+
+ - enable MPAM functionality of L3 DSU cache ([b45ec8c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b45ec8cea483a38e358146b99205504ff7f98001))
+ - add delegated attest and measurement tests ([25dd217](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/25dd2172ae564c74b7e8b42aa96d5ee9a865ec75))
+ - allow secure watchdog timer to trigger periodically ([28b2d86](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/28b2d86cd28ffc54c6272defcd6f123a925012f1))
+ - use smmu 700 ([ed80eab](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ed80eab6a686ce1042300cfbdb90e13366aa08d4))
+
+ - **Intel**
+
+ - extending to support SMMU in FCS ([4687021](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4687021d2eedea880ad8596b32e85da72f8cba02))
+ - fix bridge disable and reset ([9ce8251](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9ce82519c65f0dd93d2673ebb967d02f52b19a04))
+ - implement timer init divider via CPU frequency for N5X ([02a9d70](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/02a9d70c4deaa2102386611ac6b305838003148d))
+ - setup FPGA interface for Agilex ([3905f57](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3905f57134853f47f6e859b8b6322a7dbbfc49f7))
+
+ - **MediaTek**
+
+ - add APU init flow ([5243091](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5243091633b8fe8057cec176ac31adb72fdf3506))
+ - add new features of LPM ([917abdd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/917abdd99012d01ef4fa804ecec1503bef68ed9b))
+ - add SiP service for OP-TEE ([621eaab](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/621eaab5cc3c9d98783700b7515b1da118b3d21c))
+ - add SMC handler for EMI MPU ([c842cc0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c842cc0e5d1432a681cbddce62a852ff282169ae))
+ - add SPM's SSPM notifier ([c234ad1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c234ad17d7d7278e1afa0f416982bb0f60a04dcf))
+
+ - **MT8188**
+
+ - add apu power on/off control ([8e38b92](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8e38b928490516d308bdceebc4ad032852bf2716))
+ - add MT8188 SPM debug logs ([f85b34b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f85b34b112eec006c14afab0eadbd45d1b0d0e7e))
+ - add MT8188 SPM support ([45d5075](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/45d507599e213f8f3a26502c3ca8de6b1cfdc611))
+ - add SPM feature support ([f299efb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f299efbea685aa8075ec4d6d0f70d189cce3ee07))
+ - add the register definitions accessed by SPM ([1a64689](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1a64689df5e7bf78aa8724c1d75f414ea62750eb))
+ - enable SPM and LPM ([380f64b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/380f64b2e39c60cb9a1f751b25cbce11c5e03e20))
+ - keep infra and peri on when system suspend ([e56a939](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e56a939cabb5ae0fe967c19ddacf97304c563f37))
+ - update INFRA IOMMU enable flow ([98415e1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/98415e1a80ca025a000241cf3fc175272890c0e8))
+
+ - **MT8195**
+
+ - add support for SMC from OP-TEE ([ccc61e1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ccc61e10029b8ddfcb5cb65201862a18ebbc953d))
+
+ - **NVIDIA**
+
+ - **Tegra**
+
+ - implement 'pwr_domain_off_early' handler ([96d07af](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/96d07af402a5d191b7d1200a75c1b206f21cc395))
+
+ - **NXP**
+
+ - **i.MX**
+
+ - **i.MX 8M**
+
+ - add more dram pll setting ([4234b90](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4234b902ae37ca05640888e31405ec97c8cde316))
+ - fix the ddr4 dvfs random hang on imx8m ([093888c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/093888caaf54cbfe38d4b68406d98fbcf5c7d81f))
+ - update the ddr4 dvfs flow to include ddr3l support ([0e39488](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0e39488ff3f2edac04d7f5acb58d9a22baa3a69e))
+ - use non-fast wakeup stop mode for system suspend ([ef4e5f0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ef4e5f0f105f184f02ad4d1cc17cecec9b45502a))
+
+ - **i.MX 8Q**
+
+ - add anamix pll override setting for DSM mode ([387a1df](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/387a1df18e0b5bf1d305c72df284b1b89f3c1cd3))
+ - add BL31 PIE support ([8cfa94b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8cfa94b7a7fc398cc0ea803891f6277065bb7575))
+ - add the dram retention support for imx8mq ([dd108c3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dd108c3c1fe3f958a38ae255e57b41e5453d077f))
+ - add version for B2 ([99475c5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/99475c5dcc14123dda51bda32d21753f0b4c357d))
+ - add workaround code for ERR11171 on imx8mq ([88a2646](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/88a264657fad2f71369fec4b53478e8a595d10e9))
+ - always set up console ([36be108](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/36be10861e851e7e4df06bb08aab60d8e878d2b2))
+ - correct the slot ack setting for STOP mode ([724ac3e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/724ac3e2c23441d11f642f2ae91c8a8834ea179f))
+ - enable dram dvfs support on imx8mq ([8962bdd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8962bdd603508f649fd7a332e580c0e456ccc0ad))
+ - make IMX_BOOT_UART_BASE configurable via build parameter ([202737e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/202737efda85b2ea61934123b8ffa492f5dc3679))
+ - remove empty bl31_plat_runtime_setup ([7698dba](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7698dbab96072881e0912322db5036529bf8553c))
+
+ - **i.MX 8**
+
+ - add support for debug uart on lpuart1 ([8406447](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8406447f13c65fe93aab7ed641b7e8fe3eb47a0b))
+
+ - **Layerscape**
+
+ - **LX2**
+
+ - enable OCRAM ECC ([e8faff3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e8faff3da962ce112e32d8f1fdb8155e078eae75))
+ - support more variants ([c07f5e9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c07f5e9e50959a3667e5a96ac808d1d16bb72698))
+
+ - **QEMU**
+
+ - add "neoverse-n1" cpu support ([226f4c8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/226f4c8e35c4441e80ad523b9105eab4ca630396))
+ - add A76/N1 cpu support for virt ([6b66693](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6b66693685f828a51c7f78bfa402d6b192169a6d))
+ - combine TF-A artefacts into ROM file ([63bb905](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/63bb90569792893a4e7401004c23cde488fda0cc))
+ - increase max cpus per cluster to 16 ([73a7aca](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/73a7aca2a53d4dbb62909c5741830eee9eac5ee8))
+ - increase size of bl2 ([db2bf3a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/db2bf3ac193f66f365b962b911e7bb2ffbde0a25))
+ - make coherent memory section optional ([af994ae](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/af994ae8a089ead6082ca82036d30074f554ed52))
+ - support el3 spmc ([302f053](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/302f05354f5aab340c315e0d04915367c65c6b27))
+ - support pointer authentication ([cffc956](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cffc956edf3a14508ed5740c1ed093326ca67e72))
+ - support s-el2 spmc ([36802e2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/36802e2c792f79ab630b53298dfd4f1e5a95d173))
+ - update abi between spmd and spmc ([25ae7ad](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/25ae7ad1878244f78206cc7c91f7bdbd267331a1))
+
+ - **QTI**
+
+ - **SC7280**
+
+ - add support for PSCI_OS_INIT_MODE ([e528bbe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e528bbec74af359714203c7f8d356074733ea9cd))
+
+ - **MSM8916**
+
+ - expose more timer frames ([1781bf1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1781bf1c40594e3a3f36404da793d5c7a6bca533))
+
+ - **ST**
+
+ - mandate dtc version 1.4.7 ([38ac8bb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/38ac8bbbe450343e8545a44f370ff9da57cbed26))
+
+ - **STM32MP1**
+
+ - add mbedtls-3.3 support config ([c9498c8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c9498c8f56387ad23530dcc6e57940d2b118d907))
+
+ - **Texas Instruments**
+
+ - add PSCI system_off support ([0bdef26](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0bdef264c2bd356e2a89fc5ac7c438694618d272))
+ - add sub and patch version number support ([852378f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/852378fd60d8cc536799639774f1e4ffe124131d))
+ - disable L2 dataless UniqueClean evictions ([10d5cf1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/10d5cf1b26f03d61a90cdcff5163965fa48e291c))
+ - do not handle EAs in EL3 ([2fcd408](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2fcd408bb3a6756767a43c073c597cef06e7f2d5))
+ - set L2 cache data ram latency on A72 cores to 4 cycles ([aee2f33](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/aee2f33a675891f660fc0d06e739ce85f3472075))
+ - set L2 cache ECC and and parity on A72 cores ([81858a3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/81858a353f8e45f5cc57ce855188043b1745ea08))
+ - set snoop-delayed exclusive handling on A72 cores ([5668db7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5668db72b724dc256d9b300f6938a08625624a48))
+ - synchronize access to secure proxy threads ([312eec3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/312eec3ecde9837f61fc0d7b46b4197ec2257ee7))
+
+ - **Xilinx**
+
+ - add device node indexes ([407eb6f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/407eb6fda06d7be034dc7f1c537183f64126f074))
+ - sync copyright format ([2774965](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/27749653c7dbea1bd5b34a39085bc7cb12d46501))
+
+ - **Versal**
+
+ - replace irq array with switch case ([0ec6c31](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0ec6c31320c6d86e89dce8775af2bbdfa7a302fa))
+ - switch to xlat_v2 ([0e9f54e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0e9f54e5bb7f4b44bca9c63cce37913070fea23a))
+
+ - **Versal NET**
+
+ - add jtag dcc support ([30e8bc3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/30e8bc365c1007da97f93c71e5fa16b6be56b679))
+ - add support for set wakeup source ([c38d90f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c38d90f7964ddf186f4cbaad6da91dd0a44627e3))
+ - add support for uart1 console ([2f1b4c5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2f1b4c55502262dba0ccd147f87cdb38cf4131f2))
+
+ - **ZynqMP**
+
+ - add hooks for custom runtime setup ([88a8938](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/88a8938e62989b7319b20c46c046aa8845852ce9))
+ - add hooks for mmap and early setup ([7013400](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/70134000842cbc7c052031dd453bdec8f4cb73f1))
+ - add SMCCC_ARCH_SOC_ID support ([8f9ba3f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8f9ba3f344545740fc44e90fb8322c7728ae94ec))
+ - add support for custom sip service ([496d708](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/496d708154d893fb9f412390acd433337faccecc))
+ - build pm code as library ([3af2ee9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3af2ee906842378ee91f07aa4ea5565cd1a0f8c2))
+ - bump up version of query_data API ([aaf5ce7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/aaf5ce77fb22f54a8ca7bc8d3be6172dacbfc0c1))
+ - make stack size configurable ([5753665](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/57536653e62765f9529d045b118ad881369bc73a))
+
+- **Services**
+
+ - **RME**
+
+ - read DRAM information from FVP DTB ([8268590](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/826859049859a5bd88e142695e10a559d85721c1))
+ - set DRAM information in Boot Manifest platform data ([a97bfa5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a97bfa5ff18b2682e3b9c528cbd5fb16ceec3393))
+
+ - **RMM**
+
+ - add support for the 2nd DRAM bank ([346cfe2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/346cfe2b46a83bc9e6656f43ec55a196503b154a))
+
+ - **SPM**
+
+ - **EL3 SPMC**
+
+ - make platform logical partition optional ([555677f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/555677fe81c5e1888254ac36acb0a02b3850dc46))
+
+ - **SPMD**
+
+ - add support for FFA_EL3_INTR_HANDLE_32 ABI ([6671b3d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6671b3d8224a8c4c3fea7cbe66b56945c432393f))
+ - copy tos_fw_config in secure region ([0cea2ae](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0cea2ae07db089e60322677021da4743a084f9ca))
+ - fail safe if SPM fails to initialize ([0d33649](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0d33649e3e2a21def73327522b9861b4619fc5c2))
+ - introduce FFA_PARTITION_INFO_GET_REGS ([eaaf517](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/eaaf517cd1bd8c9d5e3e6d2d202a69a0cbcb45bf))
+ - introduce platform handler for Group0 interrupt ([f0b64e5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f0b64e507e9105813d9a5d16f70101cf0d8ca5a4))
+ - map SPMC manifest region as EL3_PAS ([8c829a9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8c829a9240109dd7a66a3c26f734f23477b12551))
+ - register handler for group0 interrupt from NWd ([a1e0e87](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a1e0e871f10201a9dbdc1dadfd27904888246adc))
+
+ - **ERRATA_ABI**
+
+ - errata management firmware interface ([ffea384](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ffea3844c00daf8dee466840a4932cac04b3eb57))
+
+- **Libraries**
+
+ - **CPU Support**
+
+ - add support for blackhawk cpu ([6578343](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6578343bb2aab6ec5ae309097047a83445aa12da))
+ - add support for chaberton cpu ([516a52f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/516a52f6f5cda6acb311ffd6e8fb77f2e09c1357))
+
+ - **EL3 Runtime**
+
+ - handle traps for IMPDEF registers accesses ([0ed3be6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0ed3be6fc2c8d275862959d1ee6a0354cc01ad5d))
+ - introduce system register trap handler ([ccd81f1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ccd81f1e097c3eafe38523110c8eebabbe662508))
+
+ - **FCONF**
+
+ - rename 'ns-load-address' to 'secondary-load-address' ([05e5503](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/05e550302103a527b9f8d3869942c203c7b2dd65))
+
+ - **OP-TEE**
+
+ - add device tree for coreboot table ([f4bbf43](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f4bbf435554e87de31c0a70039aa03b19962aaea))
+ - add loading OP-TEE image via an SMC ([05c69cf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/05c69cf75edf53478e23fce157fea72372b49597))
+
+ - **PSCI**
+
+ - add support for OS-initiated mode ([606b743](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/606b7430077c15695a5b3bcfbad4975f00c9bf95))
+ - add support for PSCI_SET_SUSPEND_MODE ([b88a441](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b88a4416b5e5f2bda2240c632ba79e15a9a75c45))
+ - introduce 'pwr_domain_off_early' hook ([6cf4ae9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6cf4ae979a5f8be23927b97ecfe789dabcb53dbd))
+ - update PSCI_FEATURES ([9a70e69](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9a70e69e059863d7aec11883e6345b54058264e0))
+
+ - **C Standard Library**
+
+ - add %c to printf/snprintf ([44d9706](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/44d9706e5428d8e3588d04565c7cd738ffc1e472))
+ - add support for fallthrough statement ([023f1be](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/023f1bed1dde23564e3b66a99c4a45b09e38992b))
+
+ - **PSA**
+
+ - add read_measurement API ([6d0525a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6d0525aafe17e7affb0f71e86a5121989c150c42))
+ - interface with RSS for NV counters ([8374508](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8374508b00909cdffbe6233cf8fddcb49924faed))
+
+- **Drivers**
+
+ - **Authentication**
+
+ - compare platform and certificate ROTPK for authentication ([f1e693a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f1e693a77548950cfffcb1d5a4b67cf349e0aed9))
+
+ - **mbedTLS**
+
+ - add support for mbedtls-3.3 ([51e0615](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/51e061591bbf13af2486c3bb5f37ed609578d145))
+
+ - **UFS**
+
+ - adds timeout and error handling ([2c5bce3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2c5bce3833848dac4fbb2ae19be418145e68c8a1))
+
+ - **Arm**
+
+ - **Ethos-N**
+
+ - add check for NPU in SiP setup ([a2cdbb1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a2cdbb1df088cde410aea1d5989dfc500aaf7939))
+ - add event and aux control support ([7820777](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7820777fa3c8ca454ab40d5d8a8ba0e311bbb6f9))
+ - add multiple asset allocators ([8a921e3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8a921e354575cd16aaa6f2f5a2aeaaaea35ab886))
+ - add NPU firmware validation ([313b776](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/313b776f851ed184abb265df2b6269fe78f48ecd))
+ - add NPU sleeping SMC call ([2a2e3e8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2a2e3e87706b56fd1b8e787d3a552cfc12725934))
+ - add NPU support in fiptool ([c91b08c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c91b08c8a44aafac4f72c64aa8d4777b8c73647e))
+ - add protected NPU firmware setup ([6dcf3e7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6dcf3e774457cf00b91abda715adfbefce822877))
+ - add protected NPU TZMP1 regions ([d77c11e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d77c11e896e04be93caa4a56e50646af6806843f))
+ - add reserved memory address support ([a19a024](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a19a0241a6f1573e11d4d747dabb756d15ac4801))
+ - add reset type to reset SMC calls ([fa37d30](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fa37d30856fef6742bd82e4e0a3252a4d0b9e091))
+ - add separate RO and RW NSAIDs ([986c4e9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/986c4e991ace5cb40bed35145184e66863c47152))
+ - add SMC call to get FW properties ([e9812dd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e9812ddca6e72c0501ef1e84753f335dcafb74cd))
+ - add stream extends and attr support ([e64abe7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e64abe7bdaeed99093ae5b4aab8956a04ff4075a))
+ - add support for NPU to cert_create ([f309607](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f309607229e049a6ff9cbc858efa4dd0c0b921b8))
+ - add support to set up NSAID ([70a296e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/70a296ee8641802dc60754aec5b18d8347820a5c))
+ - load NPU firmware at BL2 ([33bcaed](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/33bcaed1211ab27968433b546979687bc1182630))
+
+ - **GIC**
+
+ - **GICv3**
+
+ - enlarge the range for intr_num of structure interrupt_prop_t ([d5eee8f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d5eee8f3fbf53fce84c979e68433a27c93e3e96b))
+
+ - **RSS**
+
+ - add TC platform UUIDs for RSS images ([6ef63af](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6ef63af65f55e9402e4cdc534928faceb9c6e003))
+
+ - **SBSA**
+
+ - helper api for refreshing watchdog timer ([e8166d3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e8166d3e5937b8db43921b5049672b16af7f58e0))
+
+- **Miscellaneous**
+
+ - **AArch64**
+
+ - make ID system register reads non-volatile ([c2fb8ef](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c2fb8ef66ccc8222c70ab802cdaf29f1592cbbb6))
+
+ - **FDTs**
+
+ - **STM32MP1**
+
+ - use /omit-if-no-ref/ for pins nodes ([0aae96c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0aae96cfb9ef826d207f2d18d4a9f21fa1a5dee7))
+
+ - **STM32MP15**
+
+ - add support for prtt1x board family ([3812ceb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3812ceba8fcd682faeed6e71190a848771fd2022))
+
+ - **PIE/POR**
+
+ - support permission indirection and overlay ([062b6c6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/062b6c6bf23f9656332b0aa3fed59c15f34f9361))
+
+- **Documentation**
+
+ - allow verbose build ([f771a34](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f771a3446356d92c6c27df5c4f3bb07a2561b36b))
+
+- **Build System**
+
+ - add support for new binutils versions ([1f49db5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1f49db5f25cdd4e43825c9bcc0575070b80f628c))
+ - allow additional CFLAGS for library build ([5a65fcd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5a65fcd5f9c67baa681f664e4596760ca1f2606a))
+
+ - **Git Hooks**
+
+ - add pre-commit hook ([cf9346c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cf9346cb83804feb083b56a668eb0a462983e038))
+
+ - add support for poetry ([793f72c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/793f72c06ca1c2782f800c9f20980ca6b7870072))
+
+- **Tools**
+
+ - **Firmware Image Package Tool**
+
+ - handle FIP in a disk partition ([06e69f7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/06e69f7c94637c693ea5eb26038096c196d10f07))
+
+- **Dependencies**
+
+ - **Compiler runtime libraries**
+
+ - update source files ([658ce7a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/658ce7ad8eceb40741cd40f1639a6d923f922fad))
+
## [2.8.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.7.0..refs/tags/v2.8.0) (2022-11-15)
### ⚠ BREAKING CHANGES
@@ -3580,7 +4598,7 @@
- Platforms
- Arm
- - Fixed missing copyrights in arm-gic.h file
+ - Fixed missing copyrights in Arm-gic.h file
- Fixed the order of header files in several dts files
- Fixed error message printing in board makefile
- Fixed bug of overriding the last node in image load helper API
@@ -6842,7 +7860,7 @@
______________________________________________________________________
-*Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.*
[mbed tls releases]: https://tls.mbed.org/tech-updates/releases
[pr#1002]: https://github.com/ARM-software/arm-trusted-firmware/pull/1002#issuecomment-312650193
diff --git a/docs/components/ras.rst b/docs/components/ras.rst
index 871be2d..8d00345 100644
--- a/docs/components/ras.rst
+++ b/docs/components/ras.rst
@@ -1,45 +1,89 @@
Reliability, Availability, and Serviceability (RAS) Extensions
-==============================================================
+**************************************************************
This document describes |TF-A| support for Arm Reliability, Availability, and
Serviceability (RAS) extensions. RAS is a mandatory extension for Armv8.2 and
later CPUs, and also an optional extension to the base Armv8.0 architecture.
-In conjunction with the |EHF|, support for RAS extension enables firmware-first
-paradigm for handling platform errors: exceptions resulting from errors in
-Non-secure world are routed to and handled in EL3.
-Said errors are Synchronous External Abort (SEA), Asynchronous External Abort
-(signalled as SErrors), Fault Handling and Error Recovery interrupts.
-The |EHF| document mentions various :ref:`error handling
-use-cases <delegation-use-cases>` .
-
For the description of Arm RAS extensions, Standard Error Records, and the
precise definition of RAS terminology, please refer to the Arm Architecture
-Reference Manual. The rest of this document assumes familiarity with
-architecture and terminology.
+Reference Manual and `RAS Supplement`_. The rest of this document assumes
+familiarity with architecture and terminology.
+
+There are two philosophies for handling RAS errors from Non-secure world point
+of view.
+
+- :ref:`Firmware First Handling (FFH)`
+- :ref:`Kernel First Handling (KFH)`
+
+.. _Firmware First Handling (FFH):
+
+Firmware First Handling (FFH)
+=============================
+
+Introduction
+------------
+
+EA’s and Error interrupts corresponding to NS nodes are handled first in firmware
+
+- Errors signaled back to NS world via suitable mechanism
+- Kernel is prohibited from accessing the RAS error records directly
+- Firmware creates CPER records for kernel to navigate and process
+- Firmware signals error back to Kernel via SDEI
Overview
--------
+FFH works in conjunction with `Exception Handling Framework`. Exceptions resulting from
+errors in Non-secure world are routed to and handled in EL3. Said errors are Synchronous
+External Abort (SEA), Asynchronous External Abort (signalled as SErrors), Fault Handling
+and Error Recovery interrupts.
+RAS Framework in TF-A allows the platform to define an external abort handler and to
+register RAS nodes and interrupts. It also provides `helpers`__ for accessing Standard
+Error Records as introduced by the RAS extensions
+
-As mentioned above, the RAS support in |TF-A| enables routing to and handling of
-exceptions resulting from platform errors in EL3. It allows the platform to
-define an External Abort handler, and to register RAS nodes and interrupts. RAS
-framework also provides `helpers`__ for accessing Standard Error Records as
-introduced by the RAS extensions.
.. __: `Standard Error Record helpers`_
+.. _Kernel First Handling (KFH):
+
+Kernel First Handling (KFH)
+===========================
+
+Introduction
+------------
+
-The build option ``RAS_EXTENSION`` when set to ``1`` includes the RAS in run
-time firmware; ``EL3_EXCEPTION_HANDLING`` and ``HANDLE_EA_EL3_FIRST_NS`` must also
-be set ``1``. ``RAS_TRAP_NS_ERR_REC_ACCESS`` controls the access to the RAS
-error record registers from Non-secure.
+EA's originating/attributed to NS world are handled first in NS and Kernel navigates
+the std error records directly.
+
+**KFH can be supported in a platform without TF-A being aware of it but there are few
+corner cases where TF-A needs to have special handling, which is currently missing and
+will be added in future**
+
+TF-A build options
+==================
+
+- **ENABLE_FEAT_RAS**: Manage FEAT_RAS extension when switching the world.
+- **RAS_FFH_SUPPORT**: Pull in necessary framework and platform hooks for Firmware first
+ handling(FFH) of RAS errors.
+- **RAS_TRAP_NS_ERR_REC_ACCESS**: Trap Non-secure access of RAS error record registers.
+- **RAS_EXTENSION**: Deprecated macro, equivalent to ENABLE_FEAT_RAS and RAS_FFH_SUPPORT
+ put together.
+
+RAS feature has dependency on some other TF-A build flags
+
+- **EL3_EXCEPTION_HANDLING**: Required for FFH
+- **HANDLE_EA_EL3_FIRST_NS**: Required for FFH
+- **FAULT_INJECTION_SUPPORT**: Required for testing RAS feature on fvp platform
+
+RAS Framework
+=============
+
.. _ras-figure:
.. image:: ../resources/diagrams/draw.io/ras.svg
-See more on `Engaging the RAS framework`_.
-
Platform APIs
-------------
@@ -191,19 +235,10 @@
Engaging the RAS framework
--------------------------
-Enabling RAS support is a platform choice constructed from three distinct, but
-related, build options:
-
-- ``RAS_EXTENSION=1`` includes the RAS framework in the run time firmware;
-
-- ``EL3_EXCEPTION_HANDLING=1`` enables handling of exceptions at EL3. See
- `Interaction with Exception Handling Framework`_;
-
-- ``HANDLE_EA_EL3_FIRST_NS=1`` enables routing of External Aborts and SErrors,
- resulting from errors in NS world, to EL3.
+Enabling RAS support is a platform choice
The RAS support in |TF-A| introduces a default implementation of
-``plat_ea_handler``, the External Abort handler in EL3. When ``RAS_EXTENSION``
+``plat_ea_handler``, the External Abort handler in EL3. When ``RAS_FFH_SUPPORT``
is set to ``1``, it'll first call ``ras_ea_handler()`` function, which is the
top-level RAS exception handler. ``ras_ea_handler`` is responsible for iterating
to through platform-supplied error records, probe them, and when an error is
@@ -239,4 +274,6 @@
--------------
-*Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.*
+
+.. _RAS Supplement: https://developer.arm.com/documentation/ddi0587/latest
diff --git a/docs/components/secure-partition-manager.rst b/docs/components/secure-partition-manager.rst
index 871e02b..d4f0b00 100644
--- a/docs/components/secure-partition-manager.rst
+++ b/docs/components/secure-partition-manager.rst
@@ -463,8 +463,15 @@
- *cpus* node provide the platform topology and allows MPIDR to VMPIDR mapping.
Note the primary core is declared first, then secondary cores are declared
in reverse order.
-- The *memory* node provides platform information on the ranges of memory
- available to the SPMC.
+- The *memory* nodes provide platform information on the ranges of memory
+ available for use by SPs at runtime. These ranges relate to either
+ secure or non-secure memory, depending on the *device_type* field.
+ If the field specifies "memory" the range is secure, else if it specifies
+ "ns-memory" the memory is non-secure. The system integrator must exclude
+ the memory used by other components that are not SPs, such as the monitor,
+ or the SPMC itself, the OS Kernel/Hypervisor, or other NWd VMs. The SPMC
+ limits the SP's address space such that they do not access memory outside
+ of those ranges.
SPMC boot
~~~~~~~~~
@@ -564,7 +571,12 @@
- Memory regions are mapped in the SP EL1&0 Stage-2 translation regime at
load time (or EL1&0 Stage-1 for an S-EL1 SPMC). A memory region node can
specify RX/TX buffer regions in which case it is not necessary for an SP
- to explicitly invoke the ``FFA_RXTX_MAP`` interface.
+ to explicitly invoke the ``FFA_RXTX_MAP`` interface. The memory referred
+ shall be contained within the memory ranges defined in SPMC manifest. The
+ NS bit in the attributes field should be consistent with the security
+ state of the range that it relates to. I.e. non-secure memory shall be
+ part of a non-secure memory range, and secure memory shall be contained
+ in a secure memory range of a given platform.
- Device regions are mapped in the SP EL1&0 Stage-2 translation regime (or
EL1&0 Stage-1 for an S-EL1 SPMC) as peripherals and possibly allocate
additional resources (e.g. interrupts).
@@ -1031,6 +1043,68 @@
This is used in particular to convey power management messages.
+Memory Sharing
+--------------
+
+Hafnium implements the following memory sharing interfaces:
+
+ - ``FFA_MEM_SHARE`` - for shared access between lender and borrower.
+ - ``FFA_MEM_LEND`` - borrower to obtain exclusive access, though lender
+ retains ownership of the memory.
+ - ``FFA_MEM_DONATE`` - lender permanently relinquishes ownership of memory
+ to the borrower.
+
+The ``FFA_MEM_RETRIEVE_REQ`` interface is for the borrower to request the
+memory to be mapped into its address space: for S-EL1 partitions the SPM updates
+their stage 2 translation regime; for S-EL0 partitions the SPM updates their
+stage 1 translation regime. On a successful call, the SPMC responds back with
+``FFA_MEM_RETRIEVE_RESP``.
+
+The ``FFA_MEM_RELINQUISH`` interface is for when the borrower is done with using
+a memory region.
+
+The ``FFA_MEM_RECLAIM`` interface is for the owner of the memory to reestablish
+its ownership and exclusive access to the memory shared.
+
+The memory transaction descriptors are transmitted via RX/TX buffers. In
+situations where the size of the memory transaction descriptor exceeds the
+size of the RX/TX buffers, Hafnium provides support for fragmented transmission
+of the full transaction descriptor. The ``FFA_MEM_FRAG_RX`` and ``FFA_MEM_FRAG_TX``
+interfaces are for receiving and transmitting the next fragment, respectively.
+
+If lender and borrower(s) are SPs, all memory sharing operations are supported.
+
+Hafnium also supports memory sharing operations between the normal world and the
+secure world. If there is an SP involved, the SPMC allocates data to track the
+state of the operation.
+
+The SPMC is also the designated allocator for the memory handle. The hypervisor
+or OS kernel has the possibility to rely on the SPMC to maintain the state
+of the operation, thus saving memory.
+A lender SP can only donate NS memory to a borrower from the normal world.
+
+The SPMC supports the hypervisor retrieve request, as defined by the FF-A
+v1.1 EAC0 specification, in section 16.4.3. The intent is to aid with operations
+that the hypervisor must do for a VM retriever. For example, when handling
+an FFA_MEM_RECLAIM, if the hypervisor relies on SPMC to keep the state
+of the operation, the hypervisor retrieve request can be used to obtain
+that state information, do the necessary validations, and update stage 2
+memory translation.
+
+Hafnium also supports memory lend and share targetting multiple borrowers.
+This is the case for a lender SP to multiple SPs, and for a lender VM to
+multiple endpoints (from both secure world and normal world). If there is
+at least one borrower VM, the hypervisor is in charge of managing its
+stage 2 translation on a successful memory retrieve.
+The semantics of ``FFA_MEM_DONATE`` implies ownership transmission,
+which should target only one partition.
+
+The memory share interfaces are backwards compatible with memory transaction
+descriptors from FF-A v1.0. These get translated to FF-A v1.1 descriptors for
+Hafnium's internal processing of the operation. If the FF-A version of a
+borrower is v1.0, Hafnium provides FF-A v1.0 compliant memory transaction
+descriptors on memory retrieve response.
+
PE MMU configuration
--------------------
@@ -1320,6 +1394,25 @@
direct request to SP2 by invoking FFA_RUN.
- 9) SPMC resumes the pre-empted vCPU of SP2.
+EL3 interrupt handling
+~~~~~~~~~~~~~~~~~~~~~~
+
+In GICv3 based systems, EL3 interrupts are configured as Group0 secure
+interrupts. Execution traps to SPMC when a Group0 interrupt triggers while an
+SP is running. Further, SPMC running at S-EL2 uses FFA_EL3_INTR_HANDLE ABI to
+request EL3 platform firmware to handle a pending Group0 interrupt.
+Similarly, SPMD registers a handler with interrupt management framework to
+delegate handling of Group0 interrupt to the platform if the interrupt triggers
+in normal world.
+
+ - Platform hook
+
+ - plat_spmd_handle_group0_interrupt
+
+ SPMD provides platform hook to handle Group0 secure interrupts. In the
+ current design, SPMD expects the platform not to delegate handling to the
+ NWd (such as through SDEI) while processing Group0 interrupts.
+
Power management
----------------
@@ -1559,4 +1652,4 @@
--------------
-*Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2020-2023, Arm Limited and Contributors. All rights reserved.*
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 0f1f92a..758d62b 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -317,6 +317,11 @@
CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and
it is still open.
+- ``ERRATA_A78_2712571``: This applies erratum 2712571 workaround to Cortex-A78
+ CPU, this erratum affects system configurations that do not use an ARM
+ interconnect IP. This needs to be enabled for revisions r0p0, r1p0, r1p1
+ and r1p2 and it is still open.
+
- ``ERRATA_A78_2742426``: This applies erratum 2742426 workaround to Cortex-A78
CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and
it is still open.
@@ -347,6 +352,11 @@
Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
erratum is still open.
+- ``ERRATA_A78_AE_2712574`` : This applies erratum 2712574 workaround to
+ Cortex-A78 AE CPU. This erratum affects system configurations that do not use
+ an ARM interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and
+ r0p2. This erratum is still open.
+
For Cortex-A78C, the following errata build flags are defined :
- ``ERRATA_A78C_1827430`` : This applies errata 1827430 workaround to
@@ -373,6 +383,11 @@
Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This
erratum is still open.
+- ``ERRATA_A78C_2712575`` : This applies erratum 2712575 workaround to
+ Cortex-A78C CPU, this erratum affects system configurations that do not use
+ an ARM interconnect IP. This needs to be enabled for revisions r0p1 and r0p2
+ and is still open.
+
- ``ERRATA_A78C_2772121`` : This applies errata 2772121 workaround to
Cortex-A78C CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2.
This erratum is still open.
@@ -488,6 +503,11 @@
CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU.
It is still open.
+- ``ERRATA_V1_2701953``: This applies erratum 2701953 workaround to Neoverse-V1
+ CPU, this erratum affects system configurations that do not use an ARM
+ interconnect IP. This needs to be enabled for revisions r0p0, r1p0 and r1p1.
+ It has been fixed in r1p2.
+
- ``ERRATA_V1_2743093``: This applies errata 2743093 workaround to Neoverse-V1
CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 of the
CPU. It is still open.
@@ -500,6 +520,13 @@
CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, r1p2 of the
CPU. It is still open.
+For Neoverse V2, the following errata build flags are defined :
+
+- ``ERRATA_V2_2719103``: This applies errata 2719103 workaround to Neoverse-V2
+ CPU, this affects system configurations that do not use and ARM interconnect
+ IP. This needs to be enabled for revisions r0p0 and r0p1. It has been fixed
+ in r0p2.
+
For Cortex-A710, the following errata build flags are defined :
- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to
@@ -558,6 +585,11 @@
Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
of the CPU and is fixed in r2p1.
+- ``ERRATA_A710_2701952``: This applies erratum 2701952 workaround to Cortex-A710
+ CPU, and applies to system configurations that do not use and ARM
+ interconnect IP. This needs to be enabled for r0p0, r1p0, r2p0 and r2p1 and
+ is still open.
+
- ``ERRATA_A710_2768515``: This applies errata 2768515 workaround to
Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and
r2p1 of the CPU and is still open.
@@ -610,6 +642,11 @@
CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed
in r0p3.
+- ``ERRATA_N2_2728475``: This applies erratum 2728475 workaround to Neoverse-N2
+ CPU, this erratum affects system configurations that do not use and ARM
+ interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and r0p2.
+ It is fixed in r0p3.
+
For Cortex-X2, the following errata build flags are defined :
- ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2
@@ -647,6 +684,11 @@
CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU
and is fixed in r2p1.
+- ``ERRATA_X2_2701952``: This applies erratum 2701952 workaround to Cortex-X2
+ CPU and affects system configurations that do not use an ARM interconnect IP.
+ This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 and is
+ still open.
+
- ``ERRATA_X2_2768515``: This applies errata 2768515 workaround to Cortex-X2
CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the
CPU and is still open.
@@ -709,6 +751,13 @@
Cortex-A510 CPU. This needs to be applied to revision r0p0, r0p1, r0p2,
r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3.
+For Cortex-A715, the following errata build flags are defined :
+
+- ``ERRATA_A715_2701951``: This applies erratum 2701951 workaround to Cortex-A715
+ CPU and affects system configurations that do not use an ARM interconnect
+ IP. This needs to be applied to revisions r0p0, r1p0 and r1p1. It is fixed
+ in r1p2.
+
DSU Errata Workarounds
----------------------
diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst
index 97f3550..14b273e 100644
--- a/docs/design/firmware-design.rst
+++ b/docs/design/firmware-design.rst
@@ -1759,6 +1759,10 @@
DRAM
0xffffffff +----------+
+ | EL3 TZC |
+ 0xffe00000 |----------| (secure)
+ | AP TZC |
+ 0xff000000 +----------+
: :
0x82100000 |----------|
|HW_CONFIG |
@@ -1800,6 +1804,10 @@
DRAM
0xffffffff +--------------+
+ | EL3 TZC |
+ 0xffe00000 |--------------| (secure)
+ | AP TZC |
+ 0xff000000 +--------------+
: :
0x82100000 |--------------|
| HW_CONFIG |
@@ -1840,7 +1848,10 @@
DRAM
0xffffffff +----------+
- | BL32 | (secure)
+ | EL3 TZC |
+ 0xffe00000 |----------| (secure)
+ | AP TZC |
+ | (BL32) |
0xff000000 +----------+
| |
0x82100000 |----------|
@@ -1880,6 +1891,20 @@
::
+ DRAM
+ 0xFFFFFFFF +----------+
+ | SCP TZC |
+ 0xFFE00000 |----------|
+ | EL3 TZC |
+ 0xFFC00000 |----------| (secure)
+ | AP TZC |
+ 0xFF000000 +----------+
+ | |
+ : : (non-secure)
+ | |
+ 0x80000000 +----------+
+
+
Flash0
0x0C000000 +----------+
: :
@@ -1909,9 +1934,14 @@
::
DRAM
- 0xFFE00000 +----------+
- | BL32 | (secure)
- 0xFF000000 |----------|
+ 0xFFFFFFFF +----------+
+ | SCP TZC |
+ 0xFFE00000 |----------|
+ | EL3 TZC |
+ 0xFFC00000 |----------| (secure)
+ | AP TZC |
+ | (BL32) |
+ 0xFF000000 +----------+
| |
: : (non-secure)
| |
@@ -2592,16 +2622,29 @@
section lists the usage of Architecture Extensions, and build flags
controlling them.
+Build options
+~~~~~~~~~~~~~
+
+``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR``
+
-In general, and unless individually mentioned, the build options
-``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` select the Architecture Extension to
-target when building TF-A. Subsequent Arm Architecture Extensions are backward
-compatible with previous versions.
+These build options serve dual purpose
+
+- Determine the architecture extension support in TF-A build: All the mandatory
+ architectural features up to ``ARM_ARCH_MAJOR.ARM_ARCH_MINOR`` are included
+ and unconditionally enabled by TF-A build system.
+
+- Passed to compiler via "-march" option to generate binary target : Tell the
+ compiler to emit instructions upto ``ARM_ARCH_MAJOR.ARM_ARCH_MINOR``
+
+The build system requires that the platform provides a valid numeric value based on
+CPU architecture extension, otherwise it defaults to base Armv8.0-A architecture.
+Subsequent Arm Architecture versions also support extensions which were introduced
+in previous versions.
-The build system only requires that ``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` have a
-valid numeric value. These build options only control whether or not
-Architecture Extension-specific code is included in the build. Otherwise, TF-A
-targets the base Armv8.0-A architecture; i.e. as if ``ARM_ARCH_MAJOR`` == 8
-and ``ARM_ARCH_MINOR`` == 0, which are also their respective default values.
+**TO-DO** : Its planned to decouple the two functionalities and introduce a new macro
+for compiler usage. The requirement for this decoupling arises becasue TF-A code
+always provides support for the latest and greatest architecture features but this
+is not the case for the target compiler.
.. seealso:: :ref:`Build Options`
diff --git a/docs/design_documents/measured_boot_poc.rst b/docs/design_documents/measured_boot_poc.rst
index 2e25057..7f73d7e 100644
--- a/docs/design_documents/measured_boot_poc.rst
+++ b/docs/design_documents/measured_boot_poc.rst
@@ -135,11 +135,11 @@
(4) Now, you should be able to continue with step 5 in "`Get and build the solution`_"
instructions. In order to enable support for Measured Boot, you need to
- set the ``MEASURED_BOOT`` build option:
+ set the following build options:
.. code:: shell
- $ MEASURED_BOOT=y make -j `nproc`
+ $ MEASURED_BOOT=y MEASURED_BOOT_FTPM=y make -j `nproc`
.. note::
The build process will likely take a long time. It is strongly recommended to
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 2229591..4eafb39 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -436,7 +436,8 @@
(SME), SVE, and FPU/SIMD for the non-secure world only. These features share
registers so are enabled together. Using this option without
ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure
- world to trap to EL3. SME is an optional architectural feature for AArch64
+ world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a
+ superset of SVE. SME is an optional architectural feature for AArch64
and TF-A support is experimental. At this time, this build option cannot be
used on systems that have SPD=spmd/SPM_MM or ENABLE_RME, and attempting to
build with these options will fail. This flag can take the values 0 to 2, to
@@ -450,10 +451,9 @@
align with the ``FEATURE_DETECTION`` mechanism. Default is 0.
- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix
- Extension for secure world use along with SVE and FPU/SIMD, ENABLE_SME_FOR_NS
- must also be set to use this. If enabling this, the secure world MUST
- handle context switching for SME, SVE, and FPU/SIMD registers to ensure that
- no data is leaked to non-secure world. This is experimental. Default is 0.
+ Extension for secure world. Used along with SVE and FPU/SIMD.
+ ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this.
+ This is experimental. Default is 0.
- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling
extensions. This is an optional architectural feature for AArch64.
@@ -469,17 +469,15 @@
This is to avoid corruption of the Non-secure world data in the Z-registers
which are aliased by the SIMD and FP registers. The build option is not
compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
- assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` enabled.
- This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
- mechanism. The default is 2 but is automatically disabled when
- ENABLE_SME_FOR_NS is enabled ( set to 1 or 2) since SME encompasses SVE.
- At this time, this build option cannot be used on systems that have SPM_MM
- enabled.
+ assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS``
+ enabled. This flag can take the values 0 to 2, to align with the
+ ``FEATURE_DETECTION`` mechanism. At this time, this build option cannot be
+ used on systems that have SPM_MM enabled. The default is 1.
- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world.
SVE is an optional architectural feature for AArch64. Note that this option
- requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it
- is automatically disabled when the target architecture is AArch32.
+ requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is
+ automatically disabled when the target architecture is AArch32.
- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
checks in GCC. Allowed values are "all", "strong", "default" and "none". The
@@ -640,6 +638,10 @@
translation library (xlat tables v2) must be used; version 1 of translation
library is not supported.
+- ``IMPDEF_SYSREG_TRAP``: Numeric value to enable the handling traps for
+ implementation defined system register accesses from lower ELs. Default
+ value is ``0``.
+
- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the
bottom, higher addresses at the top. This build flag can be set to '1' to
invert this behavior. Lower addresses will be printed at the top and higher
@@ -773,15 +775,14 @@
- ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI
OS-initiated mode. This option defaults to 0.
-- ``RAS_EXTENSION``: Numeric value to enable Armv8.2 RAS features. RAS features
+- ``ENABLE_FEAT_RAS``: Numeric value to enable Armv8.2 RAS features. RAS features
are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2
or later CPUs. This flag can take the values 0 to 2, to align with the
``FEATURE_DETECTION`` mechanism.
- When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST_NS`` must also be
- set to ``1``.
-
- This option is disabled by default.
+- ``RAS_FFH_SUPPORT``: Support to enable Firmware first handling of RAS errors
+ originating from NS world. When ``RAS_FFH_SUPPORT`` is set to ``1``,
+ ``HANDLE_EA_EL3_FIRST_NS`` and ``ENABLE_FEAT_RAS`` must also be set to ``1``.
- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
@@ -1128,6 +1129,13 @@
means platform hook won't be checked and CMOs will always be performed when
related functions are called.
+- ``ERRATA_ABI_SUPPORT``: Boolean option to enable support for Errata management
+ firmware interface for the BL31 image. By default its disabled (``0``).
+
+- ``ERRATA_NON_ARM_INTERCONNECT``: Boolean option to enable support for the
+ errata mitigation for platforms with a non-arm interconnect using the errata
+ ABI. By default its disabled (``0``).
+
GICv3 driver options
--------------------
diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
index bf10ecf..f4c3c28 100644
--- a/docs/getting_started/prerequisites.rst
+++ b/docs/getting_started/prerequisites.rst
@@ -14,7 +14,7 @@
|TF-A| can be built using either a Linux or a Windows machine as the build host.
A relatively recent Linux distribution is recommended for building |TF-A|. We
-have performed tests using Ubuntu 20.04 LTS (64-bit) but other distributions
+have performed tests using Ubuntu 22.04 LTS (64-bit) but other distributions
should also work fine as a base, provided that the necessary tools and libraries
can be installed.
@@ -26,7 +26,7 @@
|TF-A| can be built with any of the following *cross-compiler* toolchains that
target the Armv7-A or Armv8-A architectures:
-- GCC >= 11.3.Rel1 (from the `Arm Developer website`_)
+- GCC >= 12.2.Rel1 (from the `Arm Developer website`_)
You will need the targets ``arm-none-eabi`` and ``aarch64-none-elf`` for
AArch32 and AArch64 builds respectively.
@@ -77,11 +77,11 @@
The following libraries are required for Trusted Board Boot and Measured Boot
support:
-- mbed TLS == 2.28.1 (tag: ``mbedtls-2.28.1``)
+- mbed TLS == 3.4.0 (tag: ``mbedtls-3.4.0``)
These tools are optional:
-- Device Tree Compiler (DTC) >= 1.4.6
+- Device Tree Compiler (DTC) >= 1.4.7
Needed if you want to rebuild the provided Flattened Device Tree (FDT)
source files (``.dts`` files). DTC is available for Linux through the package
diff --git a/docs/global_substitutions.txt b/docs/global_substitutions.txt
index 9428fe9..80012e7 100644
--- a/docs/global_substitutions.txt
+++ b/docs/global_substitutions.txt
@@ -69,3 +69,4 @@
.. |UEFI| replace:: :term:`UEFI`
.. |WDOG| replace:: :term:`WDOG`
.. |XLAT| replace:: :term:`XLAT`
+.. |ERRATA_ABI| replace:: :term:`ERRATA_ABI`
diff --git a/docs/glossary.rst b/docs/glossary.rst
index 12c6ab7..58b7d99 100644
--- a/docs/glossary.rst
+++ b/docs/glossary.rst
@@ -70,6 +70,9 @@
EHF
Exception Handling Framework
+ ERRATA_ABI
+ Errata management firmware interface
+
FCONF
Firmware Configuration Framework
diff --git a/docs/perf/index.rst b/docs/perf/index.rst
index bccad00..0938a17 100644
--- a/docs/perf/index.rst
+++ b/docs/perf/index.rst
@@ -5,10 +5,13 @@
:maxdepth: 1
:caption: Contents
+ psci-performance-instr
psci-performance-juno
+ psci-performance-n1sdp
+ psci-performance-methodology
tsp
performance-monitoring-unit
--------------
-*Copyright (c) 2019-2020, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2023, Arm Limited. All rights reserved.*
diff --git a/docs/perf/psci-performance-instr.rst b/docs/perf/psci-performance-instr.rst
new file mode 100644
index 0000000..16f386f
--- /dev/null
+++ b/docs/perf/psci-performance-instr.rst
@@ -0,0 +1,117 @@
+PSCI Performance Measurement
+============================
+
+TF-A provides two instrumentation tools for performing analysis of the PSCI
+implementation:
+
+* PSCI STAT
+* Runtime Instrumentation
+
+This page explains how they may be enabled and used to perform all varieties of
+analysis.
+
+Performance Measurement Framework
+---------------------------------
+
+The Performance Measurement Framework `PMF`_ is a framework that provides
+mechanisms for collecting and retrieving timestamps at runtime from the
+Performance Measurement Unit (`PMU`_). The PMU is a generalized abstraction for
+accessing CPU hardware registers used to measure hardware events. This means,
+for instance, that the PMU might be used to place instrumentation points at
+logical locations in code for tracing purposes.
+
+TF-A utilises the PMF as a backend for the two instrumentation services it
+provides--PSCI Statistics and Runtime Instrumentation. The PMF is used by
+these services to facilitate collection and retrieval of timestamps. For
+instance, the PSCI Statistics service registers the PMF service
+``psci_svc`` to track its residency statistics.
+
+This is reserved a unique ID, name, and space in memory by the PMF. The
+framework provides a convenient interface for PSCI Statistics to retrieve
+values from ``psci_svc`` at runtime. Alternatively, the service may be
+configured such that the PMF dumps those values to the console. A platform may
+choose to expose SMCs that allow retrieval of these timestamps from the
+service.
+
+This feature is enabled with the Boolean flag ``ENABLE_PMF``.
+
+PSCI Statistics
+---------------
+
+PSCI Statistics is a runtime service that provides residency statistics for
+power states used by the platform. The service tracks residency time and
+entry count. Residency time is the total time spent in a particular power
+state by a PE. The entry count is the number of times the PE has entered
+the power state. PSCI Statistics implements the optional functions
+``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT`` from the `PSCI`_
+specification.
+
+
+.. c:macro:: PSCI_STAT_RESIDENCY
+
+ :param target_cpu: Contains copy of affinity fields in the MPIDR register
+ for identifying the target core (See section 5.1.4 of `PSCI`_
+ specifications for more details).
+ :param power_state: identifier for a specific local
+ state. Generally, this parameter takes the same form as the power_state
+ parameter described for CPU_SUSPEND in section 5.4.2.
+
+ :returns: Time spent in ``power_state``, in microseconds, by ``target_cpu``
+ and the highest level expressed in ``power_state``.
+
+
+.. c:macro:: PSCI_STAT_COUNT
+
+ :param target_cpu: follows the same format as ``PSCI_STAT_RESIDENCY``.
+ :param power_state: follows the same format as ``PSCI_STAT_RESIDENCY``.
+
+ :returns: Number of times the state expressed in ``power_state`` has been
+ used by ``target_cpu`` and the highest level expressed in
+ ``power_state``.
+
+The implementation provides residency statistics only for low power states,
+and does this regardless of the entry mechanism into those states. The
+statistics it collects are set to 0 during shutdown or reset.
+
+PSCI Statistics is enabled with the Boolean build flag
+``ENABLE_PSCI_STAT``. All Arm platforms utilise the PMF unless another
+collection backend is provided (``ENABLE_PMF`` is implicitly enabled).
+
+Runtime Instrumentation
+-----------------------
+
+The Runtime Instrumentation Service is an instrumentation tool that wraps
+around the PMF to provide timestamp data. Although the service is not
+restricted to PSCI, it is used primarily in TF-A to quantify the total time
+spent in the PSCI implementation. The tool can be used to instrument other
+components in TF-A as well. It is enabled with the Boolean flag
+``ENABLE_RUNTIME_INSTRUMENTATION``, and as with PSCI STAT, requires PMF to
+be enabled.
+
+In PSCI, this service provides instrumentation points in the
+following code paths:
+
+* Entry into the PSCI SMC handler
+* Exit from the PSCI SMC handler
+* Entry to low power state
+* Exit from low power state
+* Entry into cache maintenance operations in PSCI
+* Exit from cache maintenance operations in PSCI
+
+The service captures the cycle count, which allows for the time spent in the
+implementation to be calculated, given the frequency counter.
+
+PSCI SMC Handler Instrumentation
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The timestamp during entry into the handler is captured as early as possible
+during the runtime exception, prior to entry into the handler itself. All
+timestamps are stored in memory for later retrieval. The exit timestamp is
+captured after normal return from the PSCI SMC handler, or, if a low power state
+was requested, it is captured in the warm boot path.
+
+*Copyright (c) 2023, Arm Limited. All rights reserved.*
+
+.. _PMF: ../design/firmware-design.html#performance-measurement-framework
+.. _PMU: performance-monitoring-unit.html
+.. _PSCI: https://developer.arm.com/documentation/den0022/latest/
diff --git a/docs/perf/psci-performance-juno.rst b/docs/perf/psci-performance-juno.rst
index 7418669..7a484b8 100644
--- a/docs/perf/psci-performance-juno.rst
+++ b/docs/perf/psci-performance-juno.rst
@@ -25,62 +25,189 @@
Juno supports CPU, cluster and system power down states, corresponding to power
levels 0, 1 and 2 respectively. It does not support any retention states.
-We used the upstream `TF master as of 31/01/2017`_, building the platform using
-the ``ENABLE_RUNTIME_INSTRUMENTATION`` option:
+Given that runtime instrumentation using PMF is invasive, there is a small
+(unquantified) overhead on the results. PMF uses the generic counter for
+timestamps, which runs at 50MHz on Juno.
-.. code:: shell
+The following source trees and binaries were used:
- make PLAT=juno ENABLE_RUNTIME_INSTRUMENTATION=1 \
- SCP_BL2=<path/to/scp-fw.bin> \
- BL33=<path/to/test-fw.bin> \
- all fip
+- TF-A [`v2.9-rc0`_]
+- TFTF [`v2.9-rc0`_]
-When using the debug build of TF, there was no noticeable difference in the
-results.
+Please see the Runtime Instrumentation `Testing Methodology`_ page for more
+details.
-The tests are based on an ARM-internal test framework. The release build of this
-framework was used because the results in the debug build became skewed; the
-console output prevented some of the tests from executing in parallel.
+Procedure
+---------
-The tests consist of both parallel and sequential tests, which are broadly
-described as follows:
+#. Build TFTF with runtime instrumentation enabled:
-- **Parallel Tests** This type of test powers on all the non-lead CPUs and
- brings them and the lead CPU to a common synchronization point. The lead CPU
- then initiates the test on all CPUs in parallel.
+ .. code:: shell
-- **Sequential Tests** This type of test powers on each non-lead CPU in
- sequence. The lead CPU initiates the test on a non-lead CPU then waits for the
- test to complete before proceeding to the next non-lead CPU. The lead CPU then
- executes the test on itself.
+ make CROSS_COMPILE=aarch64-none-elf- PLAT=juno \
+ TESTS=runtime-instrumentation all
-In the results below, CPUs 0-3 refer to CPUs in the little cluster (A53) and
-CPUs 4-5 refer to CPUs in the big cluster (A57). In all cases CPU 4 is the lead
-CPU.
+#. Fetch Juno's SCP binary from TF-A's archive:
-``PSCI_ENTRY`` refers to the time taken from entering the TF PSCI implementation
-to the point the hardware enters the low power state (WFI). Referring to the TF
-runtime instrumentation points, this corresponds to:
-``(RT_INSTR_ENTER_HW_LOW_PWR - RT_INSTR_ENTER_PSCI)``.
+ .. code:: shell
-``PSCI_EXIT`` refers to the time taken from the point the hardware exits the low
-power state to exiting the TF PSCI implementation. This corresponds to:
-``(RT_INSTR_EXIT_PSCI - RT_INSTR_EXIT_HW_LOW_PWR)``.
+ curl --fail --connect-timeout 5 --retry 5 -sLS -o scp_bl2.bin \
+ https://downloads.trustedfirmware.org/tf-a/css_scp_2.12.0/juno/release/juno-bl2.bin
-``CFLUSH_OVERHEAD`` refers to the part of ``PSCI_ENTRY`` taken to flush the
-caches. This corresponds to: ``(RT_INSTR_EXIT_CFLUSH - RT_INSTR_ENTER_CFLUSH)``.
+#. Build TF-A with the following build options:
-Note there is very little variance observed in the values given (~1us), although
-the values for each CPU are sometimes interchanged, depending on the order in
-which locks are acquired. Also, there is very little variance observed between
-executing the tests sequentially in a single boot or rebooting between tests.
+ .. code:: shell
-Given that runtime instrumentation using PMF is invasive, there is a small
-(unquantified) overhead on the results. PMF uses the generic counter for
-timestamps, which runs at 50MHz on Juno.
+ make CROSS_COMPILE=aarch64-none-elf- PLAT=juno \
+ BL33="/path/to/tftf.bin" SCP_BL2="scp_bl2.bin" \
+ ENABLE_RUNTIME_INSTRUMENTATION=1 fiptool all fip
+
+#. Load the following images onto the development board: ``fip.bin``,
+ ``scp_bl2.bin``.
+
+Results
+-------
+
+``CPU_SUSPEND`` to deepest power level
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
+ parallel
+
+ +---------+------+-----------+---------+-------------+
+ | Cluster | Core | Powerdown | Wakekup | Cache Flush |
+ +=========+======+===========+=========+=============+
+ | 0 | 0 | 243.76 | 239.92 | 6.32 |
+ +---------+------+-----------+---------+-------------+
+ | 0 | 1 | 663.5 | 30.32 | 167.82 |
+ +---------+------+-----------+---------+-------------+
+ | 1 | 0 | 105.12 | 22.84 | 5.88 |
+ +---------+------+-----------+---------+-------------+
+ | 1 | 1 | 384.16 | 19.06 | 4.7 |
+ +---------+------+-----------+---------+-------------+
+ | 1 | 2 | 523.98 | 270.46 | 4.74 |
+ +---------+------+-----------+---------+-------------+
+ | 1 | 3 | 950.54 | 220.9 | 89.2 |
+ +---------+------+-----------+---------+-------------+
+
+.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
+ serial
+
+ +---------+------+-----------+---------+-------------+
+ | Cluster | Core | Powerdown | Wakekup | Cache Flush |
+ +=========+======+===========+=========+=============+
+ | 0 | 0 | 266.96 | 31.74 | 167.92 |
+ +---------+------+-----------+---------+-------------+
+ | 0 | 1 | 266.9 | 31.52 | 167.82 |
+ +---------+------+-----------+---------+-------------+
+ | 1 | 0 | 279.86 | 23.42 | 87.52 |
+ +---------+------+-----------+---------+-------------+
+ | 1 | 1 | 101.38 | 18.8 | 4.64 |
+ +---------+------+-----------+---------+-------------+
+ | 1 | 2 | 101.18 | 19.28 | 4.64 |
+ +---------+------+-----------+---------+-------------+
+ | 1 | 3 | 101.32 | 19.02 | 4.62 |
+ +---------+------+-----------+---------+-------------+
+
+``CPU_SUSPEND`` to power level 0
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-Results and Commentary
-----------------------
+.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
+ parallel
+
+ +---------+------+-----------+---------+-------------+
+ | Cluster | Core | Powerdown | Wakekup | Cache Flush |
+ +=========+======+===========+=========+=============+
+ +---------+------+-----------+---------+-------------+
+ | 0 | 0 | 661.94 | 22.88 | 9.66 |
+ +---------+------+-----------+---------+-------------+
+ | 0 | 1 | 801.64 | 23.38 | 9.62 |
+ +---------+------+-----------+---------+-------------+
+ | 1 | 0 | 105.56 | 16.02 | 8.12 |
+ +---------+------+-----------+---------+-------------+
+ | 1 | 1 | 245.42 | 16.26 | 7.78 |
+ +---------+------+-----------+---------+-------------+
+ | 1 | 2 | 384.42 | 16.1 | 7.84 |
+ +---------+------+-----------+---------+-------------+
+ | 1 | 3 | 523.74 | 15.4 | 8.02 |
+ +---------+------+-----------+---------+-------------+
+
+.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial
+
+ +---------+------+-----------+---------+-------------+
+ | Cluster | Core | Powerdown | Wakekup | Cache Flush |
+ +=========+======+===========+=========+=============+
+ | 0 | 0 | 102.16 | 23.64 | 6.7 |
+ +---------+------+-----------+---------+-------------+
+ | 0 | 1 | 101.66 | 23.78 | 6.6 |
+ +---------+------+-----------+---------+-------------+
+ | 1 | 0 | 277.74 | 15.96 | 4.66 |
+ +---------+------+-----------+---------+-------------+
+ | 1 | 1 | 98.0 | 15.88 | 4.64 |
+ +---------+------+-----------+---------+-------------+
+ | 1 | 2 | 97.66 | 15.88 | 4.62 |
+ +---------+------+-----------+---------+-------------+
+ | 1 | 3 | 97.76 | 15.38 | 4.64 |
+ +---------+------+-----------+---------+-------------+
+
+``CPU_OFF`` on all non-lead CPUs
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+``CPU_OFF`` on all non-lead CPUs in sequence then, ``CPU_SUSPEND`` on the lead
+core to the deepest power level.
+
+.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs
+
+ +---------+------+-----------+---------+-------------+
+ | Cluster | Core | Powerdown | Wakekup | Cache Flush |
+ +=========+======+===========+=========+=============+
+ | 0 | 0 | 265.38 | 34.12 | 167.36 |
+ +---------+------+-----------+---------+-------------+
+ | 0 | 1 | 265.72 | 33.98 | 167.48 |
+ +---------+------+-----------+---------+-------------+
+ | 1 | 0 | 185.3 | 23.18 | 87.42 |
+ +---------+------+-----------+---------+-------------+
+ | 1 | 1 | 101.58 | 23.46 | 4.48 |
+ +---------+------+-----------+---------+-------------+
+ | 1 | 2 | 101.66 | 22.02 | 4.72 |
+ +---------+------+-----------+---------+-------------+
+ | 1 | 3 | 101.48 | 22.22 | 4.52 |
+ +---------+------+-----------+---------+-------------+
+
+``CPU_VERSION`` in parallel
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores
+
+ +-------------+--------+--------------+
+ | Cluster | Core | Latency |
+ +=============+========+==============+
+ | 0 | 0 | 1.22 |
+ +-------------+--------+--------------+
+ | 0 | 1 | 1.2 |
+ +-------------+--------+--------------+
+ | 1 | 0 | 0.6 |
+ +-------------+--------+--------------+
+ | 1 | 1 | 1.08 |
+ +-------------+--------+--------------+
+ | 1 | 2 | 1.04 |
+ +-------------+--------+--------------+
+ | 1 | 3 | 1.04 |
+ +-------------+--------+--------------+
+
+Annotated Historic Results
+--------------------------
+
+The following results are based on the upstream `TF master as of 31/01/2017`_.
+TF-A was built using the same build instructions as detailed in the procedure
+above.
+
+In the results below, CPUs 0-3 refer to CPUs in the little cluster (A53) and
+CPUs 4-5 refer to CPUs in the big cluster (A57). In all cases CPU 4 is the lead
+CPU.
+
+``PSCI_ENTRY`` corresponds to the powerdown latency, ``PSCI_EXIT`` the wakeup latency, and
+``CFLUSH_OVERHEAD`` the latency of the cache flush operation.
``CPU_SUSPEND`` to deepest power level on all CPUs in parallel
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -290,3 +417,5 @@
.. _Juno R1 platform: https://developer.arm.com/documentation/100122/latest/
.. _TF master as of 31/01/2017: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/?id=c38b36d
+.. _v2.9-rc0: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/?h=v2.9-rc0
+.. _Testing Methodology: ../perf/psci-performance-methodology.html
diff --git a/docs/perf/psci-performance-methodology.rst b/docs/perf/psci-performance-methodology.rst
new file mode 100644
index 0000000..a9f379d
--- /dev/null
+++ b/docs/perf/psci-performance-methodology.rst
@@ -0,0 +1,55 @@
+Runtime Instrumentation Methodology
+===================================
+
+This document outlines steps for undertaking performance measurements of key
+operations in the Trusted Firmware-A Power State Coordination Interface (PSCI)
+implementation, using the in-built Performance Measurement Framework (PMF) and
+runtime instrumentation timestamps.
+
+Framework
+~~~~~~~~~
+
+The tests are based on the ``runtime-instrumentation`` test suite provided by
+the Trusted Firmware Test Framework (TFTF). The release build of this framework
+was used because the results in the debug build became skewed; the console
+output prevented some of the tests from executing in parallel.
+
+The tests consist of both parallel and sequential tests, which are broadly
+described as follows:
+
+- **Parallel Tests** This type of test powers on all the non-lead CPUs and
+ brings them and the lead CPU to a common synchronization point. The lead CPU
+ then initiates the test on all CPUs in parallel.
+
+- **Sequential Tests** This type of test powers on each non-lead CPU in
+ sequence. The lead CPU initiates the test on a non-lead CPU then waits for the
+ test to complete before proceeding to the next non-lead CPU. The lead CPU then
+ executes the test on itself.
+
+Note there is very little variance observed in the values given (~1us), although
+the values for each CPU are sometimes interchanged, depending on the order in
+which locks are acquired. Also, there is very little variance observed between
+executing the tests sequentially in a single boot or rebooting between tests.
+
+Given that runtime instrumentation using PMF is invasive, there is a small
+(unquantified) overhead on the results. PMF uses the generic counter for
+timestamps, which runs at 50MHz on Juno.
+
+Metrics
+~~~~~~~
+
+.. glossary::
+
+ Powerdown Latency
+ Time taken from entering the TF PSCI implementation to the point the hardware
+ enters the low power state (WFI). Referring to the TF runtime instrumentation points, this
+ corresponds to: ``(RT_INSTR_ENTER_HW_LOW_PWR - RT_INSTR_ENTER_PSCI)``.
+
+ Wakeup Latency
+ Time taken from the point the hardware exits the low power state to exiting
+ the TF PSCI implementation. This corresponds to: ``(RT_INSTR_EXIT_PSCI -
+ RT_INSTR_EXIT_HW_LOW_PWR)``.
+
+ Cache Flush Latency
+ Time taken to flush the caches during powerdown. This corresponds to:
+ ``(RT_INSTR_EXIT_CFLUSH - RT_INSTR_ENTER_CFLUSH)``.
diff --git a/docs/perf/psci-performance-n1sdp.rst b/docs/perf/psci-performance-n1sdp.rst
new file mode 100644
index 0000000..70a1436
--- /dev/null
+++ b/docs/perf/psci-performance-n1sdp.rst
@@ -0,0 +1,203 @@
+Runtime Instrumentation Testing - N1SDP
+=======================================
+
+For this test we used the N1 System Development Platform (`N1SDP`_), which
+contains an SoC consisting of two dual-core Arm N1 clusters.
+
+The following source trees and binaries were used:
+
+- TF-A [`v2.9-rc0-16-g666aec401`_]
+- TFTF [`v2.9-rc0`_]
+- SCP/MCP `Prebuilt Images`_
+
+Please see the Runtime Instrumentation `Testing Methodology`_ page for more
+details.
+
+Procedure
+---------
+
+#. Build TFTF with runtime instrumentation enabled:
+
+ .. code:: shell
+
+ make CROSS_COMPILE=aarch64-none-elf- PLAT=n1sdp \
+ TESTS=runtime-instrumentation all
+
+#. Build TF-A with the following build options:
+
+ .. code:: shell
+
+ make CROSS_COMPILE=aarch64-none-elf- PLAT=n1sdp \
+ ENABLE_RUNTIME_INSTRUMENTATION=1 fiptool all
+
+#. Fetch the SCP firmware images:
+
+ .. code:: shell
+
+ curl --fail --connect-timeout 5 --retry 5 \
+ -sLS -o build/n1sdp/release/scp_rom.bin \
+ https://downloads.trustedfirmware.org/tf-a/css_scp_2.12.0/n1sdp/release/n1sdp-bl1.bin
+ curl --fail --connect-timeout 5 \
+ --retry 5 -sLS -o build/n1sdp/release/scp_ram.bin \
+ https://downloads.trustedfirmware.org/tf-a/css_scp_2.12.0/n1sdp/release/n1sdp-bl2.bin
+
+#. Fetch the MCP firmware images:
+
+ .. code:: shell
+
+ curl --fail --connect-timeout 5 --retry 5 \
+ -sLS -o build/n1sdp/release/mcp_rom.bin \
+ https://downloads.trustedfirmware.org/tf-a/css_scp_2.12.0/n1sdp/release/n1sdp-mcp-bl1.bin
+ curl --fail --connect-timeout 5 --retry 5 \
+ -sLS -o build/n1sdp/release/mcp_ram.bin \
+ https://downloads.trustedfirmware.org/tf-a/css_scp_2.12.0/n1sdp/release/n1sdp-mcp-bl2.bin
+
+#. Using the fiptool, create a new FIP package and append the SCP ram image onto
+ it.
+
+ .. code:: shell
+
+ ./tools/fiptool/fiptool create --blob \
+ uuid=cfacc2c4-15e8-4668-82be-430a38fad705,file=build/n1sdp/release/bl1.bin \
+ --scp-fw build/n1sdp/release/scp_ram.bin build/n1sdp/release/scp_fw.bin
+
+#. Append the MCP image to the FIP.
+
+ .. code:: shell
+
+ ./tools/fiptool/fiptool create \
+ --blob uuid=54464222-a4cf-4bf8-b1b6-cee7dade539e,file=build/n1sdp/release/mcp_ram.bin \
+ build/n1sdp/release/mcp_fw.bin
+
+#. Then, add TFTF as the Non-Secure workload in the FIP image:
+
+ .. code:: shell
+
+ make CROSS_COMPILE=aarch64-none-elf- PLAT=n1sdp \
+ ENABLE_RUNTIME_INSTRUMENTATION=1 SCP_BL2=/dev/null \
+ BL33=<path/to/tftf.bin> fip
+
+#. Load the following images onto the development board: ``fip.bin``,
+ ``scp_rom.bin``, ``scp_ram.bin``, ``mcp_rom.bin``, and ``mcp_ram.bin``.
+
+.. note::
+
+ These instructions presume you have a complete firmware stack. The N1SDP
+ `user guide`_ provides a detailed explanation on how to get setup from
+ scratch.
+
+Results
+-------
+
+``CPU_SUSPEND`` to deepest power level
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
+ parallel
+
+ +---------+------+-----------+---------+-------------+
+ | Cluster | Core | Powerdown | Wakekup | Cache Flush |
+ +=========+======+===========+=========+=============+
+ | 0 | 0 | 3.44 | 10.04 | 0.4 |
+ +---------+------+-----------+---------+-------------+
+ | 0 | 1 | 4.98 | 12.72 | 0.16 |
+ +---------+------+-----------+---------+-------------+
+ | 1 | 0 | 3.58 | 15.42 | 0.2 |
+ +---------+------+-----------+---------+-------------+
+ | 1 | 1 | 5.24 | 17.78 | 0.18 |
+ +---------+------+-----------+---------+-------------+
+
+.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
+ serial
+
+ +---------+------+-----------+---------+-------------+
+ | Cluster | Core | Powerdown | Wakekup | Cache Flush |
+ +=========+======+===========+=========+=============+
+ | 0 | 0 | 1.82 | 9.98 | 0.32 |
+ +---------+------+-----------+---------+-------------+
+ | 0 | 1 | 1.96 | 9.96 | 0.18 |
+ +---------+------+-----------+---------+-------------+
+ | 1 | 0 | 2.0 | 10.5 | 0.16 |
+ +---------+------+-----------+---------+-------------+
+ | 1 | 1 | 2.22 | 10.56 | 0.16 |
+ +---------+------+-----------+---------+-------------+
+
+``CPU_SUSPEND`` to power level 0
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
+ parallel
+
+ +---------+------+-----------+---------+-------------+
+ | Cluster | Core | Powerdown | Wakekup | Cache Flush |
+ +=========+======+===========+=========+=============+
+ | 0 | 0 | 1.52 | 11.84 | 0.34 |
+ +---------+------+-----------+---------+-------------+
+ | 0 | 1 | 1.1 | 13.66 | 0.14 |
+ +---------+------+-----------+---------+-------------+
+ | 1 | 0 | 2.18 | 9.48 | 0.18 |
+ +---------+------+-----------+---------+-------------+
+ | 1 | 1 | 2.06 | 14.4 | 0.16 |
+ +---------+------+-----------+---------+-------------+
+
+.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial
+
+ +---------+------+-----------+---------+-------------+
+ | Cluster | Core | Powerdown | Wakekup | Cache Flush |
+ +=========+======+===========+=========+=============+
+ | 0 | 0 | 1.54 | 9.34 | 0.3 |
+ +---------+------+-----------+---------+-------------+
+ | 0 | 1 | 1.88 | 9.5 | 0.16 |
+ +---------+------+-----------+---------+-------------+
+ | 1 | 0 | 1.86 | 9.86 | 0.2 |
+ +---------+------+-----------+---------+-------------+
+ | 1 | 1 | 2.02 | 9.64 | 0.18 |
+ +---------+------+-----------+---------+-------------+
+
+``CPU_OFF`` on all non-lead CPUs
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+``CPU_OFF`` on all non-lead CPUs in sequence then, ``CPU_SUSPEND`` on the lead
+core to the deepest power level.
+
+.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs
+
+ +---------+------+-----------+---------+-------------+
+ | Cluster | Core | Powerdown | Wakekup | Cache Flush |
+ +=========+======+===========+=========+=============+
+ | 0 | 0 | 1.86 | 9.88 | 0.32 |
+ +---------+------+-----------+---------+-------------+
+ | 0 | 1 | 21.1 | 12.44 | 0.42 |
+ +---------+------+-----------+---------+-------------+
+ | 1 | 0 | 21.22 | 13.2 | 0.32 |
+ +---------+------+-----------+---------+-------------+
+ | 1 | 1 | 21.56 | 13.18 | 0.54 |
+ +---------+------+-----------+---------+-------------+
+
+``CPU_VERSION`` in parallel
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores
+
+ +-------------+--------+--------------+
+ | Cluster | Core | Latency |
+ +=============+========+==============+
+ | 0 | 0 | 0.08 |
+ +-------------+--------+--------------+
+ | 0 | 1 | 0.22 |
+ +-------------+--------+--------------+
+ | 1 | 0 | 0.28 |
+ +-------------+--------+--------------+
+ | 1 | 1 | 0.26 |
+ +-------------+--------+--------------+
+
+--------------
+
+*Copyright (c) 2023, Arm Limited. All rights reserved.*
+
+.. _v2.9-rc0-16-g666aec401: https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/heads/v2.9-rc0-16-g666aec401
+.. _v2.9-rc0: https://review.trustedfirmware.org/plugins/gitiles/TF-A/tf-a-tests/+/refs/tags/v2.9-rc0
+.. _user guide: https://gitlab.arm.com/arm-reference-solutions/arm-reference-solutions-docs/-/blob/master/docs/n1sdp/user-guide.rst
+.. _Prebuilt Images: https://downloads.trustedfirmware.org/tf-a/css_scp_2.11.0/n1sdp/release/
+.. _N1SDP: https://developer.arm.com/documentation/101489/latest
+.. _Testing Methodology: ../perf/psci-performance-methodology.html
\ No newline at end of file
diff --git a/docs/plat/allwinner.rst b/docs/plat/allwinner.rst
index 3e9ce51..8e967dc 100644
--- a/docs/plat/allwinner.rst
+++ b/docs/plat/allwinner.rst
@@ -23,6 +23,8 @@
+------+-------------------+
| H313 | sun50i_h616 |
+------+-------------------+
+| T507 | sun50i_h616 |
++------+-------------------+
| R329 | sun50i_r329 |
+------+-------------------+
diff --git a/docs/plat/index.rst b/docs/plat/index.rst
index a4e2067..57c7303 100644
--- a/docs/plat/index.rst
+++ b/docs/plat/index.rst
@@ -76,7 +76,9 @@
+----------------+----------------+--------------------+--------------------+
| tc0 | Arm | 2.8 | 3.0 |
+----------------+----------------+--------------------+--------------------+
+| rde1edge | Arm | 2.9 | 3.1 |
++----------------+----------------+--------------------+--------------------+
--------------
-*Copyright (c) 2019-2022, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2023, Arm Limited. All rights reserved.*
diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst
index 25b55e8..1250071 100644
--- a/docs/porting-guide.rst
+++ b/docs/porting-guide.rst
@@ -2785,6 +2785,22 @@
by the ``MPIDR`` (first argument). The generic code expects the platform to
return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure.
+plat_psci_ops.pwr_domain_off_early() [optional]
+...............................................
+
+This optional function performs the platform specific actions to check if
+powering off the calling CPU and its higher parent power domain levels as
+indicated by the ``target_state`` (first argument) is possible or allowed.
+
+The ``target_state`` encodes the platform coordinated target local power states
+for the CPU power domain and its parent power domain levels.
+
+For this handler, the local power state for the CPU power domain will be a
+power down state where as it could be either power down, retention or run state
+for the higher power domain levels depending on the result of state
+coordination. The generic code expects PSCI_E_DENIED return code if the
+platform thinks that CPU_OFF should not proceed on the calling CPU.
+
plat_psci_ops.pwr_domain_off()
..............................
@@ -3402,11 +3418,11 @@
(``uint64_t flags``) indicates the preempted security state. These parameters
are received from the top-level exception handler.
-If ``RAS_EXTENSION`` is set to ``1``, the default implementation of this
+If ``RAS_FFH_SUPPORT`` is set to ``1``, the default implementation of this
function iterates through RAS handlers registered by the platform. If any of the
RAS handlers resolve the External Abort, no further action is taken.
-If ``RAS_EXTENSION`` is set to ``0``, or if none of the platform RAS handlers
+If ``RAS_FFH_SUPPORT`` is set to ``0``, or if none of the platform RAS handlers
could resolve the External Abort, the default implementation prints an error
message, and panics.
@@ -3502,6 +3518,38 @@
This function needs to be implemented by a platform if it enables FEAT_RNG_TRAP.
+Function : plat_handle_impdef_trap
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+ Argument : uint64_t
+ Argument : cpu_context_t *
+ Return : int
+
+This function is invoked by BL31's exception handler when there is a synchronous
+system register trap caused by access to the implementation defined registers.
+It allows platforms enabling ``IMPDEF_SYSREG_TRAP`` to emulate those system
+registers choosing to program bits of their choice.
+
+The first parameter (``uint64_t esr_el3``) contains the content of the ESR_EL3
+syndrome register, which encodes the instruction that was trapped.
+
+The second parameter (``cpu_context_t *ctx``) represents the CPU state in the
+lower exception level, at the time when the execution of the ``mrs`` instruction
+was trapped.
+
+The return value indicates how to proceed:
+
+- When returning ``TRAP_RET_UNHANDLED`` (-1), the machine will panic.
+- When returning ``TRAP_RET_REPEAT`` (0), the exception handler will return
+ to the same instruction, so its execution will be repeated.
+- When returning ``TRAP_RET_CONTINUE`` (1), the exception handler will return
+ to the next instruction.
+
+This function needs to be implemented by a platform if it enables
+IMPDEF_SYSREG_TRAP.
+
Build flags
-----------
diff --git a/docs/threat_model/threat_model_spm.rst b/docs/threat_model/threat_model_spm.rst
index 98dbf76..9458a9f 100644
--- a/docs/threat_model/threat_model_spm.rst
+++ b/docs/threat_model/threat_model_spm.rst
@@ -35,7 +35,7 @@
- The TF-A implementation for the S-EL2 SPMC based on the Hafnium hypervisor
running in the secure world of TrustZone (at S-EL2 exception level).
The threat model is not related to the normal world Hypervisor or VMs.
- The S-EL1 SPMC solution is not covered.
+ The S-EL1 and EL3 SPMC solutions are not covered.
- The implementation complies with the FF-A v1.0 specification, and a few
features of FF-A v1.1 specification.
- Secure partitions are statically provisioned at boot time.
@@ -235,8 +235,8 @@
+------------------------+------------------+-----------------+---------------+
| ``Total Risk Rating`` | High (16) | High (16) | |
+------------------------+------------------+-----------------+---------------+
-| ``Mitigations`` | In context of FF-A v1.0 this is the case of sharing|
-| | the RX/TX buffer pair and usage in the |
+| ``Mitigations`` | In context of FF-A v1.0 and v1.1 this is the case |
+| | of sharing the RX/TX buffer pair and usage in the |
| | PARTITION_INFO_GET or mem sharing primitives. |
| | The SPMC must copy the contents of the TX buffer |
| | to an internal temporary buffer before processing |
@@ -1151,11 +1151,189 @@
| | interrupted. |
+------------------------+----------------------------------------------------+
++------------------------+----------------------------------------------------+
+| ID | 25 |
++========================+====================================================+
+| ``Threat`` | **A rogue FF-A endpoint can use memory sharing |
+| | calls to exhaust SPMC resources.** |
+| | For each on-going operation that involves an SP, |
+| | the SPMC allocates resources to track its state. |
+| | If the operation is never concluded, the resources |
+| | are never freed. |
+| | In the worst scenario, multiple operations that |
+| | never conclude may exhaust the SPMC resources to a |
+| | point in which renders memory sharing operations |
+| | impossible. This could affect other, non-harmful |
+| | FF-A endpoints, from legitimately using memory |
+| | share functionality. The intent might even be |
+| | to cause the SPMC to consume excessive CPU cycles, |
+| | attempting to make it deny its service to the NWd. |
++------------------------+----------------------------------------------------+
+| ``Diagram Elements`` | DF1, DF2 |
++------------------------+----------------------------------------------------+
+| ``Affected TF-A | SPMC, SPMD |
+| Components`` | |
++------------------------+----------------------------------------------------+
+| ``Assets`` | SPMC state |
++------------------------+----------------------------------------------------+
+| ``Threat Agent`` | NS-Endpoint, S-Endpoint |
++------------------------+----------------------------------------------------+
+| ``Threat Type`` | Denial of Service |
++------------------------+------------------+-----------------+---------------+
+| ``Application`` | ``Server`` | ``Mobile`` | |
++------------------------+------------------+-----------------+---------------+
+| ``Impact`` | High (4) | Medium (3) | |
++------------------------+------------------+-----------------+---------------+
+| ``Likelihood`` | High (4) | Medium (3) | |
++------------------------+------------------+-----------------+---------------+
+| ``Total Risk Rating`` | High (16) | Medium (9) | |
++------------------------+------------------+-----------------+---------------+
+| ``Mitigations`` | The TF-A SPMC uses a statically allocated pool of |
+| | memory to keep track of on-going memory sharing |
+| | operations. After a possible attack, this could |
+| | fail due to insufficient memory, and return an |
+| | error to the caller. At this point, any other |
+| | endpoint that requires use of memory sharing for |
+| | its operation could get itself in an unusable |
+| | state. |
+| | Regarding CPU cycles starving threat, the SPMC |
+| | doesn't provide any mitigation for this, as any |
+| | FF-A endpoint, at the virtual FF-A instance is |
+| | allowed to invoke memory share/lend/donate. |
++------------------------+----------------------------------------------------+
+
++------------------------+----------------------------------------------------+
+| ID | 26 |
++========================+====================================================+
+| ``Threat`` | **A borrower may interfere with lender's |
+| | operation, if it terminates due to a fatal error |
+| | condition without releasing the memory |
+| | shared/lent.** |
+| | Such scenario may render the lender inoperable. |
++------------------------+----------------------------------------------------+
+| ``Diagram Elements`` | DF1, DF2 |
++------------------------+----------------------------------------------------+
+| ``Affected TF-A | SPMC |
+| Components`` | |
++------------------------+----------------------------------------------------+
+| ``Assets`` | SP state |
++------------------------+----------------------------------------------------+
+| ``Threat Agent`` | NS-Endpoint, S-Endpoint |
++------------------------+----------------------------------------------------+
+| ``Threat Type`` | Denial of Service |
++------------------------+------------------+-----------------+---------------+
+| ``Application`` | ``Server`` | ``Mobile`` | |
++------------------------+------------------+-----------------+---------------+
+| ``Impact`` | High (4) | Low (2) | |
++------------------------+------------------+-----------------+---------------+
+| ``Likelihood`` | Medium (3) | Medium (3) | |
++------------------------+------------------+-----------------+---------------+
+| ``Total Risk Rating`` | High (12) | Medium(6) | |
++------------------------+------------------+-----------------+---------------+
+| ``Mitigations`` | The TF-A SPMC does not provide mitigation for such |
+| | scenario. The FF-A endpoints must attempt to |
+| | relinquish memory shared/lent themselves in |
+| | case of failure. The memory used to track the |
+| | operation in the SPMC will also remain usuable. |
++------------------------+----------------------------------------------------+
+
++------------------------+----------------------------------------------------+
+| ID | 27 |
++========================+====================================================+
+| ``Threat`` | **A rogue FF-A endpoint may attempt to tamper with |
+| | the content of the memory shared/lent, whilst |
+| | being accessed by other FF-A endpoints.** |
+| | It might attempt to do so: using one of the clear |
+| | flags, when either retrieving or relinquishing |
+| | access to the memory via the respective FF-A |
+| | calls; or directly accessing memory without |
+| | respecting the synchronization protocol between |
+| | all involved endpoints. |
++------------------------+----------------------------------------------------+
+| ``Diagram Elements`` | DF1, DF2 |
++------------------------+----------------------------------------------------+
+| ``Affected TF-A | SPMC, FF-A endpoint |
+| Components`` | |
++------------------------+----------------------------------------------------+
+| ``Assets`` | SP state |
++------------------------+----------------------------------------------------+
+| ``Threat Agent`` | NS-Endpoint, S-Endpoint |
++------------------------+----------------------------------------------------+
+| ``Threat Type`` | Denial of Service, Tampering |
++------------------------+------------------+-----------------+---------------+
+| ``Application`` | ``Server`` | ``Mobile`` | |
++------------------------+------------------+-----------------+---------------+
+| ``Impact`` | Low (2) | Low (2) | |
++------------------------+------------------+-----------------+---------------+
+| ``Likelihood`` | Medium (3) | Medium (3) | |
++------------------------+------------------+-----------------+---------------+
+| ``Total Risk Rating`` | Medium (6) | Medium(6) | |
++------------------------+------------------+-----------------+---------------+
+| ``Mitigations`` | The first case defined in the threat, the TF-A |
+| | SPMC mitigates it, by ensuring a memory is cleared |
+| | only when all borrowers have relinquished access |
+| | to the memory, in a scenario involving multiple |
+| | borrowers. Also, if the receiver is granted RO, |
+| | permissions, the SPMC will reject any request |
+| | to clear memory on behalf of the borrower, by |
+| | returning an error to the respective FF-A call. |
+| | The second case defined in the threat can't be |
+| | mitigated by the SPMC. It is up to the NS/S FF-A |
+| | endpoints to establish a robust protocol for using |
+| | the shared memory. |
++------------------------+----------------------------------------------------+
+
++------------------------+----------------------------------------------------+
+| ID | 28 |
++========================+====================================================+
+| ``Threat`` | **A rogue FF-A endpoint may attempt to share |
+| | memory that is not in its translation regime, or |
+| | attempt to specify attributes more permissive than |
+| | those it possesses at a given time.** |
+| | Both ways could be an attempt for escalating its |
+| | privileges. |
++------------------------+----------------------------------------------------+
+| ``Diagram Elements`` | DF1, DF2 |
++------------------------+----------------------------------------------------+
+| ``Affected TF-A | SPMC, FF-A endpoint |
+| Components`` | |
++------------------------+----------------------------------------------------+
+| ``Assets`` | SP state |
++------------------------+----------------------------------------------------+
+| ``Threat Agent`` | NS-Endpoint, S-Endpoint |
++------------------------+----------------------------------------------------+
+| ``Threat Type`` | Denial of Service, Tampering |
++------------------------+------------------+-----------------+---------------+
+| ``Application`` | ``Server`` | ``Mobile`` | |
++------------------------+------------------+-----------------+---------------+
+| ``Impact`` | High (4) | Low (2) | |
++------------------------+------------------+-----------------+---------------+
+| ``Likelihood`` | Medium (3) | Low (2) | |
++------------------------+------------------+-----------------+---------------+
+| ``Total Risk Rating`` | High (12) | Low (2) | |
++------------------------+------------------+-----------------+---------------+
+| ``Mitigations`` | The TF-A SPMC mitigates this threat by performing |
+| | sanity checks to the provided memory region |
+| | descriptor. |
+| | For operations at the virtual FF-A instance, and |
+| | once the full memory descriptor is provided, |
+| | the SPMC validates that the memory is part of the |
+| | caller's translation regime. The SPMC also checks |
+| | that the memory attributes provided are within |
+| | those the owner possesses, in terms of |
+| | permissiveness. If more permissive attributes are |
+| | specified, the SPMC returns an error |
+| | FFA_INVALID_PARAMETERS. The permissiveness rules |
+| | are enforced in any call to share/lend or donate |
+| | the memory, and in retrieve requests. |
++------------------------+----------------------------------------------------+
+
--------------
-*Copyright (c) 2021-2022, Arm Limited. All rights reserved.*
+*Copyright (c) 2021-2023, Arm Limited. All rights reserved.*
.. _Arm Firmware Framework for Arm A-profile: https://developer.arm.com/docs/den0077/latest
.. _Secure Partition Manager: ../components/secure-partition-manager.html
.. _Generic TF-A threat model: ./threat_model.html#threat-analysis
.. _FF-A ACS: https://github.com/ARM-software/ff-a-acs/releases
+
diff --git a/drivers/arm/css/scmi/vendor/scmi_sq.c b/drivers/arm/css/scmi/vendor/scmi_sq.c
index f185424..1037633 100644
--- a/drivers/arm/css/scmi/vendor/scmi_sq.c
+++ b/drivers/arm/css/scmi/vendor/scmi_sq.c
@@ -15,7 +15,7 @@
#include <sq_common.h>
-/* SCMI messge ID to get the available DRAM region */
+/* SCMI message ID to get the available DRAM region */
#define SCMI_VENDOR_EXT_MEMINFO_GET_MSG 0x3
#define SCMI_VENDOR_EXT_MEMINFO_GET_MSG_LEN 4
diff --git a/drivers/arm/gic/v2/gicv2_main.c b/drivers/arm/gic/v2/gicv2_main.c
index 1925a13..ca2a038 100644
--- a/drivers/arm/gic/v2/gicv2_main.c
+++ b/drivers/arm/gic/v2/gicv2_main.c
@@ -252,7 +252,7 @@
* Ensure the write to peripheral registers are *complete* before the write
* to GIC_EOIR.
*
- * Note: The completion gurantee depends on various factors of system design
+ * Note: The completion guarantee depends on various factors of system design
* and the barrier is the best core can do by which execution of further
* instructions waits till the barrier is alive.
*/
diff --git a/drivers/arm/gic/v3/gic600_multichip.c b/drivers/arm/gic/v3/gic600_multichip.c
index f26e056..7f0735d 100644
--- a/drivers/arm/gic/v3/gic600_multichip.c
+++ b/drivers/arm/gic/v3/gic600_multichip.c
@@ -322,7 +322,7 @@
}
/*******************************************************************************
- * Intialize GIC-600 and GIC-700 Multichip operation.
+ * Initialize GIC-600 and GIC-700 Multichip operation.
******************************************************************************/
void gic600_multichip_init(struct gic600_multichip_data *multichip_data)
{
diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c
index 168d0eb..2c74800 100644
--- a/drivers/arm/gic/v3/gicv3_main.c
+++ b/drivers/arm/gic/v3/gicv3_main.c
@@ -330,6 +330,8 @@
/* Enable Group1 Secure interrupts */
write_icc_igrpen1_el3(read_icc_igrpen1_el3() |
IGRPEN1_EL3_ENABLE_G1S_BIT);
+ /* and restore the original */
+ write_scr_el3(scr_el3);
isb();
/* Add DSB to ensure visibility of System register writes */
dsb();
diff --git a/drivers/arm/sbsa/sbsa.c b/drivers/arm/sbsa/sbsa.c
index 79c6f26..a88e20c 100644
--- a/drivers/arm/sbsa/sbsa.c
+++ b/drivers/arm/sbsa/sbsa.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -40,3 +40,9 @@
{
mmio_write_32(base + SBSA_WDOG_WCS_OFFSET, (0x0));
}
+
+/* Refresh the secure watchdog timer explicitly */
+void sbsa_wdog_refresh(uintptr_t refresh_base)
+{
+ mmio_write_32(refresh_base + SBSA_WDOG_WRR_OFFSET, SBSA_WDOG_WRR_REFRESH);
+}
diff --git a/drivers/brcm/emmc/emmc_chal_sd.c b/drivers/brcm/emmc/emmc_chal_sd.c
index 34d761c..5379ec1 100644
--- a/drivers/brcm/emmc/emmc_chal_sd.c
+++ b/drivers/brcm/emmc/emmc_chal_sd.c
@@ -119,7 +119,7 @@
mmio_setbits_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL_OFFSET,
SD4_EMMC_TOP_CTRL_SDPWR_MASK);
- /* dummy write & ack to verify if the sdio is ready to send commads */
+ /* dummy write & ack to verify if the sdio is ready to send commands */
mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_ARG_OFFSET, 0);
mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CMD_OFFSET, 0);
@@ -600,7 +600,7 @@
if (actual_freq > desired_freq) {
/*
- * Division does not result in exact freqency match.
+ * Division does not result in exact frequency match.
* Make sure resulting frequency does not exceed requested freq.
*/
div_ctrl_setting++;
diff --git a/drivers/brcm/emmc/emmc_csl_sdcard.c b/drivers/brcm/emmc/emmc_csl_sdcard.c
index 40bc4a0..789ed9c 100644
--- a/drivers/brcm/emmc/emmc_csl_sdcard.c
+++ b/drivers/brcm/emmc/emmc_csl_sdcard.c
@@ -244,7 +244,7 @@
* The function handles real data transmission on both DMA and
* none DMA mode, In None DMA mode the data transfer starts
* when the command is sent to the card, data has to be written
- * into the host contollers buffer at this time one block
+ * into the host controllers buffer at this time one block
* at a time.
* In DMA mode, the real data transfer is done by the DMA engine
* and this functions just waits for the data transfer to complete.
@@ -318,7 +318,7 @@
/*
- * The function initalizes the SD/SDIO/MMC/CEATA and detects
+ * The function initializes the SD/SDIO/MMC/CEATA and detects
* the card according to the flag of detection.
* Once this function is called, the card is put into ready state
* so application can do data transfer to and from the card.
@@ -393,7 +393,7 @@
/*
- * The function handles MMC/CEATA card initalization.
+ * The function handles MMC/CEATA card initialization.
*/
int init_mmc_card(struct sd_handle *handle)
{
diff --git a/drivers/brcm/i2c/i2c.c b/drivers/brcm/i2c/i2c.c
index 2096a82..b45c0e7 100644
--- a/drivers/brcm/i2c/i2c.c
+++ b/drivers/brcm/i2c/i2c.c
@@ -612,7 +612,7 @@
*
* Description:
* This function reads I2C data from a device without specifying
- * a command regsiter.
+ * a command register.
*
* Parameters:
* bus_id - I2C bus ID
@@ -647,7 +647,7 @@
*
* Description:
* This function send I2C data to a device without specifying
- * a command regsiter.
+ * a command register.
*
* Parameters:
* bus_id - I2C bus ID
diff --git a/drivers/brcm/sotp.c b/drivers/brcm/sotp.c
index 63c4820..20c6441 100644
--- a/drivers/brcm/sotp.c
+++ b/drivers/brcm/sotp.c
@@ -168,7 +168,7 @@
BIT(SOTP_STATUS__FDONE))
;
- /* Enable OTP acces by CPU */
+ /* Enable OTP access by CPU */
mmio_setbits_32(SOTP_PROG_CONTROL,
BIT(SOTP_PROG_CONTROL__OTP_CPU_MODE_EN));
@@ -244,7 +244,7 @@
/* Command done is cleared w1c */
mmio_setbits_32(SOTP_STATUS_1, BIT(SOTP_STATUS_1__CMD_DONE));
- /* disable OTP acces by CPU */
+ /* disable OTP access by CPU */
mmio_clrbits_32(SOTP_PROG_CONTROL,
BIT(SOTP_PROG_CONTROL__OTP_CPU_MODE_EN));
diff --git a/drivers/io/io_dummy.c b/drivers/io/io_dummy.c
deleted file mode 100644
index 4f0cda6..0000000
--- a/drivers/io/io_dummy.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <string.h>
-
-#include <common/debug.h>
-#include <drivers/io/io_driver.h>
-#include <drivers/io/io_dummy.h>
-#include <drivers/io/io_storage.h>
-
-struct file_state {
- int in_use;
- size_t size;
-};
-
-static struct file_state current_file = {0};
-
-/* Identify the device type as dummy */
-static io_type_t device_type_dummy(void)
-{
- return IO_TYPE_DUMMY;
-}
-
-/* Dummy device functions */
-static int dummy_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info);
-static int dummy_block_open(io_dev_info_t *dev_info, const uintptr_t spec,
- io_entity_t *entity);
-static int dummy_block_len(io_entity_t *entity, size_t *length);
-static int dummy_block_read(io_entity_t *entity, uintptr_t buffer,
- size_t length, size_t *length_read);
-static int dummy_block_close(io_entity_t *entity);
-static int dummy_dev_close(io_dev_info_t *dev_info);
-
-
-static const io_dev_connector_t dummy_dev_connector = {
- .dev_open = dummy_dev_open
-};
-
-
-static const io_dev_funcs_t dummy_dev_funcs = {
- .type = device_type_dummy,
- .open = dummy_block_open,
- .seek = NULL,
- .size = dummy_block_len,
- .read = dummy_block_read,
- .write = NULL,
- .close = dummy_block_close,
- .dev_init = NULL,
- .dev_close = dummy_dev_close,
-};
-
-
-static const io_dev_info_t dummy_dev_info = {
- .funcs = &dummy_dev_funcs,
- .info = (uintptr_t)NULL
-};
-
-
-/* Open a connection to the dummy device */
-static int dummy_dev_open(const uintptr_t dev_spec __attribute__((unused)),
- io_dev_info_t **dev_info)
-{
- assert(dev_info != NULL);
- *dev_info = (io_dev_info_t *)&dummy_dev_info;
-
- return 0;
-}
-
-
-/* Close a connection to the dummy device */
-static int dummy_dev_close(io_dev_info_t *dev_info)
-{
- return 0;
-}
-
-
-/* Open a file on the dummy device */
-static int dummy_block_open(io_dev_info_t *dev_info, const uintptr_t spec,
- io_entity_t *entity)
-{
- int result;
- const io_block_spec_t *block_spec = (io_block_spec_t *)spec;
-
- if (current_file.in_use == 0) {
- assert(block_spec != NULL);
- assert(entity != NULL);
-
- current_file.in_use = 1;
- current_file.size = block_spec->length;
- entity->info = (uintptr_t)¤t_file;
- result = 0;
- } else {
- WARN("A Dummy device is already active. Close first.\n");
- result = -ENOMEM;
- }
-
- return result;
-}
-
-
-/* Return the size of a file on the dummy device */
-static int dummy_block_len(io_entity_t *entity, size_t *length)
-{
- assert(entity != NULL);
- assert(length != NULL);
-
- *length = ((struct file_state *)entity->info)->size;
-
- return 0;
-}
-
-
-/* Read data from a file on the dummy device */
-static int dummy_block_read(io_entity_t *entity, uintptr_t buffer,
- size_t length, size_t *length_read)
-{
- assert(length_read != NULL);
-
- *length_read = length;
-
- return 0;
-}
-
-
-/* Close a file on the dummy device */
-static int dummy_block_close(io_entity_t *entity)
-{
- assert(entity != NULL);
-
- entity->info = 0;
- current_file.in_use = 0;
-
- return 0;
-}
-
-
-/* Exported functions */
-
-/* Register the dummy driver with the IO abstraction */
-int register_io_dev_dummy(const io_dev_connector_t **dev_con)
-{
- int result;
-
- assert(dev_con != NULL);
-
- result = io_register_device(&dummy_dev_info);
- if (result == 0)
- *dev_con = &dummy_dev_connector;
-
- return result;
-}
diff --git a/drivers/marvell/comphy/phy-comphy-cp110.c b/drivers/marvell/comphy/phy-comphy-cp110.c
index fa9fe41..e256fa7 100644
--- a/drivers/marvell/comphy/phy-comphy-cp110.c
+++ b/drivers/marvell/comphy/phy-comphy-cp110.c
@@ -2053,7 +2053,7 @@
mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK;
data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET;
reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask);
- /* Confifure SSC amplitude */
+ /* Configure SSC amplitude */
mask = HPIPE_G2_TX_SSC_AMP_MASK;
data = 0x1f << HPIPE_G2_TX_SSC_AMP_OFFSET;
reg_set(hpipe_addr + HPIPE_G2_SET_2_REG, data, mask);
diff --git a/drivers/marvell/gwin.c b/drivers/marvell/gwin.c
index fa59cb0..40f8c93 100644
--- a/drivers/marvell/gwin.c
+++ b/drivers/marvell/gwin.c
@@ -213,7 +213,7 @@
* remote AP should be accompanied with proper configuration to
* GWIN registers group and therefore the GWIN Miss feature
* should be set into Bypass mode, need to make sure all GWIN regions
- * are defined correctly that will assure no GWIN miss occurrance
+ * are defined correctly that will assure no GWIN miss occurrence
* JIRA-AURORA2-1630
*/
INFO("Update GWIN miss bypass\n");
diff --git a/drivers/marvell/mg_conf_cm3/mg_conf_cm3.c b/drivers/marvell/mg_conf_cm3/mg_conf_cm3.c
index 98e1896..9352437 100644
--- a/drivers/marvell/mg_conf_cm3/mg_conf_cm3.c
+++ b/drivers/marvell/mg_conf_cm3/mg_conf_cm3.c
@@ -55,7 +55,7 @@
/* Don't release MG CM3 from reset - it will be done by next step
* bootloader (e.g. U-Boot), when appriopriate device-tree setup (which
- * has enabeld 802.3. auto-neg) will be choosen.
+ * has enabeld 802.3. auto-neg) will be chosen.
*/
return 0;
diff --git a/drivers/nxp/crypto/caam/src/auth/hash.c b/drivers/nxp/crypto/caam/src/auth/hash.c
index 1665df1..0f3cf95 100644
--- a/drivers/nxp/crypto/caam/src/auth/hash.c
+++ b/drivers/nxp/crypto/caam/src/auth/hash.c
@@ -106,7 +106,7 @@
* Function : hash_final
* Arguments : ctx - SHA context
* Return : SUCCESS or FAILURE
- * Description : This function sets the final bit and enqueues the decriptor
+ * Description : This function sets the final bit and enqueues the descriptor
***************************************************************************/
int hash_final(enum hash_algo algo, void *context, void *hash_ptr,
unsigned int hash_len)
diff --git a/drivers/nxp/crypto/caam/src/hw_key_blob.c b/drivers/nxp/crypto/caam/src/hw_key_blob.c
index 0720695..6bcb6ba 100644
--- a/drivers/nxp/crypto/caam/src/hw_key_blob.c
+++ b/drivers/nxp/crypto/caam/src/hw_key_blob.c
@@ -18,7 +18,7 @@
#include "sec_hw_specific.h"
-/* Callback function after Instantiation decsriptor is submitted to SEC
+/* Callback function after Instantiation descriptor is submitted to SEC
*/
static void blob_done(uint32_t *desc, uint32_t status, void *arg,
void *job_ring)
diff --git a/drivers/nxp/crypto/caam/src/rng.c b/drivers/nxp/crypto/caam/src/rng.c
index 0b9d87d..58430db 100644
--- a/drivers/nxp/crypto/caam/src/rng.c
+++ b/drivers/nxp/crypto/caam/src/rng.c
@@ -17,7 +17,7 @@
#include "sec_hw_specific.h"
-/* Callback function after Instantiation decsriptor is submitted to SEC */
+/* Callback function after Instantiation descriptor is submitted to SEC */
static void rng_done(uint32_t *desc, uint32_t status, void *arg,
void *job_ring)
{
@@ -183,7 +183,7 @@
/*if instantiate_rng(...) fails, the loop will rerun
*and the kick_trng(...) function will modify the
*upper and lower limits of the entropy sampling
- *interval, leading to a sucessful initialization of
+ *interval, leading to a successful initialization of
*/
ret = instantiate_rng();
} while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
diff --git a/drivers/nxp/ddr/nxp-ddr/ddr.c b/drivers/nxp/ddr/nxp-ddr/ddr.c
index faf20e9..17c2bbb 100644
--- a/drivers/nxp/ddr/nxp-ddr/ddr.c
+++ b/drivers/nxp/ddr/nxp-ddr/ddr.c
@@ -293,7 +293,7 @@
}
if (pdodt == NULL) {
- ERROR("Error determing ODT.\n");
+ ERROR("Error determining ODT.\n");
return -EINVAL;
}
@@ -916,7 +916,7 @@
debug("Program controller registers\n");
ret = write_ddrc_regs(priv);
if (ret != 0) {
- ERROR("Programing DDRC error\n");
+ ERROR("Programming DDRC error\n");
return ret;
}
diff --git a/drivers/nxp/ddr/nxp-ddr/ddrc.c b/drivers/nxp/ddr/nxp-ddr/ddrc.c
index 17a2b6a..4133fac 100644
--- a/drivers/nxp/ddr/nxp-ddr/ddrc.c
+++ b/drivers/nxp/ddr/nxp-ddr/ddrc.c
@@ -346,7 +346,7 @@
#ifdef ERRATA_DDR_A008511
/* Part 1 of 2 */
- /* This erraum only applies to verion 5.2.1 */
+ /* This erraum only applies to version 5.2.1 */
if (get_ddrc_version(ddr) == 0x50200) {
ERROR("Unsupported SoC.\n");
} else if (get_ddrc_version(ddr) == 0x50201) {
diff --git a/drivers/nxp/ddr/phy-gen2/messages.h b/drivers/nxp/ddr/phy-gen2/messages.h
index a2310f2..bf2d459 100644
--- a/drivers/nxp/ddr/phy-gen2/messages.h
+++ b/drivers/nxp/ddr/phy-gen2/messages.h
@@ -144,7 +144,7 @@
"PMU3: Precharge all open banks\n"
},
{0x002b0002,
- "PMU: Error: Dbyte %d nibble %d found mutliple working coarse delay setting for MRD/MWD\n"
+ "PMU: Error: Dbyte %d nibble %d found multiple working coarse delay setting for MRD/MWD\n"
},
{0x002c0000,
"PMU4: MRD Passing Regions (coarseVal, fineLeft fineRight -> fineCenter)\n"
@@ -536,7 +536,7 @@
"PMU3: Resetting DRAM\n"
},
{0x00b10000,
- "PMU3: setup for RCD initalization\n"
+ "PMU3: setup for RCD initialization\n"
},
{0x00b20000,
"PMU3: pmu_exit_SR from dev_init()\n"
@@ -974,10 +974,10 @@
"PMU0: PHY VREF @ (%d/1000) VDDQ\n"
},
{0x01430002,
- "PMU0: initalizing phy vrefDacs to %d ExtVrefRange %x\n"
+ "PMU0: initializing phy vrefDacs to %d ExtVrefRange %x\n"
},
{0x01440002,
- "PMU0: initalizing global vref to %d range %d\n"
+ "PMU0: initializing global vref to %d range %d\n"
},
{0x01450002,
"PMU4: Setting initial device vrefDQ for CS%d to MR6 = 0x%04x\n"
@@ -1811,7 +1811,7 @@
"PMU3: Precharge all open banks\n"
},
{0x00be0002,
- "PMU: Error: Dbyte %d nibble %d found mutliple working coarse delay setting for MRD/MWD\n"
+ "PMU: Error: Dbyte %d nibble %d found multiple working coarse delay setting for MRD/MWD\n"
},
{0x00bf0000,
"PMU4: MRD Passing Regions (coarseVal, fineLeft fineRight -> fineCenter)\n"
@@ -2203,7 +2203,7 @@
"PMU3: Resetting DRAM\n"
},
{0x01440000,
- "PMU3: setup for RCD initalization\n"
+ "PMU3: setup for RCD initialization\n"
},
{0x01450000,
"PMU3: pmu_exit_SR from dev_init()\n"
@@ -2641,10 +2641,10 @@
"PMU0: PHY VREF @ (%d/1000) VDDQ\n"
},
{0x01d60002,
- "PMU0: initalizing phy vrefDacs to %d ExtVrefRange %x\n"
+ "PMU0: initializing phy vrefDacs to %d ExtVrefRange %x\n"
},
{0x01d70002,
- "PMU0: initalizing global vref to %d range %d\n"
+ "PMU0: initializing global vref to %d range %d\n"
},
{0x01d80002,
"PMU4: Setting initial device vrefDQ for CS%d to MR6 = 0x%04x\n"
diff --git a/drivers/nxp/ifc/nand/ifc_nand.c b/drivers/nxp/ifc/nand/ifc_nand.c
index 1f7092a..df7ec85 100644
--- a/drivers/nxp/ifc/nand/ifc_nand.c
+++ b/drivers/nxp/ifc/nand/ifc_nand.c
@@ -531,7 +531,7 @@
return 0;
/* special case for lgb == 0 */
- /* if blk <= lgb retrun */
+ /* if blk <= lgb return */
if (nand->lgb != 0 && blk <= nand->lgb)
return 0;
diff --git a/drivers/nxp/sd/sd_mmc.c b/drivers/nxp/sd/sd_mmc.c
index f7f48e7..48b27c1 100644
--- a/drivers/nxp/sd/sd_mmc.c
+++ b/drivers/nxp/sd/sd_mmc.c
@@ -344,7 +344,7 @@
* Function : mmc_switch_to_high_frquency
* Arguments : mmc - Pointer to mmc struct
* Return : SUCCESS or Error Code
- * Description : mmc card bellow ver 4.0 does not support high speed
+ * Description : mmc card below ver 4.0 does not support high speed
* freq = 20 MHz
* Send CMD6 (CMD_SWITCH_FUNC) With args 0x03B90100
* Send CMD13 (CMD_SEND_STATUS)
@@ -358,7 +358,7 @@
uint64_t start_time;
mmc->card.bus_freq = MMC_SS_20MHZ;
- /* mmc card bellow ver 4.0 does not support high speed */
+ /* mmc card below ver 4.0 does not support high speed */
if (mmc->card.version < MMC_CARD_VERSION_4_X) {
return 0;
}
@@ -463,7 +463,7 @@
/***************************************************************************
* Function : esdhc_read_data_nodma
* Arguments : mmc - Pointer to mmc struct
- * dest_ptr - Bufffer where read data is to be copied
+ * dest_ptr - Buffer where read data is to be copied
* len - Length of Data to be read
* Return : SUCCESS or Error Code
* Description : Read data from the sdhc buffer without using DMA
@@ -698,7 +698,7 @@
/***************************************************************************
* Function : esdhc_read_data
* Arguments : mmc - Pointer to mmc struct
- * dest_ptr - Bufffer where read data is to be copied
+ * dest_ptr - Buffer where read data is to be copied
* len - Length of Data to be read
* Return : SUCCESS or Error Code
* Description : Calls esdhc_read_data_nodma and clear interrupt status
diff --git a/drivers/renesas/common/console/rcar_printf.c b/drivers/renesas/common/console/rcar_printf.c
index ad074fe..6af10ee 100644
--- a/drivers/renesas/common/console/rcar_printf.c
+++ b/drivers/renesas/common/console/rcar_printf.c
@@ -24,7 +24,7 @@
/*
* The log is initialized and used before BL31 xlat tables are initialized,
* therefore the log memory is a device memory at that point. Make sure the
- * memory is correclty aligned and accessed only with up-to 32bit, aligned,
+ * memory is correctly aligned and accessed only with up-to 32bit, aligned,
* writes.
*/
CASSERT((RCAR_BL31_LOG_BASE & 0x7) == 0, assert_bl31_log_base_unaligned);
diff --git a/drivers/renesas/common/emmc/emmc_hal.h b/drivers/renesas/common/emmc/emmc_hal.h
index 0a85517..4e6942f 100644
--- a/drivers/renesas/common/emmc/emmc_hal.h
+++ b/drivers/renesas/common/emmc/emmc_hal.h
@@ -512,7 +512,7 @@
/* maximum block count which can be transferred at once */
uint32_t max_block_count;
- /* maximum clock frequence in Hz supported by HW */
+ /* maximum clock frequency in Hz supported by HW */
uint32_t max_clock_freq;
/* maximum data bus width supported by HW */
diff --git a/drivers/renesas/common/pfc_regs.h b/drivers/renesas/common/pfc_regs.h
index 4187733..36084f5 100644
--- a/drivers/renesas/common/pfc_regs.h
+++ b/drivers/renesas/common/pfc_regs.h
@@ -146,10 +146,10 @@
#define GPIO_OUTDTL7 (GPIO_BASE + 0x5848U)
#define GPIO_BOTHEDGE7 (GPIO_BASE + 0x584CU)
-/* Pin functon base address */
+/* Pin function base address */
#define PFC_BASE (0xE6060000U)
-/* Pin functon registers */
+/* Pin function registers */
#define PFC_PMMR (PFC_BASE + 0x0000U)
#define PFC_GPSR0 (PFC_BASE + 0x0100U)
#define PFC_GPSR1 (PFC_BASE + 0x0104U)
diff --git a/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c b/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c
index 6063758..5de4f1f 100644
--- a/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c
+++ b/drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c
@@ -12,7 +12,7 @@
#include "rcar_private.h"
#include "../pfc_regs.h"
-/* Pin functon bit */
+/* Pin function bit */
#define GPSR0_DU_EXODDF_DU_ODDF_DISP_CDE BIT(21)
#define GPSR0_DU_EXVSYNC_DU_VSYNC BIT(20)
#define GPSR0_DU_EXHSYNC_DU_HSYNC BIT(19)
diff --git a/drivers/scmi-msg/clock.c b/drivers/scmi-msg/clock.c
index 85bf7d2..98fdc6a 100644
--- a/drivers/scmi-msg/clock.c
+++ b/drivers/scmi-msg/clock.c
@@ -344,7 +344,7 @@
scmi_status_response(msg, status);
} else {
/*
- * Message payload is already writen to msg->out, and
+ * Message payload is already written to msg->out, and
* msg->out_size_out updated.
*/
}
diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c
index aa5db6f..c9c3c5f 100644
--- a/drivers/st/clk/stm32mp1_clk.c
+++ b/drivers/st/clk/stm32mp1_clk.c
@@ -2049,7 +2049,7 @@
stm32mp1_pll_start(i);
}
- /* Wait and start PLLs ouptut when ready */
+ /* Wait and start PLLs output when ready */
for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) {
if (!pllcfg_valid[i]) {
continue;
diff --git a/drivers/st/crypto/stm32_pka.c b/drivers/st/crypto/stm32_pka.c
index 2bbb31d..1e7c42c 100644
--- a/drivers/st/crypto/stm32_pka.c
+++ b/drivers/st/crypto/stm32_pka.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2022-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,6 +19,11 @@
#include <platform_def.h>
+#if !PKA_USE_NIST_P256 && !PKA_USE_BRAINPOOL_P256R1 && !PKA_USE_BRAINPOOL_P256T1 && \
+ !PKA_USE_NIST_P521
+#error "At least one ECDSA curve needs to be selected"
+#endif
+
/*
* For our comprehension in this file
* _len are in BITs
@@ -690,7 +695,7 @@
mmio_setbits_32(base + _PKA_CLRFR, _PKA_IT_PROCEND);
out:
- /* Disable PKA (will stop all pending proccess and reset RAM) */
+ /* Disable PKA (will stop all pending process and reset RAM) */
pka_disable(base);
return ret;
diff --git a/drivers/st/ddr/stm32mp1_ddr.c b/drivers/st/ddr/stm32mp1_ddr.c
index 4719e1e..27d8b2c 100644
--- a/drivers/st/ddr/stm32mp1_ddr.c
+++ b/drivers/st/ddr/stm32mp1_ddr.c
@@ -755,7 +755,7 @@
stm32mp1_ddrphy_idone_wait(priv->phy);
/*
- * 12. set back registers in step 8 to the orginal values if desidered
+ * 12. set back registers in step 8 to the original values if desidered
*/
stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3,
config->c_reg.pwrctl);
diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h
index 8678bf3..227f058 100644
--- a/include/arch/aarch32/arch.h
+++ b/include/arch/aarch32/arch.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,8 +16,10 @@
#define MIDR_IMPL_SHIFT U(24)
#define MIDR_VAR_SHIFT U(20)
#define MIDR_VAR_BITS U(4)
+#define MIDR_VAR_MASK U(0xf)
#define MIDR_REV_SHIFT U(0)
#define MIDR_REV_BITS U(4)
+#define MIDR_REV_MASK U(0xf)
#define MIDR_PN_MASK U(0xfff)
#define MIDR_PN_SHIFT U(4)
@@ -264,7 +266,7 @@
#define TCP10_BIT (U(1) << 10)
#define HCPTR_RESET_VAL HCPTR_RES1
-/* VTTBR defintions */
+/* VTTBR definitions */
#define VTTBR_RESET_VAL ULL(0x0)
#define VTTBR_VMID_MASK ULL(0xff)
#define VTTBR_VMID_SHIFT U(48)
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index ac5eae2..0038893 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -393,6 +393,9 @@
#define ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED ULL(0x1)
#define ID_AA64PFR1_EL1_RNG_TRAP_NOT_SUPPORTED ULL(0x0)
+#define VDISR_EL2 S3_4_C12_C1_1
+#define VSESR_EL2 S3_4_C5_C2_3
+
/* Memory Tagging Extension is not implemented */
#define MTE_UNIMPLEMENTED U(0)
/* FEAT_MTE: MTE instructions accessible at EL0 are implemented */
@@ -752,7 +755,7 @@
#define HI_VECTOR_BASE U(0xFFFF0000)
/*
- * TCR defintions
+ * TCR definitions
*/
#define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
#define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index a0141de..d6f12f3 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -499,14 +499,22 @@
return read_feat_sve_id_field() >= ID_AA64PFR0_SVE_SUPPORTED;
}
-/*******************************************************************************
- * Function to identify the presence of FEAT_RAS (Reliability,Availability,
- * and Serviceability Extension)
- ******************************************************************************/
-static inline bool is_armv8_2_feat_ras_present(void)
+static unsigned int read_feat_ras_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_RAS);
+}
+
+static inline bool is_feat_ras_supported(void)
{
- return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_RAS_SHIFT) &
- ID_AA64PFR0_RAS_MASK) != ID_AA64PFR0_RAS_NOT_SUPPORTED);
+ if (ENABLE_FEAT_RAS == FEAT_STATE_DISABLED) {
+ return false;
+ }
+
+ if (ENABLE_FEAT_RAS == FEAT_STATE_ALWAYS) {
+ return true;
+ }
+
+ return read_feat_ras_id_field() != 0U;
}
static unsigned int read_feat_dit_id_field(void)
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index 1b4bc11..5b3d4c2 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -549,6 +549,10 @@
/* Armv8.2 ID Registers */
DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1)
+/* Armv8.2 RAS Registers */
+DEFINE_RENAME_SYSREG_RW_FUNCS(vdisr_el2, VDISR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(vsesr_el2, VSESR_EL2)
+
/* Armv8.2 MPAM Registers */
DEFINE_RENAME_SYSREG_READ_FUNC(mpamidr_el1, MPAMIDR_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(mpam3_el3, MPAM3_EL3)
diff --git a/include/bl31/ehf.h b/include/bl31/ehf.h
index c13d28c..63943a9 100644
--- a/include/bl31/ehf.h
+++ b/include/bl31/ehf.h
@@ -30,7 +30,7 @@
.ehf_handler = EHF_NO_HANDLER_, \
}
-/* Macro for platforms to regiter its exception priorities */
+/* Macro for platforms to register its exception priorities */
#define EHF_REGISTER_PRIORITIES(priorities, num, bits) \
const ehf_priorities_t exception_data = { \
.num_priorities = (num), \
diff --git a/include/bl31/sync_handle.h b/include/bl31/sync_handle.h
index e211575..1ac4f98 100644
--- a/include/bl31/sync_handle.h
+++ b/include/bl31/sync_handle.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2023, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,6 +17,7 @@
#define ISS_SYSREG_DIRECTION_MASK 0x000001UL
#define ISS_SYSREG_OPCODE_RNDR 0x30c808U
+#define ISS_SYSREG_OPCODE_IMPDEF 0x303c00U
#define ISS_SYSREG_OPCODE_RNDRRS 0x32c808U
#define TRAP_RET_UNHANDLED -1
@@ -54,6 +56,7 @@
int handle_sysreg_trap(uint64_t esr_el3, cpu_context_t *ctx);
/* Prototypes for system register emulation handlers provided by platforms. */
+int plat_handle_impdef_trap(uint64_t esr_el3, cpu_context_t *ctx);
int plat_handle_rng_trap(uint64_t esr_el3, cpu_context_t *ctx);
#endif /* __ASSEMBLER__ */
diff --git a/include/drivers/arm/cryptocell/712/cc_pal_types_plat.h b/include/drivers/arm/cryptocell/712/cc_pal_types_plat.h
index 8410024..f6d41d7 100644
--- a/include/drivers/arm/cryptocell/712/cc_pal_types_plat.h
+++ b/include/drivers/arm/cryptocell/712/cc_pal_types_plat.h
@@ -9,7 +9,7 @@
*/
#ifndef _CC_PAL_TYPES_PLAT_H
#define _CC_PAL_TYPES_PLAT_H
-/* Host specific types for standard (ISO-C99) compilant platforms */
+/* Host specific types for standard (ISO-C99) compliant platforms */
#include <stddef.h>
#include <stdint.h>
diff --git a/include/drivers/arm/cryptocell/713/cc_pal_types_plat.h b/include/drivers/arm/cryptocell/713/cc_pal_types_plat.h
index 9848472..0c102a0 100644
--- a/include/drivers/arm/cryptocell/713/cc_pal_types_plat.h
+++ b/include/drivers/arm/cryptocell/713/cc_pal_types_plat.h
@@ -9,7 +9,7 @@
*/
#ifndef _CC_PAL_TYPES_PLAT_H
#define _CC_PAL_TYPES_PLAT_H
-/* Host specific types for standard (ISO-C99) compilant platforms */
+/* Host specific types for standard (ISO-C99) compliant platforms */
#include <stddef.h>
#include <stdint.h>
diff --git a/include/drivers/arm/gic600ae_fmu.h b/include/drivers/arm/gic600ae_fmu.h
index 88b87b9..d2a92dd 100644
--- a/include/drivers/arm/gic600ae_fmu.h
+++ b/include/drivers/arm/gic600ae_fmu.h
@@ -85,7 +85,7 @@
#define FMU_BLK_PPI31 U(43)
#define FMU_BLK_PRESENT_MASK U(0xFFFFFFFFFFF)
-/* Safety Mechamism limit */
+/* Safety Mechanism limit */
#define FMU_SMID_GICD_MAX U(33)
#define FMU_SMID_PPI_MAX U(12)
#define FMU_SMID_ITS_MAX U(14)
diff --git a/include/drivers/arm/sbsa.h b/include/drivers/arm/sbsa.h
index 9403634..4ca7194 100644
--- a/include/drivers/arm/sbsa.h
+++ b/include/drivers/arm/sbsa.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,7 +9,12 @@
#include <stdint.h>
-/* Register Offsets */
+/* SBSA Secure Watchdog Register Offsets */
+/* Refresh frame */
+#define SBSA_WDOG_WRR_OFFSET UL(0x000)
+#define SBSA_WDOG_WRR_REFRESH UL(0x1)
+
+/* Control and status frame */
#define SBSA_WDOG_WCS_OFFSET UL(0x000)
#define SBSA_WDOG_WOR_LOW_OFFSET UL(0x008)
#define SBSA_WDOG_WOR_HIGH_OFFSET UL(0x00C)
@@ -20,5 +25,6 @@
void sbsa_wdog_start(uintptr_t base, uint64_t ms);
void sbsa_wdog_stop(uintptr_t base);
+void sbsa_wdog_refresh(uintptr_t refresh_base);
#endif /* SBSA_H */
diff --git a/include/drivers/auth/crypto_mod.h b/include/drivers/auth/crypto_mod.h
index 00ea8c6..bec19da 100644
--- a/include/drivers/auth/crypto_mod.h
+++ b/include/drivers/auth/crypto_mod.h
@@ -46,7 +46,7 @@
const char *name;
/* Initialize library. This function is not expected to fail. All errors
- * must be handled inside the function, asserting or panicing in case of
+ * must be handled inside the function, asserting or panicking in case of
* a non-recoverable error */
void (*init)(void);
diff --git a/include/drivers/brcm/emmc/emmc_csl_sdprot.h b/include/drivers/brcm/emmc/emmc_csl_sdprot.h
index 597e1e0..5801940 100644
--- a/include/drivers/brcm/emmc/emmc_csl_sdprot.h
+++ b/include/drivers/brcm/emmc/emmc_csl_sdprot.h
@@ -139,7 +139,7 @@
* The Common I/O area shall be implemented on all SDIO cards and
* is accessed the the host via I/O reads and writes to function 0,
* the registers within the CIA are provided to enable/disable
- * the operationo fthe i/o funciton.
+ * the operationo fthe i/o function.
*/
/* cccr_sdio_rev */
@@ -303,7 +303,7 @@
#define SBSDIO_CIS_BASE_COMMON 0x1000
/* function 0(common) cis size in bytes */
#define SBSDIO_CIS_FUNC0_LIMIT 0x020
-/* funciton 1 cis size in bytes */
+/* function 1 cis size in bytes */
#define SBSDIO_CIS_SIZE_LIMIT 0x200
/* cis offset addr is < 17 bits */
#define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
@@ -313,7 +313,7 @@
/* indirect cis access (in sprom) */
/* 8 control bytes first, CIS starts from 8th uint8_t */
#define SBSDIO_SPROM_CIS_OFFSET 0x8
-/* sdio uint8_t mode: maximum length of one data comamnd */
+/* sdio uint8_t mode: maximum length of one data command */
#define SBSDIO_BYTEMODE_DATALEN_MAX 64
/* 4317 supports less */
#define SBSDIO_BYTEMODE_DATALEN_MAX_4317 52
diff --git a/include/drivers/brcm/i2c/i2c.h b/include/drivers/brcm/i2c/i2c.h
index 24d42e2..2cc81d5 100644
--- a/include/drivers/brcm/i2c/i2c.h
+++ b/include/drivers/brcm/i2c/i2c.h
@@ -78,7 +78,7 @@
*
* Description:
* This function reads I2C data from a device without specifying
- * a command regsiter.
+ * a command register.
*
* Parameters:
* bus_id - I2C bus ID
@@ -95,7 +95,7 @@
*
* Description:
* This function send I2C data to a device without specifying
- * a command regsiter.
+ * a command register.
*
* Parameters:
* bus_id - I2C bus ID
diff --git a/include/drivers/io/io_dummy.h b/include/drivers/io/io_dummy.h
deleted file mode 100644
index edfc699..0000000
--- a/include/drivers/io/io_dummy.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef IO_DUMMY_H
-#define IO_DUMMY_H
-
-int register_io_dev_dummy(const struct io_dev_connector **dev_con);
-
-#endif /* IO_DUMMY_H */
diff --git a/include/drivers/io/io_storage.h b/include/drivers/io/io_storage.h
index 8f30ed0..3179383 100644
--- a/include/drivers/io/io_storage.h
+++ b/include/drivers/io/io_storage.h
@@ -19,7 +19,6 @@
IO_TYPE_INVALID,
IO_TYPE_SEMIHOSTING,
IO_TYPE_MEMMAP,
- IO_TYPE_DUMMY,
IO_TYPE_FIRMWARE_IMAGE_PACKAGE,
IO_TYPE_BLOCK,
IO_TYPE_MTD,
diff --git a/include/drivers/nxp/crypto/caam/sec_hw_specific.h b/include/drivers/nxp/crypto/caam/sec_hw_specific.h
index 9800793..bc11aca 100644
--- a/include/drivers/nxp/crypto/caam/sec_hw_specific.h
+++ b/include/drivers/nxp/crypto/caam/sec_hw_specific.h
@@ -221,7 +221,7 @@
/* Lists the possible states for a job ring. */
typedef enum sec_job_ring_state_e {
SEC_JOB_RING_STATE_STARTED, /* Job ring is initialized */
- SEC_JOB_RING_STATE_RESET, /* Job ring reset is in progres */
+ SEC_JOB_RING_STATE_RESET, /* Job ring reset is in progress */
} sec_job_ring_state_t;
struct sec_job_ring_t {
diff --git a/include/drivers/nxp/crypto/caam/sec_jr_driver.h b/include/drivers/nxp/crypto/caam/sec_jr_driver.h
index 57e0fa0..a6570d8 100644
--- a/include/drivers/nxp/crypto/caam/sec_jr_driver.h
+++ b/include/drivers/nxp/crypto/caam/sec_jr_driver.h
@@ -57,7 +57,7 @@
/*
* Structure encompassing a job descriptor which is to be processed
* by SEC. User should also initialise this structure with the callback
- * function pointer which will be called by driver after recieving proccessed
+ * function pointer which will be called by driver after receiving proccessed
* descriptor from SEC. User data is also passed in this data structure which
* will be sent as an argument to the user callback function.
*/
diff --git a/include/drivers/nxp/dcfg/dcfg_lsch2.h b/include/drivers/nxp/dcfg/dcfg_lsch2.h
index 882ba5a..bdef6de 100644
--- a/include/drivers/nxp/dcfg/dcfg_lsch2.h
+++ b/include/drivers/nxp/dcfg/dcfg_lsch2.h
@@ -55,7 +55,7 @@
#define DISR5_DDRC1_MASK 0x1
#define DISR5_OCRAM_MASK 0x40
-/* DCFG regsiters bit masks */
+/* DCFG registers bit masks */
#define RCWSR0_SYS_PLL_RAT_SHIFT 25
#define RCWSR0_SYS_PLL_RAT_MASK 0x1f
#define RCWSR0_MEM_PLL_RAT_SHIFT 16
diff --git a/include/drivers/st/stm32_pka.h b/include/drivers/st/stm32_pka.h
index ad4690a..34b3f6b 100644
--- a/include/drivers/st/stm32_pka.h
+++ b/include/drivers/st/stm32_pka.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2022-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,24 +9,11 @@
#include <stdint.h>
-#if !PKA_USE_NIST_P256 && !PKA_USE_BRAINPOOL_P256R1 && !PKA_USE_BRAINPOOL_P256T1 && \
- !PKA_USE_NIST_P521
-#error "At least one ECDSA curve needs to be selected"
-#endif
-
enum stm32_pka_ecdsa_curve_id {
-#if PKA_USE_NIST_P256
PKA_NIST_P256,
-#endif
-#if PKA_USE_BRAINPOOL_P256R1
PKA_BRAINPOOL_P256R1,
-#endif
-#if PKA_USE_BRAINPOOL_P256T1
PKA_BRAINPOOL_P256T1,
-#endif
-#if PKA_USE_NIST_P521
PKA_NIST_P521,
-#endif
};
struct stm32_pka_platdata {
diff --git a/include/lib/coreboot.h b/include/lib/coreboot.h
index 0aa6579..42d4149 100644
--- a/include/lib/coreboot.h
+++ b/include/lib/coreboot.h
@@ -41,5 +41,6 @@
coreboot_memory_t coreboot_get_memory_type(uintptr_t start, size_t size);
void coreboot_table_setup(void *base);
+void coreboot_get_table_location(uint64_t *address, uint32_t *size);
#endif /* COREBOOT_H */
diff --git a/include/lib/cpus/aarch64/generic.h b/include/lib/cpus/aarch64/generic.h
index 53df587..dd71554 100644
--- a/include/lib/cpus/aarch64/generic.h
+++ b/include/lib/cpus/aarch64/generic.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, Arm Limited. All rights reserverd.
+ * Copyright (c) 2020, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index dd2b836..e6af43e 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -523,10 +523,6 @@
void el2_sysregs_context_save_mte(el2_sysregs_t *regs);
void el2_sysregs_context_restore_mte(el2_sysregs_t *regs);
#endif /* CTX_INCLUDE_MTE_REGS */
-#if RAS_EXTENSION
-void el2_sysregs_context_save_ras(el2_sysregs_t *regs);
-void el2_sysregs_context_restore_ras(el2_sysregs_t *regs);
-#endif /* RAS_EXTENSION */
#endif /* CTX_INCLUDE_EL2_REGS */
#if CTX_INCLUDE_FPREGS
diff --git a/include/lib/psci/psci.h b/include/lib/psci/psci.h
index 6d27b7b..4d7e58e 100644
--- a/include/lib/psci/psci.h
+++ b/include/lib/psci/psci.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2023, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -317,6 +318,7 @@
void (*cpu_standby)(plat_local_state_t cpu_state);
int (*pwr_domain_on)(u_register_t mpidr);
void (*pwr_domain_off)(const psci_power_state_t *target_state);
+ int (*pwr_domain_off_early)(const psci_power_state_t *target_state);
void (*pwr_domain_suspend_pwrdown_early)(
const psci_power_state_t *target_state);
#if PSCI_OS_INIT_MODE
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index 925ff21..16be971 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -731,7 +731,7 @@
# define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE
# define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE
# define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \
- + (UL(1) << 21))
+ + SZ_4M)
# elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID
# define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE
# define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index ffbd4ca..e8461f5 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -364,6 +364,7 @@
/* secure watchdog */
void plat_arm_secure_wdt_start(void);
void plat_arm_secure_wdt_stop(void);
+void plat_arm_secure_wdt_refresh(void);
/* Get SOC-ID of ARM platform */
uint32_t plat_arm_get_soc_id(void);
diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h
index dde174c..f87f857 100644
--- a/include/plat/arm/css/common/css_def.h
+++ b/include/plat/arm/css/common/css_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -52,18 +52,21 @@
* terminology. On a GICv2 system or mode, the interrupts will be treated as
* Group 0 interrupts.
*/
-#define CSS_G1S_IRQ_PROPS(grp) \
+#define CSS_G1S_INT_PROPS(grp) \
INTR_PROP_DESC(CSS_IRQ_MHU, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(CSS_IRQ_GPU_SMMU_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(CSS_IRQ_TZC, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_LEVEL), \
- INTR_PROP_DESC(CSS_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \
- GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(CSS_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_LEVEL)
+#define CSS_G1S_IRQ_PROPS(grp) \
+ CSS_G1S_INT_PROPS(grp), \
+ INTR_PROP_DESC(CSS_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_LEVEL)
+
#if CSS_USE_SCMI_SDS_DRIVER
/* Memory region for shared data storage */
#define PLAT_ARM_SDS_MEM_BASE ARM_SHARED_RAM_BASE
diff --git a/include/services/errata_abi_svc.h b/include/services/errata_abi_svc.h
new file mode 100644
index 0000000..1250066
--- /dev/null
+++ b/include/services/errata_abi_svc.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2023, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ERRATA_ABI_SVC_H
+#define ERRATA_ABI_SVC_H
+
+#include <lib/smccc.h>
+
+#define ARM_EM_VERSION U(0x840000F0)
+#define ARM_EM_FEATURES U(0x840000F1)
+#define ARM_EM_CPU_ERRATUM_FEATURES U(0x840000F2)
+
+/* EM version numbers */
+#define EM_VERSION_MAJOR (0x1)
+#define EM_VERSION_MINOR (0x0)
+
+/* EM CPU_ERRATUM_FEATURES return codes */
+#define EM_HIGHER_EL_MITIGATION (3)
+#define EM_NOT_AFFECTED (2)
+#define EM_AFFECTED (1)
+#define EM_SUCCESS (0)
+#define EM_NOT_SUPPORTED (-1)
+#define EM_INVALID_PARAMETERS (-2)
+#define EM_UNKNOWN_ERRATUM (-3)
+
+#if ERRATA_ABI_SUPPORT
+bool is_errata_fid(uint32_t smc_fid);
+#else
+static inline bool is_errata_fid(uint32_t smc_fid)
+{
+ return false;
+}
+#endif /* ERRATA_ABI_SUPPORT */
+uintptr_t errata_abi_smc_handler(
+ uint32_t smc_fid,
+ u_register_t x1,
+ u_register_t x2,
+ u_register_t x3,
+ u_register_t x4,
+ void *cookie,
+ void *handle,
+ u_register_t flags
+);
+#endif /* ERRATA_ABI_SVC_H */
+
diff --git a/include/services/ffa_svc.h b/include/services/ffa_svc.h
index 8bc911a..64af437 100644
--- a/include/services/ffa_svc.h
+++ b/include/services/ffa_svc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -24,7 +24,7 @@
/* The macros below are used to identify FFA calls from the SMC function ID */
#define FFA_FNUM_MIN_VALUE U(0x60)
-#define FFA_FNUM_MAX_VALUE U(0x8B)
+#define FFA_FNUM_MAX_VALUE U(0x8C)
#define is_ffa_fid(fid) __extension__ ({ \
__typeof__(fid) _fid = (fid); \
((GET_SMC_NUM(_fid) >= FFA_FNUM_MIN_VALUE) && \
@@ -118,6 +118,7 @@
#define FFA_FNUM_MSG_SEND2 U(0x86)
#define FFA_FNUM_SECONDARY_EP_REGISTER U(0x87)
#define FFA_FNUM_PARTITION_INFO_GET_REGS U(0x8B)
+#define FFA_FNUM_EL3_INTR_HANDLE U(0x8C)
/* FFA SMC32 FIDs */
#define FFA_ERROR FFA_FID(SMC_32, FFA_FNUM_ERROR)
@@ -163,6 +164,7 @@
#define FFA_MEM_FRAG_TX FFA_FID(SMC_32, FFA_FNUM_MEM_FRAG_TX)
#define FFA_SPM_ID_GET FFA_FID(SMC_32, FFA_FNUM_SPM_ID_GET)
#define FFA_NORMAL_WORLD_RESUME FFA_FID(SMC_32, FFA_FNUM_NORMAL_WORLD_RESUME)
+#define FFA_EL3_INTR_HANDLE FFA_FID(SMC_32, FFA_FNUM_EL3_INTR_HANDLE)
/* FFA SMC64 FIDs */
#define FFA_ERROR_SMC64 FFA_FID(SMC_64, FFA_FNUM_ERROR)
diff --git a/lib/compiler-rt/builtins/assembly.h b/lib/compiler-rt/builtins/assembly.h
index 69a3d86..169d496 100644
--- a/lib/compiler-rt/builtins/assembly.h
+++ b/lib/compiler-rt/builtins/assembly.h
@@ -267,7 +267,7 @@
#define DEFINE_COMPILERRT_FUNCTION_ALIAS(name, target) \
.globl SYMBOL_NAME(name) SEPARATOR \
SYMBOL_IS_FUNC(SYMBOL_NAME(name)) SEPARATOR \
- DECLARE_SYMBOL_VISIBILITY(SYMBOL_NAME(name)) SEPARATOR \
+ DECLARE_SYMBOL_VISIBILITY(name) SEPARATOR \
.set SYMBOL_NAME(name), SYMBOL_NAME(target) SEPARATOR
#if defined(__ARM_EABI__)
diff --git a/lib/compiler-rt/builtins/int_types.h b/lib/compiler-rt/builtins/int_types.h
index 7a72de4..e94d315 100644
--- a/lib/compiler-rt/builtins/int_types.h
+++ b/lib/compiler-rt/builtins/int_types.h
@@ -64,7 +64,7 @@
} udwords;
#if defined(__LP64__) || defined(__wasm__) || defined(__mips64) || \
- defined(__riscv) || defined(_WIN64)
+ defined(__SIZEOF_INT128__) || defined(_WIN64)
#define CRT_HAS_128BIT
#endif
diff --git a/lib/coreboot/coreboot_table.c b/lib/coreboot/coreboot_table.c
index fb31ef1..43e9835 100644
--- a/lib/coreboot/coreboot_table.c
+++ b/lib/coreboot/coreboot_table.c
@@ -46,6 +46,8 @@
coreboot_memrange_t coreboot_memranges[COREBOOT_MAX_MEMRANGES];
coreboot_serial_t coreboot_serial;
+uint64_t coreboot_table_addr;
+uint32_t coreboot_table_size;
/*
* The coreboot table is parsed before the MMU is enabled (i.e. with strongly
@@ -108,6 +110,12 @@
return CB_MEM_NONE;
}
+void coreboot_get_table_location(uint64_t *address, uint32_t *size)
+{
+ *address = coreboot_table_addr;
+ *size = coreboot_table_size;
+}
+
void coreboot_table_setup(void *base)
{
cb_header_t *header = base;
@@ -118,6 +126,8 @@
ERROR("coreboot table signature corrupt!\n");
return;
}
+ coreboot_table_addr = (uint64_t) base;
+ coreboot_table_size = header->header_bytes + header->table_bytes;
ptr = base + header->header_bytes;
for (i = 0; i < header->table_entries; i++) {
diff --git a/lib/cpus/aarch64/cortex_x1.S b/lib/cpus/aarch64/cortex_x1.S
index 9a7f666..de65365 100644
--- a/lib/cpus/aarch64/cortex_x1.S
+++ b/lib/cpus/aarch64/cortex_x1.S
@@ -37,7 +37,7 @@
bl check_errata_1821534
cbz x0, 1f
mrs x1, CORTEX_X1_ACTLR2_EL1
- orr x1, x1, BIT(2)
+ orr x1, x1, #BIT(2)
msr CORTEX_X1_ACTLR2_EL1, x1
isb
1:
@@ -64,7 +64,7 @@
bl check_errata_1688305
cbz x0, 1f
mrs x0, CORTEX_X1_ACTLR2_EL1
- orr x0, x0, BIT(1)
+ orr x0, x0, #BIT(1)
msr CORTEX_X1_ACTLR2_EL1, x0
isb
@@ -92,7 +92,7 @@
bl check_errata_1827429
cbz x0, 1f
mrs x0, CORTEX_X1_CPUECTLR_EL1
- orr x0, x0, BIT(53)
+ orr x0, x0, #BIT(53)
msr CORTEX_X1_CPUECTLR_EL1, x0
isb
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 82a4890..e16c8e4 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -324,6 +324,11 @@
# to revisions r0p0, r1p0, r1p1, and r1p2 of the A78 cpu. It is still open.
CPU_FLAG_LIST += ERRATA_A78_2395406
+# Flag to apply erratum 2712571 workaround for non-arm interconnect ip. This
+# erratum applies to revisions r0p0, r1p0, r1p1, and r1p2 of the A78 cpu.
+# It is fixed in r1p2.
+CPU_FLAG_LIST += ERRATA_A78_2712571
+
# Flag to apply erratum 2742426 workaround during reset. This erratum
# applies to revisions r0p0, r1p0, r1p1 and r1p2 of the A78 cpu. It is still
# open.
@@ -362,6 +367,11 @@
# to revision r0p0 of the A78C cpu. It is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_A78C_1827440
+# Flag to apply erratum 2712574 workaround for non-arm interconnect ip. This
+# erratum applies to revisions r0p0, r0p1 and r0p2 of the A78 AE cpu.
+# It is still open.
+CPU_FLAG_LIST += ERRATA_A78_AE_2712574
+
# Flag to apply erratum 2132064 workaround during reset. This erratum applies
# to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
CPU_FLAG_LIST += ERRATA_A78C_2132064
@@ -378,6 +388,11 @@
# to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
CPU_FLAG_LIST += ERRATA_A78C_2395411
+# Flag to apply erratum 2712575 workaround for non-arm interconnect ip. This
+# erratum applies to revisions r0p1 and r0p2 of the A78C cpu.
+# It is still open.
+CPU_FLAG_LIST += ERRATA_A78C_2712575
+
# Flag to apply erratum 2772121 workaround during powerdown. This erratum
# applies to revisions r0p0, r0p1 and r0p2 of the A78C cpu. It is still open.
CPU_FLAG_LIST += ERRATA_A78C_2772121
@@ -509,6 +524,11 @@
# to revisions r0p0, r1p0 and r1p1 of the Neoverse V1 cpu and is still open.
CPU_FLAG_LIST += ERRATA_V1_2372203
+# Flag to apply erratum 2701953 workaround to non-arm interconnect ip. This
+# erratum applies to revisions r0p0, r1p0, r1p1 of the Neoverse V1 cpu,
+# it is fixed in r1p2.
+CPU_FLAG_LIST += ERRATA_V1_2701953
+
# Flag to apply erratum 2743093 workaround during powerdown. This erratum
# applies to revisions r0p0, r1p0, r1p1 and r1p2 of the Neoverse V1 cpu and is
# still open.
@@ -581,6 +601,11 @@
# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is fixed in r2p1.
CPU_FLAG_LIST += ERRATA_A710_2371105
+# Flag to apply erratum 2701952 workaround for non-arm interconnect ip. This
+# erratum applies to revision r0p0, r1p0, r2p0, r2p1 of the Cortex-A710 cpu
+# and is still open.
+CPU_FLAG_LIST += ERRATA_A710_2701952
+
# Flag to apply erratum 2768515 workaround during power down. This erratum
# applies to revision r0p0, r1p0, r2p0 and r2p1 of the Cortex-A710 cpu and is
# still open.
@@ -638,6 +663,11 @@
# to revision r0p0 of the Neoverse N2 cpu, it is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2388450
+# Flag to apply erratum 2728475 workaround for non-arm interconnect ip. This
+# erratum applies to r0p0, r0p1, r0p2 of the Neoverse N2 cpu, it is fixed in
+# r0p3.
+CPU_FLAG_LIST += ERRATA_N2_2728475
+
# Flag to apply erratum 2743089 workaround during during powerdown. This erratum
# applies to all revisions <= r0p2 of the Neoverse N2 cpu, it is fixed in r0p3.
CPU_FLAG_LIST += ERRATA_N2_2743089
@@ -682,6 +712,11 @@
# to revision r0p0, r1p0 and r2p0 of the Cortex-X2 cpu and is fixed in r2p1.
CPU_FLAG_LIST += ERRATA_X2_2371105
+# Flag to apply erratum 2701952 workaround for non-arm interconnect ip. This
+# erratum applies to revisions r0p0, r1p0, r2p0, r2p1 of the Cortex-x2 cpu
+# and is still open.
+CPU_FLAG_LIST += ERRATA_X2_2701952
+
# Flag to apply erratum 2768515 workaround during power down. This erratum
# applies to revision r0p0, r1p0, r2p0 and r2p1 of the Cortex-X2 cpu and is
# still open.
@@ -743,6 +778,14 @@
# Cortex-A510 cpu and is fixed in r1p3.
CPU_FLAG_LIST += ERRATA_A510_2684597
+# Flag to apply erratum 2719103 workaround for non-arm interconnect ip. This
+# erratum applies to revisions r0p0, rop1. Fixed in r0p2.
+CPU_FLAG_LIST += ERRATA_V2_2719103
+
+# Flag to apply erratum 2701951 workaround for non-arm interconnect ip.
+# This erratum applies to revisions r0p0, r1p0, and r1p1. Its is fixed in r1p2.
+CPU_FLAG_LIST += ERRATA_A715_2701951
+
# Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
# Applying the workaround results in higher DSU power consumption on idle.
CPU_FLAG_LIST += ERRATA_DSU_798953
diff --git a/lib/debugfs/debugfs_smc.c b/lib/debugfs/debugfs_smc.c
index 400c166..13ced3d 100644
--- a/lib/debugfs/debugfs_smc.c
+++ b/lib/debugfs/debugfs_smc.c
@@ -54,7 +54,7 @@
} parms;
/* debugfs_access_lock protects shared buffer and internal */
-/* FS functions from concurrent acccesses. */
+/* FS functions from concurrent accesses. */
static spinlock_t debugfs_access_lock;
static bool debugfs_initialized;
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index 7691171..9922fb1 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -17,10 +17,6 @@
.global el2_sysregs_context_save_mte
.global el2_sysregs_context_restore_mte
#endif /* CTX_INCLUDE_MTE_REGS */
-#if RAS_EXTENSION
- .global el2_sysregs_context_save_ras
- .global el2_sysregs_context_restore_ras
-#endif /* RAS_EXTENSION */
#endif /* CTX_INCLUDE_EL2_REGS */
.global el1_sysregs_context_save
@@ -210,30 +206,6 @@
endfunc el2_sysregs_context_restore_mte
#endif /* CTX_INCLUDE_MTE_REGS */
-#if RAS_EXTENSION
-func el2_sysregs_context_save_ras
- /*
- * VDISR_EL2 and VSESR_EL2 registers are saved only when
- * FEAT_RAS is supported.
- */
- mrs x11, vdisr_el2
- mrs x12, vsesr_el2
- stp x11, x12, [x0, #CTX_VDISR_EL2]
- ret
-endfunc el2_sysregs_context_save_ras
-
-func el2_sysregs_context_restore_ras
- /*
- * VDISR_EL2 and VSESR_EL2 registers are restored only when FEAT_RAS
- * is supported.
- */
- ldp x11, x12, [x0, #CTX_VDISR_EL2]
- msr vdisr_el2, x11
- msr vsesr_el2, x12
- ret
-endfunc el2_sysregs_context_restore_ras
-#endif /* RAS_EXTENSION */
-
#endif /* CTX_INCLUDE_EL2_REGS */
/* ------------------------------------------------------------------
@@ -596,48 +568,12 @@
stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
mrs x18, sp_el0
str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0]
-
- /* ----------------------------------------------------------
- * Check if earlier initialization of MDCR_EL3.SCCD/MCCD to 1
- * has failed.
- *
- * MDCR_EL3:
- * MCCD bit set, Prohibits the Cycle Counter PMCCNTR_EL0 from
- * counting at EL3.
- * SCCD bit set, Secure Cycle Counter Disable. Prohibits PMCCNTR_EL0
- * from counting in Secure state.
- * If these bits are not set, meaning that FEAT_PMUv3p5/7 is
- * not implemented and PMCR_EL0 should be saved in non-secure
- * context.
- * ----------------------------------------------------------
- */
- mov_imm x10, (MDCR_SCCD_BIT | MDCR_MCCD_BIT)
- mrs x9, mdcr_el3
- tst x9, x10
- bne 1f
-
- /* ----------------------------------------------------------
- * If control reaches here, it ensures the Secure Cycle
- * Counter (PMCCNTR_EL0) is not prohibited from counting at
- * EL3 and in secure states.
- * Henceforth, PMCR_EL0 to be saved before world switch.
- * ----------------------------------------------------------
- */
mrs x9, pmcr_el0
-
- /* Check caller's security state */
- mrs x10, scr_el3
- tst x10, #SCR_NS_BIT
- beq 2f
-
- /* Save PMCR_EL0 if called from Non-secure state */
str x9, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0]
-
/* Disable cycle counter when event counting is prohibited */
-2: orr x9, x9, #PMCR_EL0_DP_BIT
+ orr x9, x9, #PMCR_EL0_DP_BIT
msr pmcr_el0, x9
isb
-1:
#if CTX_INCLUDE_PAUTH_REGS
/* ----------------------------------------------------------
* Save the ARMv8.3-PAuth keys as they are not banked
@@ -715,31 +651,8 @@
msr APGAKeyLo_EL1, x8
msr APGAKeyHi_EL1, x9
#endif /* CTX_INCLUDE_PAUTH_REGS */
-
- /* ----------------------------------------------------------
- * Restore PMCR_EL0 when returning to Non-secure state if
- * Secure Cycle Counter is not disabled in MDCR_EL3 when
- * ARMv8.5-PMU is implemented.
- * ----------------------------------------------------------
- */
- mrs x0, scr_el3
- tst x0, #SCR_NS_BIT
- beq 2f
-
- /* ----------------------------------------------------------
- * Back to Non-secure state.
- * Check if earlier initialization MDCR_EL3.SCCD/MCCD to 1
- * failed, meaning that FEAT_PMUv3p5/7 is not implemented and
- * PMCR_EL0 should be restored from non-secure context.
- * ----------------------------------------------------------
- */
- mov_imm x1, (MDCR_SCCD_BIT | MDCR_MCCD_BIT)
- mrs x0, mdcr_el3
- tst x0, x1
- bne 2f
ldr x0, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0]
msr pmcr_el0, x0
-2:
ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
@@ -855,7 +768,12 @@
1:
#endif /* IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639 */
-#if IMAGE_BL31 && RAS_EXTENSION
+/*
+ * This is a hot path, so we don't want to do some actual FEAT_RAS runtime
+ * detection here. The "esb" is a cheaper variant, so using "dsb" in the
+ * ENABLE_FEAT_RAS==2 case is not ideal, but won't hurt.
+ */
+#if IMAGE_BL31 && ENABLE_FEAT_RAS == 1
/* ----------------------------------------------------------
* Issue Error Synchronization Barrier to synchronize SErrors
* before exiting EL3. We're running with EAs unmasked, so
@@ -866,7 +784,7 @@
esb
#else
dsb sy
-#endif /* IMAGE_BL31 && RAS_EXTENSION */
+#endif /* IMAGE_BL31 && ENABLE_FEAT_RAS */
/* ----------------------------------------------------------
* Restore SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index e38b34d..3760b8f 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -457,7 +457,7 @@
void __init cm_init(void)
{
/*
- * The context management library has only global data to intialize, but
+ * The context management library has only global data to initialize, but
* that will be done when the BSS is zeroed out.
*/
}
@@ -517,12 +517,13 @@
amu_enable(el2_unused, ctx);
}
- /* Enable SME, SVE, and FPU/SIMD for non-secure world. */
+ /* Enable SVE and FPU/SIMD */
+ if (is_feat_sve_supported()) {
+ sve_enable(ctx);
+ }
+
if (is_feat_sme_supported()) {
sme_enable(ctx);
- } else if (is_feat_sve_supported()) {
- /* Enable SVE and FPU/SIMD for non-secure world. */
- sve_enable(ctx);
}
if (is_feat_mpam_supported()) {
@@ -553,22 +554,7 @@
static void manage_extensions_secure(cpu_context_t *ctx)
{
#if IMAGE_BL31
-
- if (is_feat_sme_supported()) {
- if (ENABLE_SME_FOR_SWD) {
- /*
- * Enable SME, SVE, FPU/SIMD in secure context, secure manager
- * must ensure SME, SVE, and FPU/SIMD context properly managed.
- */
- sme_enable(ctx);
- } else {
- /*
- * Disable SME, SVE, FPU/SIMD in secure context so non-secure
- * world can safely use the associated registers.
- */
- sme_disable(ctx);
- }
- } else if (is_feat_sve_supported()) {
+ if (is_feat_sve_supported()) {
if (ENABLE_SVE_FOR_SWD) {
/*
* Enable SVE and FPU in secure context, secure manager must
@@ -585,6 +571,21 @@
}
}
+ if (is_feat_sme_supported()) {
+ if (ENABLE_SME_FOR_SWD) {
+ /*
+ * Enable SME, SVE, FPU/SIMD in secure context, secure manager
+ * must ensure SME, SVE, and FPU/SIMD context properly managed.
+ */
+ sme_enable(ctx);
+ } else {
+ /*
+ * Disable SME, SVE, FPU/SIMD in secure context so non-secure
+ * world can safely use the associated registers.
+ */
+ sme_disable(ctx);
+ }
+ }
#endif /* IMAGE_BL31 */
}
@@ -1012,9 +1013,13 @@
write_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2,
read_ttbr1_el2());
}
-#if RAS_EXTENSION
- el2_sysregs_context_save_ras(el2_sysregs_ctx);
-#endif
+
+ if (is_feat_ras_supported()) {
+ write_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2,
+ read_vdisr_el2());
+ write_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2,
+ read_vsesr_el2());
+ }
if (is_feat_nv2_supported()) {
write_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2,
@@ -1095,9 +1100,11 @@
write_contextidr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2));
write_ttbr1_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2));
}
-#if RAS_EXTENSION
- el2_sysregs_context_restore_ras(el2_sysregs_ctx);
-#endif
+
+ if (is_feat_ras_supported()) {
+ write_vdisr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2));
+ write_vsesr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2));
+ }
if (is_feat_nv2_supported()) {
write_vncr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2));
diff --git a/lib/extensions/sme/sme.c b/lib/extensions/sme/sme.c
index f888d12..3423dba 100644
--- a/lib/extensions/sme/sme.c
+++ b/lib/extensions/sme/sme.c
@@ -65,9 +65,6 @@
/* Reset CPTR_EL3 value. */
write_cptr_el3(cptr_el3);
isb();
-
- /* Enable SVE/FPU in addition to SME. */
- sve_enable(context);
}
void sme_disable(cpu_context_t *context)
diff --git a/lib/libc/printf.c b/lib/libc/printf.c
index e52cbed..faccfdf 100644
--- a/lib/libc/printf.c
+++ b/lib/libc/printf.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -81,6 +81,7 @@
* %x - hexadecimal format
* %s - string format
* %d or %i - signed decimal format
+ * %c - character format
* %u - unsigned decimal format
* %p - pointer format
*
@@ -130,6 +131,10 @@
count += unsigned_num_print(unum, 10,
padc, padn);
break;
+ case 'c':
+ (void)putchar(va_arg(args, int));
+ count++;
+ break;
case 's':
str = va_arg(args, char *);
count += string_print(str);
diff --git a/lib/libc/snprintf.c b/lib/libc/snprintf.c
index 0e3256c..21d3416 100644
--- a/lib/libc/snprintf.c
+++ b/lib/libc/snprintf.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -85,6 +85,7 @@
*
* %x (or %X) - hexadecimal format
* %d or %i - signed decimal format
+ * %c - character format
* %s - string format
* %u - unsigned decimal format
* %p - pointer format
@@ -181,6 +182,9 @@
unsigned_num_print(&s, n, &chars_printed,
unum, 10, padc, padn, false);
break;
+ case 'c':
+ CHECK_AND_PUT_CHAR(s, n, chars_printed, va_arg(args, int));
+ break;
case 's':
str = va_arg(args, char *);
string_print(&s, n, &chars_printed, str);
diff --git a/lib/libfdt/fdt.c b/lib/libfdt/fdt.c
index 9fe7cf4..20c6415 100644
--- a/lib/libfdt/fdt.c
+++ b/lib/libfdt/fdt.c
@@ -106,7 +106,6 @@
}
hdrsize = fdt_header_size(fdt);
if (!can_assume(VALID_DTB)) {
-
if ((fdt_totalsize(fdt) < hdrsize)
|| (fdt_totalsize(fdt) > INT_MAX))
return -FDT_ERR_TRUNCATED;
@@ -115,9 +114,7 @@
if (!check_off_(hdrsize, fdt_totalsize(fdt),
fdt_off_mem_rsvmap(fdt)))
return -FDT_ERR_TRUNCATED;
- }
- if (!can_assume(VALID_DTB)) {
/* Bounds check structure block */
if (!can_assume(LATEST) && fdt_version(fdt) < 17) {
if (!check_off_(hdrsize, fdt_totalsize(fdt),
@@ -165,7 +162,7 @@
uint32_t fdt_next_tag(const void *fdt, int startoffset, int *nextoffset)
{
const fdt32_t *tagp, *lenp;
- uint32_t tag;
+ uint32_t tag, len, sum;
int offset = startoffset;
const char *p;
@@ -191,12 +188,19 @@
lenp = fdt_offset_ptr(fdt, offset, sizeof(*lenp));
if (!can_assume(VALID_DTB) && !lenp)
return FDT_END; /* premature end */
+
+ len = fdt32_to_cpu(*lenp);
+ sum = len + offset;
+ if (!can_assume(VALID_DTB) &&
+ (INT_MAX <= sum || sum < (uint32_t) offset))
+ return FDT_END; /* premature end */
+
/* skip-name offset, length and value */
- offset += sizeof(struct fdt_property) - FDT_TAGSIZE
- + fdt32_to_cpu(*lenp);
+ offset += sizeof(struct fdt_property) - FDT_TAGSIZE + len;
+
if (!can_assume(LATEST) &&
- fdt_version(fdt) < 0x10 && fdt32_to_cpu(*lenp) >= 8 &&
- ((offset - fdt32_to_cpu(*lenp)) % 8) != 0)
+ fdt_version(fdt) < 0x10 && len >= 8 &&
+ ((offset - len) % 8) != 0)
offset += 4;
break;
diff --git a/lib/optee/optee_utils.c b/lib/optee/optee_utils.c
index 25272fc..6641db9 100644
--- a/lib/optee/optee_utils.c
+++ b/lib/optee/optee_utils.c
@@ -180,7 +180,7 @@
/*
* Update "pc" value which should comes from pager image. After the
- * header image is parsed, it will be unuseful, and the actual
+ * header image is parsed, it will be useless, and the actual
* execution image after BL31 is pager image.
*/
header_ep->pc = pager_image_info->image_base;
diff --git a/lib/cpus/aarch64/runtime_errata.S b/lib/psci/aarch64/runtime_errata.S
similarity index 100%
rename from lib/cpus/aarch64/runtime_errata.S
rename to lib/psci/aarch64/runtime_errata.S
diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index ebeb10b..c893476 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c
@@ -829,8 +829,11 @@
******************************************************************************/
int psci_validate_mpidr(u_register_t mpidr)
{
- if (plat_core_pos_by_mpidr(mpidr) < 0)
+ int pos = plat_core_pos_by_mpidr(mpidr);
+
+ if ((pos < 0) || ((unsigned int)pos >= PLATFORM_CORE_COUNT)) {
return PSCI_E_INVALID_PARAMS;
+ }
return PSCI_E_SUCCESS;
}
diff --git a/lib/psci/psci_lib.mk b/lib/psci/psci_lib.mk
index 6864202..c71580f 100644
--- a/lib/psci/psci_lib.mk
+++ b/lib/psci/psci_lib.mk
@@ -22,7 +22,7 @@
ifeq (${ARCH}, aarch64)
PSCI_LIB_SOURCES += lib/el3_runtime/aarch64/context.S \
- lib/cpus/aarch64/runtime_errata.S
+ lib/psci/aarch64/runtime_errata.S
endif
ifeq (${USE_COHERENT_MEM}, 1)
diff --git a/lib/psci/psci_off.c b/lib/psci/psci_off.c
index 637adb9..9f36ac7 100644
--- a/lib/psci/psci_off.c
+++ b/lib/psci/psci_off.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2023, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -57,6 +58,19 @@
psci_set_power_off_state(&state_info);
/*
+ * Call the platform provided early CPU_OFF handler to allow
+ * platforms to perform any housekeeping activities before
+ * actually powering the CPU off. PSCI_E_DENIED indicates that
+ * the CPU off sequence should be aborted at this time.
+ */
+ if (psci_plat_pm_ops->pwr_domain_off_early) {
+ rc = psci_plat_pm_ops->pwr_domain_off_early(&state_info);
+ if (rc == PSCI_E_DENIED) {
+ return rc;
+ }
+ }
+
+ /*
* Get the parent nodes here, this is important to do before we
* initiate the power down sequence as after that point the core may
* have exited coherency and its cache may be disabled, any access to
diff --git a/lib/psci/psci_on.c b/lib/psci/psci_on.c
index 6c6b23c..76eb50c 100644
--- a/lib/psci/psci_on.c
+++ b/lib/psci/psci_on.c
@@ -65,13 +65,10 @@
unsigned int target_idx;
/* Calling function must supply valid input arguments */
+ assert(ret >= 0);
+ assert((unsigned int)ret < PLATFORM_CORE_COUNT);
assert(ep != NULL);
- if ((ret < 0) || (ret >= (int)PLATFORM_CORE_COUNT)) {
- ERROR("Unexpected core index.\n");
- panic();
- }
-
target_idx = (unsigned int)ret;
/*
diff --git a/lib/xlat_tables/aarch32/nonlpae_tables.c b/lib/xlat_tables/aarch32/nonlpae_tables.c
index 5646f34..f582404 100644
--- a/lib/xlat_tables/aarch32/nonlpae_tables.c
+++ b/lib/xlat_tables/aarch32/nonlpae_tables.c
@@ -272,7 +272,7 @@
/* Make room for new region by moving other regions up by one place */
(void)memmove(mm + 1, mm, (uintptr_t)mm_last - (uintptr_t)mm);
- /* Check we haven't lost the empty sentinal from the end of the array */
+ /* Check we haven't lost the empty sentinel from the end of the array */
assert(mm_last->size == 0U);
mm->base_pa = base_pa;
diff --git a/lib/xlat_tables/xlat_tables_common.c b/lib/xlat_tables/xlat_tables_common.c
index 71273cb..e2c8370 100644
--- a/lib/xlat_tables/xlat_tables_common.c
+++ b/lib/xlat_tables/xlat_tables_common.c
@@ -161,7 +161,7 @@
/* Make room for new region by moving other regions up by one place */
(void)memmove(mm + 1, mm, (uintptr_t)mm_last - (uintptr_t)mm);
- /* Check we haven't lost the empty sentinal from the end of the array */
+ /* Check we haven't lost the empty sentinel from the end of the array */
assert(mm_last->size == 0U);
mm->base_pa = base_pa;
diff --git a/lib/xlat_tables_v2/xlat_tables_core.c b/lib/xlat_tables_v2/xlat_tables_core.c
index de57184..3a9c058 100644
--- a/lib/xlat_tables_v2/xlat_tables_core.c
+++ b/lib/xlat_tables_v2/xlat_tables_core.c
@@ -988,7 +988,7 @@
(uintptr_t)mm_last - (uintptr_t)mm_cursor);
/*
- * Check we haven't lost the empty sentinal from the end of the array.
+ * Check we haven't lost the empty sentinel from the end of the array.
* This shouldn't happen as we have checked in mmap_add_region_check
* that there is free space.
*/
diff --git a/lib/xlat_tables_v2/xlat_tables_utils.c b/lib/xlat_tables_v2/xlat_tables_utils.c
index 38a375e..f3a53cc 100644
--- a/lib/xlat_tables_v2/xlat_tables_utils.c
+++ b/lib/xlat_tables_v2/xlat_tables_utils.c
@@ -585,7 +585,7 @@
base_va += PAGE_SIZE;
}
- /* Ensure that the last descriptor writen is seen by the system. */
+ /* Ensure that the last descriptor written is seen by the system. */
dsbish();
return 0;
diff --git a/make_helpers/arch_features.mk b/make_helpers/arch_features.mk
index 01e3e09..b799697 100644
--- a/make_helpers/arch_features.mk
+++ b/make_helpers/arch_features.mk
@@ -13,6 +13,11 @@
ENABLE_FEAT_VHE = 1
endif
+# Enable the features which are mandatory from ARCH version 8.2 and upwards.
+ifeq "8.2" "$(word 1, $(sort 8.2 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
+ENABLE_FEAT_RAS = 1
+endif
+
# Enable the features which are mandatory from ARCH version 8.4 and upwards.
ifeq "8.4" "$(word 1, $(sort 8.4 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
ENABLE_FEAT_DIT = 1
diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk
index 9ca6bdf..3bce3a5 100644
--- a/make_helpers/build_macros.mk
+++ b/make_helpers/build_macros.mk
@@ -73,6 +73,7 @@
# Convenience function for verifying option has a boolean value
# $(eval $(call assert_boolean,FOO)) will assert FOO is 0 or 1
define assert_boolean
+ $(if $($(1)),,$(error $(1) must not be empty))
$(if $(filter-out 0 1,$($1)),$(error $1 must be boolean))
endef
@@ -104,6 +105,12 @@
$(shell if $(LD) $(1) -v >/dev/null 2>&1; then echo $(1); fi )
endef
+# Convenience function to check for a given compiler option. A call to
+# $(call cc_option, --no-XYZ) will return --no-XYZ if supported by the compiler
+define cc_option
+ $(shell if $(CC) $(1) -c -x c /dev/null -o /dev/null >/dev/null 2>&1; then echo $(1); fi )
+endef
+
# CREATE_SEQ is a recursive function to create sequence of numbers from 1 to
# $(2) and assign the sequence to $(1)
define CREATE_SEQ
@@ -326,7 +333,10 @@
$(eval OBJ := $(1)/$(patsubst %.c,%.o,$(notdir $(2))))
$(eval DEP := $(patsubst %.o,%.d,$(OBJ)))
-$(eval BL_CPPFLAGS := $($(call uppercase,$(3))_CPPFLAGS) -DIMAGE_$(call uppercase,$(3)))
+
+$(eval BL_DEFINES := $($(call uppercase,$(3))_DEFINES))
+$(eval BL_INCLUDE_DIRS := $($(call uppercase,$(3))_INCLUDE_DIRS))
+$(eval BL_CPPFLAGS := $($(call uppercase,$(3))_CPPFLAGS) -DIMAGE_$(call uppercase,$(3)) $(addprefix -D,$(BL_DEFINES)) $(addprefix -I,$(BL_INCLUDE_DIRS)))
$(eval BL_CFLAGS := $($(call uppercase,$(3))_CFLAGS))
$(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | $(3)_dirs
@@ -346,7 +356,10 @@
$(eval OBJ := $(1)/$(patsubst %.S,%.o,$(notdir $(2))))
$(eval DEP := $(patsubst %.o,%.d,$(OBJ)))
-$(eval BL_CPPFLAGS := $($(call uppercase,$(3))_CPPFLAGS) -DIMAGE_$(call uppercase,$(3)))
+
+$(eval BL_DEFINES := $($(call uppercase,$(3))_DEFINES))
+$(eval BL_INCLUDE_DIRS := $($(call uppercase,$(3))_INCLUDE_DIRS))
+$(eval BL_CPPFLAGS := $($(call uppercase,$(3))_CPPFLAGS) -DIMAGE_$(call uppercase,$(3)) $(addprefix -D,$(BL_DEFINES)) $(addprefix -I,$(BL_INCLUDE_DIRS)))
$(eval BL_ASFLAGS := $($(call uppercase,$(3))_ASFLAGS))
$(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | $(3)_dirs
@@ -365,7 +378,10 @@
define MAKE_LD
$(eval DEP := $(1).d)
-$(eval BL_CPPFLAGS := $($(call uppercase,$(3))_CPPFLAGS) -DIMAGE_$(call uppercase,$(3)))
+
+$(eval BL_DEFINES := $($(call uppercase,$(3))_DEFINES))
+$(eval BL_INCLUDE_DIRS := $($(call uppercase,$(3))_INCLUDE_DIRS))
+$(eval BL_CPPFLAGS := $($(call uppercase,$(3))_CPPFLAGS) -DIMAGE_$(call uppercase,$(3)) $(addprefix -D,$(BL_DEFINES)) $(addprefix -I,$(BL_INCLUDE_DIRS)))
$(1): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | $(3)_dirs
$$(ECHO) " PP $$<"
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index 021893c..f9077eb 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -243,6 +243,9 @@
# operations.
HW_ASSISTED_COHERENCY := 0
+# Flag to enable trapping of implementation defined sytem registers
+IMPDEF_SYSREG_TRAP := 0
+
# Set the default algorithm for the generation of Trusted Board Boot keys
KEY_ALG := rsa
@@ -273,8 +276,9 @@
# Enable PSCI OS-initiated mode support
PSCI_OS_INIT_MODE := 0
-# Enable RAS support
-RAS_EXTENSION := 0
+# Enable RAS Support
+ENABLE_FEAT_RAS := 0
+RAS_FFH_SUPPORT := 0
# By default, BL1 acts as the reset handler, not BL31
RESET_TO_BL31 := 0
@@ -288,6 +292,12 @@
# True Random Number firmware Interface support
TRNG_SUPPORT := 0
+# Check to see if Errata ABI is supported
+ERRATA_ABI_SUPPORT := 0
+
+# Check to enable Errata ABI for platforms with non-arm interconnect
+ERRATA_NON_ARM_INTERCONNECT := 0
+
# SMCCC PCI support
SMC_PCI_SUPPORT := 0
@@ -398,14 +408,6 @@
# SME defaults to disabled
ENABLE_SME_FOR_NS := 0
ENABLE_SME_FOR_SWD := 0
-
-# If SME is enabled then force SVE off
-ifneq (${ENABLE_SME_FOR_NS},0)
- override ENABLE_SVE_FOR_NS := 0
- override ENABLE_SVE_FOR_SWD := 0
-endif
-
-# SME2 defaults to disabled
ENABLE_SME2_FOR_NS := 0
SANITIZE_UB := off
diff --git a/package-lock.json b/package-lock.json
index a3e0ff9..89ebd51 100644
--- a/package-lock.json
+++ b/package-lock.json
@@ -1,12 +1,12 @@
{
"name": "trusted-firmware-a",
- "version": "2.8.0",
+ "version": "2.9.0",
"lockfileVersion": 2,
"requires": true,
"packages": {
"": {
"name": "trusted-firmware-a",
- "version": "2.8.0",
+ "version": "2.9.0",
"hasInstallScript": true,
"license": "BSD-3-Clause",
"devDependencies": {
diff --git a/package.json b/package.json
index 8d4dd54..8b724dae 100644
--- a/package.json
+++ b/package.json
@@ -1,6 +1,6 @@
{
"name": "trusted-firmware-a",
- "version": "2.8.0",
+ "version": "2.9.0",
"license": "BSD-3-Clause",
"private": true,
"scripts": {
diff --git a/plat/allwinner/common/include/sunxi_cpucfg_ncat.h b/plat/allwinner/common/include/sunxi_cpucfg_ncat.h
new file mode 100644
index 0000000..22828c2
--- /dev/null
+++ b/plat/allwinner/common/include/sunxi_cpucfg_ncat.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SUNXI_CPUCFG_H
+#define SUNXI_CPUCFG_H
+
+#include <sunxi_mmap.h>
+
+/* c = cluster, n = core */
+#define SUNXI_CPUCFG_CLS_CTRL_REG0(c) (SUNXI_CPUCFG_BASE + 0x0010 + (c) * 0x10)
+#define SUNXI_CPUCFG_CLS_CTRL_REG1(c) (SUNXI_CPUCFG_BASE + 0x0014 + (c) * 0x10)
+#define SUNXI_CPUCFG_CACHE_CFG_REG (SUNXI_CPUCFG_BASE + 0x0024)
+/* The T507 datasheet does not mention this register. */
+#define SUNXI_CPUCFG_DBG_REG0 (SUNXI_CPUCFG_BASE + 0x00c0)
+
+#define SUNXI_CPUCFG_RST_CTRL_REG(c) (SUNXI_CPUCFG_BASE + 0x0000 + (c) * 4)
+#define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8)
+#define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8)
+
+#define SUNXI_C0_CPU_CTRL_REG(n) (SUNXI_CPUCFG_BASE + 0x0060 + (n) * 4)
+
+#define SUNXI_CPU_CTRL_REG(n) (SUNXI_CPUSUBSYS_BASE + 0x20 + (n) * 4)
+#define SUNXI_ALT_RVBAR_LO_REG(n) (SUNXI_CPUSUBSYS_BASE + 0x40 + (n) * 8)
+#define SUNXI_ALT_RVBAR_HI_REG(n) (SUNXI_CPUSUBSYS_BASE + 0x44 + (n) * 8)
+
+#define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0040 + (c) * 4)
+#define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0044 + (c) * 4)
+#define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \
+ (c) * 0x10 + (n) * 4)
+#define SUNXI_CPU_UNK_REG(n) (SUNXI_R_CPUCFG_BASE + 0x0070 + (n) * 4)
+
+#define SUNXI_CPUIDLE_EN_REG (SUNXI_R_CPUCFG_BASE + 0x0100)
+#define SUNXI_CORE_CLOSE_REG (SUNXI_R_CPUCFG_BASE + 0x0104)
+#define SUNXI_PWR_SW_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0140)
+#define SUNXI_CONFIG_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0144)
+
+#define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_CLS_CTRL_REG0
+#define SUNXI_AA64nAA32_OFFSET 24
+
+#endif /* SUNXI_CPUCFG_H */
diff --git a/plat/allwinner/common/include/sunxi_cpucfg_ncat2.h b/plat/allwinner/common/include/sunxi_cpucfg_ncat2.h
new file mode 100644
index 0000000..d4aec19
--- /dev/null
+++ b/plat/allwinner/common/include/sunxi_cpucfg_ncat2.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2021 Sipeed
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SUNXI_CPUCFG_H
+#define SUNXI_CPUCFG_H
+
+#include <sunxi_mmap.h>
+
+/* c = cluster, n = core */
+#define SUNXI_CPUCFG_CLS_CTRL_REG0(c) (SUNXI_C0_CPUXCFG_BASE + 0x0010)
+#define SUNXI_CPUCFG_CLS_CTRL_REG1(c) (SUNXI_C0_CPUXCFG_BASE + 0x0014)
+#define SUNXI_CPUCFG_CACHE_CFG_REG (SUNXI_C0_CPUXCFG_BASE + 0x0024)
+#define SUNXI_CPUCFG_DBG_REG0 (SUNXI_C0_CPUXCFG_BASE + 0x00c0)
+
+#define SUNXI_CPUCFG_RST_CTRL_REG(c) (SUNXI_C0_CPUXCFG_BASE + 0x0000)
+#define SUNXI_CPUCFG_GEN_CTRL_REG0(c) (SUNXI_CPUCFG_BASE + 0x0000)
+#define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8)
+#define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8)
+
+#define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0040 + (c) * 4)
+#define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0044 + (c) * 4)
+#define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \
+ (c) * 0x10 + (n) * 4)
+
+#define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_GEN_CTRL_REG0
+#define SUNXI_AA64nAA32_OFFSET 4
+
+static inline bool sunxi_cpucfg_has_per_cluster_regs(void)
+{
+ return true;
+}
+
+#endif /* SUNXI_CPUCFG_H */
diff --git a/plat/allwinner/common/include/sunxi_def.h b/plat/allwinner/common/include/sunxi_def.h
index c17ef95..20f6c49 100644
--- a/plat/allwinner/common/include/sunxi_def.h
+++ b/plat/allwinner/common/include/sunxi_def.h
@@ -20,6 +20,7 @@
#define SUNXI_SOC_H616 0x1823
#define SUNXI_SOC_R329 0x1851
+#define SUNXI_VER_BITS_MASK 0xffU
#define JEDEC_ALLWINNER_BKID 9U
#define JEDEC_ALLWINNER_MFID 0x9eU
diff --git a/plat/allwinner/common/sunxi_common.c b/plat/allwinner/common/sunxi_common.c
index 092659c..62f4fcb 100644
--- a/plat/allwinner/common/sunxi_common.c
+++ b/plat/allwinner/common/sunxi_common.c
@@ -183,5 +183,5 @@
{
uint32_t reg = mmio_read_32(SRAM_VER_REG);
- return reg & GENMASK_32(7, 0);
+ return reg & SUNXI_VER_BITS_MASK;
}
diff --git a/plat/allwinner/common/sunxi_cpu_ops.c b/plat/allwinner/common/sunxi_cpu_ops.c
index 46e7090..30841e2 100644
--- a/plat/allwinner/common/sunxi_cpu_ops.c
+++ b/plat/allwinner/common/sunxi_cpu_ops.c
@@ -19,6 +19,12 @@
#include <sunxi_mmap.h>
#include <sunxi_private.h>
+#ifndef SUNXI_C0_CPU_CTRL_REG
+#define SUNXI_C0_CPU_CTRL_REG(n) 0
+#define SUNXI_CPU_UNK_REG(n) 0
+#define SUNXI_CPU_CTRL_REG(n) 0
+#endif
+
static void sunxi_cpu_disable_power(unsigned int cluster, unsigned int core)
{
if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0xff)
@@ -53,15 +59,30 @@
VERBOSE("PSCI: Powering off cluster %d core %d\n", cluster, core);
- /* Deassert DBGPWRDUP */
- mmio_clrbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
- /* Activate the core output clamps, but not for core 0. */
- if (core != 0)
- mmio_setbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core));
- /* Assert CPU power-on reset */
- mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
- /* Remove power from the CPU */
- sunxi_cpu_disable_power(cluster, core);
+ if (sunxi_cpucfg_has_per_cluster_regs()) {
+ /* Deassert DBGPWRDUP */
+ mmio_clrbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
+ /* Activate the core output clamps, but not for core 0. */
+ if (core != 0) {
+ mmio_setbits_32(SUNXI_POWEROFF_GATING_REG(cluster),
+ BIT(core));
+ }
+ /* Assert CPU power-on reset */
+ mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
+ /* Remove power from the CPU */
+ sunxi_cpu_disable_power(cluster, core);
+ } else {
+ /* power down(?) debug core */
+ mmio_clrbits_32(SUNXI_C0_CPU_CTRL_REG(core), BIT(8));
+ /* ??? Activate the core output clamps, but not for core 0 */
+ if (core != 0) {
+ mmio_setbits_32(SUNXI_CPU_UNK_REG(core), BIT(1));
+ }
+ /* ??? Assert CPU power-on reset ??? */
+ mmio_clrbits_32(SUNXI_CPU_UNK_REG(core), BIT(0));
+ /* Remove power from the CPU */
+ sunxi_cpu_disable_power(cluster, core);
+ }
}
void sunxi_cpu_on(u_register_t mpidr)
@@ -71,23 +92,45 @@
VERBOSE("PSCI: Powering on cluster %d core %d\n", cluster, core);
+ if (sunxi_cpucfg_has_per_cluster_regs()) {
+ /* Assert CPU core reset */
+ mmio_clrbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core));
+ /* Assert CPU power-on reset */
+ mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
+ /* Set CPU to start in AArch64 mode */
+ mmio_setbits_32(SUNXI_AA64nAA32_REG(cluster),
+ BIT(SUNXI_AA64nAA32_OFFSET + core));
+ /* Apply power to the CPU */
+ sunxi_cpu_enable_power(cluster, core);
+ /* Release the core output clamps */
+ mmio_clrbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core));
+ /* Deassert CPU power-on reset */
+ mmio_setbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
+ /* Deassert CPU core reset */
+ mmio_setbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core));
+ /* Assert DBGPWRDUP */
+ mmio_setbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
+ } else {
+ /* Assert CPU core reset */
+ mmio_clrbits_32(SUNXI_C0_CPU_CTRL_REG(core), BIT(0));
+ /* ??? Assert CPU power-on reset ??? */
+ mmio_clrbits_32(SUNXI_CPU_UNK_REG(core), BIT(0));
+
+ /* Set CPU to start in AArch64 mode */
+ mmio_setbits_32(SUNXI_CPU_CTRL_REG(core), BIT(0));
+
+ /* Apply power to the CPU */
+ sunxi_cpu_enable_power(cluster, core);
+
- /* Assert CPU core reset */
- mmio_clrbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core));
- /* Assert CPU power-on reset */
- mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
- /* Set CPU to start in AArch64 mode */
- mmio_setbits_32(SUNXI_AA64nAA32_REG(cluster),
- BIT(SUNXI_AA64nAA32_OFFSET + core));
- /* Apply power to the CPU */
- sunxi_cpu_enable_power(cluster, core);
- /* Release the core output clamps */
- mmio_clrbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core));
- /* Deassert CPU power-on reset */
- mmio_setbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
- /* Deassert CPU core reset */
- mmio_setbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core));
- /* Assert DBGPWRDUP */
- mmio_setbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
+ /* ??? Release the core output clamps ??? */
+ mmio_clrbits_32(SUNXI_CPU_UNK_REG(core), BIT(1));
+ /* ??? Deassert CPU power-on reset ??? */
+ mmio_setbits_32(SUNXI_CPU_UNK_REG(core), BIT(0));
+ /* Deassert CPU core reset */
+ mmio_setbits_32(SUNXI_C0_CPU_CTRL_REG(core), BIT(0));
+ /* power up(?) debug core */
+ mmio_setbits_32(SUNXI_C0_CPU_CTRL_REG(core), BIT(8));
+ }
}
void sunxi_cpu_power_off_others(void)
diff --git a/plat/allwinner/common/sunxi_pm.c b/plat/allwinner/common/sunxi_pm.c
index 3772b4a..ebc406b 100644
--- a/plat/allwinner/common/sunxi_pm.c
+++ b/plat/allwinner/common/sunxi_pm.c
@@ -25,6 +25,11 @@
}
#endif
+#ifndef SUNXI_ALT_RVBAR_LO_REG
+#define SUNXI_ALT_RVBAR_LO_REG(n) 0
+#define SUNXI_ALT_RVBAR_HI_REG(n) 0
+#endif
+
int sunxi_validate_ns_entrypoint(uintptr_t ns_entrypoint)
{
/* The non-secure entry point must be in DRAM */
@@ -42,10 +47,17 @@
/* Program all CPU entry points. */
for (unsigned int cpu = 0; cpu < PLATFORM_CORE_COUNT; ++cpu) {
- mmio_write_32(SUNXI_CPUCFG_RVBAR_LO_REG(cpu),
- sec_entrypoint & 0xffffffff);
- mmio_write_32(SUNXI_CPUCFG_RVBAR_HI_REG(cpu),
- sec_entrypoint >> 32);
+ if (sunxi_cpucfg_has_per_cluster_regs()) {
+ mmio_write_32(SUNXI_CPUCFG_RVBAR_LO_REG(cpu),
+ sec_entrypoint & 0xffffffff);
+ mmio_write_32(SUNXI_CPUCFG_RVBAR_HI_REG(cpu),
+ sec_entrypoint >> 32);
+ } else {
+ mmio_write_32(SUNXI_ALT_RVBAR_LO_REG(cpu),
+ sec_entrypoint & 0xffffffff);
+ mmio_write_32(SUNXI_ALT_RVBAR_HI_REG(cpu),
+ sec_entrypoint >> 32);
+ }
}
if (sunxi_set_scpi_psci_ops(psci_ops) == 0) {
diff --git a/plat/allwinner/sun50i_a64/include/sunxi_cpucfg.h b/plat/allwinner/sun50i_a64/include/sunxi_cpucfg.h
index aed3585..ddd53ba 100644
--- a/plat/allwinner/sun50i_a64/include/sunxi_cpucfg.h
+++ b/plat/allwinner/sun50i_a64/include/sunxi_cpucfg.h
@@ -36,4 +36,9 @@
#define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_CLS_CTRL_REG0
#define SUNXI_AA64nAA32_OFFSET 24
+static inline bool sunxi_cpucfg_has_per_cluster_regs(void)
+{
+ return true;
+}
+
#endif /* SUNXI_CPUCFG_H */
diff --git a/plat/allwinner/sun50i_h6/include/sunxi_cpucfg.h b/plat/allwinner/sun50i_h6/include/sunxi_cpucfg.h
index 5bfda5d..585c51b 100644
--- a/plat/allwinner/sun50i_h6/include/sunxi_cpucfg.h
+++ b/plat/allwinner/sun50i_h6/include/sunxi_cpucfg.h
@@ -1,35 +1,6 @@
-/*
- * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef SUNXI_CPUCFG_H
-#define SUNXI_CPUCFG_H
-
-#include <sunxi_mmap.h>
-
-/* c = cluster, n = core */
-#define SUNXI_CPUCFG_CLS_CTRL_REG0(c) (SUNXI_CPUCFG_BASE + 0x0010 + (c) * 0x10)
-#define SUNXI_CPUCFG_CLS_CTRL_REG1(c) (SUNXI_CPUCFG_BASE + 0x0014 + (c) * 0x10)
-#define SUNXI_CPUCFG_CACHE_CFG_REG (SUNXI_CPUCFG_BASE + 0x0024)
-#define SUNXI_CPUCFG_DBG_REG0 (SUNXI_CPUCFG_BASE + 0x00c0)
-
-#define SUNXI_CPUCFG_RST_CTRL_REG(c) (SUNXI_CPUCFG_BASE + 0x0000 + (c) * 4)
-#define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8)
-#define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8)
-
-#define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0040 + (c) * 4)
-#define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0044 + (c) * 4)
-#define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \
- (c) * 0x10 + (n) * 4)
-
-#define SUNXI_CPUIDLE_EN_REG (SUNXI_R_CPUCFG_BASE + 0x0100)
-#define SUNXI_CORE_CLOSE_REG (SUNXI_R_CPUCFG_BASE + 0x0104)
-#define SUNXI_PWR_SW_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0140)
-#define SUNXI_CONFIG_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0144)
-
-#define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_CLS_CTRL_REG0
-#define SUNXI_AA64nAA32_OFFSET 24
+#include <sunxi_cpucfg_ncat.h>
-#endif /* SUNXI_CPUCFG_H */
+static inline bool sunxi_cpucfg_has_per_cluster_regs(void)
+{
+ return true;
+}
diff --git a/plat/allwinner/sun50i_h6/include/sunxi_mmap.h b/plat/allwinner/sun50i_h6/include/sunxi_mmap.h
index 58216d8..43133be 100644
--- a/plat/allwinner/sun50i_h6/include/sunxi_mmap.h
+++ b/plat/allwinner/sun50i_h6/include/sunxi_mmap.h
@@ -59,5 +59,6 @@
#define SUNXI_R_RSB_BASE 0x07083000
#define SUNXI_R_UART_BASE 0x07080000
#define SUNXI_R_PIO_BASE 0x07022000
+#define SUNXI_CPUSUBSYS_BASE 0x08100000
#endif /* SUNXI_MMAP_H */
diff --git a/plat/allwinner/sun50i_h616/include/sunxi_cpucfg.h b/plat/allwinner/sun50i_h616/include/sunxi_cpucfg.h
index dab663b..5c590e4 100644
--- a/plat/allwinner/sun50i_h616/include/sunxi_cpucfg.h
+++ b/plat/allwinner/sun50i_h616/include/sunxi_cpucfg.h
@@ -1,35 +1,8 @@
-/*
- * Copyright (c) 2017-2020, ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
+#include <plat/common/platform.h>
-#ifndef SUNXI_CPUCFG_H
-#define SUNXI_CPUCFG_H
-
-#include <sunxi_mmap.h>
-
-/* c = cluster, n = core */
-#define SUNXI_CPUCFG_CLS_CTRL_REG0(c) (SUNXI_CPUCFG_BASE + 0x0010 + (c) * 0x10)
-#define SUNXI_CPUCFG_CLS_CTRL_REG1(c) (SUNXI_CPUCFG_BASE + 0x0014 + (c) * 0x10)
-#define SUNXI_CPUCFG_CACHE_CFG_REG (SUNXI_CPUCFG_BASE + 0x0024)
-#define SUNXI_CPUCFG_DBG_REG0 (SUNXI_CPUCFG_BASE + 0x00c0)
-
-#define SUNXI_CPUCFG_RST_CTRL_REG(c) (SUNXI_CPUCFG_BASE + 0x0000 + (c) * 4)
-#define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8)
-#define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8)
-
-#define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0040 + (c) * 4)
-#define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0044 + (c) * 4)
-#define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \
- (c) * 0x10 + (n) * 4)
-
-#define SUNXI_CPUIDLE_EN_REG (SUNXI_R_CPUCFG_BASE + 0x0100)
-#define SUNXI_CORE_CLOSE_REG (SUNXI_R_CPUCFG_BASE + 0x0104)
-#define SUNXI_PWR_SW_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0140)
-#define SUNXI_CONFIG_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0144)
-
-#define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_CLS_CTRL_REG0
-#define SUNXI_AA64nAA32_OFFSET 24
+#include <sunxi_cpucfg_ncat.h>
-#endif /* SUNXI_CPUCFG_H */
+static inline bool sunxi_cpucfg_has_per_cluster_regs(void)
+{
+ return (plat_get_soc_revision() != 2);
+}
diff --git a/plat/allwinner/sun50i_h616/include/sunxi_mmap.h b/plat/allwinner/sun50i_h616/include/sunxi_mmap.h
index 3b4f4a0..24a4ba8 100644
--- a/plat/allwinner/sun50i_h616/include/sunxi_mmap.h
+++ b/plat/allwinner/sun50i_h616/include/sunxi_mmap.h
@@ -41,6 +41,7 @@
#define SUNXI_R_UART_BASE 0x07080000
#define SUNXI_R_I2C_BASE 0x07081400
#define SUNXI_R_RSB_BASE 0x07083000
+#define SUNXI_CPUSUBSYS_BASE 0x08100000
#define SUNXI_CPUCFG_BASE 0x09010000
#endif /* SUNXI_MMAP_H */
diff --git a/plat/allwinner/sun50i_r329/include/sunxi_cpucfg.h b/plat/allwinner/sun50i_r329/include/sunxi_cpucfg.h
index 9478f32..3c3530f 100644
--- a/plat/allwinner/sun50i_r329/include/sunxi_cpucfg.h
+++ b/plat/allwinner/sun50i_r329/include/sunxi_cpucfg.h
@@ -1,31 +1 @@
-/*
- * Copyright (c) 2021 Sipeed
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef SUNXI_CPUCFG_H
-#define SUNXI_CPUCFG_H
-
-#include <sunxi_mmap.h>
-
-/* c = cluster, n = core */
-#define SUNXI_CPUCFG_CLS_CTRL_REG0(c) (SUNXI_C0_CPUXCFG_BASE + 0x0010)
-#define SUNXI_CPUCFG_CLS_CTRL_REG1(c) (SUNXI_C0_CPUXCFG_BASE + 0x0014)
-#define SUNXI_CPUCFG_CACHE_CFG_REG (SUNXI_C0_CPUXCFG_BASE + 0x0024)
-#define SUNXI_CPUCFG_DBG_REG0 (SUNXI_C0_CPUXCFG_BASE + 0x00c0)
-
-#define SUNXI_CPUCFG_RST_CTRL_REG(c) (SUNXI_C0_CPUXCFG_BASE + 0x0000)
-#define SUNXI_CPUCFG_GEN_CTRL_REG0(c) (SUNXI_CPUCFG_BASE + 0x0000)
-#define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8)
-#define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8)
-
-#define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0040 + (c) * 4)
-#define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0044 + (c) * 4)
-#define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \
- (c) * 0x10 + (n) * 4)
-
-#define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_GEN_CTRL_REG0
-#define SUNXI_AA64nAA32_OFFSET 4
-
-#endif /* SUNXI_CPUCFG_H */
+#include <sunxi_cpucfg_ncat2.h>
diff --git a/plat/arm/board/a5ds/platform.mk b/plat/arm/board/a5ds/platform.mk
index 4f87306..6fcf080 100644
--- a/plat/arm/board/a5ds/platform.mk
+++ b/plat/arm/board/a5ds/platform.mk
@@ -100,6 +100,8 @@
MULTI_CONSOLE_API := 1
+ARM_DISABLE_TRUSTED_WDOG := 1
+
PLAT_BL_COMMON_SOURCES += lib/xlat_tables/aarch32/nonlpae_tables.c
# Use translation tables library v1 when using Cortex-A5
diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk
index 109bfbe..f88eaa8 100644
--- a/plat/arm/board/arm_fpga/platform.mk
+++ b/plat/arm/board/arm_fpga/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+# Copyright (c) 2021-2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -58,23 +58,19 @@
lib/cpus/aarch64/cortex_a73.S
else
# AArch64-only cores
- FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \
- lib/cpus/aarch64/cortex_a76ae.S \
- lib/cpus/aarch64/cortex_a77.S \
- lib/cpus/aarch64/cortex_a78.S \
- lib/cpus/aarch64/neoverse_n_common.S \
- lib/cpus/aarch64/neoverse_n1.S \
- lib/cpus/aarch64/neoverse_n2.S \
- lib/cpus/aarch64/neoverse_e1.S \
- lib/cpus/aarch64/neoverse_v1.S \
- lib/cpus/aarch64/cortex_a78_ae.S \
- lib/cpus/aarch64/cortex_a65.S \
- lib/cpus/aarch64/cortex_a65ae.S \
- lib/cpus/aarch64/cortex_a510.S \
- lib/cpus/aarch64/cortex_a710.S \
- lib/cpus/aarch64/cortex_a715.S \
- lib/cpus/aarch64/cortex_x3.S \
- lib/cpus/aarch64/cortex_a78c.S
+ FPGA_CPU_LIBS +=lib/cpus/aarch64/cortex_a510.S \
+ lib/cpus/aarch64/cortex_a710.S \
+ lib/cpus/aarch64/cortex_a715.S \
+ lib/cpus/aarch64/cortex_x3.S \
+ lib/cpus/aarch64/neoverse_n_common.S \
+ lib/cpus/aarch64/neoverse_n1.S \
+ lib/cpus/aarch64/neoverse_n2.S \
+ lib/cpus/aarch64/neoverse_v1.S \
+ lib/cpus/aarch64/cortex_hayes.S \
+ lib/cpus/aarch64/cortex_hunter.S \
+ lib/cpus/aarch64/cortex_hunter_elp_arm.S \
+ lib/cpus/aarch64/cortex_chaberton.S \
+ lib/cpus/aarch64/cortex_blackhawk.S
# AArch64/AArch32 cores
FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
diff --git a/plat/arm/board/corstone1000/common/corstone1000_bl31_setup.c b/plat/arm/board/corstone1000/common/corstone1000_bl31_setup.c
new file mode 100644
index 0000000..2549d35
--- /dev/null
+++ b/plat/arm/board/corstone1000/common/corstone1000_bl31_setup.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#if defined(SPD_spmd) && (SPMC_AT_EL3 == 0)
+/*
+ * A dummy implementation of the platform handler for Group0 secure interrupt.
+ */
+int plat_spmd_handle_group0_interrupt(uint32_t intid)
+{
+ (void)intid;
+ return -1;
+}
+#endif /*defined(SPD_spmd) && (SPMC_AT_EL3 == 0)*/
diff --git a/plat/arm/board/corstone1000/platform.mk b/plat/arm/board/corstone1000/platform.mk
index d891691..3edffe0 100644
--- a/plat/arm/board/corstone1000/platform.mk
+++ b/plat/arm/board/corstone1000/platform.mk
@@ -56,6 +56,7 @@
plat/arm/board/corstone1000/common/corstone1000_security.c \
plat/arm/board/corstone1000/common/corstone1000_plat.c \
plat/arm/board/corstone1000/common/corstone1000_pm.c \
+ plat/arm/board/corstone1000/common/corstone1000_bl31_setup.c \
${CORSTONE1000_CPU_LIBS} \
${CORSTONE1000_GIC_SOURCES}
diff --git a/plat/arm/board/fvp/aarch64/fvp_ras.c b/plat/arm/board/fvp/aarch64/fvp_ras.c
index 759f6d0..f9b9634 100644
--- a/plat/arm/board/fvp/aarch64/fvp_ras.c
+++ b/plat/arm/board/fvp/aarch64/fvp_ras.c
@@ -4,12 +4,63 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <inttypes.h>
+#include <stdint.h>
+
#include <lib/extensions/ras.h>
+#include <services/sdei.h>
+
+#ifdef PLATFORM_TEST_RAS_FFH
+static int injected_fault_handler(const struct err_record_info *info,
+ int probe_data, const struct err_handler_data *const data)
+{
+ uint64_t status;
+ int ret;
+
+ /*
+ * The faulting error record is already selected by the SER probe
+ * function.
+ */
+ status = read_erxstatus_el1();
+
+ ERROR("Fault reported by system error record %d on 0x%lx: status=0x%" PRIx64 "\n",
+ probe_data, read_mpidr_el1(), status);
+ ERROR(" exception reason=%u syndrome=0x%" PRIx64 "\n", data->ea_reason,
+ data->flags);
+
+ /* Clear error */
+ write_erxstatus_el1(status);
+
+ ret = sdei_dispatch_event(5000);
+ if (ret < 0) {
+ ERROR("Can't dispatch event to SDEI\n");
+ panic();
+ } else {
+ INFO("SDEI event dispatched\n");
+ }
+
+ return 0;
+}
+
+void plat_handle_uncontainable_ea(void)
+{
+ /* Do not change the string, CI expects it. Wait forever */
+ INFO("Injected Uncontainable Error\n");
+ while (true) {
+ wfe();
+ }
+}
+#endif
struct ras_interrupt fvp_ras_interrupts[] = {
};
struct err_record_info fvp_err_records[] = {
+#ifdef PLATFORM_TEST_RAS_FFH
+ /* Record for injected fault */
+ ERR_RECORD_SYSREG_V1(0, 2, ras_err_ser_probe_sysreg,
+ injected_fault_handler, NULL),
+#endif
};
REGISTER_ERR_RECORD_INFO(fvp_err_records);
diff --git a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
index 4543671..4f97339 100644
--- a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
+++ b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -15,7 +15,7 @@
/ {
compatible = "arm,ffa-core-manifest-1.0";
#address-cells = <2>;
- #size-cells = <1>;
+ #size-cells = <2>;
attribute {
spmc_id = <0x8000>;
@@ -78,9 +78,17 @@
CPU_1
};
- memory@6000000 {
+ memory@0 {
device_type = "memory";
- reg = <0x0 0x6000000 0x2000000>; /* Trusted DRAM */
+ reg = <0x0 0xfd000000 0x0 0x2000000>,
+ <0x0 0x7000000 0x0 0x1000000>,
+ <0x0 0xff000000 0x0 0x1000000>;
+ };
+
+ memory@1 {
+ device_type = "ns-memory";
+ reg = <0x00008800 0x80000000 0x0 0x7f000000>,
+ <0x0 0x88000000 0x0 0x10000000>;
};
#if MEASURED_BOOT
diff --git a/plat/arm/board/fvp/fvp_cpu_errata.mk b/plat/arm/board/fvp/fvp_cpu_errata.mk
new file mode 100644
index 0000000..944571d
--- /dev/null
+++ b/plat/arm/board/fvp/fvp_cpu_errata.mk
@@ -0,0 +1,61 @@
+#
+# Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+
+#/*
+# * TODO: below lines of code to be removed
+# * after abi and framework are synchronized
+# */
+
+ifeq (${ERRATA_ABI_SUPPORT}, 1)
+# enable the cpu macros for errata abi interface
+ifeq (${ARCH}, aarch64)
+ifeq (${HW_ASSISTED_COHERENCY}, 0)
+CORTEX_A35_H_INC := 1
+CORTEX_A53_H_INC := 1
+CORTEX_A57_H_INC := 1
+CORTEX_A72_H_INC := 1
+CORTEX_A73_H_INC := 1
+$(eval $(call add_define, CORTEX_A35_H_INC))
+$(eval $(call add_define, CORTEX_A53_H_INC))
+$(eval $(call add_define, CORTEX_A57_H_INC))
+$(eval $(call add_define, CORTEX_A72_H_INC))
+$(eval $(call add_define, CORTEX_A73_H_INC))
+else
+ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0)
+CORTEX_A76_H_INC := 1
+CORTEX_A77_H_INC := 1
+CORTEX_A78_H_INC := 1
+NEOVERSE_N1_H_INC := 1
+NEOVERSE_V1_H_INC := 1
+CORTEX_A78_AE_H_INC := 1
+CORTEX_A510_H_INC := 1
+CORTEX_A710_H_INC := 1
+CORTEX_A715_H_INC := 1
+CORTEX_A78C_H_INC := 1
+CORTEX_X2_H_INC := 1
+$(eval $(call add_define, CORTEX_A76_H_INC))
+$(eval $(call add_define, CORTEX_A77_H_INC))
+$(eval $(call add_define, CORTEX_A78_H_INC))
+$(eval $(call add_define, NEOVERSE_N1_H_INC))
+$(eval $(call add_define, NEOVERSE_V1_H_INC))
+$(eval $(call add_define, CORTEX_A78_AE_H_INC))
+$(eval $(call add_define, CORTEX_A510_H_INC))
+$(eval $(call add_define, CORTEX_A710_H_INC))
+$(eval $(call add_define, CORTEX_A715_H_INC))
+$(eval $(call add_define, CORTEX_A78C_H_INC))
+$(eval $(call add_define, CORTEX_X2_H_INC))
+endif
+CORTEX_A55_H_INC := 1
+CORTEX_A75_H_INC := 1
+$(eval $(call add_define, CORTEX_A55_H_INC))
+$(eval $(call add_define, CORTEX_A75_H_INC))
+endif
+else
+CORTEX_A32_H_INC := 1
+$(eval $(call add_define, CORTEX_A32_H_INC))
+endif
+endif
diff --git a/plat/arm/board/fvp/fvp_spmd.c b/plat/arm/board/fvp/fvp_spmd.c
new file mode 100644
index 0000000..8213e5e
--- /dev/null
+++ b/plat/arm/board/fvp/fvp_spmd.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+int plat_spmd_handle_group0_interrupt(uint32_t intid)
+{
+ /*
+ * As of now, there are no sources of Group0 secure interrupt enabled
+ * for FVP.
+ */
+ (void)intid;
+ return -1;
+}
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index 79d7451..9e72ba0 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -397,7 +397,17 @@
#define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT
#define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT
#else
-#define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS
+ #if PLATFORM_TEST_RAS_FFH
+ #define PLAT_ARM_PRIVATE_SDEI_EVENTS \
+ ARM_SDEI_PRIVATE_EVENTS, \
+ SDEI_EXPLICIT_EVENT(5000, SDEI_MAPF_NORMAL), \
+ SDEI_EXPLICIT_EVENT(5001, SDEI_MAPF_NORMAL), \
+ SDEI_EXPLICIT_EVENT(5002, SDEI_MAPF_NORMAL), \
+ SDEI_EXPLICIT_EVENT(5003, SDEI_MAPF_CRITICAL), \
+ SDEI_EXPLICIT_EVENT(5004, SDEI_MAPF_CRITICAL)
+ #else
+ #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS
+ #endif
#define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS
#endif
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index af082ba..0433b61 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -50,7 +50,9 @@
ENABLE_FEAT_RNG := 2
ENABLE_FEAT_TWED := 2
ENABLE_FEAT_GCS := 2
-ifeq (${ARCH},aarch64)
+ ENABLE_FEAT_RAS := 2
+ifeq (${ARCH}, aarch64)
+ifneq (${SPD}, spmd)
ifeq (${SPM_MM}, 0)
ifeq (${ENABLE_RME}, 0)
ifeq (${CTX_INCLUDE_FPREGS}, 0)
@@ -61,6 +63,7 @@
endif
endif
endif
+endif
# enable unconditionally for all builds
ifeq (${ARCH}, aarch64)
@@ -385,7 +388,7 @@
endif
endif
-ifeq (${RAS_EXTENSION},1)
+ifeq (${RAS_FFH_SUPPORT},1)
BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c
endif
@@ -503,6 +506,11 @@
PSCI_OS_INIT_MODE := 1
+ifeq (${SPD},spmd)
+BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c
+endif
+
+# Test specific macros, keep them at bottom of this file
$(eval $(call add_define,PLATFORM_TEST_EA_FFH))
ifeq (${PLATFORM_TEST_EA_FFH}, 1)
ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0)
@@ -510,3 +518,14 @@
endif
BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c
endif
+
+$(eval $(call add_define,PLATFORM_TEST_RAS_FFH))
+ifeq (${PLATFORM_TEST_RAS_FFH}, 1)
+ ifeq (${RAS_EXTENSION}, 0)
+ $(error "PLATFORM_TEST_RAS_FFH expects RAS_EXTENSION to be 1")
+ endif
+endif
+
+ifeq (${ERRATA_ABI_SUPPORT}, 1)
+include plat/arm/board/fvp/fvp_cpu_errata.mk
+endif
diff --git a/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c b/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c
index b961da9..705ec38 100644
--- a/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c
+++ b/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c
@@ -84,7 +84,7 @@
(void *)hw_config_info->config_addr);
/*
- * Preferrably we expect this address and size are page aligned,
+ * Preferably we expect this address and size are page aligned,
* but if they are not then align it.
*/
hw_config_base_align = page_align(hw_config_info->config_addr, DOWN);
diff --git a/plat/arm/board/morello/morello_bl31_setup.c b/plat/arm/board/morello/morello_bl31_setup.c
index cef42f4..8469cd1 100644
--- a/plat/arm/board/morello/morello_bl31_setup.c
+++ b/plat/arm/board/morello/morello_bl31_setup.c
@@ -12,6 +12,7 @@
#include <services/arm_arch_svc.h>
#include "morello_def.h"
+#include "morello_private.h"
#include <platform_def.h>
#ifdef TARGET_PLATFORM_SOC
@@ -33,6 +34,7 @@
const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
{
+ ops->pwr_domain_off = morello_pwr_domain_off;
return css_scmi_override_pm_ops(ops);
}
diff --git a/plat/arm/board/morello/morello_pm.c b/plat/arm/board/morello/morello_pm.c
new file mode 100644
index 0000000..fa7bd1d
--- /dev/null
+++ b/plat/arm/board/morello/morello_pm.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2023, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/psci/psci.h>
+#include <plat/arm/common/plat_arm.h>
+#include <plat/arm/css/common/css_pm.h>
+
+#include "morello_private.h"
+
+/*******************************************************************************
+ * Morello specific function called when turning off a power domain.
+ * Additionally disables the GIC redistributor interface as cores are disabled
+ * to let cluster-PPU state transition to completion when a cluster is
+ * powered down.
+ ******************************************************************************/
+void morello_pwr_domain_off(const psci_power_state_t *target_state)
+{
+ css_pwr_domain_off(target_state);
+ plat_arm_gic_redistif_off();
+}
diff --git a/plat/arm/board/morello/morello_private.h b/plat/arm/board/morello/morello_private.h
new file mode 100644
index 0000000..dea70fb
--- /dev/null
+++ b/plat/arm/board/morello/morello_private.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2023, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MORELLO_PRIVATE_H
+#define MORELLO_PRIVATE_H
+
+#include <lib/psci/psci.h>
+
+void morello_pwr_domain_off(const psci_power_state_t *target_state);
+
+#endif /* MORELLO_PRIVATE_H */
diff --git a/plat/arm/board/morello/platform.mk b/plat/arm/board/morello/platform.mk
index 0f0cabb..0ae7693 100644
--- a/plat/arm/board/morello/platform.mk
+++ b/plat/arm/board/morello/platform.mk
@@ -49,6 +49,7 @@
${INTERCONNECT_SOURCES} \
${MORELLO_GIC_SOURCES} \
${MORELLO_BASE}/morello_bl31_setup.c \
+ ${MORELLO_BASE}/morello_pm.c \
${MORELLO_BASE}/morello_topology.c \
${MORELLO_BASE}/morello_security.c \
drivers/arm/css/sds/sds.c
diff --git a/plat/arm/board/n1sdp/n1sdp_bl31_setup.c b/plat/arm/board/n1sdp/n1sdp_bl31_setup.c
index 4941a4b..2b9ed25 100644
--- a/plat/arm/board/n1sdp/n1sdp_bl31_setup.c
+++ b/plat/arm/board/n1sdp/n1sdp_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,6 +14,7 @@
#include <plat/arm/common/plat_arm.h>
#include "n1sdp_def.h"
+#include "n1sdp_private.h"
#include <platform_def.h>
/*
@@ -69,6 +70,7 @@
const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
{
+ ops->pwr_domain_off = n1sdp_pwr_domain_off;
return css_scmi_override_pm_ops(ops);
}
@@ -159,3 +161,14 @@
if ((plat_info.multichip_mode) && (plat_info.remote_ddr_size != 0))
remote_dmc_ecc_setup(plat_info.remote_ddr_size);
}
+
+#if defined(SPD_spmd) && (SPMC_AT_EL3 == 0)
+/*
+ * A dummy implementation of the platform handler for Group0 secure interrupt.
+ */
+int plat_spmd_handle_group0_interrupt(uint32_t intid)
+{
+ (void)intid;
+ return -1;
+}
+#endif /*defined(SPD_spmd) && (SPMC_AT_EL3 == 0)*/
diff --git a/plat/arm/board/n1sdp/n1sdp_pm.c b/plat/arm/board/n1sdp/n1sdp_pm.c
new file mode 100644
index 0000000..8d45354
--- /dev/null
+++ b/plat/arm/board/n1sdp/n1sdp_pm.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2023, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/psci/psci.h>
+#include <plat/arm/common/plat_arm.h>
+#include <plat/arm/css/common/css_pm.h>
+
+#include "n1sdp_private.h"
+
+/*******************************************************************************
+ * N1SDP specific function called when turning off a power domain. Additionally
+ * disables the GIC redistributor interface as cores are disabled to
+ * let cluster-PPU state transition to completion when a cluster is powered
+ * down.
+ ******************************************************************************/
+void n1sdp_pwr_domain_off(const psci_power_state_t *target_state)
+{
+ css_pwr_domain_off(target_state);
+ plat_arm_gic_redistif_off();
+}
diff --git a/plat/arm/board/n1sdp/n1sdp_private.h b/plat/arm/board/n1sdp/n1sdp_private.h
new file mode 100644
index 0000000..4e48c0f
--- /dev/null
+++ b/plat/arm/board/n1sdp/n1sdp_private.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2023, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef N1SDP_PRIVATE_H
+#define N1SDP_PRIVATE_H
+
+#include <lib/psci/psci.h>
+
+void n1sdp_pwr_domain_off(const psci_power_state_t *target_state);
+
+#endif /* N1SDP_PRIVATE_H */
diff --git a/plat/arm/board/n1sdp/platform.mk b/plat/arm/board/n1sdp/platform.mk
index 9c0cc02..bd62614 100644
--- a/plat/arm/board/n1sdp/platform.mk
+++ b/plat/arm/board/n1sdp/platform.mk
@@ -47,6 +47,7 @@
${INTERCONNECT_SOURCES} \
${N1SDP_GIC_SOURCES} \
${N1SDP_BASE}/n1sdp_bl31_setup.c \
+ ${N1SDP_BASE}/n1sdp_pm.c \
${N1SDP_BASE}/n1sdp_topology.c \
${N1SDP_BASE}/n1sdp_security.c \
drivers/arm/css/sds/sds.c
diff --git a/plat/arm/board/rde1edge/platform.mk b/plat/arm/board/rde1edge/platform.mk
index 0f9dd49..4a9a467 100644
--- a/plat/arm/board/rde1edge/platform.mk
+++ b/plat/arm/board/rde1edge/platform.mk
@@ -1,9 +1,12 @@
#
-# Copyright (c) 2018-2020, Arm Limited. All rights reserved.
+# Copyright (c) 2018-2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
+$(warning Platform ${PLAT} is deprecated. \
+ Some of the features might not work as expected)
+
include plat/arm/css/sgi/sgi-common.mk
RDE1EDGE_BASE = plat/arm/board/rde1edge
diff --git a/plat/arm/board/tc/fdts/tc_spmc_manifest.dts b/plat/arm/board/tc/fdts/tc_spmc_manifest.dts
index d3a5e1a..b64e076 100644
--- a/plat/arm/board/tc/fdts/tc_spmc_manifest.dts
+++ b/plat/arm/board/tc/fdts/tc_spmc_manifest.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,7 +8,7 @@
/ {
compatible = "arm,ffa-core-manifest-1.0";
#address-cells = <2>;
- #size-cells = <1>;
+ #size-cells = <2>;
attribute {
spmc_id = <0x8000>;
@@ -117,9 +117,16 @@
};
};
- /* 32MB of TC_TZC_DRAM1_BASE */
- memory@fd000000 {
+ memory@0 {
device_type = "memory";
- reg = <0x0 0xfd000000 0x2000000>;
+ reg = <0x0 0xfd000000 0x0 0x2000000>,
+ <0x0 0x7000000 0x0 0x1000000>,
+ <0x0 0xff000000 0x0 0x1000000>;
+ };
+
+ memory@1 {
+ device_type = "ns-memory";
+ reg = <0x00008800 0x80000000 0x0 0x7f000000>,
+ <0x0 0x88000000 0x1 0x00000000>;
};
};
diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h
index eea1be6..59fff6e 100644
--- a/plat/arm/board/tc/include/platform_def.h
+++ b/plat/arm/board/tc/include/platform_def.h
@@ -212,8 +212,11 @@
#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
#define PLAT_ARM_DRAM2_END (PLAT_ARM_DRAM2_BASE + PLAT_ARM_DRAM2_SIZE - 1ULL)
-#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp)
-#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
+#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_INT_PROPS(grp)
+#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp), \
+ INTR_PROP_DESC(SBSA_SECURE_WDOG_INTID, \
+ GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_LEVEL)
#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
PLAT_SP_IMAGE_NS_BUF_SIZE)
@@ -229,9 +232,11 @@
#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
-/*Secure Watchdog Constants */
-#define SBSA_SECURE_WDOG_BASE UL(0x2A480000)
+/* Secure Watchdog Constants */
+#define SBSA_SECURE_WDOG_CONTROL_BASE UL(0x2A480000)
+#define SBSA_SECURE_WDOG_REFRESH_BASE UL(0x2A490000)
#define SBSA_SECURE_WDOG_TIMEOUT UL(100)
+#define SBSA_SECURE_WDOG_INTID 86
#define PLAT_ARM_SCMI_CHANNEL_COUNT 1
diff --git a/plat/arm/board/tc/include/tc_plat.h b/plat/arm/board/tc/include/tc_plat.h
index ba1831f..117fbb4 100644
--- a/plat/arm/board/tc/include/tc_plat.h
+++ b/plat/arm/board/tc/include/tc_plat.h
@@ -9,9 +9,12 @@
void tc_bl31_common_platform_setup(void);
-#ifdef PLATFORM_TEST
-void run_platform_tests(void);
-void nv_counter_test(void);
+#ifdef PLATFORM_TEST_TFM_TESTSUITE
+int run_platform_tests(void);
+#endif
+
+#ifdef PLATFORM_TEST_NV_COUNTERS
+int nv_counter_test(void);
#endif
#endif /* TC_PLAT_H */
diff --git a/plat/arm/board/tc/nv_counter_test.c b/plat/arm/board/tc/nv_counter_test.c
index 76c9915..f9e001e 100644
--- a/plat/arm/board/tc/nv_counter_test.c
+++ b/plat/arm/board/tc/nv_counter_test.c
@@ -13,7 +13,7 @@
#include <platform_def.h>
-void nv_counter_test(void)
+int nv_counter_test(void)
{
psa_status_t status;
uint32_t old_val;
@@ -23,7 +23,7 @@
status = rss_comms_init(PLAT_RSS_AP_SND_MHU_BASE, PLAT_RSS_AP_RCV_MHU_BASE);
if (status != PSA_SUCCESS) {
printf("Failed to initialize RSS communication channel\n");
- plat_error_handler(-1);
+ return -1;
}
for (id = 0; id < 3; id++) {
@@ -31,28 +31,30 @@
if (status != PSA_SUCCESS) {
printf("Failed during first id=(%d) rss_platform_nv_counter_read\n",
id);
- plat_error_handler(-1);
+ return -1;
}
status = rss_platform_nv_counter_increment(id);
if (status != PSA_SUCCESS) {
printf("Failed during id=(%d) rss_platform_nv_counter_increment\n",
id);
- plat_error_handler(-1);
+ return -1;
}
status = rss_platform_nv_counter_read(id, sizeof(new_val), (uint8_t *)&new_val);
if (status != PSA_SUCCESS) {
printf("Failed during second id=(%d) rss_platform_nv_counter_read\n",
id);
- plat_error_handler(-1);
+ return -1;
}
if (old_val + 1 != new_val) {
printf("Failed nv_counter_test: old_val (%d) + 1 != new_val (%d)\n",
old_val, new_val);
- plat_error_handler(-1);
+ return -1;
}
}
printf("Passed nv_counter_test\n");
+
+ return 0;
}
diff --git a/plat/arm/board/tc/plat_fiptool.mk b/plat/arm/board/tc/plat_fiptool.mk
deleted file mode 100644
index 0e13556..0000000
--- a/plat/arm/board/tc/plat_fiptool.mk
+++ /dev/null
@@ -1,33 +0,0 @@
-#
-# Copyright (c) 2021, NXP. All rights reserved.
-# Copyright (c) 2022, Arm Limited. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-# Name of the platform defined source file name,
-# which contains platform defined UUID entries populated
-# in the plat_def_toc_entries[].
-PLAT_DEF_UUID_CONFIG_FILE_NAME := plat_def_uuid_config
-
-PLAT_DEF_UUID_CONFIG_FILE_PATH := ../../plat/arm/board/tc
-
-PLAT_DEF_UUID := yes
-PLAT_DEF_UUID_OID_CONFIG_PATH := ../../plat/arm/board/tc
-
-
-INCLUDE_PATHS += -I${PLAT_DEF_UUID_OID_CONFIG_PATH} \
- -I./
-# Clean the stale object file.
-$(shell rm ${PLAT_DEF_UUID_CONFIG_FILE_PATH}/${PLAT_DEF_UUID_CONFIG_FILE_NAME}.o)
-
-ifeq (${PLAT_DEF_OID},yes)
-HOSTCCFLAGS += -DPLAT_DEF_OID
-endif
-
-ifeq (${PLAT_DEF_UUID},yes)
-HOSTCCFLAGS += -DPLAT_DEF_FIP_UUID
-PLAT_OBJECTS += ${PLAT_DEF_UUID_CONFIG_FILE_PATH}/${PLAT_DEF_UUID_CONFIG_FILE_NAME}.o
-endif
-
-OBJECTS += ${PLAT_OBJECTS}
diff --git a/plat/arm/board/tc/plat_tc_mbedtls_config.h b/plat/arm/board/tc/plat_tc_mbedtls_config.h
index d776b63..f0aa60b 100644
--- a/plat/arm/board/tc/plat_tc_mbedtls_config.h
+++ b/plat/arm/board/tc/plat_tc_mbedtls_config.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, Arm Ltd. All rights reserved.
+ * Copyright (c) 2022-2023, Arm Ltd. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,8 +7,8 @@
#ifndef PLAT_TC_MBEDTLS_CONFIG_H
#define PLAT_TC_MBEDTLS_CONFIG_H
-#include <mbedtls_config.h>
#include <export/lib/utils_def_exp.h>
+#include <mbedtls_config-3.h>
#ifndef TF_MBEDTLS_HEAP_SIZE
#error TF_MBEDTLS_HEAP_SIZE is not defined
diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk
index 7fdc4fd..c29537c 100644
--- a/plat/arm/board/tc/platform.mk
+++ b/plat/arm/board/tc/platform.mk
@@ -20,7 +20,9 @@
CSS_USE_SCMI_SDS_DRIVER := 1
-RAS_EXTENSION := 0
+ENABLE_FEAT_RAS := 1
+
+RAS_FFH_SUPPORT := 0
SDEI_SUPPORT := 0
@@ -53,9 +55,6 @@
# enable trace filter control registers access to NS by default
ENABLE_TRF_FOR_NS := 1
-# Enable RSS-required FIP UUIDs
-$(shell cp plat/arm/board/tc/plat_fiptool.mk ${PLAT_DIR})
-
# Include GICv3 driver files
include drivers/arm/gic/v3/gicv3.mk
@@ -121,7 +120,8 @@
lib/fconf/fconf_dyn_cfg_getter.c \
drivers/cfi/v2m/v2m_flash.c \
lib/utils/mem_region.c \
- plat/arm/common/arm_nor_psci_mem_protect.c
+ plat/arm/common/arm_nor_psci_mem_protect.c \
+ drivers/arm/sbsa/sbsa.c
BL31_SOURCES += ${FDT_WRAPPERS_SOURCES}
@@ -196,28 +196,32 @@
endif
-ifeq (${PLATFORM_TEST},rss-nv-counters)
- include drivers/arm/rss/rss_comms.mk
+ifneq (${PLATFORM_TEST},)
+ $(eval $(call add_define,PLATFORM_TESTS))
- # Test code.
- BL31_SOURCES += plat/arm/board/tc/nv_counter_test.c
+ ifeq (${PLATFORM_TEST},rss-nv-counters)
+ include drivers/arm/rss/rss_comms.mk
- # Code under testing.
- BL31_SOURCES += lib/psa/rss_platform.c \
+ # Test code.
+ BL31_SOURCES += plat/arm/board/tc/nv_counter_test.c
+
+ # Code under testing.
+ BL31_SOURCES += lib/psa/rss_platform.c \
drivers/arm/rss/rss_comms.c \
${RSS_COMMS_SOURCES}
- PLAT_INCLUDES += -Iinclude/lib/psa
+ PLAT_INCLUDES += -Iinclude/lib/psa
- $(eval $(call add_define,PLATFORM_TEST))
-else ifeq (${PLATFORM_TEST},tfm-testsuite)
- # Add this include as first, before arm_common.mk. This is necessary
- # because arm_common.mk builds Mbed TLS, and platform_test.mk can
- # change the list of Mbed TLS files that are to be compiled
- # (LIBMBEDTLS_SRCS).
- include plat/arm/board/tc/platform_test.mk
-else ifneq (${PLATFORM_TEST},)
- $(error "Unsupported PLATFORM_TEST value")
+ $(eval $(call add_define,PLATFORM_TEST_NV_COUNTERS))
+ else ifeq (${PLATFORM_TEST},tfm-testsuite)
+ # Add this include as first, before arm_common.mk. This is necessary
+ # because arm_common.mk builds Mbed TLS, and platform_test.mk can
+ # change the list of Mbed TLS files that are to be compiled
+ # (LIBMBEDTLS_SRCS).
+ include plat/arm/board/tc/platform_test.mk
+ else
+ $(error "Unsupported PLATFORM_TEST value")
+ endif
endif
diff --git a/plat/arm/board/tc/platform_test.mk b/plat/arm/board/tc/platform_test.mk
index 5cdbb86..e974855 100644
--- a/plat/arm/board/tc/platform_test.mk
+++ b/plat/arm/board/tc/platform_test.mk
@@ -76,5 +76,5 @@
$(eval $(call add_define,MEASURED_BOOT_HASH_ALG))
$(eval $(call add_define,DELEG_ATTEST_DUMP_TOKEN_AND_KEY))
- $(eval $(call add_define,PLATFORM_TEST))
+ $(eval $(call add_define,PLATFORM_TEST_TFM_TESTSUITE))
endif
diff --git a/plat/arm/board/tc/rss_ap_tests.c b/plat/arm/board/tc/rss_ap_tests.c
index b62043e..8c40271 100644
--- a/plat/arm/board/tc/rss_ap_tests.c
+++ b/plat/arm/board/tc/rss_ap_tests.c
@@ -19,21 +19,28 @@
{.freg = register_testsuite_measured_boot},
};
-static void run_tests(void)
+/*
+ * Return 0 if we could run all tests.
+ * Note that this does not mean that all tests passed - only that they all run.
+ * One should then look at each individual test result inside the
+ * test_suites[].val field.
+ */
+static int run_tests(void)
{
enum test_suite_err_t ret;
psa_status_t status;
size_t i;
+ /* Initialize test environment. */
rss_comms_init(PLAT_RSS_AP_SND_MHU_BASE, PLAT_RSS_AP_RCV_MHU_BASE);
mbedtls_init();
status = psa_crypto_init();
if (status != PSA_SUCCESS) {
printf("\n\npsa_crypto_init failed (status = %d)\n", status);
- assert(false);
- plat_error_handler(-1);
+ return -1;
}
+ /* Run all tests. */
for (i = 0; i < ARRAY_SIZE(test_suites); ++i) {
struct test_suite_t *suite = &(test_suites[i]);
@@ -41,22 +48,33 @@
ret = run_testsuite(suite);
if (ret != TEST_SUITE_ERR_NO_ERROR) {
printf("\n\nError during executing testsuite '%s'.\n", suite->name);
- assert(false);
- plat_error_handler(-1);
+ return -1;
}
}
printf("\nAll tests are run.\n");
+
+ return 0;
}
void run_platform_tests(void)
{
size_t i;
+ int ret;
+ int failures = 0;
- run_tests();
+ ret = run_tests();
+ if (ret != 0) {
+ /* For some reason, we could not run all tests. */
+ return ret;
+ }
printf("\n\n");
- /* Print a summary of all the tests that had been run. */
+ /*
+ * Print a summary of all the tests that had been run.
+ * Also count the number of tests failure and report that back to the
+ * caller.
+ */
printf("SUMMARY:\n");
for (i = 0; i < ARRAY_SIZE(test_suites); ++i) {
@@ -67,6 +85,7 @@
printf(" %s PASSED.\n", suite->name);
break;
case TEST_FAILED:
+ failures++;
printf(" %s FAILED.\n", suite->name);
break;
case TEST_SKIPPED:
@@ -79,4 +98,6 @@
}
printf("\n\n");
+
+ return failures;
}
diff --git a/plat/arm/board/tc/tc_bl31_setup.c b/plat/arm/board/tc/tc_bl31_setup.c
index 1c1e2fb..ca3a032 100644
--- a/plat/arm/board/tc/tc_bl31_setup.c
+++ b/plat/arm/board/tc/tc_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,6 +13,7 @@
#include <common/debug.h>
#include <drivers/arm/css/css_mhu_doorbell.h>
#include <drivers/arm/css/scmi.h>
+#include <drivers/arm/sbsa.h>
#include <lib/fconf/fconf.h>
#include <lib/fconf/fconf_dyn_cfg_getter.h>
#include <plat/arm/common/plat_arm.h>
@@ -49,18 +50,34 @@
fconf_populate("FW_CONFIG", arg1);
}
-void tc_bl31_common_platform_setup(void)
+#ifdef PLATFORM_TESTS
+static __dead2 void tc_run_platform_tests(void)
{
- arm_bl31_platform_setup();
+ int tests_failed;
-#ifdef PLATFORM_TEST
-#if PLATFORM_TEST == rss-nv-counters
- nv_counter_test();
-#elif PLATFORM_TEST == tfm-testsuite
- run_platform_tests()
+ printf("\nStarting platform tests...\n");
+
+#ifdef PLATFORM_TEST_NV_COUNTERS
+ tests_failed = nv_counter_test();
+#elif PLATFORM_TEST_TFM_TESTSUITE
+ tests_failed = run_platform_tests();
#endif
- /* Suspend booting */
+
+ printf("Platform tests %s.\n",
+ (tests_failed != 0) ? "failed" : "succeeded");
+
+ /* Suspend booting, no matter the tests outcome. */
+ printf("Suspend booting...\n");
plat_error_handler(-1);
+}
+#endif
+
+void tc_bl31_common_platform_setup(void)
+{
+ arm_bl31_platform_setup();
+
+#ifdef PLATFORM_TESTS
+ tc_run_platform_tests();
#endif
}
@@ -81,3 +98,37 @@
fconf_populate("HW_CONFIG", hw_config_info->config_addr);
}
+
+#if defined(SPD_spmd) && (SPMC_AT_EL3 == 0)
+void tc_bl31_plat_runtime_setup(void)
+{
+ arm_bl31_plat_runtime_setup();
+
+ /* Start secure watchdog timer. */
+ plat_arm_secure_wdt_start();
+}
+
+void bl31_plat_runtime_setup(void)
+{
+ tc_bl31_plat_runtime_setup();
+}
+
+/*
+ * Platform handler for Group0 secure interrupt.
+ */
+int plat_spmd_handle_group0_interrupt(uint32_t intid)
+{
+ /* Trusted Watchdog timer is the only source of Group0 interrupt now. */
+ if (intid == SBSA_SECURE_WDOG_INTID) {
+ INFO("Watchdog restarted\n");
+ /* Refresh the timer. */
+ plat_arm_secure_wdt_refresh();
+
+ /* Deactivate the corresponding interrupt. */
+ plat_ic_end_of_interrupt(intid);
+ return 0;
+ }
+
+ return -1;
+}
+#endif /*defined(SPD_spmd) && (SPMC_AT_EL3 == 0)*/
diff --git a/plat/arm/board/tc/tc_plat.c b/plat/arm/board/tc/tc_plat.c
index 228f2fa..766bfb5 100644
--- a/plat/arm/board/tc/tc_plat.c
+++ b/plat/arm/board/tc/tc_plat.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -147,10 +147,15 @@
void plat_arm_secure_wdt_start(void)
{
- sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT);
+ sbsa_wdog_start(SBSA_SECURE_WDOG_CONTROL_BASE, SBSA_SECURE_WDOG_TIMEOUT);
}
void plat_arm_secure_wdt_stop(void)
{
- sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE);
+ sbsa_wdog_stop(SBSA_SECURE_WDOG_CONTROL_BASE);
+}
+
+void plat_arm_secure_wdt_refresh(void)
+{
+ sbsa_wdog_refresh(SBSA_SECURE_WDOG_REFRESH_BASE);
}
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index 19efdd3..cfd1aac 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -43,6 +43,7 @@
#pragma weak bl31_platform_setup
#pragma weak bl31_plat_arch_setup
#pragma weak bl31_plat_get_next_image_ep_info
+#pragma weak bl31_plat_runtime_setup
#define MAP_BL31_TOTAL MAP_REGION_FLAT( \
BL31_START, \
@@ -294,7 +295,7 @@
/* Initialize power controller before setting up topology */
plat_arm_pwrc_setup();
-#if RAS_EXTENSION
+#if RAS_FFH_SUPPORT
ras_init();
#endif
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index fca6f4f..647a9d9 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -386,7 +386,7 @@
endif
# RAS sources
-ifeq (${RAS_EXTENSION},1)
+ifeq (${RAS_FFH_SUPPORT},1)
BL31_SOURCES += lib/extensions/ras/std_err_record.c \
lib/extensions/ras/ras_common.c
endif
diff --git a/plat/arm/common/tsp/arm_tsp_setup.c b/plat/arm/common/tsp/arm_tsp_setup.c
index a4da8c3..df3488b 100644
--- a/plat/arm/common/tsp/arm_tsp_setup.c
+++ b/plat/arm/common/tsp/arm_tsp_setup.c
@@ -62,7 +62,7 @@
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the MMU
+ * moment this is only initializes the MMU
******************************************************************************/
void tsp_plat_arch_setup(void)
{
diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h
index c1fadc6..c6cf0e6 100644
--- a/plat/arm/css/sgi/include/sgi_base_platform_def.h
+++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h
@@ -206,7 +206,7 @@
#define PLAT_SP_PRI PLAT_RAS_PRI
-#if SPM_MM && RAS_EXTENSION
+#if SPM_MM && RAS_FFH_SUPPORT
/*
* CPER buffer memory of 128KB is reserved and it is placed adjacent to the
* memory shared between EL3 and S-EL0.
@@ -235,7 +235,7 @@
*/
#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
PLAT_SP_IMAGE_NS_BUF_SIZE)
-#endif /* SPM_MM && RAS_EXTENSION */
+#endif /* SPM_MM && RAS_FFH_SUPPORT */
/* Platform ID address */
#define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET)
diff --git a/plat/arm/css/sgi/sgi-common.mk b/plat/arm/css/sgi/sgi-common.mk
index 282a5f0..6d17bc2 100644
--- a/plat/arm/css/sgi/sgi-common.mk
+++ b/plat/arm/css/sgi/sgi-common.mk
@@ -8,7 +8,9 @@
CSS_ENT_BASE := plat/arm/css/sgi
-RAS_EXTENSION := 0
+ENABLE_FEAT_RAS := 1
+
+RAS_FFH_SUPPORT := 0
SDEI_SUPPORT := 0
@@ -52,7 +54,7 @@
${CSS_ENT_BASE}/sgi_bl31_setup.c \
${CSS_ENT_BASE}/sgi_topology.c
-ifeq (${RAS_EXTENSION},1)
+ifeq (${RAS_FFH_SUPPORT},1)
BL31_SOURCES += ${CSS_ENT_BASE}/sgi_ras.c
endif
diff --git a/plat/arm/css/sgi/sgi_bl31_setup.c b/plat/arm/css/sgi/sgi_bl31_setup.c
index df2ce38..9c8d163 100644
--- a/plat/arm/css/sgi/sgi_bl31_setup.c
+++ b/plat/arm/css/sgi/sgi_bl31_setup.c
@@ -106,7 +106,7 @@
{
arm_bl31_platform_setup();
-#if RAS_EXTENSION
+#if RAS_FFH_SUPPORT
sgi_ras_intr_handler_setup();
#endif
diff --git a/plat/arm/css/sgi/sgi_plat.c b/plat/arm/css/sgi/sgi_plat.c
index b8ba49f..7f79d54 100644
--- a/plat/arm/css/sgi/sgi_plat.c
+++ b/plat/arm/css/sgi/sgi_plat.c
@@ -93,7 +93,7 @@
PLAT_ARM_SECURE_MAP_DEVICE,
ARM_SP_IMAGE_MMAP,
ARM_SP_IMAGE_NS_BUF_MMAP,
-#if RAS_EXTENSION
+#if RAS_FFH_SUPPORT
CSS_SGI_SP_CPER_BUF_MMAP,
#endif
ARM_SP_IMAGE_RW_MMAP,
diff --git a/plat/brcm/board/stingray/driver/swreg.c b/plat/brcm/board/stingray/driver/swreg.c
index 2b7c53b..a5b5b9f 100644
--- a/plat/brcm/board/stingray/driver/swreg.c
+++ b/plat/brcm/board/stingray/driver/swreg.c
@@ -296,7 +296,7 @@
return ret;
}
-/* Update SWREG firmware for all power doman for A2 chip */
+/* Update SWREG firmware for all power domain for A2 chip */
int swreg_firmware_update(void)
{
enum sw_reg reg_id;
diff --git a/plat/common/aarch64/plat_common.c b/plat/common/aarch64/plat_common.c
index 042916a..eca81b1 100644
--- a/plat/common/aarch64/plat_common.c
+++ b/plat/common/aarch64/plat_common.c
@@ -11,7 +11,7 @@
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/console.h>
-#if RAS_EXTENSION
+#if RAS_FFH_SUPPORT
#include <lib/extensions/ras.h>
#endif
#include <lib/xlat_tables/xlat_mmu_helpers.h>
@@ -81,7 +81,7 @@
void plat_default_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie,
void *handle, uint64_t flags)
{
-#if RAS_EXTENSION
+#if RAS_FFH_SUPPORT
/* Call RAS EA handler */
int handled = ras_ea_handler(ea_reason, syndrome, cookie, handle, flags);
if (handled != 0)
diff --git a/plat/common/aarch64/plat_ehf.c b/plat/common/aarch64/plat_ehf.c
index da76884..4ec69b1 100644
--- a/plat/common/aarch64/plat_ehf.c
+++ b/plat/common/aarch64/plat_ehf.c
@@ -12,7 +12,7 @@
* Enumeration of priority levels on ARM platforms.
*/
ehf_pri_desc_t plat_exceptions[] = {
-#if RAS_EXTENSION
+#if RAS_FFH_SUPPORT
/* RAS Priority */
EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_RAS_PRI),
#endif
@@ -27,7 +27,7 @@
#if SPM_MM
EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SP_PRI),
#endif
- /* Plaform specific exceptions description */
+ /* Platform specific exceptions description */
#ifdef PLAT_EHF_DESC
PLAT_EHF_DESC,
#endif
diff --git a/plat/hisilicon/hikey960/hikey960_bl31_setup.c b/plat/hisilicon/hikey960/hikey960_bl31_setup.c
index 50751ee..159eee9 100644
--- a/plat/hisilicon/hikey960/hikey960_bl31_setup.c
+++ b/plat/hisilicon/hikey960/hikey960_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -245,6 +245,15 @@
return 0;
}
+#elif defined(SPD_spmd) && (SPMC_AT_EL3 == 0)
+/*
+ * A dummy implementation of the platform handler for Group0 secure interrupt.
+ */
+int plat_spmd_handle_group0_interrupt(uint32_t intid)
+{
+ (void)intid;
+ return -1;
+}
#endif
void bl31_plat_runtime_setup(void)
diff --git a/plat/imx/common/include/sci/sci_rpc.h b/plat/imx/common/include/sci/sci_rpc.h
index 60dbc27..b6adf33 100644
--- a/plat/imx/common/include/sci/sci_rpc.h
+++ b/plat/imx/common/include/sci/sci_rpc.h
@@ -100,7 +100,7 @@
void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, bool no_resp);
/*!
- * This is an internal function to dispath an RPC call that has
+ * This is an internal function to dispatch an RPC call that has
* arrived via IPC over an MU. It is called by server-side SCFW.
*
* @param[in] mu MU message arrived on
diff --git a/plat/imx/common/include/sci/svc/pad/sci_pad_api.h b/plat/imx/common/include/sci/svc/pad/sci_pad_api.h
index dc23eed..ac93aae 100644
--- a/plat/imx/common/include/sci/svc/pad/sci_pad_api.h
+++ b/plat/imx/common/include/sci/svc/pad/sci_pad_api.h
@@ -42,7 +42,7 @@
*
* Pads are managed as a resource by the Resource Manager (RM). They have
* assigned owners and only the owners can configure the pads. Some of the
- * pads are reserved for use by the SCFW itself and this can be overriden
+ * pads are reserved for use by the SCFW itself and this can be overridden
* with the implementation of board_config_sc(). Additionally, pads may
* be assigned to various other partitions via the implementation of
* board_system_config().
@@ -156,7 +156,7 @@
* This type is used to declare a pad low-power isolation config.
* ISO_LATE is the most common setting. ISO_EARLY is only used when
* an output pad is directly determined by another input pad. The
- * other two are only used when SW wants to directly contol isolation.
+ * other two are only used when SW wants to directly control isolation.
*/
typedef uint8_t sc_pad_iso_t;
diff --git a/plat/imx/common/include/sci/svc/pm/sci_pm_api.h b/plat/imx/common/include/sci/svc/pm/sci_pm_api.h
index 76ca5c4..1364795 100644
--- a/plat/imx/common/include/sci/svc/pm/sci_pm_api.h
+++ b/plat/imx/common/include/sci/svc/pm/sci_pm_api.h
@@ -294,7 +294,7 @@
* Note some resources are still not accessible even when powered up if bus
* transactions go through a fabric not powered up. Examples of this are
* resources in display and capture subsystems which require the display
- * controller or the imaging subsytem to be powered up first.
+ * controller or the imaging subsystem to be powered up first.
*
* Not that resources are grouped into power domains by the underlying
* hardware. If any resource in the domain is on, the entire power domain
diff --git a/plat/imx/imx8m/gpc_common.c b/plat/imx/imx8m/gpc_common.c
index 32a35ef..71e0af1 100644
--- a/plat/imx/imx8m/gpc_common.c
+++ b/plat/imx/imx8m/gpc_common.c
@@ -98,7 +98,7 @@
/* assert the pcg pcr bit of the core */
mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1);
} else {
- /* disbale CORE WFI PDN & IRQ PUP */
+ /* disable CORE WFI PDN & IRQ PUP */
mmio_clrbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) |
COREx_IRQ_WUP(core_id));
/* deassert the pcg pcr bit of the core */
diff --git a/plat/imx/imx8m/imx8mm/gpc.c b/plat/imx/imx8m/imx8mm/gpc.c
index cc1cb10..e0e38a9 100644
--- a/plat/imx/imx8m/imx8mm/gpc.c
+++ b/plat/imx/imx8m/imx8mm/gpc.c
@@ -376,7 +376,7 @@
/*
* Set the CORE & SCU power up timing:
* SW = 0x1, SW2ISO = 0x1;
- * the CPU CORE and SCU power up timming counter
+ * the CPU CORE and SCU power up timing counter
* is drived by 32K OSC, each domain's power up
* latency is (SW + SW2ISO) / 32768
*/
diff --git a/plat/imx/imx8m/imx8mn/gpc.c b/plat/imx/imx8m/imx8mn/gpc.c
index 4e05297..20c9a55 100644
--- a/plat/imx/imx8m/imx8mn/gpc.c
+++ b/plat/imx/imx8m/imx8mn/gpc.c
@@ -170,7 +170,7 @@
/*
* Set the CORE & SCU power up timing:
* SW = 0x1, SW2ISO = 0x1;
- * the CPU CORE and SCU power up timming counter
+ * the CPU CORE and SCU power up timing counter
* is drived by 32K OSC, each domain's power up
* latency is (SW + SW2ISO) / 32768
*/
diff --git a/plat/imx/imx8m/imx8mp/gpc.c b/plat/imx/imx8m/imx8mp/gpc.c
index 452e788..956b508 100644
--- a/plat/imx/imx8m/imx8mp/gpc.c
+++ b/plat/imx/imx8m/imx8mp/gpc.c
@@ -337,7 +337,7 @@
/*
* Set the CORE & SCU power up timing:
* SW = 0x1, SW2ISO = 0x1;
- * the CPU CORE and SCU power up timming counter
+ * the CPU CORE and SCU power up timing counter
* is drived by 32K OSC, each domain's power up
* latency is (SW + SW2ISO) / 32768
*/
diff --git a/plat/imx/imx8m/imx8mq/gpc.c b/plat/imx/imx8m/imx8mq/gpc.c
index 0a029d6..ebf92f7 100644
--- a/plat/imx/imx8m/imx8mq/gpc.c
+++ b/plat/imx/imx8m/imx8mq/gpc.c
@@ -417,7 +417,7 @@
/* set all mix/PU in A53 domain */
mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0xfffd);
- /* set SCU timming */
+ /* set SCU timing */
mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING,
(0x59 << 10) | 0x5B | (0x2 << 20));
diff --git a/plat/intel/soc/agilex/bl31_plat_setup.c b/plat/intel/soc/agilex/bl31_plat_setup.c
index 26ed7ef..b4e19de 100644
--- a/plat/intel/soc/agilex/bl31_plat_setup.c
+++ b/plat/intel/soc/agilex/bl31_plat_setup.c
@@ -155,7 +155,7 @@
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the mmu in a quick and dirty way.
+ * moment this is only initializes the mmu in a quick and dirty way.
******************************************************************************/
void bl31_plat_arch_setup(void)
{
diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h
index 3abf39d..564b4ee 100644
--- a/plat/intel/soc/common/include/socfpga_mailbox.h
+++ b/plat/intel/soc/common/include/socfpga_mailbox.h
@@ -63,6 +63,9 @@
#define MBOX_CMD_QSPI_SET_CS 0x34
#define MBOX_CMD_QSPI_DIRECT 0x3B
+/* SEU Commands */
+#define MBOX_CMD_SEU_ERR_READ 0x3C
+
/* RSU Commands */
#define MBOX_GET_SUBPARTITION_TABLE 0x5A
#define MBOX_RSU_STATUS 0x5B
@@ -241,5 +244,6 @@
int mailbox_hps_stage_notify(uint32_t execution_stage);
int mailbox_hwmon_readtemp(uint32_t chan, uint32_t *resp_buf);
int mailbox_hwmon_readvolt(uint32_t chan, uint32_t *resp_buf);
+int mailbox_seu_err_status(uint32_t *resp_buf, uint32_t resp_buf_len);
#endif /* SOCFPGA_MBOX_H */
diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h
index 21169f7..6708edb 100644
--- a/plat/intel/soc/common/include/socfpga_sip_svc.h
+++ b/plat/intel/soc/common/include/socfpga_sip_svc.h
@@ -15,6 +15,7 @@
#define INTEL_SIP_SMC_STATUS_NO_RESPONSE 0x3
#define INTEL_SIP_SMC_STATUS_ERROR 0x4
#define INTEL_SIP_SMC_RSU_ERROR 0x7
+#define INTEL_SIP_SMC_SEU_ERR_READ_ERROR 0x8
/* SiP mailbox error code */
#define GENERIC_RESPONSE_ERROR 0x3FF
@@ -138,6 +139,9 @@
#define INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT 0xC200008C
#define INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE 0xC200008E
+/* SEU ERR */
+#define INTEL_SIP_SMC_SEU_ERR_STATUS 0xC2000099
+
#define INTEL_SIP_SMC_FCS_SHA_MODE_MASK 0xF
#define INTEL_SIP_SMC_FCS_DIGEST_SIZE_MASK 0xF
#define INTEL_SIP_SMC_FCS_DIGEST_SIZE_OFFSET 4U
diff --git a/plat/intel/soc/common/sip/socfpga_sip_fcs.c b/plat/intel/soc/common/sip/socfpga_sip_fcs.c
index 508043f..d99026b 100644
--- a/plat/intel/soc/common/sip/socfpga_sip_fcs.c
+++ b/plat/intel/soc/common/sip/socfpga_sip_fcs.c
@@ -1804,7 +1804,7 @@
/*
* Source data must be 4 bytes aligned
- * Source addrress must be 8 bytes aligned
+ * Source address must be 8 bytes aligned
* User data must be 8 bytes aligned
*/
if ((dst_size == NULL) || (mbox_error == NULL) ||
diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c
index 7010d81..1f09715 100644
--- a/plat/intel/soc/common/soc/socfpga_mailbox.c
+++ b/plat/intel/soc/common/soc/socfpga_mailbox.c
@@ -669,3 +669,10 @@
CMD_CASUAL, resp_buf,
&resp_len);
}
+
+int mailbox_seu_err_status(uint32_t *resp_buf, uint32_t resp_buf_len)
+{
+ return mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_SEU_ERR_READ, NULL, 0U,
+ CMD_CASUAL, resp_buf,
+ &resp_buf_len);;
+}
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index 79f743f..4366214 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -648,6 +648,16 @@
return INTEL_SIP_SMC_STATUS_OK;
}
+/* SDM SEU Error services */
+static uint32_t intel_sdm_seu_err_read(uint64_t *respbuf, unsigned int respbuf_sz)
+{
+ if (mailbox_seu_err_status((uint32_t *)respbuf, respbuf_sz) < 0) {
+ return INTEL_SIP_SMC_SEU_ERR_READ_ERROR;
+ }
+
+ return INTEL_SIP_SMC_STATUS_OK;
+}
+
/*
* This function is responsible for handling all SiP calls from the NS world
*/
@@ -664,7 +674,7 @@
uint32_t retval = 0, completed_addr[3];
uint32_t retval2 = 0;
uint32_t mbox_error = 0;
- uint64_t retval64, rsu_respbuf[9];
+ uint64_t retval64, rsu_respbuf[9], seu_respbuf[3];
int status = INTEL_SIP_SMC_STATUS_OK;
int mbox_status;
unsigned int len_in_resp;
@@ -1170,6 +1180,15 @@
SIP_SVC_VERSION_MAJOR,
SIP_SVC_VERSION_MINOR);
+ case INTEL_SIP_SMC_SEU_ERR_STATUS:
+ status = intel_sdm_seu_err_read(seu_respbuf,
+ ARRAY_SIZE(seu_respbuf));
+ if (status) {
+ SMC_RET1(handle, status);
+ } else {
+ SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]);
+ }
+
default:
return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
cookie, handle, flags);
diff --git a/plat/intel/soc/n5x/bl31_plat_setup.c b/plat/intel/soc/n5x/bl31_plat_setup.c
index 5ca1a71..a5337ce 100644
--- a/plat/intel/soc/n5x/bl31_plat_setup.c
+++ b/plat/intel/soc/n5x/bl31_plat_setup.c
@@ -140,7 +140,7 @@
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the mmu in a quick and dirty way.
+ * moment this is only initializes the mmu in a quick and dirty way.
******************************************************************************/
void bl31_plat_arch_setup(void)
{
diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c
index be0fae5..ba00e82 100644
--- a/plat/intel/soc/stratix10/bl31_plat_setup.c
+++ b/plat/intel/soc/stratix10/bl31_plat_setup.c
@@ -147,7 +147,7 @@
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the mmu in a quick and dirty way.
+ * moment this is only initializes the mmu in a quick and dirty way.
******************************************************************************/
void bl31_plat_arch_setup(void)
{
diff --git a/plat/marvell/armada/a8k/common/plat_pm.c b/plat/marvell/armada/a8k/common/plat_pm.c
index 9ea9276..f08f08a 100644
--- a/plat/marvell/armada/a8k/common/plat_pm.c
+++ b/plat/marvell/armada/a8k/common/plat_pm.c
@@ -423,7 +423,7 @@
} else
#endif
{
- /* proprietary CPU ON exection flow */
+ /* proprietary CPU ON execution flow */
plat_marvell_cpu_on(mpidr);
}
return 0;
diff --git a/plat/marvell/armada/common/marvell_ddr_info.c b/plat/marvell/armada/common/marvell_ddr_info.c
index 7340996..1ae0254 100644
--- a/plat/marvell/armada/common/marvell_ddr_info.c
+++ b/plat/marvell/armada/common/marvell_ddr_info.c
@@ -34,7 +34,7 @@
DRAM_AREA_LENGTH_MASK) >> DRAM_AREA_LENGTH_OFFS
/* Mapping between DDR area length and real DDR size is specific and looks like
- * bellow:
+ * below:
* 0 => 384 MB
* 1 => 768 MB
* 2 => 1536 MB
diff --git a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_bus26m.c b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_bus26m.c
index 0b792ab..c8a2d4c 100644
--- a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_bus26m.c
+++ b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_bus26m.c
@@ -53,6 +53,7 @@
static struct mt_irqremain *refer2remain_irq;
static struct mt_spm_cond_tables cond_bus26m = {
+ .name = "bus26m",
.table_cg = {
0xFF5DD002, /* MTCMOS1 */
0x0000003C, /* MTCMOS2 */
@@ -175,7 +176,7 @@
(IS_PLAT_SUSPEND_ID(state_id) || (state_id == MT_PLAT_PWR_STATE_SYSTEM_BUS)));
}
-static int update_rc_condition(const void *val)
+static int update_rc_condition(int state_id, const void *val)
{
const struct mt_spm_cond_tables *tlb = (const struct mt_spm_cond_tables *)val;
const struct mt_spm_cond_tables *tlb_check =
@@ -185,7 +186,7 @@
return MT_RM_STATUS_BAD;
}
- status.is_cond_block = mt_spm_cond_check(tlb, tlb_check,
+ status.is_cond_block = mt_spm_cond_check(state_id, tlb, tlb_check,
(status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ?
&cond_bus26m_res : NULL);
status.all_pll_dump = mt_spm_dump_all_pll(tlb, tlb_check,
@@ -279,7 +280,7 @@
switch (type) {
case PLAT_RC_UPDATE_CONDITION:
- res = update_rc_condition(val);
+ res = update_rc_condition(state_id, val);
break;
case PLAT_RC_UPDATE_REMAIN_IRQS:
update_rc_remain_irqs(val);
diff --git a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_dram.c b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_dram.c
index d1a2435..82b38ad 100644
--- a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_dram.c
+++ b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_dram.c
@@ -37,6 +37,7 @@
#define CONSTRAINT_DRAM_RESOURCE_REQ (MT_SPM_SYSPLL | MT_SPM_INFRA | MT_SPM_26M)
static struct mt_spm_cond_tables cond_dram = {
+ .name = "dram",
.table_cg = {
0xFF5DD002, /* MTCMOS1 */
0x0000003C, /* MTCMOS2 */
@@ -104,7 +105,7 @@
(state_id == MT_PLAT_PWR_STATE_SYSTEM_BUS)));
}
-static int update_rc_condition(const void *val)
+static int update_rc_condition(int state_id, const void *val)
{
const struct mt_spm_cond_tables *tlb = (const struct mt_spm_cond_tables *)val;
const struct mt_spm_cond_tables *tlb_check = (const struct mt_spm_cond_tables *)&cond_dram;
@@ -113,7 +114,7 @@
return MT_RM_STATUS_BAD;
}
- status.is_cond_block = mt_spm_cond_check(tlb, tlb_check,
+ status.is_cond_block = mt_spm_cond_check(state_id, tlb, tlb_check,
(status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ?
&cond_dram_res : NULL);
return MT_RM_STATUS_OK;
@@ -185,7 +186,7 @@
switch (type) {
case PLAT_RC_UPDATE_CONDITION:
- res = update_rc_condition(val);
+ res = update_rc_condition(state_id, val);
break;
case PLAT_RC_CLKBUF_STATUS:
update_rc_clkbuf_status(val);
diff --git a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_syspll.c b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_syspll.c
index 700f500..5359c7c 100644
--- a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_syspll.c
+++ b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_syspll.c
@@ -49,6 +49,7 @@
static unsigned short ext_status_syspll;
static struct mt_spm_cond_tables cond_syspll = {
+ .name = "syspll",
.table_cg = {
0xFF5DD002, /* MTCMOS1 */
0x0000003C, /* MTCMOS2 */
@@ -113,7 +114,7 @@
(state_id == MT_PLAT_PWR_STATE_SYSTEM_BUS)));
}
-static int update_rc_condition(const void *val)
+static int update_rc_condition(int state_id, const void *val)
{
int res = MT_RM_STATUS_OK;
@@ -126,7 +127,7 @@
return MT_RM_STATUS_BAD;
}
- status.is_cond_block = mt_spm_cond_check(tlb, tlb_check,
+ status.is_cond_block = mt_spm_cond_check(state_id, tlb, tlb_check,
(status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ?
&cond_syspll_res : NULL);
return res;
@@ -228,7 +229,7 @@
switch (type) {
case PLAT_RC_UPDATE_CONDITION:
- res = update_rc_condition(val);
+ res = update_rc_condition(state_id, val);
break;
case PLAT_RC_CLKBUF_STATUS:
update_rc_clkbuf_status(val);
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.c b/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.c
index fe6e598..bed55c9 100644
--- a/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.c
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.c
@@ -126,12 +126,14 @@
#define PLL_APLL4 MT_LP_TZ_APMIXEDSYS(0x404)
#define PLL_APLL5 MT_LP_TZ_APMIXEDSYS(0x418)
-unsigned int mt_spm_cond_check(const struct mt_spm_cond_tables *src,
+unsigned int mt_spm_cond_check(int state_id,
+ const struct mt_spm_cond_tables *src,
const struct mt_spm_cond_tables *dest,
struct mt_spm_cond_tables *res)
{
unsigned int b_res = 0U;
unsigned int i;
+ bool is_system_suspend = IS_PLAT_SUSPEND_ID(state_id);
if ((src == NULL) || (dest == NULL)) {
return SPM_COND_CHECK_FAIL;
@@ -140,6 +142,11 @@
for (i = 0; i < PLAT_SPM_COND_MAX; i++) {
if (res != NULL) {
res->table_cg[i] = (src->table_cg[i] & dest->table_cg[i]);
+ if (is_system_suspend && ((res->table_cg[i]) != 0U)) {
+ INFO("suspend: %s block[%u](0x%lx) = 0x%08x\n",
+ dest->name, i, idle_cg_info[i].addr,
+ res->table_cg[i]);
+ }
if ((res->table_cg[i]) != 0U) {
b_res |= BIT(i);
@@ -161,6 +168,10 @@
b_res |= SPM_COND_CHECK_BLOCKED_PLL;
}
+ if (is_system_suspend && ((b_res) != 0U)) {
+ INFO("suspend: %s total blocked = 0x%08x\n", dest->name, b_res);
+ }
+
return b_res;
}
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.h b/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.h
index 793d5e8..d93df57 100644
--- a/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.h
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.h
@@ -75,13 +75,15 @@
#define SPM_COND_CHECK_FAIL BIT(31)
struct mt_spm_cond_tables {
+ char *name;
unsigned int table_cg[PLAT_SPM_COND_MAX];
unsigned int table_pll;
unsigned int table_all_pll;
void *priv;
};
-unsigned int mt_spm_cond_check(const struct mt_spm_cond_tables *src,
+unsigned int mt_spm_cond_check(int state_id,
+ const struct mt_spm_cond_tables *src,
const struct mt_spm_cond_tables *dest,
struct mt_spm_cond_tables *res);
unsigned int mt_spm_dump_all_pll(const struct mt_spm_cond_tables *src,
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_conservation.c b/plat/mediatek/drivers/spm/mt8188/mt_spm_conservation.c
index bcb2df6..395448a 100644
--- a/plat/mediatek/drivers/spm/mt8188/mt_spm_conservation.c
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_conservation.c
@@ -61,6 +61,14 @@
__spm_send_cpu_wakeup_event();
+ INFO("cpu%d: wakesrc = 0x%x, settle = 0x%x, sec = %u\n",
+ cpu, pwrctrl->wake_src, mmio_read_32(SPM_CLK_SETTLE),
+ (mmio_read_32(PCM_TIMER_VAL) / 32768));
+ INFO("sw_flag = 0x%x 0x%x, req = 0x%x, pwr = 0x%x 0x%x\n",
+ pwrctrl->pcm_flags, pwrctrl->pcm_flags1,
+ mmio_read_32(SPM_SRC_REQ), mmio_read_32(PWR_STATUS),
+ mmio_read_32(PWR_STATUS_2ND));
+
return ret;
}
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.c b/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.c
index b38a6d0..5eb16b3 100644
--- a/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.c
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.c
@@ -24,6 +24,7 @@
wake_reason_t __spm_output_wake_reason(const struct wake_status *wakesta)
{
+ uint32_t bk_vtcxo_dur, spm_26m_off_pct;
wake_reason_t wr = WR_UNKNOWN;
if (wakesta == NULL) {
@@ -46,6 +47,33 @@
}
}
+ INFO("r12 = 0x%x, r12_ext = 0x%x, r13 = 0x%x, debug_flag = 0x%x 0x%x\n",
+ wakesta->tr.comm.r12, wakesta->r12_ext, wakesta->tr.comm.r13, wakesta->tr.comm.debug_flag,
+ wakesta->tr.comm.debug_flag1);
+ INFO("raw_sta = 0x%x 0x%x 0x%x, idle_sta = 0x%x, cg_check_sta = 0x%x\n",
+ wakesta->tr.comm.raw_sta, wakesta->md32pcm_wakeup_sta,
+ wakesta->md32pcm_event_sta, wakesta->idle_sta,
+ wakesta->cg_check_sta);
+ INFO("req_sta = 0x%x 0x%x 0x%x 0x%x 0x%x, isr = 0x%x\n",
+ wakesta->tr.comm.req_sta0, wakesta->tr.comm.req_sta1, wakesta->tr.comm.req_sta2,
+ wakesta->tr.comm.req_sta3, wakesta->tr.comm.req_sta4, wakesta->isr);
+ INFO("rt_req_sta0 = 0x%x, rt_req_sta1 = 0x%x, rt_req_sta2 = 0x%x\n",
+ wakesta->rt_req_sta0, wakesta->rt_req_sta1, wakesta->rt_req_sta2);
+ INFO("rt_req_sta3 = 0x%x, dram_sw_con_3 = 0x%x, raw_ext_sta = 0x%x\n",
+ wakesta->rt_req_sta3, wakesta->rt_req_sta4, wakesta->raw_ext_sta);
+ INFO("wake_misc = 0x%x, pcm_flag = 0x%x 0x%x 0x%x 0x%x, req = 0x%x\n",
+ wakesta->wake_misc, wakesta->sw_flag0, wakesta->sw_flag1,
+ wakesta->tr.comm.b_sw_flag0, wakesta->tr.comm.b_sw_flag1, wakesta->src_req);
+ INFO("clk_settle = 0x%x, wlk_cntcv_l = 0x%x, wlk_cntcv_h = 0x%x\n",
+ wakesta->clk_settle, mmio_read_32(SYS_TIMER_VALUE_L),
+ mmio_read_32(SYS_TIMER_VALUE_H));
+
+ if (wakesta->tr.comm.timer_out != 0U) {
+ bk_vtcxo_dur = mmio_read_32(SPM_BK_VTCXO_DUR);
+ spm_26m_off_pct = (100 * bk_vtcxo_dur) / wakesta->tr.comm.timer_out;
+ INFO("spm_26m_off_pct = %u\n", spm_26m_off_pct);
+ }
+
return wr;
}
@@ -331,6 +359,18 @@
wakesta->tr.comm.b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7); /* SPM_SW_RSV_7 */
wakesta->tr.comm.b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8); /* SPM_SW_RSV_8 */
+ /* record below spm info for debug */
+ wakesta->src_req = mmio_read_32(SPM_SRC_REQ);
+
+ /* get HW CG check status */
+ wakesta->cg_check_sta = mmio_read_32(SPM_CG_CHECK_STA);
+
+ wakesta->rt_req_sta0 = mmio_read_32(SPM_SW_RSV_2);
+ wakesta->rt_req_sta1 = mmio_read_32(SPM_SW_RSV_3);
+ wakesta->rt_req_sta2 = mmio_read_32(SPM_SW_RSV_4);
+ wakesta->rt_req_sta3 = mmio_read_32(SPM_SW_RSV_5);
+ wakesta->rt_req_sta4 = mmio_read_32(SPM_SW_RSV_6);
+
/* get ISR status */
wakesta->isr = mmio_read_32(SPM_IRQ_STA);
@@ -338,6 +378,9 @@
wakesta->sw_flag0 = mmio_read_32(SPM_SW_FLAG_0);
wakesta->sw_flag1 = mmio_read_32(SPM_SW_FLAG_1);
+ /* get CLK SETTLE */
+ wakesta->clk_settle = mmio_read_32(SPM_CLK_SETTLE);
+
/* check abort */
wakesta->is_abort = wakesta->tr.comm.debug_flag & DEBUG_ABORT_MASK;
wakesta->is_abort |= wakesta->tr.comm.debug_flag1 & DEBUG_ABORT_MASK_1;
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.h b/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.h
index c719caf..5e3390f 100644
--- a/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.h
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.h
@@ -628,11 +628,19 @@
uint32_t md32pcm_event_sta; /* MD32PCM_EVENT_STA */
uint32_t wake_misc; /* SPM_SW_RSV_5 */
uint32_t idle_sta; /* SUBSYS_IDLE_STA */
+ uint32_t cg_check_sta; /* SPM_CG_CHECK_STA */
uint32_t sw_flag0; /* SPM_SW_FLAG_0 */
uint32_t sw_flag1; /* SPM_SW_FLAG_1 */
uint32_t isr; /* SPM_IRQ_STA */
+ uint32_t clk_settle; /* SPM_CLK_SETTLE */
+ uint32_t src_req; /* SPM_SRC_REQ */
uint32_t log_index;
uint32_t is_abort;
+ uint32_t rt_req_sta0; /* SPM_SW_RSV_2 */
+ uint32_t rt_req_sta1; /* SPM_SW_RSV_3 */
+ uint32_t rt_req_sta2; /* SPM_SW_RSV_4 */
+ uint32_t rt_req_sta3; /* SPM_SW_RSV_5 */
+ uint32_t rt_req_sta4; /* SPM_SW_RSV_6 */
};
struct spm_lp_scen {
diff --git a/plat/mediatek/include/mtk_sip_svc.h b/plat/mediatek/include/mtk_sip_svc.h
index f677915..684f951 100644
--- a/plat/mediatek/include/mtk_sip_svc.h
+++ b/plat/mediatek/include/mtk_sip_svc.h
@@ -97,7 +97,7 @@
};
/*
- * This function should be implemented in MediaTek SOC directory. It fullfills
+ * This function should be implemented in MediaTek SOC directory. It fulfills
* MTK_SIP_SET_AUTHORIZED_SECURE_REG SiP call by checking the sreg with the
* predefined secure register list, if a match was found, set val to sreg.
*
diff --git a/plat/mediatek/mt8173/bl31_plat_setup.c b/plat/mediatek/mt8173/bl31_plat_setup.c
index bd7d0b0..fd7874f 100644
--- a/plat/mediatek/mt8173/bl31_plat_setup.c
+++ b/plat/mediatek/mt8173/bl31_plat_setup.c
@@ -129,7 +129,7 @@
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the mmu in a quick and dirty way.
+ * moment this is only initializes the mmu in a quick and dirty way.
******************************************************************************/
void bl31_plat_arch_setup(void)
{
diff --git a/plat/mediatek/mt8173/drivers/spm/spm.c b/plat/mediatek/mt8173/drivers/spm/spm.c
index 8980e07..0d3acb2 100644
--- a/plat/mediatek/mt8173/drivers/spm/spm.c
+++ b/plat/mediatek/mt8173/drivers/spm/spm.c
@@ -20,7 +20,7 @@
* - spm_suspend.c for system power control in system suspend scenario.
*
* This file provide utility functions common to hotplug, mcdi(idle), suspend
- * power scenarios. A bakery lock (software lock) is incoporated to protect
+ * power scenarios. A bakery lock (software lock) is incorporated to protect
* certain critical sections to avoid kicking different SPM firmware
* concurrently.
*/
diff --git a/plat/mediatek/mt8183/bl31_plat_setup.c b/plat/mediatek/mt8183/bl31_plat_setup.c
index 7dac8a4..f608da3 100644
--- a/plat/mediatek/mt8183/bl31_plat_setup.c
+++ b/plat/mediatek/mt8183/bl31_plat_setup.c
@@ -163,7 +163,7 @@
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the mmu in a quick and dirty way.
+ * moment this is only initializes the mmu in a quick and dirty way.
******************************************************************************/
void bl31_plat_arch_setup(void)
{
diff --git a/plat/mediatek/mt8186/bl31_plat_setup.c b/plat/mediatek/mt8186/bl31_plat_setup.c
index 5fc6b6e..fb826be 100644
--- a/plat/mediatek/mt8186/bl31_plat_setup.c
+++ b/plat/mediatek/mt8186/bl31_plat_setup.c
@@ -102,7 +102,7 @@
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the mmu in a quick and dirty way.
+ * moment this is only initializes the mmu in a quick and dirty way.
******************************************************************************/
void bl31_plat_arch_setup(void)
{
diff --git a/plat/mediatek/mt8192/bl31_plat_setup.c b/plat/mediatek/mt8192/bl31_plat_setup.c
index c3cb9a5..3b23027 100644
--- a/plat/mediatek/mt8192/bl31_plat_setup.c
+++ b/plat/mediatek/mt8192/bl31_plat_setup.c
@@ -110,7 +110,7 @@
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the mmu in a quick and dirty way.
+ * moment this is only initializes the mmu in a quick and dirty way.
******************************************************************************/
void bl31_plat_arch_setup(void)
{
diff --git a/plat/mediatek/mt8195/bl31_plat_setup.c b/plat/mediatek/mt8195/bl31_plat_setup.c
index dff6670..0f5674f 100644
--- a/plat/mediatek/mt8195/bl31_plat_setup.c
+++ b/plat/mediatek/mt8195/bl31_plat_setup.c
@@ -106,7 +106,7 @@
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the mmu in a quick and dirty way.
+ * moment this is only initializes the mmu in a quick and dirty way.
******************************************************************************/
void bl31_plat_arch_setup(void)
{
diff --git a/plat/mediatek/mt8195/drivers/apusys/apupll.c b/plat/mediatek/mt8195/drivers/apusys/apupll.c
index 0eb8d4a..3c18798 100644
--- a/plat/mediatek/mt8195/drivers/apusys/apupll.c
+++ b/plat/mediatek/mt8195/drivers/apusys/apupll.c
@@ -268,7 +268,7 @@
* @pll_idx: Which PLL to enable/disable
* @on: 1 -> enable, 0 -> disable.
*
- * This funciton will only change RG_PLL_EN of CON1 for pll[pll_idx].
+ * This function will only change RG_PLL_EN of CON1 for pll[pll_idx].
*
* Context: Any context.
*/
@@ -286,7 +286,7 @@
* @pll_idx: Which PLL to enable/disable
* @on: 1 -> enable, 0 -> disable.
*
- * This funciton will only change PLL_SDM_PWR_ON of CON3 for pll[pll_idx].
+ * This function will only change PLL_SDM_PWR_ON of CON3 for pll[pll_idx].
*
* Context: Any context.
*/
@@ -304,7 +304,7 @@
* @pll_idx: Which PLL to enable/disable
* @enable: 1 -> turn on isolation, 0 -> turn off isolation.
*
- * This funciton will turn on/off pll isolation by
+ * This function will turn on/off pll isolation by
* changing PLL_SDM_PWR_ON of CON3 for pll[pll_idx].
*
* Context: Any context.
@@ -324,7 +324,7 @@
* @on: 1 -> enable, 0 -> disable.
* @fhctl_en: enable or disable fhctl function
*
- * This is the entry poing for controlling pll and fhctl funciton on/off.
+ * This is the entry poing for controlling pll and fhctl function on/off.
* Caller can chose only enable pll instead of fhctl function.
*
* Context: Any context.
diff --git a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
index 6c8c4f0..72ecd54 100644
--- a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
+++ b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
@@ -125,15 +125,18 @@
.endm
/* -----------------------------------------------------
- * unsigned int plat_is_my_cpu_primary(void);
+ * bool plat_is_my_cpu_primary(void);
*
* This function checks if this is the Primary CPU
+ *
+ * Registers clobbered: x0, x1
* -----------------------------------------------------
*/
func plat_is_my_cpu_primary
mrs x0, mpidr_el1
- and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
- cmp x0, #TEGRA_PRIMARY_CPU
+ adr x1, tegra_primary_cpu_mpid
+ ldr x1, [x1]
+ cmp x0, x1
cset x0, eq
ret
endfunc plat_is_my_cpu_primary
@@ -251,6 +254,14 @@
adr x18, bl31_entrypoint
str x18, [x17]
+ /* -----------------------------------
+ * save the boot CPU MPID value
+ * -----------------------------------
+ */
+ mrs x0, mpidr_el1
+ adr x1, tegra_primary_cpu_mpid
+ str x0, [x1]
+
1: cpu_init_common
ret
@@ -426,3 +437,10 @@
*/
tegra_console_base:
.quad 0
+
+ /* --------------------------------------------------
+ * MPID value for the boot CPU
+ * --------------------------------------------------
+ */
+tegra_primary_cpu_mpid:
+ .quad 0
diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index 6a3eae0..e3068b6 100644
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2020-2023, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -92,21 +92,16 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
- struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0;
- plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1;
+ struct tegra_bl31_params *arg_from_bl2 = plat_get_bl31_params();
+ plat_params_from_bl2_t *plat_params = plat_get_bl31_plat_params();
int32_t ret;
/*
- * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so
- * there's no argument to relay from a previous bootloader. Platforms
- * might use custom ways to get arguments.
+ * Tegra platforms will receive boot parameters through custom
+ * mechanisms. So, we ignore the input parameters.
*/
- if (arg_from_bl2 == NULL) {
- arg_from_bl2 = plat_get_bl31_params();
- }
- if (plat_params == NULL) {
- plat_params = plat_get_bl31_plat_params();
- }
+ (void)arg0;
+ (void)arg1;
/*
* Copy BL3-3, BL3-2 entry point information.
@@ -267,7 +262,7 @@
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
- * moment this only intializes the mmu in a quick and dirty way.
+ * moment this only initializes the mmu in a quick and dirty way.
******************************************************************************/
void bl31_plat_arch_setup(void)
{
diff --git a/plat/nvidia/tegra/common/tegra_pm.c b/plat/nvidia/tegra/common/tegra_pm.c
index ec34a85..8edb024 100644
--- a/plat/nvidia/tegra/common/tegra_pm.c
+++ b/plat/nvidia/tegra/common/tegra_pm.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2020-2023, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -92,6 +92,16 @@
/*******************************************************************************
* Handler called when a power domain is about to be turned off. The
* target_state encodes the power state that each level should transition to.
+ * Return error if CPU off sequence is not allowed for the current core.
+ ******************************************************************************/
+static int tegra_pwr_domain_off_early(const psci_power_state_t *target_state)
+{
+ return tegra_soc_pwr_domain_off_early(target_state);
+}
+
+/*******************************************************************************
+ * Handler called when a power domain is about to be turned off. The
+ * target_state encodes the power state that each level should transition to.
******************************************************************************/
static void tegra_pwr_domain_off(const psci_power_state_t *target_state)
{
@@ -268,6 +278,7 @@
static plat_psci_ops_t tegra_plat_psci_ops = {
.cpu_standby = tegra_cpu_standby,
.pwr_domain_on = tegra_pwr_domain_on,
+ .pwr_domain_off_early = tegra_pwr_domain_off_early,
.pwr_domain_off = tegra_pwr_domain_off,
.pwr_domain_suspend_pwrdown_early = tegra_pwr_domain_suspend_pwrdown_early,
.pwr_domain_suspend = tegra_pwr_domain_suspend,
diff --git a/plat/nvidia/tegra/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/drivers/memctrl/memctrl_v2.c
index 92120b5..0644fd2 100644
--- a/plat/nvidia/tegra/drivers/memctrl/memctrl_v2.c
+++ b/plat/nvidia/tegra/drivers/memctrl/memctrl_v2.c
@@ -301,7 +301,7 @@
if (video_mem_base != 0U) {
/*
* Lock the non overlapping memory being cleared so that
- * other masters do not accidently write to it. The memory
+ * other masters do not accidentally write to it. The memory
* would be unlocked once the non overlapping region is
* cleared and the new memory settings take effect.
*/
diff --git a/plat/nvidia/tegra/include/drivers/tegra_gic.h b/plat/nvidia/tegra/include/drivers/tegra_gic.h
index 6661dff..9f9477c 100644
--- a/plat/nvidia/tegra/include/drivers/tegra_gic.h
+++ b/plat/nvidia/tegra/include/drivers/tegra_gic.h
@@ -19,7 +19,7 @@
} pcpu_fiq_state_t;
/*******************************************************************************
- * Fucntion declarations
+ * Function declarations
******************************************************************************/
void tegra_gic_cpuif_deactivate(void);
void tegra_gic_init(void);
diff --git a/plat/nvidia/tegra/include/platform_def.h b/plat/nvidia/tegra/include/platform_def.h
index 84b3297..958a3f9 100644
--- a/plat/nvidia/tegra/include/platform_def.h
+++ b/plat/nvidia/tegra/include/platform_def.h
@@ -41,8 +41,6 @@
#define PLATFORM_STACK_SIZE U(0x400)
#endif
-#define TEGRA_PRIMARY_CPU U(0x0)
-
#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
PLATFORM_MAX_CPUS_PER_CLUSTER)
diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h
index a971cec..cf8778b 100644
--- a/plat/nvidia/tegra/include/t186/tegra_def.h
+++ b/plat/nvidia/tegra/include/t186/tegra_def.h
@@ -84,7 +84,7 @@
#define TEGRA_CLK_SE TEGRA186_CLK_SE
/*******************************************************************************
- * Tegra Miscellanous register constants
+ * Tegra Miscellaneous register constants
******************************************************************************/
#define TEGRA_MISC_BASE U(0x00100000)
#define HARDWARE_REVISION_OFFSET U(0x4)
diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h
index abe193f..2158913 100644
--- a/plat/nvidia/tegra/include/t194/tegra_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_def.h
@@ -60,7 +60,7 @@
#define TEGRA_CLK_SE TEGRA194_CLK_SE
/*******************************************************************************
- * Tegra Miscellanous register constants
+ * Tegra Miscellaneous register constants
******************************************************************************/
#define TEGRA_MISC_BASE U(0x00100000)
diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h
index cc2ad86..f93585d 100644
--- a/plat/nvidia/tegra/include/tegra_private.h
+++ b/plat/nvidia/tegra/include/tegra_private.h
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2020-2023, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -98,6 +98,9 @@
int32_t tegra_fiq_get_intr_context(void);
void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint);
+/* Declarations for tegra_helpers.S */
+bool plat_is_my_cpu_primary(void);
+
/* Declarations for tegra_security.c */
void tegra_security_setup(void);
void tegra_security_setup_videomem(uintptr_t base, uint64_t size);
@@ -109,6 +112,7 @@
int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state);
int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state);
int32_t tegra_soc_pwr_domain_on(u_register_t mpidr);
+int32_t tegra_soc_pwr_domain_off_early(const psci_power_state_t *target_state);
int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state);
int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state);
int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state);
@@ -150,7 +154,7 @@
void *handle,
uint64_t flags);
-#if RAS_EXTENSION
+#if RAS_FFH_SUPPORT
void tegra194_ras_enable(void);
void tegra194_ras_corrected_err_clear(uint64_t *cookie);
#endif
diff --git a/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h b/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h
index ecfb3f4..45302da 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h
+++ b/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h
@@ -40,7 +40,7 @@
/* index 83 is deprecated */
TEGRA_ARI_PERFMON = 84U,
TEGRA_ARI_UPDATE_CCPLEX_GSC = 85U,
- /* index 86 is depracated */
+ /* index 86 is deprecated */
/* index 87 is deprecated */
TEGRA_ARI_ROC_FLUSH_CACHE_ONLY = 88U,
TEGRA_ARI_ROC_FLUSH_CACHE_TRBITS = 89U,
diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
index af4182e..8f88e28 100644
--- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
@@ -433,6 +433,16 @@
return PSCI_E_SUCCESS;
}
+int32_t tegra_soc_pwr_domain_off_early(const psci_power_state_t *target_state)
+{
+ /* Do not power off the boot CPU */
+ if (plat_is_my_cpu_primary()) {
+ return PSCI_E_DENIED;
+ }
+
+ return PSCI_E_SUCCESS;
+}
+
int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
{
uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK;
diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h
index 7a68a43..ca74d2c 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h
+++ b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h
@@ -17,7 +17,7 @@
/**
* Current version - Major version increments may break backwards
- * compatiblity and binary compatibility. Minor version increments
+ * compatibility and binary compatibility. Minor version increments
* occur when there is only new functionality.
*/
enum {
diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
index 41a85ee..83d815a 100644
--- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
@@ -463,6 +463,16 @@
return PSCI_E_SUCCESS;
}
+int32_t tegra_soc_pwr_domain_off_early(const psci_power_state_t *target_state)
+{
+ /* Do not power off the boot CPU */
+ if (plat_is_my_cpu_primary()) {
+ return PSCI_E_DENIED;
+ }
+
+ return PSCI_E_SUCCESS;
+}
+
int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
{
uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
diff --git a/plat/nvidia/tegra/soc/t194/plat_ras.c b/plat/nvidia/tegra/soc/t194/plat_ras.c
index a9fed0a..2f438c3 100644
--- a/plat/nvidia/tegra/soc/t194/plat_ras.c
+++ b/plat/nvidia/tegra/soc/t194/plat_ras.c
@@ -284,7 +284,7 @@
ERROR("RAS Error in %s, ERRSELR_EL1=0x%x:\n", name, errselr);
ERROR("\tStatus = 0x%" PRIx64 "\n", status);
- /* Print uncorrectable errror information. */
+ /* Print uncorrectable error information. */
if (ERR_STATUS_GET_FIELD(status, UE) != 0U) {
ERR_STATUS_SET_FIELD(val, UE, 1);
@@ -484,7 +484,7 @@
void plat_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie,
void *handle, uint64_t flags)
{
-#if RAS_EXTENSION
+#if RAS_FFH_SUPPORT
tegra194_ea_handler(ea_reason, syndrome, cookie, handle, flags);
#else
plat_default_ea_handler(ea_reason, syndrome, cookie, handle, flags);
diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c
index 8f7d1e9..d3d09d3 100644
--- a/plat/nvidia/tegra/soc/t194/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t194/plat_setup.c
@@ -254,7 +254,7 @@
/* sanity check MCE firmware compatibility */
mce_verify_firmware_version();
-#if RAS_EXTENSION
+#if RAS_FFH_SUPPORT
/* Enable Uncorrectable RAS error */
tegra194_ras_enable();
#endif
diff --git a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c
index 1eef559..f0704ed 100644
--- a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c
+++ b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c
@@ -71,7 +71,7 @@
break;
-#if RAS_EXTENSION
+#if RAS_FFH_SUPPORT
case TEGRA_SIP_CLEAR_RAS_CORRECTED_ERRORS:
{
/*
diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk
index 631c926..a183d0e 100644
--- a/plat/nvidia/tegra/soc/t194/platform_t194.mk
+++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk
@@ -34,7 +34,8 @@
# enable RAS handling
HANDLE_EA_EL3_FIRST_NS := 1
-RAS_EXTENSION := 1
+ENABLE_FEAT_RAS := 1
+RAS_FFH_SUPPORT := 1
# platform files
PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t194 \
@@ -68,7 +69,7 @@
endif
# RAS sources
-ifeq (${RAS_EXTENSION},1)
+ifeq (${RAS_FFH_SUPPORT},1)
BL31_SOURCES += lib/extensions/ras/std_err_record.c \
lib/extensions/ras/ras_common.c \
${SOC_DIR}/plat_ras.c
diff --git a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
index 7f73ea5..2ec044c 100644
--- a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
@@ -575,6 +575,16 @@
return PSCI_E_SUCCESS;
}
+int32_t tegra_soc_pwr_domain_off_early(const psci_power_state_t *target_state)
+{
+ /* Do not power off the boot CPU */
+ if (plat_is_my_cpu_primary()) {
+ return PSCI_E_DENIED;
+ }
+
+ return PSCI_E_SUCCESS;
+}
+
int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
{
tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK);
diff --git a/plat/nvidia/tegra/soc/t210/plat_sip_calls.c b/plat/nvidia/tegra/soc/t210/plat_sip_calls.c
index 93d1283..f3ebd4b 100644
--- a/plat/nvidia/tegra/soc/t210/plat_sip_calls.c
+++ b/plat/nvidia/tegra/soc/t210/plat_sip_calls.c
@@ -33,8 +33,7 @@
/*******************************************************************************
* Tegra210 SiP SMCs
******************************************************************************/
-#define TEGRA_SIP_PMC_COMMANDS_LEGACY U(0xC2FEFE00)
-#define TEGRA_SIP_PMC_COMMANDS U(0xC2FFFE00)
+#define TEGRA_SIP_PMC_COMMANDS U(0xC200FE00)
/*******************************************************************************
* This function is responsible for handling all T210 SiP calls
@@ -55,10 +54,12 @@
if (!ns)
SMC_RET1(handle, SMC_UNK);
- if ((smc_fid == TEGRA_SIP_PMC_COMMANDS) || (smc_fid == TEGRA_SIP_PMC_COMMANDS_LEGACY)) {
+ if (smc_fid == TEGRA_SIP_PMC_COMMANDS) {
+
/* check the address is within PMC range and is 4byte aligned */
- if ((x2 >= TEGRA_PMC_SIZE) || (x2 & 0x3))
+ if ((x2 >= TEGRA_PMC_SIZE) || (x2 & 0x3)) {
return -EINVAL;
+ }
switch (x2) {
/* Black listed PMC registers */
diff --git a/plat/nxp/common/fip_handler/ddr_fip/ddr_fip_io.mk b/plat/nxp/common/fip_handler/ddr_fip/ddr_fip_io.mk
index 7d673ba..36c07b7 100644
--- a/plat/nxp/common/fip_handler/ddr_fip/ddr_fip_io.mk
+++ b/plat/nxp/common/fip_handler/ddr_fip/ddr_fip_io.mk
@@ -1,5 +1,6 @@
#
# Copyright 2020 NXP
+# Copyright (c) 2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -22,8 +23,6 @@
DDR_FIP_IO_SOURCES += $(DDR_FIP_IO_STORAGE_PATH)/ddr_io_storage.c
-$(shell cp tools/nxp/plat_fiptool/plat_fiptool.mk ${PLAT_DIR})
-
ifeq (${BL_COMM_DDR_FIP_IO_NEEDED},yes)
BL_COMMON_SOURCES += ${DDR_FIP_IO_SOURCES}
else
diff --git a/plat/nxp/common/fip_handler/fuse_fip/fuse.mk b/plat/nxp/common/fip_handler/fuse_fip/fuse.mk
index d8f5ae6..4e84d02 100644
--- a/plat/nxp/common/fip_handler/fuse_fip/fuse.mk
+++ b/plat/nxp/common/fip_handler/fuse_fip/fuse.mk
@@ -1,5 +1,6 @@
#
# Copyright 2018-2020 NXP
+# Copyright (c) 2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -29,8 +30,6 @@
ifeq (${FUSE_PROV_FILE},)
-$(shell cp tools/nxp/plat_fiptool/plat_fiptool.mk ${PLAT_DIR})
-
else
ifeq (${TRUSTED_BOARD_BOOT},1)
FUSE_PROV_FILE_SB = $(notdir ${FUSE_PROV_FILE})_prov.sb
diff --git a/plat/nxp/common/setup/ls_bl31_setup.c b/plat/nxp/common/setup/ls_bl31_setup.c
index bd0ab4f..3d0d804 100644
--- a/plat/nxp/common/setup/ls_bl31_setup.c
+++ b/plat/nxp/common/setup/ls_bl31_setup.c
@@ -174,7 +174,7 @@
soc_platform_setup();
/* Console logs gone missing as part going to
- * EL1 for initilizing Bl32 if present.
+ * EL1 for initializing Bl32 if present.
* console flush is necessary to avoid it.
*/
(void)console_flush();
diff --git a/plat/nxp/soc-ls1088a/include/soc.h b/plat/nxp/soc-ls1088a/include/soc.h
index eb36c2e..793feee 100644
--- a/plat/nxp/soc-ls1088a/include/soc.h
+++ b/plat/nxp/soc-ls1088a/include/soc.h
@@ -112,7 +112,7 @@
#define IPSTPCR1_VALUE 0x000003FF
#define IPSTPCR2_VALUE 0x00013006
-/* Dont' stop UART */
+/* Don't stop UART */
#define IPSTPCR3_VALUE 0x0000033A
#define IPSTPCR4_VALUE 0x00103300
diff --git a/plat/qemu/common/qemu_common.c b/plat/qemu/common/qemu_common.c
index 935ba7a..98be491 100644
--- a/plat/qemu/common/qemu_common.c
+++ b/plat/qemu/common/qemu_common.c
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -162,3 +162,14 @@
return 0;
}
#endif
+
+#if defined(SPD_spmd) && (SPMC_AT_EL3 == 0)
+/*
+ * A dummy implementation of the platform handler for Group0 secure interrupt.
+ */
+int plat_spmd_handle_group0_interrupt(uint32_t intid)
+{
+ (void)intid;
+ return -1;
+}
+#endif /*defined(SPD_spmd) && (SPMC_AT_EL3 == 0)*/
diff --git a/plat/qemu/qemu_sbsa/platform.mk b/plat/qemu/qemu_sbsa/platform.mk
index 7b3129c..8b8d76b 100644
--- a/plat/qemu/qemu_sbsa/platform.mk
+++ b/plat/qemu/qemu_sbsa/platform.mk
@@ -139,3 +139,6 @@
# Later QEMU versions support SME and SVE.
ENABLE_SVE_FOR_NS := 2
ENABLE_SME_FOR_NS := 2
+
+# QEMU 7.2+ has support for FGT and Linux needs it enabled to boot on max
+ENABLE_FEAT_FGT := 2
diff --git a/plat/qti/common/src/qti_bl31_setup.c b/plat/qti/common/src/qti_bl31_setup.c
index dac0253..a5f5858 100644
--- a/plat/qti/common/src/qti_bl31_setup.c
+++ b/plat/qti/common/src/qti_bl31_setup.c
@@ -81,7 +81,7 @@
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
- * moment this only intializes the mmu in a quick and dirty way.
+ * moment this only initializes the mmu in a quick and dirty way.
******************************************************************************/
void bl31_plat_arch_setup(void)
{
diff --git a/plat/qti/msm8916/aarch64/msm8916_helpers.S b/plat/qti/msm8916/aarch64/msm8916_helpers.S
index dad9968..528c5a4 100644
--- a/plat/qti/msm8916/aarch64/msm8916_helpers.S
+++ b/plat/qti/msm8916/aarch64/msm8916_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net>
+ * Copyright (c) 2021-2023, Stephan Gerhold <stephan@gerhold.net>
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -31,17 +31,6 @@
*/
func plat_crash_console_init
mov x1, #BLSP_UART2_BASE
-
- /*
- * If the non-secure world has been actively using the UART there might
- * be still some characters left to be sent in the FIFO. In that case,
- * resetting the transmitter too early might cause all output to become
- * corrupted. To avoid that, try to flush (wait until FIFO empty) first.
- */
- mov x4, lr
- bl console_uartdm_core_flush
- mov lr, x4
-
mov x0, #1
b console_uartdm_core_init
endfunc plat_crash_console_init
diff --git a/plat/qti/msm8916/aarch64/uartdm_console.S b/plat/qti/msm8916/aarch64/uartdm_console.S
index c69c193..6c65daf 100644
--- a/plat/qti/msm8916/aarch64/uartdm_console.S
+++ b/plat/qti/msm8916/aarch64/uartdm_console.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net>
+ * Copyright (c) 2021-2023, Stephan Gerhold <stephan@gerhold.net>
*
* Based on aarch64/skeleton_console.S:
* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
@@ -65,7 +65,21 @@
* -----------------------------------------------------------
*/
func console_uartdm_core_init
- /* Reset receiver */
+ /*
+ * Try to flush remaining characters from the TX FIFO before resetting
+ * the transmitter. Unfortunately there is no good way to check if
+ * the transmitter is actually enabled (and will finish eventually),
+ * so use a timeout to avoid looping forever.
+ */
+ mov w2, #65536
+1:
+ ldr w3, [x1, #UART_DM_SR]
+ tbnz w3, #UART_DM_SR_TXEMT_BIT, 2f
+ subs w2, w2, #1
+ b.ne 1b
+ /* Timeout */
+
+2: /* Reset receiver */
mov w3, #UART_DM_CR_RESET_RX
str w3, [x1, #UART_DM_CR]
@@ -113,10 +127,21 @@
* -----------------------------------------------------------
*/
func console_uartdm_core_putc
+ cmp w0, #'\n'
+ b.ne 2f
+
1: /* Loop until TX FIFO has space */
ldr w2, [x1, #UART_DM_SR]
tbz w2, #UART_DM_SR_TXRDY_BIT, 1b
+ /* Prepend '\r' to '\n' */
+ mov w2, #'\r'
+ str w2, [x1, #UART_DM_TF]
+
+2: /* Loop until TX FIFO has space */
+ ldr w2, [x1, #UART_DM_SR]
+ tbz w2, #UART_DM_SR_TXRDY_BIT, 2b
+
/* Write character to FIFO */
str w0, [x1, #UART_DM_TF]
ret
diff --git a/plat/qti/msm8916/include/msm8916_mmap.h b/plat/qti/msm8916/include/msm8916_mmap.h
index 406ae6b..d201536 100644
--- a/plat/qti/msm8916/include/msm8916_mmap.h
+++ b/plat/qti/msm8916/include/msm8916_mmap.h
@@ -8,9 +8,9 @@
#define MSM8916_MMAP_H
#define PCNOC_BASE 0x00000000
-#define PCNOC_SIZE 0x8000000 /* 128 MiB */
+#define PCNOC_SIZE SZ_128M
#define APCS_BASE 0x0b000000
-#define APCS_SIZE 0x800000 /* 8 MiB */
+#define APCS_SIZE SZ_8M
#define MPM_BASE (PCNOC_BASE + 0x04a0000)
#define MPM_PS_HOLD (MPM_BASE + 0xb000)
diff --git a/plat/qti/msm8916/include/platform_def.h b/plat/qti/msm8916/include/platform_def.h
index bfade70..6d5ff2b 100644
--- a/plat/qti/msm8916/include/platform_def.h
+++ b/plat/qti/msm8916/include/platform_def.h
@@ -16,11 +16,11 @@
* the overall limit to 128 KiB. This could be increased if needed by placing
* the "msm8916_entry_point" variable explicitly in the first 64 KiB of BL31.
*/
-#define BL31_LIMIT (BL31_BASE + 0x20000) /* 128 KiB */
-#define BL31_PROGBITS_LIMIT (BL31_BASE + 0x10000) /* 64 KiB */
+#define BL31_LIMIT (BL31_BASE + SZ_128K)
+#define BL31_PROGBITS_LIMIT (BL31_BASE + SZ_64K)
#define CACHE_WRITEBACK_GRANULE U(64)
-#define PLATFORM_STACK_SIZE U(0x1000)
+#define PLATFORM_STACK_SIZE SZ_4K
/* CPU topology: single cluster with 4 cores */
#define PLATFORM_CLUSTER_COUNT U(1)
diff --git a/plat/qti/msm8916/msm8916_bl31_setup.c b/plat/qti/msm8916/msm8916_bl31_setup.c
index 638cd09..8cba5c5 100644
--- a/plat/qti/msm8916/msm8916_bl31_setup.c
+++ b/plat/qti/msm8916/msm8916_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net>
+ * Copyright (c) 2021-2023, Stephan Gerhold <stephan@gerhold.net>
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -119,12 +119,8 @@
/* Set timer frequency */
mmio_write_32(APCS_QTMR + CNTCTLBASE_CNTFRQ, plat_get_syscnt_freq2());
- /* Make frame 0 available to non-secure world */
- mmio_write_32(APCS_QTMR + CNTNSAR, BIT_32(CNTNSAR_NS_SHIFT(0)));
- mmio_write_32(APCS_QTMR + CNTACR_BASE(0),
- BIT_32(CNTACR_RPCT_SHIFT) | BIT_32(CNTACR_RVCT_SHIFT) |
- BIT_32(CNTACR_RFRQ_SHIFT) | BIT_32(CNTACR_RVOFF_SHIFT) |
- BIT_32(CNTACR_RWVT_SHIFT) | BIT_32(CNTACR_RWPT_SHIFT));
+ /* Make all timer frames available to non-secure world */
+ mmio_write_32(APCS_QTMR + CNTNSAR, GENMASK_32(7, 0));
}
/*
diff --git a/plat/qti/msm8916/msm8916_pm.c b/plat/qti/msm8916/msm8916_pm.c
index 6891e38..792a096 100644
--- a/plat/qti/msm8916/msm8916_pm.c
+++ b/plat/qti/msm8916/msm8916_pm.c
@@ -1,10 +1,11 @@
/*
- * Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net>
+ * Copyright (c) 2021-2022, Stephan Gerhold <stephan@gerhold.net>
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
+#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/arm/gicv2.h>
#include <drivers/delay_timer.h>
@@ -53,7 +54,14 @@
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
const plat_psci_ops_t **psci_ops)
{
+ /*
+ * The entry point is read with caches off (and even from two different
+ * physical addresses when read through the "boot remapper"), so make
+ * sure it is flushed to memory.
+ */
msm8916_entry_point = sec_entrypoint;
+ flush_dcache_range((uintptr_t)&msm8916_entry_point, sizeof(uintptr_t));
+
*psci_ops = &msm8916_psci_ops;
return 0;
}
diff --git a/plat/qti/msm8916/platform.mk b/plat/qti/msm8916/platform.mk
index 2baf203..107296b 100644
--- a/plat/qti/msm8916/platform.mk
+++ b/plat/qti/msm8916/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net>
+# Copyright (c) 2021-2023, Stephan Gerhold <stephan@gerhold.net>
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -46,6 +46,10 @@
ENABLE_SPE_FOR_NS := 0
ENABLE_SVE_FOR_NS := 0
+# Disable workarounds unnecessary for Cortex-A53
+WORKAROUND_CVE_2017_5715 := 0
+WORKAROUND_CVE_2022_23960 := 0
+
# MSM8916 uses ARM Cortex-A53 r0p0 so likely all the errata apply
ERRATA_A53_819472 := 1
ERRATA_A53_824069 := 1
diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c
index f85db8d..9ec4bcd 100644
--- a/plat/renesas/rcar/bl2_plat_setup.c
+++ b/plat/renesas/rcar/bl2_plat_setup.c
@@ -1190,7 +1190,7 @@
break;
}
#endif /* RCAR_LSI == RCAR_E3 */
- /* Update memory mapped and register based freqency */
+ /* Update memory mapped and register based frequency */
write_cntfrq_el0((u_register_t )reg_cntfid);
mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid);
/* Enable counter */
diff --git a/plat/rockchip/common/bl31_plat_setup.c b/plat/rockchip/common/bl31_plat_setup.c
index 98ef415..59db3d8 100644
--- a/plat/rockchip/common/bl31_plat_setup.c
+++ b/plat/rockchip/common/bl31_plat_setup.c
@@ -87,7 +87,7 @@
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the mmu in a quick and dirty way.
+ * moment this is only initializes the mmu in a quick and dirty way.
******************************************************************************/
void bl31_plat_arch_setup(void)
{
diff --git a/plat/rockchip/common/drivers/pmu/pmu_com.h b/plat/rockchip/common/drivers/pmu/pmu_com.h
index 5359f73..022bb02 100644
--- a/plat/rockchip/common/drivers/pmu/pmu_com.h
+++ b/plat/rockchip/common/drivers/pmu/pmu_com.h
@@ -90,7 +90,7 @@
/*
* wfe/wfi tracking not possible, hopefully the host
- * was sucessful in enabling wfe/wfi.
+ * was successful in enabling wfe/wfi.
* We'll give a bit of additional time, like the kernel does.
*/
if ((cluster_id && clstb_cpu_wfe < 0) ||
diff --git a/plat/rockchip/common/sp_min_plat_setup.c b/plat/rockchip/common/sp_min_plat_setup.c
index 0237b16..8fb3f8e 100644
--- a/plat/rockchip/common/sp_min_plat_setup.c
+++ b/plat/rockchip/common/sp_min_plat_setup.c
@@ -82,7 +82,7 @@
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the mmu in a quick and dirty way.
+ * moment this is only initializes the mmu in a quick and dirty way.
******************************************************************************/
void sp_min_plat_arch_setup(void)
{
diff --git a/plat/rockchip/rk3288/drivers/pmu/pmu.c b/plat/rockchip/rk3288/drivers/pmu/pmu.c
index d6d7098..085976c 100644
--- a/plat/rockchip/rk3288/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3288/drivers/pmu/pmu.c
@@ -288,7 +288,7 @@
/*
* We communicate with the bootrom to active the cpus other
* than cpu0, after a blob of initialize code, they will
- * stay at wfe state, once they are actived, they will check
+ * stay at wfe state, once they are activated, they will check
* the mailbox:
* sram_base_addr + 4: 0xdeadbeaf
* sram_base_addr + 8: start address for pc
diff --git a/plat/rockchip/rk3288/drivers/soc/soc.c b/plat/rockchip/rk3288/drivers/soc/soc.c
index 36f410b..2316fbe 100644
--- a/plat/rockchip/rk3288/drivers/soc/soc.c
+++ b/plat/rockchip/rk3288/drivers/soc/soc.c
@@ -216,7 +216,7 @@
/*
* Maybe the HW needs some times to reset the system,
- * so we do not hope the core to excute valid codes.
+ * so we do not hope the core to execute valid codes.
*/
while (1)
;
diff --git a/plat/rockchip/rk3328/drivers/pmu/pmu.c b/plat/rockchip/rk3328/drivers/pmu/pmu.c
index a17fef9..597db97 100644
--- a/plat/rockchip/rk3328/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3328/drivers/pmu/pmu.c
@@ -202,7 +202,7 @@
dsb();
/*
* Maybe the HW needs some times to reset the system,
- * so we do not hope the core to excute valid codes.
+ * so we do not hope the core to execute valid codes.
*/
while (1)
;
@@ -210,7 +210,7 @@
/*
* For PMIC RK805, its sleep pin is connect with gpio2_d2 from rk3328.
- * If the PMIC is configed for responding the sleep pin to power off it,
+ * If the PMIC is configured for responding the sleep pin to power off it,
* once the pin is output high, it will get the pmic power off.
*/
void __dead2 rockchip_soc_system_off(void)
@@ -462,7 +462,7 @@
/*
* For PMIC RK805, its sleep pin is connect with gpio2_d2 from rk3328.
- * If the PMIC is configed for responding the sleep pin
+ * If the PMIC is configured for responding the sleep pin
* to get it into sleep mode,
* once the pin is output high, it will get the pmic into sleep mode.
*/
diff --git a/plat/rockchip/rk3328/drivers/soc/soc.h b/plat/rockchip/rk3328/drivers/soc/soc.h
index e8cbc09..e081f71 100644
--- a/plat/rockchip/rk3328/drivers/soc/soc.h
+++ b/plat/rockchip/rk3328/drivers/soc/soc.h
@@ -27,7 +27,7 @@
DPLL_ID,
CPLL_ID,
GPLL_ID,
- REVERVE,
+ RESERVE,
NPLL_ID,
MAX_PLL,
};
diff --git a/plat/rockchip/rk3368/drivers/soc/soc.c b/plat/rockchip/rk3368/drivers/soc/soc.c
index 7d51bb8..9bb237f 100644
--- a/plat/rockchip/rk3368/drivers/soc/soc.c
+++ b/plat/rockchip/rk3368/drivers/soc/soc.c
@@ -202,7 +202,7 @@
/*
* Maybe the HW needs some times to reset the system,
- * so we do not hope the core to excute valid codes.
+ * so we do not hope the core to execute valid codes.
*/
while (1)
;
diff --git a/plat/rockchip/rk3399/drivers/dram/dfs.c b/plat/rockchip/rk3399/drivers/dram/dfs.c
index 816372b..11b0373 100644
--- a/plat/rockchip/rk3399/drivers/dram/dfs.c
+++ b/plat/rockchip/rk3399/drivers/dram/dfs.c
@@ -1696,7 +1696,7 @@
pll_cnt = ARRAY_SIZE(dpll_rates_table);
- /* Assumming rate_table is in descending order */
+ /* Assuming rate_table is in descending order */
for (i = 0; i < pll_cnt; i++) {
if (mhz >= dpll_rates_table[i].mhz)
break;
diff --git a/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.h b/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.h
index 9cda22c..102ba78 100644
--- a/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.h
+++ b/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.h
@@ -103,7 +103,7 @@
uint32_t tcksre;
uint32_t tcksrx;
uint32_t tdpd;
- /* mode regiter timing */
+ /* mode register timing */
uint32_t tmod;
uint32_t tmrd;
uint32_t tmrr;
diff --git a/plat/rockchip/rk3399/drivers/dram/suspend.c b/plat/rockchip/rk3399/drivers/dram/suspend.c
index a8b1c32..caa784c 100644
--- a/plat/rockchip/rk3399/drivers/dram/suspend.c
+++ b/plat/rockchip/rk3399/drivers/dram/suspend.c
@@ -561,7 +561,7 @@
ch_count = sdram_params->num_channels;
- /* LPDDR4 f2 cann't do training, all training will fail */
+ /* LPDDR4 f2 can't do training, all training will fail */
for (ch = 0; ch < ch_count; ch++) {
/*
* Without this disabled for LPDDR4 we end up writing 0's
diff --git a/plat/rockchip/rk3399/drivers/gpio/rk3399_gpio.c b/plat/rockchip/rk3399/drivers/gpio/rk3399_gpio.c
index 724968f..96b4753 100644
--- a/plat/rockchip/rk3399/drivers/gpio/rk3399_gpio.c
+++ b/plat/rockchip/rk3399/drivers/gpio/rk3399_gpio.c
@@ -376,7 +376,7 @@
mmio_write_32(base + SWPORTA_DDR, save->swporta_ddr);
mmio_write_32(base + INTEN, save->inten);
mmio_write_32(base + INTMASK, save->intmask);
- mmio_write_32(base + INTTYPE_LEVEL, save->inttype_level),
+ mmio_write_32(base + INTTYPE_LEVEL, save->inttype_level);
mmio_write_32(base + INT_POLARITY, save->int_polarity);
mmio_write_32(base + DEBOUNCE, save->debounce);
mmio_write_32(base + LS_SYNC, save->ls_sync);
diff --git a/plat/rockchip/rk3399/drivers/m0/src/suspend.c b/plat/rockchip/rk3399/drivers/m0/src/suspend.c
index 9ad2fa2..8a0ea32 100644
--- a/plat/rockchip/rk3399/drivers/m0/src/suspend.c
+++ b/plat/rockchip/rk3399/drivers/m0/src/suspend.c
@@ -30,7 +30,7 @@
}
/*
- * FSM power secquence is .. -> ST_INPUT_CLAMP(step.17) -> .. ->
+ * FSM power sequence is .. -> ST_INPUT_CLAMP(step.17) -> .. ->
* ST_WAKEUP_RESET -> ST_EXT_PWRUP-> ST_RELEASE_CLAMP ->
* ST_24M_OSC_EN -> .. -> ST_WAKEUP_RESET_CLR(step.26) -> ..,
* INPUT_CLAMP and WAKEUP_RESET will hold the SOC not affect by
diff --git a/plat/rockchip/rk3399/drivers/secure/secure.h b/plat/rockchip/rk3399/drivers/secure/secure.h
index e31c999..79997b2 100644
--- a/plat/rockchip/rk3399/drivers/secure/secure.h
+++ b/plat/rockchip/rk3399/drivers/secure/secure.h
@@ -32,7 +32,7 @@
/* security config pmu slave ip */
/* All of slaves is ns */
#define SGRF_PMU_SLV_S_NS BIT_WITH_WMSK(0)
-/* slaves secure attr is configed */
+/* slaves secure attr is configured */
#define SGRF_PMU_SLV_S_CFGED WMSK_BIT(0)
#define SGRF_PMU_SLV_CRYPTO1_NS WMSK_BIT(1)
diff --git a/plat/rockchip/rk3399/drivers/soc/soc.c b/plat/rockchip/rk3399/drivers/soc/soc.c
index 98b5ad6..e2b2934 100644
--- a/plat/rockchip/rk3399/drivers/soc/soc.c
+++ b/plat/rockchip/rk3399/drivers/soc/soc.c
@@ -343,7 +343,7 @@
/*
* Maybe the HW needs some times to reset the system,
- * so we do not hope the core to excute valid codes.
+ * so we do not hope the core to execute valid codes.
*/
while (1)
;
diff --git a/plat/rpi/rpi4/rpi4_pci_svc.c b/plat/rpi/rpi4/rpi4_pci_svc.c
index 7d1ca5c..e4ef5c1 100644
--- a/plat/rpi/rpi4/rpi4_pci_svc.c
+++ b/plat/rpi/rpi4/rpi4_pci_svc.c
@@ -11,7 +11,7 @@
* it. Given that it's not ECAM compliant yet reasonably simple, it makes for
* an excellent example of the PCI SMCCC interface.
*
- * The PCI SMCCC interface is described in DEN0115 availabe from:
+ * The PCI SMCCC interface is described in DEN0115 available from:
* https://developer.arm.com/documentation/den0115/latest
*/
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index 1d93983..55423ae 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -73,6 +73,9 @@
endif
endif
+PKA_USE_NIST_P256 ?= 0
+PKA_USE_BRAINPOOL_P256T1 ?= 0
+
ifeq ($(AARCH32_SP),sp_min)
# Disable Neon support: sp_min runtime may conflict with non-secure world
TF_CFLAGS += -mfloat-abi=soft
@@ -158,7 +161,6 @@
$(sort \
PKA_USE_BRAINPOOL_P256T1 \
PKA_USE_NIST_P256 \
- PLAT_TBBR_IMG_DEF \
STM32MP_CRYPTO_ROM_LIB \
STM32MP_DDR_32BIT_INTERFACE \
STM32MP_DDR_DUAL_AXI_PORT \
diff --git a/plat/st/stm32mp1/stm32mp1_pm.c b/plat/st/stm32mp1/stm32mp1_pm.c
index 7439381..8e1c1cf 100644
--- a/plat/st/stm32mp1/stm32mp1_pm.c
+++ b/plat/st/stm32mp1/stm32mp1_pm.c
@@ -42,7 +42,7 @@
while (interrupt == GIC_SPURIOUS_INTERRUPT) {
wfi();
- /* Acknoledge IT */
+ /* Acknowledge IT */
interrupt = gicv2_acknowledge_interrupt();
/* If Interrupt == 1022 it will be acknowledged by non secure */
if ((interrupt != PENDING_G1_INTID) &&
diff --git a/plat/xilinx/common/include/plat_startup.h b/plat/xilinx/common/include/plat_startup.h
index ae9d52a..ed3946f 100644
--- a/plat/xilinx/common/include/plat_startup.h
+++ b/plat/xilinx/common/include/plat_startup.h
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.
- * Copyright (C) 2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/xilinx/common/plat_startup.c b/plat/xilinx/common/plat_startup.c
index 6a83e9e..539aba2 100644
--- a/plat/xilinx/common/plat_startup.c
+++ b/plat/xilinx/common/plat_startup.c
@@ -135,7 +135,7 @@
* @bl33: BL33 image info structure
* atf_handoff_addr: ATF handoff address
*
- * Process the handoff paramters from the FSBL and populate the BL32 and BL33
+ * Process the handoff parameters from the FSBL and populate the BL32 and BL33
* image info structures accordingly.
*
* Return: Return the status of the handoff. The value will be from the
diff --git a/plat/xilinx/versal/aarch64/versal_common.c b/plat/xilinx/versal/aarch64/versal_common.c
index 0c8ee1e..88da279 100644
--- a/plat/xilinx/versal/aarch64/versal_common.c
+++ b/plat/xilinx/versal/aarch64/versal_common.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
- * Copyright (C) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/xilinx/versal_net/aarch64/versal_net_common.c b/plat/xilinx/versal_net/aarch64/versal_net_common.c
index 253c382..1a57330 100644
--- a/plat/xilinx/versal_net/aarch64/versal_net_common.c
+++ b/plat/xilinx/versal_net/aarch64/versal_net_common.c
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
- * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/xilinx/versal_net/aarch64/versal_net_helpers.S b/plat/xilinx/versal_net/aarch64/versal_net_helpers.S
index bbd937b..e1e2317 100644
--- a/plat/xilinx/versal_net/aarch64/versal_net_helpers.S
+++ b/plat/xilinx/versal_net/aarch64/versal_net_helpers.S
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
- * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/xilinx/versal_net/bl31_versal_net_setup.c b/plat/xilinx/versal_net/bl31_versal_net_setup.c
index 48be081..ae9dfe8 100644
--- a/plat/xilinx/versal_net/bl31_versal_net_setup.c
+++ b/plat/xilinx/versal_net/bl31_versal_net_setup.c
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
- * Copyright (C) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/xilinx/versal_net/include/plat_ipi.h b/plat/xilinx/versal_net/include/plat_ipi.h
index 5ac611c..30c51b5 100644
--- a/plat/xilinx/versal_net/include/plat_ipi.h
+++ b/plat/xilinx/versal_net/include/plat_ipi.h
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2022, Xilinx, Inc. All rights reserved.
- * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/xilinx/versal_net/include/plat_pm_common.h b/plat/xilinx/versal_net/include/plat_pm_common.h
index ad7b40f..6485df7 100644
--- a/plat/xilinx/versal_net/include/plat_pm_common.h
+++ b/plat/xilinx/versal_net/include/plat_pm_common.h
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2022, Xilinx, Inc. All rights reserved.
- * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/xilinx/versal_net/include/versal_net_def.h b/plat/xilinx/versal_net/include/versal_net_def.h
index ec36e55..8fb71f9 100644
--- a/plat/xilinx/versal_net/include/versal_net_def.h
+++ b/plat/xilinx/versal_net/include/versal_net_def.h
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
- * Copyright (C) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/xilinx/versal_net/plat_psci_pm.c b/plat/xilinx/versal_net/plat_psci_pm.c
index 9d401a5..d39fc2e 100644
--- a/plat/xilinx/versal_net/plat_psci_pm.c
+++ b/plat/xilinx/versal_net/plat_psci_pm.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2022, Xilinx, Inc. All rights reserved.
- * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/xilinx/versal_net/plat_topology.c b/plat/xilinx/versal_net/plat_topology.c
index c74faf2..ee756c4 100644
--- a/plat/xilinx/versal_net/plat_topology.c
+++ b/plat/xilinx/versal_net/plat_topology.c
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
- * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/xilinx/versal_net/sip_svc_setup.c b/plat/xilinx/versal_net/sip_svc_setup.c
index cc8306e..f6240f3 100644
--- a/plat/xilinx/versal_net/sip_svc_setup.c
+++ b/plat/xilinx/versal_net/sip_svc_setup.c
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
- * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/xilinx/versal_net/versal_net_gicv3.c b/plat/xilinx/versal_net/versal_net_gicv3.c
index e7d8e75..2fdef12 100644
--- a/plat/xilinx/versal_net/versal_net_gicv3.c
+++ b/plat/xilinx/versal_net/versal_net_gicv3.c
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
- * Copyright (C) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/xilinx/versal_net/versal_net_ipi.c b/plat/xilinx/versal_net/versal_net_ipi.c
index 26ded89..cf897e3 100644
--- a/plat/xilinx/versal_net/versal_net_ipi.c
+++ b/plat/xilinx/versal_net/versal_net_ipi.c
@@ -1,6 +1,6 @@
/*
- * Copyright (C) 2022, Xilinx, Inc. All rights reserved.
- * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
index fb7b009..85e1464 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
@@ -635,7 +635,7 @@
* pm_secure_rsaaes() - Load the secure images.
*
* This function provides access to the xilsecure library to load
- * the authenticated, encrypted, and authenicated/encrypted images.
+ * the authenticated, encrypted, and authenticated/encrypted images.
*
* address_low: lower 32-bit Linear memory space address
*
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
index c0c5d14..7b15443 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
@@ -99,7 +99,7 @@
* for warm restart.
*
* In presence of non-secure software layers (EL1/2) sets the interrupt
- * at registered entrance in GIC and informs that PMU responsed or demands
+ * at registered entrance in GIC and informs that PMU responded or demands
* action.
*/
static uint64_t ttc_fiq_handler(uint32_t id, uint32_t flags, void *handle,
diff --git a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
index b51369a..eaecb89 100644
--- a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
+++ b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
@@ -43,7 +43,7 @@
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
- * moment this is only intializes the MMU
+ * moment this is only initializes the MMU
******************************************************************************/
void tsp_plat_arch_setup(void)
{
diff --git a/pyproject.toml b/pyproject.toml
index b99f777..437290a 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -1,6 +1,6 @@
[tool.poetry]
name = "trusted-firmware-a"
-version = "2.8.0"
+version = "2.9.0"
description = "Trusted Firmware-A (TF-A) Python dependencies."
authors = ["Arm Ltd."]
license = "BSD-3-Clause"
diff --git a/services/spd/opteed/opteed.mk b/services/spd/opteed/opteed.mk
index 477b45d..f394744 100644
--- a/services/spd/opteed/opteed.mk
+++ b/services/spd/opteed/opteed.mk
@@ -31,4 +31,5 @@
platform")
$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
$(eval $(call add_define,OPTEE_ALLOW_SMC_LOAD))
+include lib/libfdt/libfdt.mk
endif
diff --git a/services/spd/opteed/opteed_main.c b/services/spd/opteed/opteed_main.c
index f069775..4d055db 100644
--- a/services/spd/opteed/opteed_main.c
+++ b/services/spd/opteed/opteed_main.c
@@ -24,9 +24,13 @@
#include <common/bl_common.h>
#include <common/debug.h>
#include <common/runtime_svc.h>
+#include <lib/coreboot.h>
#include <lib/el3_runtime/context_mgmt.h>
#include <lib/optee_utils.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
+#if OPTEE_ALLOW_SMC_LOAD
+#include <libfdt.h>
+#endif /* OPTEE_ALLOW_SMC_LOAD */
#include <plat/common/platform.h>
#include <tools_share/uuid.h>
@@ -51,6 +55,10 @@
DEFINE_SVC_UUID2(optee_image_load_uuid,
0xb1eafba3, 0x5d31, 0x4612, 0xb9, 0x06,
0xc4, 0xc7, 0xa4, 0xbe, 0x3c, 0xc0);
+
+#define OPTEED_FDT_SIZE 256
+static uint8_t fdt_buf[OPTEED_FDT_SIZE] __aligned(CACHE_WRITEBACK_GRANULE);
+
#else
static int32_t opteed_init(void);
#endif
@@ -209,6 +217,91 @@
#endif /* !OPTEE_ALLOW_SMC_LOAD */
#if OPTEE_ALLOW_SMC_LOAD
+#if COREBOOT
+/*
+ * Adds a firmware/coreboot node with the coreboot table information to a device
+ * tree. Returns zero on success or if there is no coreboot table information;
+ * failure code otherwise.
+ */
+static int add_coreboot_node(void *fdt)
+{
+ int ret;
+ uint64_t coreboot_table_addr;
+ uint32_t coreboot_table_size;
+ struct {
+ uint64_t addr;
+ uint32_t size;
+ } reg_node;
+ coreboot_get_table_location(&coreboot_table_addr, &coreboot_table_size);
+ if (!coreboot_table_addr || !coreboot_table_size) {
+ WARN("Unable to get coreboot table location for device tree");
+ return 0;
+ }
+ ret = fdt_begin_node(fdt, "firmware");
+ if (ret)
+ return ret;
+
+ ret = fdt_property(fdt, "ranges", NULL, 0);
+ if (ret)
+ return ret;
+
+ ret = fdt_begin_node(fdt, "coreboot");
+ if (ret)
+ return ret;
+
+ ret = fdt_property_string(fdt, "compatible", "coreboot");
+ if (ret)
+ return ret;
+
+ reg_node.addr = cpu_to_fdt64(coreboot_table_addr);
+ reg_node.size = cpu_to_fdt32(coreboot_table_size);
+ ret = fdt_property(fdt, "reg", ®_node,
+ sizeof(uint64_t) + sizeof(uint32_t));
+ if (ret)
+ return ret;
+
+ ret = fdt_end_node(fdt);
+ if (ret)
+ return ret;
+
+ return fdt_end_node(fdt);
+}
+#endif /* COREBOOT */
+
+/*
+ * Creates a device tree for passing into OP-TEE. Currently is populated with
+ * the coreboot table address.
+ * Returns 0 on success, error code otherwise.
+ */
+static int create_opteed_dt(void)
+{
+ int ret;
+
+ ret = fdt_create(fdt_buf, OPTEED_FDT_SIZE);
+ if (ret)
+ return ret;
+
+ ret = fdt_finish_reservemap(fdt_buf);
+ if (ret)
+ return ret;
+
+ ret = fdt_begin_node(fdt_buf, "");
+ if (ret)
+ return ret;
+
+#if COREBOOT
+ ret = add_coreboot_node(fdt_buf);
+ if (ret)
+ return ret;
+#endif /* COREBOOT */
+
+ ret = fdt_end_node(fdt_buf);
+ if (ret)
+ return ret;
+
+ return fdt_finish(fdt_buf);
+}
+
/*******************************************************************************
* This function is responsible for handling the SMC that loads the OP-TEE
* binary image via a non-secure SMC call. It takes the size and physical
@@ -232,6 +325,7 @@
uint64_t target_size;
entry_point_info_t optee_ep_info;
uint32_t linear_id = plat_my_core_pos();
+ uint64_t dt_addr = 0;
mapped_data_pa = page_align(data_pa, DOWN);
mapped_data_va = mapped_data_pa;
@@ -292,12 +386,20 @@
/* Save the non-secure state */
cm_el1_sysregs_context_save(NON_SECURE);
+ rc = create_opteed_dt();
+ if (rc) {
+ ERROR("Failed device tree creation %d\n", rc);
+ return rc;
+ }
+ dt_addr = (uint64_t)fdt_buf;
+ flush_dcache_range(dt_addr, OPTEED_FDT_SIZE);
+
opteed_init_optee_ep_state(&optee_ep_info,
opteed_rw,
image_pa,
0,
0,
- 0,
+ dt_addr,
&opteed_sp_context[linear_id]);
if (opteed_init_with_entry_point(&optee_ep_info) == 0) {
rc = -EFAULT;
diff --git a/services/std_svc/drtm/drtm_measurements.c b/services/std_svc/drtm/drtm_measurements.c
index a8f2b32..8d514b7 100644
--- a/services/std_svc/drtm/drtm_measurements.c
+++ b/services/std_svc/drtm/drtm_measurements.c
@@ -47,7 +47,7 @@
metadata.pcr = pcr;
/*
- * Measure the payloads requested by D-CRTM and DCE commponents
+ * Measure the payloads requested by D-CRTM and DCE components
* Hash algorithm decided by the Event Log driver at build-time
*/
rc = event_log_measure(data_base, data_size, hash_data);
diff --git a/services/std_svc/errata_abi/cpu_errata_info.h b/services/std_svc/errata_abi/cpu_errata_info.h
new file mode 100644
index 0000000..671a694
--- /dev/null
+++ b/services/std_svc/errata_abi/cpu_errata_info.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ERRATA_CPUSPEC_H
+#define ERRATA_CPUSPEC_H
+
+#include <stdint.h>
+#include <arch_helpers.h>
+
+#if __aarch64__
+#include <cortex_a35.h>
+#include <cortex_a510.h>
+#include <cortex_a53.h>
+#include <cortex_a57.h>
+#include <cortex_a55.h>
+#include <cortex_a710.h>
+#include <cortex_a72.h>
+#include <cortex_a73.h>
+#include <cortex_a75.h>
+#include <cortex_a76.h>
+#include <cortex_a77.h>
+#include <cortex_a78.h>
+#include <cortex_a78_ae.h>
+#include <cortex_a78c.h>
+#include <cortex_makalu.h>
+#include <cortex_x1.h>
+#include <cortex_x2.h>
+#include <neoverse_n1.h>
+#include <neoverse_n2.h>
+#include <neoverse_v1.h>
+#include <neoverse_v2.h>
+#else
+#include <cortex_a15.h>
+#include <cortex_a17.h>
+#include <cortex_a57.h>
+#include <cortex_a9.h>
+#endif
+
+#define MAX_ERRATA_ENTRIES 16
+
+#define ERRATA_LIST_END (MAX_ERRATA_ENTRIES - 1)
+
+/* Default values for unused memory in the array */
+#define UNDEF_ERRATA {UINT_MAX, UCHAR_MAX, UCHAR_MAX, false, false}
+
+#define EXTRACT_PARTNUM(x) ((x >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
+
+#define RXPX_RANGE(x, y, z) (((x >= y) && (x <= z)) ? true : false)
+
+/*
+ * CPU specific values for errata handling
+ */
+struct em_cpu{
+ unsigned int em_errata_id;
+ unsigned char em_rxpx_lo; /* lowest revision of errata applicable for the cpu */
+ unsigned char em_rxpx_hi; /* highest revision of errata applicable for the cpu */
+ bool errata_enabled; /* indicate if errata enabled */
+ /* flag to indicate if errata query is based out of non-arm interconnect */
+ bool non_arm_interconnect;
+};
+
+struct em_cpu_list{
+ /* field to hold cpu specific part number defined in midr reg */
+ unsigned long cpu_partnumber;
+ struct em_cpu cpu_errata_list[MAX_ERRATA_ENTRIES];
+};
+
+int32_t verify_errata_implemented(uint32_t errata_id, uint32_t forward_flag);
+#endif /* ERRATA_CPUSPEC_H */
diff --git a/services/std_svc/errata_abi/errata_abi_main.c b/services/std_svc/errata_abi/errata_abi_main.c
new file mode 100644
index 0000000..bf9409d
--- /dev/null
+++ b/services/std_svc/errata_abi/errata_abi_main.c
@@ -0,0 +1,570 @@
+/*
+ * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include "cpu_errata_info.h"
+#include <lib/smccc.h>
+#include <lib/utils_def.h>
+#include <services/errata_abi_svc.h>
+#include <smccc_helpers.h>
+
+/*
+ * Global pointer that points to the specific
+ * structure based on the MIDR part number
+ */
+struct em_cpu_list *cpu_ptr;
+
+extern uint8_t cpu_get_rev_var(void);
+
+/* Structure array that holds CPU specific errata information */
+struct em_cpu_list cpu_list[] = {
+#if CORTEX_A9_H_INC
+{
+ .cpu_partnumber = CORTEX_A9_MIDR,
+ .cpu_errata_list = {
+ [0] = {794073, 0x00, 0xFF, ERRATA_A9_794073},
+ [1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ }
+},
+#endif /* CORTEX_A9_H_INC */
+
+#if CORTEX_A15_H_INC
+{
+ .cpu_partnumber = CORTEX_A15_MIDR,
+ .cpu_errata_list = {
+ [0] = {816470, 0x30, 0xFF, ERRATA_A15_816470},
+ [1] = {827671, 0x30, 0xFF, ERRATA_A15_827671},
+ [2 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ }
+},
+#endif /* CORTEX_A15_H_INC */
+
+#if CORTEX_A17_H_INC
+{
+ .cpu_partnumber = CORTEX_A17_MIDR,
+ .cpu_errata_list = {
+ [0] = {852421, 0x00, 0x12, ERRATA_A17_852421},
+ [1] = {852423, 0x00, 0x12, ERRATA_A17_852423},
+ [2 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ }
+},
+#endif /* CORTEX_A17_H_INC */
+
+#if CORTEX_A35_H_INC
+{
+ .cpu_partnumber = CORTEX_A35_MIDR,
+ .cpu_errata_list = {
+ [0] = {855472, 0x00, 0x00, ERRATA_A35_855472},
+ [1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ }
+},
+#endif /* CORTEX_A35_H_INC */
+
+#if CORTEX_A53_H_INC
+{
+ .cpu_partnumber = CORTEX_A53_MIDR,
+ .cpu_errata_list = {
+ [0] = {819472, 0x00, 0x01, ERRATA_A53_819472},
+ [1] = {824069, 0x00, 0x02, ERRATA_A53_824069},
+ [2] = {826319, 0x00, 0x02, ERRATA_A53_826319},
+ [3] = {827319, 0x00, 0x02, ERRATA_A53_827319},
+ [4] = {835769, 0x00, 0x04, ERRATA_A53_835769},
+ [5] = {836870, 0x00, 0x03, ERRATA_A53_836870},
+ [6] = {843419, 0x00, 0x04, ERRATA_A53_843419},
+ [7] = {855873, 0x03, 0xFF, ERRATA_A53_855873},
+ [8] = {1530924, 0x00, 0xFF, ERRATA_A53_1530924},
+ [9 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ }
+},
+#endif /* CORTEX_A53_H_INC */
+
+#if CORTEX_A55_H_INC
+{
+ .cpu_partnumber = CORTEX_A55_MIDR,
+ .cpu_errata_list = {
+ [0] = {768277, 0x00, 0x00, ERRATA_A55_768277},
+ [1] = {778703, 0x00, 0x00, ERRATA_A55_778703},
+ [2] = {798797, 0x00, 0x00, ERRATA_A55_798797},
+ [3] = {846532, 0x00, 0x01, ERRATA_A55_846532},
+ [4] = {903758, 0x00, 0x01, ERRATA_A55_903758},
+ [5] = {1221012, 0x00, 0x10, ERRATA_A55_1221012},
+ [6] = {1530923, 0x00, 0xFF, ERRATA_A55_1530923},
+ [7 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ }
+},
+#endif /* CORTEX_A55_H_INC */
+
+#if CORTEX_A57_H_INC
+{
+ .cpu_partnumber = CORTEX_A57_MIDR,
+ .cpu_errata_list = {
+ [0] = {806969, 0x00, 0x00, ERRATA_A57_806969},
+ [1] = {813419, 0x00, 0x00, ERRATA_A57_813419},
+ [2] = {813420, 0x00, 0x00, ERRATA_A57_813420},
+ [3] = {814670, 0x00, 0x00, ERRATA_A57_814670},
+ [4] = {817169, 0x00, 0x01, ERRATA_A57_817169},
+ [5] = {826974, 0x00, 0x11, ERRATA_A57_826974},
+ [6] = {826977, 0x00, 0x11, ERRATA_A57_826977},
+ [7] = {828024, 0x00, 0x11, ERRATA_A57_828024},
+ [8] = {829520, 0x00, 0x12, ERRATA_A57_829520},
+ [9] = {833471, 0x00, 0x12, ERRATA_A57_833471},
+ [10] = {859972, 0x00, 0x13, ERRATA_A57_859972},
+ [11] = {1319537, 0x00, 0xFF, ERRATA_A57_1319537},
+ [12 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ }
+},
+#endif /* CORTEX_A57_H_INC */
+
+#if CORTEX_A72_H_INC
+{
+ .cpu_partnumber = CORTEX_A72_MIDR,
+ .cpu_errata_list = {
+ [0] = {859971, 0x00, 0x03, ERRATA_A72_859971},
+ [1] = {1319367, 0x00, 0xFF, ERRATA_A72_1319367},
+ [2 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ }
+},
+#endif /* CORTEX_A72_H_INC */
+
+#if CORTEX_A73_H_INC
+{
+ .cpu_partnumber = CORTEX_A73_MIDR,
+ .cpu_errata_list = {
+ [0] = {852427, 0x00, 0x00, ERRATA_A73_852427},
+ [1] = {855423, 0x00, 0x01, ERRATA_A73_855423},
+ [2 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ }
+},
+#endif /* CORTEX_A73_H_INC */
+
+#if CORTEX_A75_H_INC
+{
+ .cpu_partnumber = CORTEX_A75_MIDR,
+ .cpu_errata_list = {
+ [0] = {764081, 0x00, 0x00, ERRATA_A75_764081},
+ [1] = {790748, 0x00, 0x00, ERRATA_A75_790748},
+ [2 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ }
+},
+#endif /* CORTEX_A75_H_INC */
+
+#if CORTEX_A76_H_INC
+{
+ .cpu_partnumber = CORTEX_A76_MIDR,
+ .cpu_errata_list = {
+ [0] = {1073348, 0x00, 0x10, ERRATA_A76_1073348},
+ [1] = {1130799, 0x00, 0x20, ERRATA_A76_1130799},
+ [2] = {1165522, 0x00, 0xFF, ERRATA_A76_1165522},
+ [3] = {1220197, 0x00, 0x20, ERRATA_A76_1220197},
+ [4] = {1257314, 0x00, 0x30, ERRATA_A76_1257314},
+ [5] = {1262606, 0x00, 0x30, ERRATA_A76_1262606},
+ [6] = {1262888, 0x00, 0x30, ERRATA_A76_1262888},
+ [7] = {1275112, 0x00, 0x30, ERRATA_A76_1275112},
+ [8] = {1791580, 0x00, 0x40, ERRATA_A76_1791580},
+ [9] = {1868343, 0x00, 0x40, ERRATA_A76_1868343},
+ [10] = {1946160, 0x30, 0x41, ERRATA_A76_1946160},
+ [11 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ }
+},
+#endif /* CORTEX_A76_H_INC */
+
+#if CORTEX_A77_H_INC
+{
+ .cpu_partnumber = CORTEX_A77_MIDR,
+ .cpu_errata_list = {
+ [0] = {1508412, 0x00, 0x10, ERRATA_A77_1508412},
+ [1] = {1791578, 0x00, 0x11, ERRATA_A77_1791578},
+ [2] = {1800714, 0x00, 0x11, ERRATA_A77_1800714},
+ [3] = {1925769, 0x00, 0x11, ERRATA_A77_1925769},
+ [4] = {1946167, 0x00, 0x11, ERRATA_A77_1946167},
+ [5] = {2356587, 0x00, 0x11, ERRATA_A77_2356587},
+ [6] = {2743100, 0x00, 0x11, ERRATA_A77_2743100},
+ [7 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ }
+},
+#endif /* CORTEX_A77_H_INC */
+
+#if CORTEX_A78_H_INC
+{
+ .cpu_partnumber = CORTEX_A78_MIDR,
+ .cpu_errata_list = {
+ [0] = {1688305, 0x00, 0x10, ERRATA_A78_1688305},
+ [1] = {1821534, 0x00, 0x10, ERRATA_A78_1821534},
+ [2] = {1941498, 0x00, 0x11, ERRATA_A78_1941498},
+ [3] = {1951500, 0x10, 0x11, ERRATA_A78_1951500},
+ [4] = {1952683, 0x00, 0x00, ERRATA_A78_1952683},
+ [5] = {2132060, 0x00, 0x12, ERRATA_A78_2132060},
+ [6] = {2242635, 0x10, 0x12, ERRATA_A78_2242635},
+ [7] = {2376745, 0x00, 0x12, ERRATA_A78_2376745},
+ [8] = {2395406, 0x00, 0x12, ERRATA_A78_2395406},
+ [9] = {2712571, 0x00, 0x12, ERRATA_A78_2712571, \
+ ERRATA_NON_ARM_INTERCONNECT},
+ [10] = {2742426, 0x00, 0x12, ERRATA_A78_2742426},
+ [11] = {2772019, 0x00, 0x12, ERRATA_A78_2772019},
+ [12] = {2779479, 0x00, 0x12, ERRATA_A78_2779479},
+ [13 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ }
+},
+#endif /* CORTEX_A78_H_INC */
+
+#if CORTEX_A78_AE_H_INC
+{
+ .cpu_partnumber = CORTEX_A78_AE_MIDR,
+ .cpu_errata_list = {
+ [0] = {1941500, 0x00, 0x01, ERRATA_A78_AE_1941500},
+ [1] = {1951502, 0x00, 0x01, ERRATA_A78_AE_1951502},
+ [2] = {2376748, 0x00, 0x01, ERRATA_A78_AE_2376748},
+ [3] = {2395408, 0x00, 0x01, ERRATA_A78_AE_2395408},
+ [4] = {2712574, 0x00, 0x02, ERRATA_A78_AE_2712574, \
+ ERRATA_NON_ARM_INTERCONNECT},
+ [5 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ }
+},
+#endif /* CORTEX_A78_AE_H_INC */
+
+#if CORTEX_A78C_H_INC
+{
+ .cpu_partnumber = CORTEX_A78C_MIDR,
+ .cpu_errata_list = {
+ [0] = {2132064, 0x01, 0x02, ERRATA_A78C_2132064},
+ [1] = {2242638, 0x01, 0x02, ERRATA_A78C_2242638},
+ [2] = {2376749, 0x01, 0x02, ERRATA_A78C_2376749},
+ [3] = {2395411, 0x01, 0x02, ERRATA_A78C_2395411},
+ [4] = {2712575, 0x01, 0x02, ERRATA_A78C_2712575, \
+ ERRATA_NON_ARM_INTERCONNECT},
+ [5] = {2772121, 0x00, 0x02, ERRATA_A78C_2772121},
+ [6] = {2779484, 0x01, 0x02, ERRATA_A78C_2779484},
+ [7 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ }
+},
+#endif /* CORTEX_A78C_H_INC */
+
+#if CORTEX_X1_H_INC
+{
+ .cpu_partnumber = CORTEX_X1_MIDR,
+ .cpu_errata_list = {
+ [0] = {1688305, 0x00, 0x10, ERRATA_X1_1688305},
+ [1] = {1821534, 0x00, 0x10, ERRATA_X1_1821534},
+ [2] = {1827429, 0x00, 0x10, ERRATA_X1_1827429},
+ [3 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ }
+},
+#endif /* CORTEX_X1_H_INC */
+
+#if NEOVERSE_N1_H_INC
+{
+ .cpu_partnumber = NEOVERSE_N1_MIDR,
+ .cpu_errata_list = {
+ [0] = {1073348, 0x00, 0x10, ERRATA_N1_1073348},
+ [1] = {1130799, 0x00, 0x20, ERRATA_N1_1130799},
+ [2] = {1165347, 0x00, 0x20, ERRATA_N1_1165347},
+ [3] = {1207823, 0x00, 0x20, ERRATA_N1_1207823},
+ [4] = {1220197, 0x00, 0x20, ERRATA_N1_1220197},
+ [5] = {1257314, 0x00, 0x30, ERRATA_N1_1257314},
+ [6] = {1262606, 0x00, 0x30, ERRATA_N1_1262606},
+ [7] = {1262888, 0x00, 0x30, ERRATA_N1_1262888},
+ [8] = {1275112, 0x00, 0x30, ERRATA_N1_1275112},
+ [9] = {1315703, 0x00, 0x30, ERRATA_N1_1315703},
+ [10] = {1542419, 0x30, 0x40, ERRATA_N1_1542419},
+ [11] = {1868343, 0x00, 0x40, ERRATA_N1_1868343},
+ [12] = {1946160, 0x30, 0x41, ERRATA_N1_1946160},
+ [13] = {2743102, 0x00, 0x41, ERRATA_N1_2743102},
+ [14 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ }
+},
+#endif /* NEOVERSE_N1_H_INC */
+
+#if NEOVERSE_V1_H_INC
+{
+ .cpu_partnumber = NEOVERSE_V1_MIDR,
+ .cpu_errata_list = {
+ [0] = {1618635, 0x00, 0x0F, ERRATA_V1_1618635},
+ [1] = {1774420, 0x00, 0x10, ERRATA_V1_1774420},
+ [2] = {1791573, 0x00, 0x10, ERRATA_V1_1791573},
+ [3] = {1852267, 0x00, 0x10, ERRATA_V1_1852267},
+ [4] = {1925756, 0x00, 0x11, ERRATA_V1_1925756},
+ [5] = {1940577, 0x10, 0x11, ERRATA_V1_1940577},
+ [6] = {1966096, 0x10, 0x11, ERRATA_V1_1966096},
+ [7] = {2108267, 0x00, 0x11, ERRATA_V1_2108267},
+ [8] = {2139242, 0x00, 0x11, ERRATA_V1_2139242},
+ [9] = {2216392, 0x10, 0x11, ERRATA_V1_2216392},
+ [10] = {2294912, 0x00, 0x11, ERRATA_V1_2294912},
+ [11] = {2372203, 0x00, 0x11, ERRATA_V1_2372203},
+ [12] = {2701953, 0x00, 0x11, ERRATA_V1_2701953, \
+ ERRATA_NON_ARM_INTERCONNECT},
+ [13] = {2743093, 0x00, 0x12, ERRATA_V1_2743093},
+ [14] = {2779461, 0x00, 0x12, ERRATA_V1_2779461},
+ [15 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ }
+},
+#endif /* NEOVERSE_V1_H_INC */
+
+#if CORTEX_A710_H_INC
+{
+ .cpu_partnumber = CORTEX_A710_MIDR,
+ .cpu_errata_list = {
+ [0] = {1987031, 0x00, 0x20, ERRATA_A710_1987031},
+ [1] = {2008768, 0x00, 0x20, ERRATA_A710_2008768},
+ [2] = {2017096, 0x00, 0x20, ERRATA_A710_2017096},
+ [3] = {2055002, 0x10, 0x20, ERRATA_A710_2055002},
+ [4] = {2058056, 0x00, 0x10, ERRATA_A710_2058056},
+ [5] = {2081180, 0x00, 0x20, ERRATA_A710_2081180},
+ [6] = {2083908, 0x20, 0x20, ERRATA_A710_2083908},
+ [7] = {2136059, 0x00, 0x20, ERRATA_A710_2136059},
+ [8] = {2147715, 0x20, 0x20, ERRATA_A710_2147715},
+ [9] = {2216384, 0x00, 0x20, ERRATA_A710_2216384},
+ [10] = {2267065, 0x00, 0x20, ERRATA_A710_2267065},
+ [11] = {2282622, 0x00, 0x21, ERRATA_A710_2282622},
+ [12] = {2291219, 0x00, 0x20, ERRATA_A710_2291219},
+ [13] = {2371105, 0x00, 0x20, ERRATA_A710_2371105},
+ [14] = {2701952, 0x00, 0x21, ERRATA_A710_2701952, \
+ ERRATA_NON_ARM_INTERCONNECT},
+ [15] = {2768515, 0x00, 0x21, ERRATA_A710_2768515}
+ }
+},
+#endif /* CORTEX_A710_H_INC */
+
+#if NEOVERSE_N2_H_INC
+{
+ .cpu_partnumber = NEOVERSE_N2_MIDR,
+ .cpu_errata_list = {
+ [0] = {2002655, 0x00, 0x00, ERRATA_N2_2002655},
+ [1] = {2025414, 0x00, 0x00, ERRATA_N2_2025414},
+ [2] = {2067956, 0x00, 0x00, ERRATA_N2_2067956},
+ [3] = {2138953, 0x00, 0x00, ERRATA_N2_2138953},
+ [4] = {2138956, 0x00, 0x00, ERRATA_N2_2138956},
+ [5] = {2138958, 0x00, 0x00, ERRATA_N2_2138958},
+ [6] = {2189731, 0x00, 0x00, ERRATA_N2_2189731},
+ [7] = {2242400, 0x00, 0x00, ERRATA_N2_2242400},
+ [8] = {2242415, 0x00, 0x00, ERRATA_N2_2242415},
+ [9] = {2280757, 0x00, 0x00, ERRATA_N2_2280757},
+ [10] = {2326639, 0x00, 0x00, ERRATA_N2_2326639},
+ [11] = {2376738, 0x00, 0x00, ERRATA_N2_2376738},
+ [12] = {2388450, 0x00, 0x00, ERRATA_N2_2388450},
+ [13] = {2728475, 0x00, 0x02, ERRATA_N2_2728475, \
+ ERRATA_NON_ARM_INTERCONNECT},
+ [14] = {2743089, 0x00, 0x02, ERRATA_N2_2743089},
+ [15 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ }
+},
+#endif /* NEOVERSE_N2_H_INC */
+
+#if CORTEX_X2_H_INC
+{
+ .cpu_partnumber = CORTEX_X2_MIDR,
+ .cpu_errata_list = {
+ [0] = {2002765, 0x00, 0x20, ERRATA_X2_2002765},
+ [1] = {2017096, 0x00, 0x20, ERRATA_X2_2017096},
+ [2] = {2058056, 0x00, 0x20, ERRATA_X2_2058056},
+ [3] = {2081180, 0x00, 0x20, ERRATA_X2_2081180},
+ [4] = {2083908, 0x00, 0x20, ERRATA_X2_2083908},
+ [5] = {2147715, 0x20, 0x20, ERRATA_X2_2147715},
+ [6] = {2216384, 0x00, 0x20, ERRATA_X2_2216384},
+ [7] = {2282622, 0x00, 0x21, ERRATA_X2_2282622},
+ [8] = {2371105, 0x00, 0x21, ERRATA_X2_2371105},
+ [9] = {2701952, 0x00, 0x21, ERRATA_X2_2701952, \
+ ERRATA_NON_ARM_INTERCONNECT},
+ [10] = {2768515, 0x00, 0x21, ERRATA_X2_2768515},
+ [11 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ }
+},
+#endif /* CORTEX_X2_H_INC */
+
+#if CORTEX_A510_H_INC
+{
+ .cpu_partnumber = CORTEX_A510_MIDR,
+ .cpu_errata_list = {
+ [0] = {1922240, 0x00, 0x00, ERRATA_A510_1922240},
+ [1] = {2041909, 0x02, 0x02, ERRATA_A510_2041909},
+ [2] = {2042739, 0x00, 0x02, ERRATA_A510_2042739},
+ [3] = {2172148, 0x00, 0x10, ERRATA_A510_2172148},
+ [4] = {2218950, 0x00, 0x10, ERRATA_A510_2218950},
+ [5] = {2250311, 0x00, 0x10, ERRATA_A510_2250311},
+ [6] = {2288014, 0x00, 0x10, ERRATA_A510_2288014},
+ [7] = {2347730, 0x00, 0x11, ERRATA_A510_2347730},
+ [8] = {2371937, 0x00, 0x11, ERRATA_A510_2371937},
+ [9] = {2666669, 0x00, 0x11, ERRATA_A510_2666669},
+ [10] = {2684597, 0x00, 0x12, ERRATA_A510_2684597},
+ [11 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ }
+},
+#endif /* CORTEX_A510_H_INC */
+
+#if NEOVERSE_V2_H_INC
+{
+ .cpu_partnumber = NEOVERSE_V2_MIDR,
+ .cpu_errata_list = {
+ [0] = {2719103, 0x00, 0x01, ERRATA_V2_2719103, \
+ ERRATA_NON_ARM_INTERCONNECT},
+ [1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ }
+},
+#endif /* NEOVERSE_V2_H_INC */
+
+#if CORTEX_A715_H_INC
+{
+ .cpu_partnumber = CORTEX_MAKALU_MIDR,
+ .cpu_errata_list = {
+ [0] = {2701951, 0x00, 0x11, ERRATA_A715_2701951, \
+ ERRATA_NON_ARM_INTERCONNECT},
+ [1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ }
+},
+#endif /* CORTEX_A715_H_INC */
+};
+
+/*
+ * Function to do binary search and check for the specific errata ID
+ * in the array of structures specific to the cpu identified.
+ */
+int32_t binary_search(struct em_cpu_list *ptr, uint32_t erratum_id, uint8_t rxpx_val)
+{
+ int low_index = 0U, mid_index = 0U;
+
+ int high_index = MAX_ERRATA_ENTRIES - 1;
+
+ assert(ptr != NULL);
+
+ /*
+ * Pointer to the errata list of the cpu that matches
+ * extracted partnumber in the cpu list
+ */
+ struct em_cpu *erratum_ptr = NULL;
+
+ while (low_index <= high_index) {
+ mid_index = (low_index + high_index) / 2;
+
+ erratum_ptr = &ptr->cpu_errata_list[mid_index];
+ assert(erratum_ptr != NULL);
+
+ if (erratum_id < erratum_ptr->em_errata_id) {
+ high_index = mid_index - 1;
+ } else if (erratum_id > erratum_ptr->em_errata_id) {
+ low_index = mid_index + 1;
+ } else if (erratum_id == erratum_ptr->em_errata_id) {
+ if (RXPX_RANGE(rxpx_val, erratum_ptr->em_rxpx_lo, \
+ erratum_ptr->em_rxpx_hi)) {
+ if ((erratum_ptr->errata_enabled) && \
+ (!(erratum_ptr->non_arm_interconnect))) {
+ return EM_HIGHER_EL_MITIGATION;
+ }
+ return EM_AFFECTED;
+ }
+ return EM_NOT_AFFECTED;
+ }
+ }
+ /* no matching errata ID */
+ return EM_UNKNOWN_ERRATUM;
+}
+
+/* Function to check if the errata exists for the specific CPU and rxpx */
+int32_t verify_errata_implemented(uint32_t errata_id, uint32_t forward_flag)
+{
+ /*
+ * Read MIDR value and extract the revision, variant and partnumber
+ */
+ static uint32_t midr_val, cpu_partnum;
+ static uint8_t cpu_rxpx_val;
+ int32_t ret_val = EM_UNKNOWN_ERRATUM;
+
+ /* Determine the number of cpu listed in the cpu list */
+ uint8_t size_cpulist = ARRAY_SIZE(cpu_list);
+
+ /* Read the midr reg to extract cpu, revision and variant info */
+ midr_val = read_midr();
+
+ /* Extract revision and variant from the MIDR register */
+ cpu_rxpx_val = cpu_get_rev_var();
+
+ /* Extract the cpu partnumber and check if the cpu is in the cpu list */
+ cpu_partnum = EXTRACT_PARTNUM(midr_val);
+
+ for (uint8_t i = 0; i < size_cpulist; i++) {
+ cpu_ptr = &cpu_list[i];
+ uint16_t partnum_extracted = EXTRACT_PARTNUM(cpu_ptr->cpu_partnumber);
+
+ if (partnum_extracted == cpu_partnum) {
+ /*
+ * If the midr value is in the cpu list, binary search
+ * for the errata ID and specific revision in the list.
+ */
+ ret_val = binary_search(cpu_ptr, errata_id, cpu_rxpx_val);
+ break;
+ }
+ }
+ return ret_val;
+}
+
+/* Predicate indicating that a function id is part of EM_ABI */
+bool is_errata_fid(uint32_t smc_fid)
+{
+ return ((smc_fid == ARM_EM_VERSION) ||
+ (smc_fid == ARM_EM_FEATURES) ||
+ (smc_fid == ARM_EM_CPU_ERRATUM_FEATURES));
+
+}
+
+bool validate_spsr_mode(void)
+{
+ /* In AArch64, if the caller is EL1, return true */
+
+ #if __aarch64__
+ if (GET_EL(read_spsr_el3()) == MODE_EL1) {
+ return true;
+ }
+ return false;
+ #else
+
+ /* In AArch32, if in system/svc mode, return true */
+ uint8_t read_el_state = GET_M32(read_spsr());
+
+ if ((read_el_state == (MODE32_svc)) || (read_el_state == MODE32_sys)) {
+ return true;
+ }
+ return false;
+ #endif /* __aarch64__ */
+}
+
+uintptr_t errata_abi_smc_handler(uint32_t smc_fid, u_register_t x1,
+ u_register_t x2, u_register_t x3, u_register_t x4,
+ void *cookie, void *handle, u_register_t flags)
+{
+ int32_t ret_id = EM_UNKNOWN_ERRATUM;
+
+ switch (smc_fid) {
+ case ARM_EM_VERSION:
+ SMC_RET1(handle, MAKE_SMCCC_VERSION(
+ EM_VERSION_MAJOR, EM_VERSION_MINOR
+ ));
+ break; /* unreachable */
+ case ARM_EM_FEATURES:
+ if (is_errata_fid((uint32_t)x1)) {
+ SMC_RET1(handle, EM_SUCCESS);
+ }
+
+ SMC_RET1(handle, EM_NOT_SUPPORTED);
+ break; /* unreachable */
+ case ARM_EM_CPU_ERRATUM_FEATURES:
+
+ /*
+ * If the forward flag is greater than zero and the calling EL
+ * is EL1 in AArch64 or in system mode or svc mode in case of AArch32,
+ * return Invalid Parameters.
+ */
+ if (((uint32_t)x2 != 0) && (validate_spsr_mode())) {
+ SMC_RET1(handle, EM_INVALID_PARAMETERS);
+ }
+ ret_id = verify_errata_implemented((uint32_t)x1, (uint32_t)x2);
+ SMC_RET1(handle, ret_id);
+ break; /* unreachable */
+ default:
+ {
+ WARN("Unimplemented Errata ABI Service Call: 0x%x\n", smc_fid);
+ SMC_RET1(handle, EM_UNKNOWN_ERRATUM);
+ break; /* unreachable */
+ }
+ }
+}
diff --git a/services/std_svc/spm/el3_spmc/spmc_setup.c b/services/std_svc/spm/el3_spmc/spmc_setup.c
index 8ebae28..6de25f6 100644
--- a/services/std_svc/spm/el3_spmc/spmc_setup.c
+++ b/services/std_svc/spm/el3_spmc/spmc_setup.c
@@ -90,7 +90,7 @@
boot_header->offset_boot_info_desc);
/*
- * We must use the FF-A version coresponding to the version implemented
+ * We must use the FF-A version corresponding to the version implemented
* by the SP. Currently this can only be v1.1.
*/
boot_header->version = sp->ffa_version;
diff --git a/services/std_svc/spm/spm_mm/spm_mm_main.c b/services/std_svc/spm/spm_mm/spm_mm_main.c
index 8525cd2..1ff7bb7 100644
--- a/services/std_svc/spm/spm_mm/spm_mm_main.c
+++ b/services/std_svc/spm/spm_mm/spm_mm_main.c
@@ -254,7 +254,7 @@
/*
* The current secure partition design mandates
* - at any point, only a single core can be
- * executing in the secure partiton.
+ * executing in the secure partition.
* - a core cannot be preempted by an interrupt
* while executing in secure partition.
* Raise the running priority of the core to the
diff --git a/services/std_svc/spmd/spmd_main.c b/services/std_svc/spmd/spmd_main.c
index 0e1899e..80b506b 100644
--- a/services/std_svc/spmd/spmd_main.c
+++ b/services/std_svc/spmd/spmd_main.c
@@ -249,6 +249,74 @@
SMC_RET0(&ctx->cpu_ctx);
}
+/*******************************************************************************
+ * spmd_group0_interrupt_handler_nwd
+ * Group0 secure interrupt in the normal world are trapped to EL3. Delegate the
+ * handling of the interrupt to the platform handler, and return only upon
+ * successfully handling the Group0 interrupt.
+ ******************************************************************************/
+static uint64_t spmd_group0_interrupt_handler_nwd(uint32_t id,
+ uint32_t flags,
+ void *handle,
+ void *cookie)
+{
+ uint32_t intid;
+
+ /* Sanity check the security state when the exception was generated. */
+ assert(get_interrupt_src_ss(flags) == NON_SECURE);
+
+ /* Sanity check the pointer to this cpu's context. */
+ assert(handle == cm_get_context(NON_SECURE));
+
+ assert(id == INTR_ID_UNAVAILABLE);
+
+ assert(plat_ic_get_pending_interrupt_type() == INTR_TYPE_EL3);
+
+ intid = plat_ic_get_pending_interrupt_id();
+
+ if (plat_spmd_handle_group0_interrupt(intid) < 0) {
+ ERROR("Group0 interrupt %u not handled\n", intid);
+ panic();
+ }
+
+ return 0U;
+}
+
+/*******************************************************************************
+ * spmd_handle_group0_intr_swd
+ * SPMC delegates handling of Group0 secure interrupt to EL3 firmware using
+ * FFA_EL3_INTR_HANDLE SMC call. Further, SPMD delegates the handling of the
+ * interrupt to the platform handler, and returns only upon successfully
+ * handling the Group0 interrupt.
+ ******************************************************************************/
+static uint64_t spmd_handle_group0_intr_swd(void *handle)
+{
+ uint32_t intid;
+
+ /* Sanity check the pointer to this cpu's context */
+ assert(handle == cm_get_context(SECURE));
+
+ assert(plat_ic_get_pending_interrupt_type() == INTR_TYPE_EL3);
+
+ intid = plat_ic_get_pending_interrupt_id();
+
+ /*
+ * TODO: Currently due to a limitation in SPMD implementation, the
+ * platform handler is expected to not delegate handling to NWd while
+ * processing Group0 secure interrupt.
+ */
+ if (plat_spmd_handle_group0_interrupt(intid) < 0) {
+ /* Group0 interrupt was not handled by the platform. */
+ ERROR("Group0 interrupt %u not handled\n", intid);
+ panic();
+ }
+
+ /* Return success. */
+ SMC_RET8(handle, FFA_SUCCESS_SMC32, FFA_PARAM_MBZ, FFA_PARAM_MBZ,
+ FFA_PARAM_MBZ, FFA_PARAM_MBZ, FFA_PARAM_MBZ, FFA_PARAM_MBZ,
+ FFA_PARAM_MBZ);
+}
+
#if ENABLE_RME && SPMD_SPM_AT_SEL2 && !RESET_TO_BL31
static int spmd_dynamic_map_mem(uintptr_t base_addr, size_t size,
unsigned int attr, uintptr_t *align_addr,
@@ -492,6 +560,16 @@
panic();
}
+ /*
+ * Register an interrupt handler routing Group0 interrupts to SPMD
+ * while the NWd is running.
+ */
+ rc = register_interrupt_type_handler(INTR_TYPE_EL3,
+ spmd_group0_interrupt_handler_nwd,
+ flags);
+ if (rc != 0) {
+ panic();
+ }
return 0;
}
@@ -1089,6 +1167,12 @@
handle, flags);
break; /* Not reached */
#endif
+ case FFA_EL3_INTR_HANDLE:
+ if (secure_origin) {
+ return spmd_handle_group0_intr_swd(handle);
+ } else {
+ return spmd_ffa_error_return(handle, FFA_ERROR_DENIED);
+ }
default:
WARN("SPM: Unsupported call 0x%08x\n", smc_fid);
return spmd_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED);
diff --git a/services/std_svc/spmd/spmd_private.h b/services/std_svc/spmd/spmd_private.h
index d21a622..ff6942e 100644
--- a/services/std_svc/spmd/spmd_private.h
+++ b/services/std_svc/spmd/spmd_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -93,6 +93,13 @@
int spmd_pm_secondary_ep_register(uintptr_t entry_point);
bool spmd_check_address_in_binary_image(uint64_t address);
+/*
+ * Platform hook in EL3 firmware to handle for Group0 secure interrupt.
+ * Return values:
+ * 0 = success
+ * otherwise it returns a negative value
+ */
+int plat_spmd_handle_group0_interrupt(uint32_t id);
#endif /* __ASSEMBLER__ */
#endif /* SPMD_PRIVATE_H */
diff --git a/services/std_svc/std_svc_setup.c b/services/std_svc/std_svc_setup.c
index 2884a3b..e782d09 100644
--- a/services/std_svc/std_svc_setup.c
+++ b/services/std_svc/std_svc_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,6 +14,7 @@
#include <lib/psci/psci.h>
#include <lib/runtime_instr.h>
#include <services/drtm_svc.h>
+#include <services/errata_abi_svc.h>
#include <services/pci_svc.h>
#include <services/rmmd_svc.h>
#include <services/sdei.h>
@@ -177,6 +178,13 @@
}
#endif /* TRNG_SUPPORT */
+#if ERRATA_ABI_SUPPORT
+ if (is_errata_fid(smc_fid)) {
+ return errata_abi_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
+ handle, flags);
+ }
+#endif /* ERRATA_ABI_SUPPORT */
+
#if ENABLE_RME
if (is_rmmd_el3_fid(smc_fid)) {
diff --git a/tools/conventional-changelog-tf-a/package.json b/tools/conventional-changelog-tf-a/package.json
index 3dd9877..116b28b 100644
--- a/tools/conventional-changelog-tf-a/package.json
+++ b/tools/conventional-changelog-tf-a/package.json
@@ -1,6 +1,6 @@
{
"name": "conventional-changelog-tf-a",
- "version": "2.8.0",
+ "version": "2.9.0",
"license": "BSD-3-Clause",
"private": true,
"main": "index.js",
diff --git a/tools/fiptool/Makefile b/tools/fiptool/Makefile
index ac262cd..2ebee33 100644
--- a/tools/fiptool/Makefile
+++ b/tools/fiptool/Makefile
@@ -54,10 +54,13 @@
ifneq (${PLAT},)
TF_PLATFORM_ROOT := ../../plat/
include ${MAKE_HELPERS_DIRECTORY}plat_helpers.mk
-PLAT_FIPTOOL_HELPER_MK := ${PLAT_DIR}/plat_fiptool.mk
+COMBINED_PATH_FRAG := plat_fiptool/
+PLAT_FIPTOOL_HELPER_MK := $(foreach path_frag,$(subst /, ,$(patsubst ../../plat/%/,%,${PLAT_DIR})),\
+ $(eval COMBINED_PATH_FRAG := ${COMBINED_PATH_FRAG}/${path_frag})\
+ $(wildcard ${COMBINED_PATH_FRAG}/plat_fiptool.mk))
endif
-ifneq (,$(wildcard ${PLAT_FIPTOOL_HELPER_MK}))
+ifneq (,$(wildcard $(lastword ${PLAT_FIPTOOL_HELPER_MK})))
include ${PLAT_FIPTOOL_HELPER_MK}
endif
diff --git a/plat/arm/board/tc/plat_def_uuid_config.c b/tools/fiptool/plat_fiptool/arm/board/tc/plat_def_uuid_config.c
similarity index 100%
rename from plat/arm/board/tc/plat_def_uuid_config.c
rename to tools/fiptool/plat_fiptool/arm/board/tc/plat_def_uuid_config.c
diff --git a/tools/fiptool/plat_fiptool/arm/board/tc/plat_fiptool.mk b/tools/fiptool/plat_fiptool/arm/board/tc/plat_fiptool.mk
new file mode 100644
index 0000000..70ccfc5
--- /dev/null
+++ b/tools/fiptool/plat_fiptool/arm/board/tc/plat_fiptool.mk
@@ -0,0 +1,12 @@
+#
+# Copyright (c) 2021, NXP. All rights reserved.
+# Copyright (c) 2022-2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+INCLUDE_PATHS += -I./ \
+ -I../../plat/arm/board/tc
+
+HOSTCCFLAGS += -DPLAT_DEF_FIP_UUID
+OBJECTS += plat_fiptool/arm/board/tc/plat_def_uuid_config.o
diff --git a/tools/nxp/plat_fiptool/plat_def_uuid_config.c b/tools/fiptool/plat_fiptool/nxp/plat_def_uuid_config.c
similarity index 100%
rename from tools/nxp/plat_fiptool/plat_def_uuid_config.c
rename to tools/fiptool/plat_fiptool/nxp/plat_def_uuid_config.c
diff --git a/tools/nxp/plat_fiptool/plat_fiptool.mk b/tools/fiptool/plat_fiptool/nxp/plat_fiptool.mk
similarity index 80%
rename from tools/nxp/plat_fiptool/plat_fiptool.mk
rename to tools/fiptool/plat_fiptool/nxp/plat_fiptool.mk
index ca2962a..6d7b07b 100644
--- a/tools/nxp/plat_fiptool/plat_fiptool.mk
+++ b/tools/fiptool/plat_fiptool/nxp/plat_fiptool.mk
@@ -1,5 +1,6 @@
#
# Copyright (c) 2021, NXP. All rights reserved.
+# Copyright (c) 2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -9,7 +10,7 @@
# in the plat_def_toc_entries[].
PLAT_DEF_UUID_CONFIG_FILE_NAME := plat_def_uuid_config
-PLAT_DEF_UUID_CONFIG_FILE_PATH := ../nxp/plat_fiptool
+PLAT_DEF_UUID_CONFIG_FILE_PATH := plat_fiptool/nxp/
PLAT_DEF_OID := yes
PLAT_DEF_UUID := yes
@@ -18,8 +19,6 @@
INCLUDE_PATHS += -I${PLAT_DEF_UUID_OID_CONFIG_PATH} \
-I./
-# Clean the stale object file.
-$(shell rm ${PLAT_DEF_UUID_CONFIG_FILE_PATH}/${PLAT_DEF_UUID_CONFIG_FILE_NAME}.o)
ifeq (${PLAT_DEF_OID},yes)
HOSTCCFLAGS += -DPLAT_DEF_OID
diff --git a/plat/st/stm32mp1/plat_def_uuid_config.c b/tools/fiptool/plat_fiptool/st/stm32mp1/plat_def_uuid_config.c
similarity index 100%
rename from plat/st/stm32mp1/plat_def_uuid_config.c
rename to tools/fiptool/plat_fiptool/st/stm32mp1/plat_def_uuid_config.c
diff --git a/plat/st/stm32mp1/plat_fiptool.mk b/tools/fiptool/plat_fiptool/st/stm32mp1/plat_fiptool.mk
similarity index 87%
rename from plat/st/stm32mp1/plat_fiptool.mk
rename to tools/fiptool/plat_fiptool/st/stm32mp1/plat_fiptool.mk
index 00570c2..1ba47c1 100644
--- a/plat/st/stm32mp1/plat_fiptool.mk
+++ b/tools/fiptool/plat_fiptool/st/stm32mp1/plat_fiptool.mk
@@ -16,7 +16,7 @@
ifeq (${PLAT_DEF_UUID},yes)
HOSTCCFLAGS += -DPLAT_DEF_FIP_UUID
-${PLAT_DEF_UUID_FILE_NAME}.o: ${PLAT_DIR}${PLAT_DEF_UUID_FILE_NAME}.c
+${PLAT_DEF_UUID_FILE_NAME}.o: plat_fiptool/st/stm32mp1/${PLAT_DEF_UUID_FILE_NAME}.c
${HOSTCC} -c ${CPPFLAGS} ${HOSTCCFLAGS} ${INCLUDE_PATHS} $< -o $@
PLAT_OBJECTS += ${PLAT_DEF_UUID_FILE_NAME}.o
diff --git a/tools/fiptool/win_posix.h b/tools/fiptool/win_posix.h
index 6f0d8e6..1340640 100644
--- a/tools/fiptool/win_posix.h
+++ b/tools/fiptool/win_posix.h
@@ -149,7 +149,7 @@
* Windows does not have the getopt family of functions, as it normally
* uses '/' instead of '-' as the command line option delimiter.
* These functions provide a Windows version that uses '-', which precludes
- * using '-' as the intial letter of a program argument.
+ * using '-' as the initial letter of a program argument.
* This is not seen as a problem in the specific instance of fiptool,
* and enables existing makefiles to work on a Windows build environment.
*/
diff --git a/tools/nxp/create_pbl/create_pbl.c b/tools/nxp/create_pbl/create_pbl.c
index 792747f..c277e39 100644
--- a/tools/nxp/create_pbl/create_pbl.c
+++ b/tools/nxp/create_pbl/create_pbl.c
@@ -912,7 +912,7 @@
while (word != 0x808f0000 && word != 0x80ff0000) {
pbl_size++;
/* 11th words in RCW has PBL length. Update it
- * with new length. 2 comamnds get added
+ * with new length. 2 commands get added
* Block copy + CCSR Write/CSF header write
*/
if (pbl_size == 11) {