Unique names for defines in the CPU libraries
This patch makes all the defines in the CPU libraries unique,
by prefixing them with the CPU name.
NOTE: PLATFORMS USING THESE MACROS WILL HAVE TO UPDATE THEIR CODE
TO START USING THE UPDATED NAMES
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/plat/arm/board/juno/aarch64/juno_helpers.S b/plat/arm/board/juno/aarch64/juno_helpers.S
index e411360..8d00a1a 100644
--- a/plat/arm/board/juno/aarch64/juno_helpers.S
+++ b/plat/arm/board/juno/aarch64/juno_helpers.S
@@ -86,9 +86,9 @@
* Cortex-A57 specific settings
* --------------------------------------------------------------------
*/
- mov x0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
- (L2_TAG_RAM_LATENCY_3_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT))
- msr L2CTLR_EL1, x0
+ mov x0, #((CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
+ (CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT))
+ msr CORTEX_A57_L2CTLR_EL1, x0
1:
isb
ret
@@ -123,8 +123,8 @@
* Cortex-A57 specific settings
* --------------------------------------------------------------------
*/
- mov x0, #(L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT)
- msr L2CTLR_EL1, x0
+ mov x0, #(CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT)
+ msr CORTEX_A57_L2CTLR_EL1, x0
isb
ret
endfunc JUNO_HANDLER(1)
@@ -157,9 +157,9 @@
* Cortex-A72 specific settings
* --------------------------------------------------------------------
*/
- mov x0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
- (L2_TAG_RAM_LATENCY_2_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT))
- msr L2CTLR_EL1, x0
+ mov x0, #((CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
+ (CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES << CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT))
+ msr CORTEX_A57_L2CTLR_EL1, x0
isb
ret
endfunc JUNO_HANDLER(2)
diff --git a/plat/hisilicon/hikey/hisi_pwrc_sram.S b/plat/hisilicon/hikey/hisi_pwrc_sram.S
index 054763b..1fb63ea 100644
--- a/plat/hisilicon/hikey/hisi_pwrc_sram.S
+++ b/plat/hisilicon/hikey/hisi_pwrc_sram.S
@@ -20,11 +20,11 @@
mov x0, 0
msr oslar_el1, x0
- mrs x0, CPUACTLR_EL1
- bic x0, x0, #(CPUACTLR_RADIS | CPUACTLR_L1RADIS)
+ mrs x0, CORTEX_A53_ACTLR_EL1
+ bic x0, x0, #(CORTEX_A53_ACTLR_RADIS | CORTEX_A53_ACTLR_L1RADIS)
orr x0, x0, #0x180000
orr x0, x0, #0xe000
- msr CPUACTLR_EL1, x0
+ msr CORTEX_A53_ACTLR_EL1, x0
mrs x3, actlr_el3
orr x3, x3, #ACTLR_EL3_L2ECTLR_BIT
diff --git a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
index 1a4236f..22389f2 100644
--- a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
+++ b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
@@ -68,18 +68,18 @@
* Enable processor retention
* ---------------------------
*/
- mrs x0, L2ECTLR_EL1
- mov x1, #RETENTION_ENTRY_TICKS_512 << L2ECTLR_RET_CTRL_SHIFT
- bic x0, x0, #L2ECTLR_RET_CTRL_MASK
+ mrs x0, CORTEX_A57_L2ECTLR_EL1
+ mov x1, #RETENTION_ENTRY_TICKS_512
+ bic x0, x0, #CORTEX_A57_L2ECTLR_RET_CTRL_MASK
orr x0, x0, x1
- msr L2ECTLR_EL1, x0
+ msr CORTEX_A57_L2ECTLR_EL1, x0
isb
- mrs x0, CPUECTLR_EL1
- mov x1, #RETENTION_ENTRY_TICKS_512 << CPUECTLR_CPU_RET_CTRL_SHIFT
- bic x0, x0, #CPUECTLR_CPU_RET_CTRL_MASK
+ mrs x0, CORTEX_A57_ECTLR_EL1
+ mov x1, #RETENTION_ENTRY_TICKS_512
+ bic x0, x0, #CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK
orr x0, x0, x1
- msr CPUECTLR_EL1, x0
+ msr CORTEX_A57_ECTLR_EL1, x0
isb
/* -------------------------------------------------------
@@ -98,11 +98,11 @@
adr x0, tegra_enable_l2_ecc_parity_prot
ldr x0, [x0]
cbz x0, 1f
- mrs x0, L2CTLR_EL1
- and x1, x0, #L2_ECC_PARITY_PROTECTION_BIT
+ mrs x0, CORTEX_A57_L2CTLR_EL1
+ and x1, x0, #CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT
cbnz x1, 1f
- orr x0, x0, #L2_ECC_PARITY_PROTECTION_BIT
- msr L2CTLR_EL1, x0
+ orr x0, x0, #CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT
+ msr CORTEX_A57_L2CTLR_EL1, x0
isb
/* --------------------------------
@@ -317,18 +317,18 @@
* entries from the branch predictor array.
* -------------------------------------------------------
*/
- mrs x0, CPUACTLR_EL1
+ mrs x0, CORTEX_A57_ACTLR_EL1
orr x0, x0, #1
- msr CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */
+ msr CORTEX_A57_ACTLR_EL1, x0 /* invalidate BTB and I$ together */
dsb sy
isb
ic iallu /* actual invalidate */
dsb sy
isb
- mrs x0, CPUACTLR_EL1
+ mrs x0, CORTEX_A57_ACTLR_EL1
bic x0, x0, #1
- msr CPUACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */
+ msr CORTEX_A57_ACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */
dsb sy
isb
@@ -352,7 +352,7 @@
msr oslar_el1, x0 /* os lock stays 0 across warm reset */
mov x3, #3
movz x4, #0x8000, lsl #48
- msr CPUACTLR_EL1, x4 /* turn off RCG */
+ msr CORTEX_A57_ACTLR_EL1, x4 /* turn off RCG */
isb
msr rmr_el3, x3 /* request warm reset */
isb
diff --git a/plat/nvidia/tegra/soc/t186/plat_setup.c b/plat/nvidia/tegra/soc/t186/plat_setup.c
index 151b757..ba24579 100644
--- a/plat/nvidia/tegra/soc/t186/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t186/plat_setup.c
@@ -22,7 +22,7 @@
#include <tegra_private.h>
#include <xlat_tables.h>
-DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, L2CTLR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, CORTEX_A57_L2CTLR_EL1)
extern uint64_t tegra_enable_l2_ecc_parity_prot;
/*******************************************************************************
@@ -172,7 +172,7 @@
if (val >= TEGRA186_VER_A02P) {
val = read_l2ctlr_el1();
- val |= L2_ECC_PARITY_PROTECTION_BIT;
+ val |= CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT;
write_l2ctlr_el1(val);
/*
diff --git a/plat/rockchip/common/aarch64/plat_helpers.S b/plat/rockchip/common/aarch64/plat_helpers.S
index 8a7be74..1c8aefc 100644
--- a/plat/rockchip/common/aarch64/plat_helpers.S
+++ b/plat/rockchip/common/aarch64/plat_helpers.S
@@ -43,9 +43,9 @@
* Set the L2 Data RAM latency for Cortex-A72.
* Set the L2 Tag RAM latency to for Cortex-A72.
*/
- mov x0, #((5 << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
+ mov x0, #((5 << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
(0x1 << 5))
- msr L2CTLR_EL1, x0
+ msr CORTEX_A72_L2CTLR_EL1, x0
isb
handler_end:
ret