Unique names for defines in the CPU libraries
This patch makes all the defines in the CPU libraries unique,
by prefixing them with the CPU name.
NOTE: PLATFORMS USING THESE MACROS WILL HAVE TO UPDATE THEIR CODE
TO START USING THE UPDATED NAMES
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S
index 77c564a..d369c6d 100644
--- a/lib/cpus/aarch64/cortex_a53.S
+++ b/lib/cpus/aarch64/cortex_a53.S
@@ -33,9 +33,9 @@
* ---------------------------------------------
*/
func cortex_a53_disable_smp
- mrs x0, CPUECTLR_EL1
- bic x0, x0, #CPUECTLR_SMP_BIT
- msr CPUECTLR_EL1, x0
+ mrs x0, CORTEX_A53_ECTLR_EL1
+ bic x0, x0, #CORTEX_A53_ECTLR_SMP_BIT
+ msr CORTEX_A53_ECTLR_EL1, x0
isb
dsb sy
ret
@@ -56,10 +56,10 @@
mov x17, x30
bl check_errata_826319
cbz x0, 1f
- mrs x1, L2ACTLR_EL1
- bic x1, x1, #L2ACTLR_ENABLE_UNIQUECLEAN
- orr x1, x1, #L2ACTLR_DISABLE_CLEAN_PUSH
- msr L2ACTLR_EL1, x1
+ mrs x1, CORTEX_A53_L2ACTLR_EL1
+ bic x1, x1, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN
+ orr x1, x1, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH
+ msr CORTEX_A53_L2ACTLR_EL1, x1
1:
ret x17
endfunc errata_a53_826319_wa
@@ -93,9 +93,9 @@
mov x17, x30
bl check_errata_disable_non_temporal_hint
cbz x0, 1f
- mrs x1, CPUACTLR_EL1
- orr x1, x1, #CPUACTLR_DTAH
- msr CPUACTLR_EL1, x1
+ mrs x1, CORTEX_A53_ACTLR_EL1
+ orr x1, x1, #CORTEX_A53_ACTLR_DTAH
+ msr CORTEX_A53_ACTLR_EL1, x1
1:
ret x17
endfunc a53_disable_non_temporal_hint
@@ -126,9 +126,9 @@
bl check_errata_855873
cbz x0, 1f
- mrs x1, CPUACTLR_EL1
- orr x1, x1, #CPUACTLR_ENDCCASCI
- msr CPUACTLR_EL1, x1
+ mrs x1, CORTEX_A53_ACTLR_EL1
+ orr x1, x1, #CORTEX_A53_ACTLR_ENDCCASCI
+ msr CORTEX_A53_ACTLR_EL1, x1
1:
ret x17
endfunc errata_a53_855873_wa
@@ -168,9 +168,9 @@
* Enable the SMP bit.
* ---------------------------------------------
*/
- mrs x0, CPUECTLR_EL1
- orr x0, x0, #CPUECTLR_SMP_BIT
- msr CPUECTLR_EL1, x0
+ mrs x0, CORTEX_A53_ECTLR_EL1
+ orr x0, x0, #CORTEX_A53_ECTLR_SMP_BIT
+ msr CORTEX_A53_ECTLR_EL1, x0
isb
ret x19
endfunc cortex_a53_reset_func
@@ -275,10 +275,10 @@
func cortex_a53_cpu_reg_dump
adr x6, cortex_a53_regs
- mrs x8, CPUECTLR_EL1
- mrs x9, CPUMERRSR_EL1
- mrs x10, L2MERRSR_EL1
- mrs x11, CPUACTLR_EL1
+ mrs x8, CORTEX_A53_ECTLR_EL1
+ mrs x9, CORTEX_A53_MERRSR_EL1
+ mrs x10, CORTEX_A53_L2MERRSR_EL1
+ mrs x11, CORTEX_A53_ACTLR_EL1
ret
endfunc cortex_a53_cpu_reg_dump
diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S
index ffaf44e..9e8480a 100644
--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S
@@ -29,12 +29,12 @@
* ---------------------------------------------
*/
func cortex_a57_disable_l2_prefetch
- mrs x0, CPUECTLR_EL1
- orr x0, x0, #CPUECTLR_DIS_TWD_ACC_PFTCH_BIT
- mov x1, #CPUECTLR_L2_IPFTCH_DIST_MASK
- orr x1, x1, #CPUECTLR_L2_DPFTCH_DIST_MASK
+ mrs x0, CORTEX_A57_ECTLR_EL1
+ orr x0, x0, #CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT
+ mov x1, #CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK
+ orr x1, x1, #CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK
bic x0, x0, x1
- msr CPUECTLR_EL1, x0
+ msr CORTEX_A57_ECTLR_EL1, x0
isb
dsb ish
ret
@@ -45,9 +45,9 @@
* ---------------------------------------------
*/
func cortex_a57_disable_smp
- mrs x0, CPUECTLR_EL1
- bic x0, x0, #CPUECTLR_SMP_BIT
- msr CPUECTLR_EL1, x0
+ mrs x0, CORTEX_A57_ECTLR_EL1
+ bic x0, x0, #CORTEX_A57_ECTLR_SMP_BIT
+ msr CORTEX_A57_ECTLR_EL1, x0
ret
endfunc cortex_a57_disable_smp
@@ -78,9 +78,9 @@
mov x17, x30
bl check_errata_806969
cbz x0, 1f
- mrs x1, CPUACTLR_EL1
- orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA
- msr CPUACTLR_EL1, x1
+ mrs x1, CORTEX_A57_ACTLR_EL1
+ orr x1, x1, #CORTEX_A57_ACTLR_NO_ALLOC_WBWA
+ msr CORTEX_A57_ACTLR_EL1, x1
1:
ret x17
endfunc errata_a57_806969_wa
@@ -120,9 +120,9 @@
mov x17, x30
bl check_errata_813420
cbz x0, 1f
- mrs x1, CPUACTLR_EL1
- orr x1, x1, #CPUACTLR_DCC_AS_DCCI
- msr CPUACTLR_EL1, x1
+ mrs x1, CORTEX_A57_ACTLR_EL1
+ orr x1, x1, #CORTEX_A57_ACTLR_DCC_AS_DCCI
+ msr CORTEX_A57_ACTLR_EL1, x1
1:
ret x17
endfunc errata_a57_813420_wa
@@ -150,9 +150,9 @@
mov x17, x30
bl check_errata_disable_ldnp_overread
cbz x0, 1f
- mrs x1, CPUACTLR_EL1
- orr x1, x1, #CPUACTLR_DIS_OVERREAD
- msr CPUACTLR_EL1, x1
+ mrs x1, CORTEX_A57_ACTLR_EL1
+ orr x1, x1, #CORTEX_A57_ACTLR_DIS_OVERREAD
+ msr CORTEX_A57_ACTLR_EL1, x1
1:
ret x17
endfunc a57_disable_ldnp_overread
@@ -177,9 +177,9 @@
mov x17, x30
bl check_errata_826974
cbz x0, 1f
- mrs x1, CPUACTLR_EL1
- orr x1, x1, #CPUACTLR_DIS_LOAD_PASS_DMB
- msr CPUACTLR_EL1, x1
+ mrs x1, CORTEX_A57_ACTLR_EL1
+ orr x1, x1, #CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB
+ msr CORTEX_A57_ACTLR_EL1, x1
1:
ret x17
endfunc errata_a57_826974_wa
@@ -204,9 +204,9 @@
mov x17, x30
bl check_errata_826977
cbz x0, 1f
- mrs x1, CPUACTLR_EL1
- orr x1, x1, #CPUACTLR_GRE_NGRE_AS_NGNRE
- msr CPUACTLR_EL1, x1
+ mrs x1, CORTEX_A57_ACTLR_EL1
+ orr x1, x1, #CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE
+ msr CORTEX_A57_ACTLR_EL1, x1
1:
ret x17
endfunc errata_a57_826977_wa
@@ -231,15 +231,16 @@
mov x17, x30
bl check_errata_828024
cbz x0, 1f
- mrs x1, CPUACTLR_EL1
+ mrs x1, CORTEX_A57_ACTLR_EL1
/*
* Setting the relevant bits in CPUACTLR_EL1 has to be done in 2
* instructions here because the resulting bitmask doesn't fit in a
* 16-bit value so it cannot be encoded in a single instruction.
*/
- orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA
- orr x1, x1, #(CPUACTLR_DIS_L1_STREAMING | CPUACTLR_DIS_STREAMING)
- msr CPUACTLR_EL1, x1
+ orr x1, x1, #CORTEX_A57_ACTLR_NO_ALLOC_WBWA
+ orr x1, x1, #(CORTEX_A57_ACTLR_DIS_L1_STREAMING | \
+ CORTEX_A57_ACTLR_DIS_STREAMING)
+ msr CORTEX_A57_ACTLR_EL1, x1
1:
ret x17
endfunc errata_a57_828024_wa
@@ -264,9 +265,9 @@
mov x17, x30
bl check_errata_829520
cbz x0, 1f
- mrs x1, CPUACTLR_EL1
- orr x1, x1, #CPUACTLR_DIS_INDIRECT_PREDICTOR
- msr CPUACTLR_EL1, x1
+ mrs x1, CORTEX_A57_ACTLR_EL1
+ orr x1, x1, #CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR
+ msr CORTEX_A57_ACTLR_EL1, x1
1:
ret x17
endfunc errata_a57_829520_wa
@@ -291,9 +292,9 @@
mov x17, x30
bl check_errata_833471
cbz x0, 1f
- mrs x1, CPUACTLR_EL1
- orr x1, x1, #CPUACTLR_FORCE_FPSCR_FLUSH
- msr CPUACTLR_EL1, x1
+ mrs x1, CORTEX_A57_ACTLR_EL1
+ orr x1, x1, #CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH
+ msr CORTEX_A57_ACTLR_EL1, x1
1:
ret x17
endfunc errata_a57_833471_wa
@@ -357,9 +358,9 @@
* Enable the SMP bit.
* ---------------------------------------------
*/
- mrs x0, CPUECTLR_EL1
- orr x0, x0, #CPUECTLR_SMP_BIT
- msr CPUECTLR_EL1, x0
+ mrs x0, CORTEX_A57_ECTLR_EL1
+ orr x0, x0, #CORTEX_A57_ECTLR_SMP_BIT
+ msr CORTEX_A57_ECTLR_EL1, x0
isb
ret x19
endfunc cortex_a57_reset_func
@@ -503,9 +504,9 @@
func cortex_a57_cpu_reg_dump
adr x6, cortex_a57_regs
- mrs x8, CPUECTLR_EL1
- mrs x9, CPUMERRSR_EL1
- mrs x10, L2MERRSR_EL1
+ mrs x8, CORTEX_A57_ECTLR_EL1
+ mrs x9, CORTEX_A57_MERRSR_EL1
+ mrs x10, CORTEX_A57_L2MERRSR_EL1
ret
endfunc cortex_a57_cpu_reg_dump
diff --git a/lib/cpus/aarch64/cortex_a72.S b/lib/cpus/aarch64/cortex_a72.S
index acd2d96..0307627 100644
--- a/lib/cpus/aarch64/cortex_a72.S
+++ b/lib/cpus/aarch64/cortex_a72.S
@@ -27,12 +27,12 @@
* ---------------------------------------------
*/
func cortex_a72_disable_l2_prefetch
- mrs x0, CPUECTLR_EL1
- orr x0, x0, #CPUECTLR_DIS_TWD_ACC_PFTCH_BIT
- mov x1, #CPUECTLR_L2_IPFTCH_DIST_MASK
- orr x1, x1, #CPUECTLR_L2_DPFTCH_DIST_MASK
+ mrs x0, CORTEX_A72_ECTLR_EL1
+ orr x0, x0, #CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT
+ mov x1, #CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK
+ orr x1, x1, #CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK
bic x0, x0, x1
- msr CPUECTLR_EL1, x0
+ msr CORTEX_A72_ECTLR_EL1, x0
isb
ret
endfunc cortex_a72_disable_l2_prefetch
@@ -42,9 +42,9 @@
* ---------------------------------------------
*/
func cortex_a72_disable_hw_prefetcher
- mrs x0, CPUACTLR_EL1
- orr x0, x0, #CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH
- msr CPUACTLR_EL1, x0
+ mrs x0, CORTEX_A72_ACTLR_EL1
+ orr x0, x0, #CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH
+ msr CORTEX_A72_ACTLR_EL1, x0
isb
dsb ish
ret
@@ -55,9 +55,9 @@
* ---------------------------------------------
*/
func cortex_a72_disable_smp
- mrs x0, CPUECTLR_EL1
- bic x0, x0, #CPUECTLR_SMP_BIT
- msr CPUECTLR_EL1, x0
+ mrs x0, CORTEX_A72_ECTLR_EL1
+ bic x0, x0, #CORTEX_A72_ECTLR_SMP_BIT
+ msr CORTEX_A72_ECTLR_EL1, x0
ret
endfunc cortex_a72_disable_smp
@@ -82,9 +82,9 @@
* As a bare minimum enable the SMP bit.
* ---------------------------------------------
*/
- mrs x0, CPUECTLR_EL1
- orr x0, x0, #CPUECTLR_SMP_BIT
- msr CPUECTLR_EL1, x0
+ mrs x0, CORTEX_A72_ECTLR_EL1
+ orr x0, x0, #CORTEX_A72_ECTLR_SMP_BIT
+ msr CORTEX_A72_ECTLR_EL1, x0
isb
ret
endfunc cortex_a72_reset_func
@@ -211,9 +211,9 @@
func cortex_a72_cpu_reg_dump
adr x6, cortex_a72_regs
- mrs x8, CPUECTLR_EL1
- mrs x9, CPUMERRSR_EL1
- mrs x10, L2MERRSR_EL1
+ mrs x8, CORTEX_A72_ECTLR_EL1
+ mrs x9, CORTEX_A72_MERRSR_EL1
+ mrs x10, CORTEX_A72_L2MERRSR_EL1
ret
endfunc cortex_a72_cpu_reg_dump