diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h
index 10d9ee6..e87e969 100644
--- a/include/lib/cpus/aarch64/cortex_a53.h
+++ b/include/lib/cpus/aarch64/cortex_a53.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -22,54 +22,54 @@
 /*******************************************************************************
  * CPU Extended Control register specific definitions.
  ******************************************************************************/
-#define CPUECTLR_EL1			S3_1_C15_C2_1	/* Instruction def. */
+#define CORTEX_A53_ECTLR_EL1		S3_1_C15_C2_1
 
-#define CPUECTLR_SMP_BIT		(1 << 6)
+#define CORTEX_A53_ECTLR_SMP_BIT	(1 << 6)
 
-#define CPUECTLR_CPU_RET_CTRL_SHIFT	0
-#define CPUECTLR_CPU_RET_CTRL_MASK	(0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT)
+#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT	0
+#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK	(0x7 << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT)
 
-#define CPUECTLR_FPU_RET_CTRL_SHIFT	3
-#define CPUECTLR_FPU_RET_CTRL_MASK	(0x7 << CPUECTLR_FPU_RET_CTRL_SHIFT)
+#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT	3
+#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK	(0x7 << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT)
 
 /*******************************************************************************
  * CPU Memory Error Syndrome register specific definitions.
  ******************************************************************************/
-#define CPUMERRSR_EL1			S3_1_C15_C2_2	/* Instruction def. */
+#define CORTEX_A53_MERRSR_EL1			S3_1_C15_C2_2
 
 /*******************************************************************************
  * CPU Auxiliary Control register specific definitions.
  ******************************************************************************/
-#define CPUACTLR_EL1			S3_1_C15_C2_0	/* Instruction def. */
+#define CORTEX_A53_ACTLR_EL1			S3_1_C15_C2_0
 
-#define CPUACTLR_ENDCCASCI_SHIFT	44
-#define CPUACTLR_ENDCCASCI		(1 << CPUACTLR_ENDCCASCI_SHIFT)
-#define CPUACTLR_RADIS_SHIFT		27
-#define CPUACTLR_RADIS			(3 << CPUACTLR_RADIS_SHIFT)
-#define CPUACTLR_L1RADIS_SHIFT		25
-#define CPUACTLR_L1RADIS		(3 << CPUACTLR_L1RADIS_SHIFT)
-#define CPUACTLR_DTAH_SHIFT		24
-#define CPUACTLR_DTAH			(1 << CPUACTLR_DTAH_SHIFT)
+#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT	44
+#define CORTEX_A53_ACTLR_ENDCCASCI		(1 << CORTEX_A53_ACTLR_ENDCCASCI_SHIFT)
+#define CORTEX_A53_ACTLR_RADIS_SHIFT		27
+#define CORTEX_A53_ACTLR_RADIS			(3 << CORTEX_A53_ACTLR_RADIS_SHIFT)
+#define CORTEX_A53_ACTLR_L1RADIS_SHIFT		25
+#define CORTEX_A53_ACTLR_L1RADIS		(3 << CORTEX_A53_ACTLR_L1RADIS_SHIFT)
+#define CORTEX_A53_ACTLR_DTAH_SHIFT		24
+#define CORTEX_A53_ACTLR_DTAH			(1 << CORTEX_A53_ACTLR_DTAH_SHIFT)
 
 /*******************************************************************************
  * L2 Auxiliary Control register specific definitions.
  ******************************************************************************/
-#define L2ACTLR_EL1			S3_1_C15_C0_0	/* Instruction def. */
+#define CORTEX_A53_L2ACTLR_EL1			S3_1_C15_C0_0
 
-#define L2ACTLR_ENABLE_UNIQUECLEAN	(1 << 14)
-#define L2ACTLR_DISABLE_CLEAN_PUSH	(1 << 3)
+#define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN	(1 << 14)
+#define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH	(1 << 3)
 
 /*******************************************************************************
  * L2 Extended Control register specific definitions.
  ******************************************************************************/
-#define L2ECTLR_EL1			S3_1_C11_C0_3	/* Instruction def. */
+#define CORTEX_A53_L2ECTLR_EL1			S3_1_C11_C0_3
 
-#define L2ECTLR_RET_CTRL_SHIFT		0
-#define L2ECTLR_RET_CTRL_MASK		(0x7 << L2ECTLR_RET_CTRL_SHIFT)
+#define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT	0
+#define CORTEX_A53_L2ECTLR_RET_CTRL_MASK	(0x7 << L2ECTLR_RET_CTRL_SHIFT)
 
 /*******************************************************************************
  * L2 Memory Error Syndrome register specific definitions.
  ******************************************************************************/
-#define L2MERRSR_EL1			S3_1_C15_C2_3	/* Instruction def. */
+#define CORTEX_A53_L2MERRSR_EL1			S3_1_C15_C2_3
 
 #endif /* __CORTEX_A53_H__ */