diff --git a/plat/mediatek/drivers/apusys/apusys.c b/plat/mediatek/drivers/apusys/apusys.c
index c82b3a7..e3a986e 100644
--- a/plat/mediatek/drivers/apusys/apusys.c
+++ b/plat/mediatek/drivers/apusys/apusys.c
@@ -9,6 +9,7 @@
 
 /* Vendor header */
 #include "apusys.h"
+#include "apusys_devapc.h"
 #include "apusys_power.h"
 #include <lib/mtk_init/mtk_init.h>
 #include <mtk_sip_svc.h>
@@ -43,7 +44,14 @@
 
 int apusys_init(void)
 {
-	apusys_power_init();
+	if (apusys_power_init() != 0) {
+		return -1;
+	}
+
+	if (apusys_devapc_ao_init() != 0) {
+		return -1;
+	}
+
 	return 0;
 }
 MTK_PLAT_SETUP_1_INIT(apusys_init);
diff --git a/plat/mediatek/drivers/apusys/devapc/apusys_dapc_v1.c b/plat/mediatek/drivers/apusys/devapc/apusys_dapc_v1.c
new file mode 100644
index 0000000..4bd4272
--- /dev/null
+++ b/plat/mediatek/drivers/apusys/devapc/apusys_dapc_v1.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* TF-A system header */
+#include <common/debug.h>
+#include <lib/utils_def.h>
+
+/* Vendor header */
+#include "apusys.h"
+#include "apusys_dapc_v1.h"
+#include <platform_def.h>
+
+enum apusys_apc_err_status set_apusys_dapc_v1(const struct apc_dom_16 *dapc,
+					      uint32_t size, dapc_cfg_func cfg)
+{
+	enum apusys_apc_err_status ret = APUSYS_APC_OK;
+	uint32_t i;
+
+	if ((dapc == NULL) || (cfg == NULL)) {
+		return APUSYS_APC_ERR_GENERIC;
+	}
+
+	for (i = 0; i < size; i++) {
+		ret += cfg(i, DOMAIN_0,	 dapc[i].d0_permission);
+		ret += cfg(i, DOMAIN_1,	 dapc[i].d1_permission);
+		ret += cfg(i, DOMAIN_2,	 dapc[i].d2_permission);
+		ret += cfg(i, DOMAIN_3,	 dapc[i].d3_permission);
+		ret += cfg(i, DOMAIN_4,	 dapc[i].d4_permission);
+		ret += cfg(i, DOMAIN_5,	 dapc[i].d5_permission);
+		ret += cfg(i, DOMAIN_6,	 dapc[i].d6_permission);
+		ret += cfg(i, DOMAIN_7,	 dapc[i].d7_permission);
+		ret += cfg(i, DOMAIN_8,	 dapc[i].d8_permission);
+		ret += cfg(i, DOMAIN_9,	 dapc[i].d9_permission);
+		ret += cfg(i, DOMAIN_10, dapc[i].d10_permission);
+		ret += cfg(i, DOMAIN_11, dapc[i].d11_permission);
+		ret += cfg(i, DOMAIN_12, dapc[i].d12_permission);
+		ret += cfg(i, DOMAIN_13, dapc[i].d13_permission);
+		ret += cfg(i, DOMAIN_14, dapc[i].d14_permission);
+		ret += cfg(i, DOMAIN_15, dapc[i].d15_permission);
+	}
+
+	if (ret != APUSYS_APC_OK) {
+		ret = APUSYS_APC_ERR_GENERIC;
+	}
+
+	return ret;
+}
+
+void dump_apusys_dapc_v1(const char *name, uintptr_t base, uint32_t reg_num, uint32_t dom_num)
+{
+	uint32_t d, i;
+
+	if ((name == NULL) || (base == 0)) {
+		return;
+	}
+
+	for (d = 0; d < dom_num; d++) {
+		for (i = 0; i <= reg_num; i++) {
+			INFO(MODULE_TAG "[%s] D%d_APC_%d: 0x%x\n", name, d, i,
+			     mmio_read_32(base + d * DEVAPC_DOM_SIZE + i * DEVAPC_REG_SIZE));
+		}
+	}
+
+	INFO(MODULE_TAG "[%s] APC_CON: 0x%x\n", name, mmio_read_32(APUSYS_DAPC_CON(base)));
+}
diff --git a/plat/mediatek/drivers/apusys/devapc/apusys_dapc_v1.h b/plat/mediatek/drivers/apusys/devapc/apusys_dapc_v1.h
new file mode 100644
index 0000000..621a08c
--- /dev/null
+++ b/plat/mediatek/drivers/apusys/devapc/apusys_dapc_v1.h
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef APUSYS_DAPC_V1_H
+#define APUSYS_DAPC_V1_H
+
+#include <lib/mmio.h>
+
+/******************************************************************************
+ * STRUCTURE DEFINITION
+ ******************************************************************************/
+enum apusys_apc_err_status {
+	APUSYS_APC_OK		= 0x0,
+	APUSYS_APC_ERR_GENERIC	= 0x1,
+};
+
+enum apusys_apc_perm_type {
+	NO_PROTECTION	= 0,
+	SEC_RW_ONLY	= 1,
+	SEC_RW_NS_R	= 2,
+	FORBIDDEN	= 3,
+	PERM_NUM	= 4,
+};
+
+enum apusys_apc_domain_id {
+	DOMAIN_0	=  0,
+	DOMAIN_1	=  1,
+	DOMAIN_2	=  2,
+	DOMAIN_3	=  3,
+	DOMAIN_4	=  4,
+	DOMAIN_5	=  5,
+	DOMAIN_6	=  6,
+	DOMAIN_7	=  7,
+	DOMAIN_8	=  8,
+	DOMAIN_9	=  9,
+	DOMAIN_10	= 10,
+	DOMAIN_11	= 11,
+	DOMAIN_12	= 12,
+	DOMAIN_13	= 13,
+	DOMAIN_14	= 14,
+	DOMAIN_15	= 15,
+};
+
+struct apc_dom_16 {
+	unsigned char d0_permission;
+	unsigned char d1_permission;
+	unsigned char d2_permission;
+	unsigned char d3_permission;
+	unsigned char d4_permission;
+	unsigned char d5_permission;
+	unsigned char d6_permission;
+	unsigned char d7_permission;
+	unsigned char d8_permission;
+	unsigned char d9_permission;
+	unsigned char d10_permission;
+	unsigned char d11_permission;
+	unsigned char d12_permission;
+	unsigned char d13_permission;
+	unsigned char d14_permission;
+	unsigned char d15_permission;
+};
+
+#define APUSYS_APC_AO_ATTR(DEV_NAME,					       \
+			   PERM_ATTR0,  PERM_ATTR1,  PERM_ATTR2,  PERM_ATTR3,  \
+			   PERM_ATTR4,  PERM_ATTR5,  PERM_ATTR6,  PERM_ATTR7,  \
+			   PERM_ATTR8,  PERM_ATTR9,  PERM_ATTR10, PERM_ATTR11, \
+			   PERM_ATTR12, PERM_ATTR13, PERM_ATTR14, PERM_ATTR15) \
+	{(unsigned char)PERM_ATTR0,  (unsigned char)PERM_ATTR1,  \
+	 (unsigned char)PERM_ATTR2,  (unsigned char)PERM_ATTR3,  \
+	 (unsigned char)PERM_ATTR4,  (unsigned char)PERM_ATTR5,  \
+	 (unsigned char)PERM_ATTR6,  (unsigned char)PERM_ATTR7,  \
+	 (unsigned char)PERM_ATTR8,  (unsigned char)PERM_ATTR9,  \
+	 (unsigned char)PERM_ATTR10, (unsigned char)PERM_ATTR11, \
+	 (unsigned char)PERM_ATTR12, (unsigned char)PERM_ATTR13, \
+	 (unsigned char)PERM_ATTR14, (unsigned char)PERM_ATTR15}
+
+typedef enum apusys_apc_err_status (*dapc_cfg_func)(uint32_t slave,
+						    enum apusys_apc_domain_id domain_id,
+						    enum apusys_apc_perm_type perm);
+
+/* Register */
+#define DEVAPC_DOM_SIZE			(0x40)
+#define DEVAPC_REG_SIZE			(4)
+
+/* APUSYS APC offsets */
+#define APUSYS_DAPC_CON_VIO_MASK	(0x80000000)
+#define APUSYS_DAPC_CON(base)		((base) + 0x00f00)
+
+/******************************************************************************
+ * DAPC Common Function
+ ******************************************************************************/
+#define SET_APUSYS_DAPC_V1(dapc, cfg) \
+	set_apusys_dapc_v1(dapc, ARRAY_SIZE(dapc), cfg)
+
+#define DUMP_APUSYS_DAPC_V1(apc) \
+	dump_apusys_dapc_v1(#apc, apc##_BASE, \
+			    (apc##_SLAVE_NUM / apc##_SLAVE_NUM_IN_1_DOM), apc##_DOM_NUM)
+
+enum apusys_apc_err_status set_apusys_dapc_v1(const struct apc_dom_16 *dapc,
+					      uint32_t size, dapc_cfg_func cfg);
+
+void dump_apusys_dapc_v1(const char *name, uintptr_t base, uint32_t reg_num, uint32_t dom_num);
+
+/******************************************************************************
+ * DAPC Permission Policy
+ ******************************************************************************/
+#define SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT(domain)		     \
+	APUSYS_APC_AO_ATTR(domain,					     \
+			   SEC_RW_ONLY, FORBIDDEN,     FORBIDDEN, FORBIDDEN, \
+			   FORBIDDEN,   NO_PROTECTION, FORBIDDEN, FORBIDDEN, \
+			   FORBIDDEN,   FORBIDDEN,     FORBIDDEN, FORBIDDEN, \
+			   FORBIDDEN,   FORBIDDEN,     FORBIDDEN, FORBIDDEN)
+
+#define SLAVE_FORBID_EXCEPT_D5_NO_PROTECT(domain)			   \
+	APUSYS_APC_AO_ATTR(domain,					   \
+			   FORBIDDEN, FORBIDDEN,     FORBIDDEN, FORBIDDEN, \
+			   FORBIDDEN, NO_PROTECTION, FORBIDDEN, FORBIDDEN, \
+			   FORBIDDEN, FORBIDDEN,     FORBIDDEN, FORBIDDEN, \
+			   FORBIDDEN, FORBIDDEN,     FORBIDDEN, FORBIDDEN)
+
+#define SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT(domain)	     \
+	APUSYS_APC_AO_ATTR(domain,					     \
+			   SEC_RW_NS_R, FORBIDDEN,     FORBIDDEN, FORBIDDEN, \
+			   FORBIDDEN,   NO_PROTECTION, FORBIDDEN, FORBIDDEN, \
+			   FORBIDDEN,   FORBIDDEN,     FORBIDDEN, FORBIDDEN, \
+			   FORBIDDEN,   FORBIDDEN,     FORBIDDEN, FORBIDDEN)
+
+#define SLAVE_FORBID_EXCEPT_D7_NO_PROTECT(domain)			   \
+	APUSYS_APC_AO_ATTR(domain,					   \
+			   FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,     \
+			   FORBIDDEN, FORBIDDEN, FORBIDDEN, NO_PROTECTION, \
+			   FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,     \
+			   FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN)
+
+#define SLAVE_FORBID_EXCEPT_D5_D7_NO_PROTECT(domain)			       \
+	APUSYS_APC_AO_ATTR(domain,					       \
+			   FORBIDDEN, FORBIDDEN,     FORBIDDEN, FORBIDDEN,     \
+			   FORBIDDEN, NO_PROTECTION, FORBIDDEN, NO_PROTECTION, \
+			   FORBIDDEN, FORBIDDEN,     FORBIDDEN, FORBIDDEN,     \
+			   FORBIDDEN, FORBIDDEN,     FORBIDDEN, FORBIDDEN)
+
+#define SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT(domain)			       \
+	APUSYS_APC_AO_ATTR(domain,					       \
+			   NO_PROTECTION, FORBIDDEN,     FORBIDDEN, FORBIDDEN, \
+			   FORBIDDEN,     NO_PROTECTION, FORBIDDEN, FORBIDDEN, \
+			   FORBIDDEN,     FORBIDDEN,     FORBIDDEN, FORBIDDEN, \
+			   FORBIDDEN,     FORBIDDEN,     FORBIDDEN, FORBIDDEN)
+
+#define SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW(domain)			 \
+	APUSYS_APC_AO_ATTR(domain,						 \
+			   NO_PROTECTION, FORBIDDEN,     FORBIDDEN, SEC_RW_ONLY, \
+			   FORBIDDEN,     NO_PROTECTION, FORBIDDEN, FORBIDDEN,   \
+			   FORBIDDEN,     FORBIDDEN,     FORBIDDEN, FORBIDDEN,   \
+			   FORBIDDEN,     FORBIDDEN,     FORBIDDEN, FORBIDDEN)
+
+#endif /* APUSYS_DAPC_V1_H */
diff --git a/plat/mediatek/drivers/apusys/devapc/rules.mk b/plat/mediatek/drivers/apusys/devapc/rules.mk
new file mode 100644
index 0000000..6153b31
--- /dev/null
+++ b/plat/mediatek/drivers/apusys/devapc/rules.mk
@@ -0,0 +1,13 @@
+#
+# Copyright (c) 2023, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+LOCAL_DIR := $(call GET_LOCAL_DIR)
+
+MODULE := apusys_devapc
+
+LOCAL_SRCS-y := ${LOCAL_DIR}/apusys_dapc_v1.c
+
+$(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.c b/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.c
new file mode 100644
index 0000000..9bdf875
--- /dev/null
+++ b/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* TF-A system header */
+#include <common/debug.h>
+#include <lib/utils_def.h>
+
+/* Vendor header */
+#include "apusys.h"
+#include "apusys_devapc.h"
+#include "apusys_devapc_def.h"
+#include <platform_def.h>
+
+#define DUMP_APUSYS_DAPC	(0)
+
+static const struct apc_dom_16 APU_CTRL_DAPC_AO[] = {
+	/* ctrl index = 0 */
+	SLAVE_VCORE("apu_ao_ctl_o-0"),
+	SLAVE_RPC("apu_ao_ctl_o-2"),
+	SLAVE_PCU("apu_ao_ctl_o-3"),
+	SLAVE_AO_CTRL("apu_ao_ctl_o-4"),
+	SLAVE_PLL("apu_ao_ctl_o-5"),
+	SLAVE_ACC("apu_ao_ctl_o-6"),
+	SLAVE_SEC("apu_ao_ctl_o-7"),
+	SLAVE_ARE0("apu_ao_ctl_o-8"),
+	SLAVE_ARE1("apu_ao_ctl_o-9"),
+	SLAVE_ARE2("apu_ao_ctl_o-10"),
+
+	/* ctrl index = 10 */
+	SLAVE_UNKNOWN("apu_ao_ctl_o-11"),
+	SLAVE_AO_BCRM("apu_ao_ctl_o-12"),
+	SLAVE_AO_DAPC_WRAP("apu_ao_ctl_o-13"),
+	SLAVE_AO_DAPC_CON("apu_ao_ctl_o-14"),
+	SLAVE_RCX_ACX_BULK("apu_ao_ctl_o-15"),
+	SLAVE_UNKNOWN("apu_ao_ctl_o-16"),
+	SLAVE_UNKNOWN("apu_ao_ctl_o-17"),
+	SLAVE_APU_BULK("apu_ao_ctl_o-18"),
+	SLAVE_ACX0_BCRM("apu_ao_ctl_o-20"),
+	SLAVE_RPCTOP_LITE_ACX0("apu_ao_ctl_o-21"),
+
+	/* ctrl index = 20 */
+	SLAVE_ACX1_BCRM("apu_ao_ctl_o-22"),
+	SLAVE_RPCTOP_LITE_ACX1("apu_ao_ctl_o-23"),
+	SLAVE_RCX_TO_ACX0_0("apu_rcx2acx0_o-0"),
+	SLAVE_RCX_TO_ACX0_1("apu_rcx2acx0_o-1"),
+	SLAVE_SAE_TO_ACX0_0("apu_sae2acx0_o-0"),
+	SLAVE_SAE_TO_ACX0_1("apu_sae2acx0_o-1"),
+	SLAVE_RCX_TO_ACX1_0("apu_rcx2acx1_o-0"),
+	SLAVE_RCX_TO_ACX1_1("apu_rcx2acx1_o-1"),
+	SLAVE_SAE_TO_ACX1_0("apu_sae2acx1_o-0"),
+	SLAVE_SAE_TO_ACX1_1("apu_sae2acx1_o-1"),
+};
+
+static enum apusys_apc_err_status set_slave_ao_ctrl_apc(uint32_t slave,
+							enum apusys_apc_domain_id domain_id,
+							enum apusys_apc_perm_type perm)
+{
+	uint32_t apc_register_index;
+	uint32_t apc_set_index;
+	uint32_t base;
+	uint32_t clr_bit;
+	uint32_t set_bit;
+
+	if ((perm < 0) || (perm >= PERM_NUM)) {
+		ERROR(MODULE_TAG "%s: permission type:0x%x is not supported!\n", __func__, perm);
+		return APUSYS_APC_ERR_GENERIC;
+	}
+
+	if ((slave >= APU_CTRL_DAPC_AO_SLAVE_NUM) ||
+	    ((domain_id < 0) || (domain_id >= APU_CTRL_DAPC_AO_DOM_NUM))) {
+		ERROR(MODULE_TAG "%s: out of boundary, slave:0x%x, domain_id:0x%x\n",
+		      __func__, slave, domain_id);
+		return APUSYS_APC_ERR_GENERIC;
+	}
+
+	apc_register_index = slave / APU_CTRL_DAPC_AO_SLAVE_NUM_IN_1_DOM;
+	apc_set_index = slave % APU_CTRL_DAPC_AO_SLAVE_NUM_IN_1_DOM;
+
+	clr_bit = (DEVAPC_MASK << (apc_set_index * DEVAPC_DOM_SHIFT));
+	set_bit = (uint32_t)perm << (apc_set_index * DEVAPC_DOM_SHIFT);
+
+	base = (APU_CTRL_DAPC_AO_BASE + domain_id * DEVAPC_DOM_SIZE +
+		apc_register_index * DEVAPC_REG_SIZE);
+
+	mmio_clrsetbits_32(base, clr_bit, set_bit);
+	return APUSYS_APC_OK;
+}
+
+static void apusys_devapc_init(const char *name, uint32_t base)
+{
+	mmio_write_32(APUSYS_DAPC_CON(base), APUSYS_DAPC_CON_VIO_MASK);
+}
+
+int apusys_devapc_ao_init(void)
+{
+	enum apusys_apc_err_status ret;
+
+	apusys_devapc_init("APUAPC_CTRL_AO", APU_CTRL_DAPC_AO_BASE);
+
+	ret = SET_APUSYS_DAPC_V1(APU_CTRL_DAPC_AO, set_slave_ao_ctrl_apc);
+	if (ret != APUSYS_APC_OK) {
+		ERROR(MODULE_TAG "%s: set_apusys_ao_ctrl_dap FAILED!\n", __func__);
+		return -1;
+	}
+
+#if DUMP_APUSYS_DAPC
+	DUMP_APUSYS_DAPC_V1(APU_CTRL_DAPC_AO);
+#endif
+
+	return 0;
+}
diff --git a/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.h b/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.h
new file mode 100644
index 0000000..345705c
--- /dev/null
+++ b/plat/mediatek/drivers/apusys/mt8188/apusys_devapc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef APUSYS_DEVAPC_H
+#define APUSYS_DEVAPC_H
+
+int apusys_devapc_ao_init(void);
+
+#endif /* APUSYS_DEVAPC_H */
diff --git a/plat/mediatek/drivers/apusys/mt8188/apusys_devapc_def.h b/plat/mediatek/drivers/apusys/mt8188/apusys_devapc_def.h
new file mode 100644
index 0000000..3fe69d2
--- /dev/null
+++ b/plat/mediatek/drivers/apusys/mt8188/apusys_devapc_def.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef APUSYS_DEVAPC_DEF_H
+#define APUSYS_DEVAPC_DEF_H
+
+#include <lib/mmio.h>
+#include "../devapc/apusys_dapc_v1.h"
+
+/* Control */
+#define SLAVE_VCORE		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_RPC		SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT
+#define SLAVE_PCU		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_AO_CTRL		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_PLL		SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT
+#define SLAVE_ACC		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_SEC		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_ARE0		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_ARE1		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_ARE2		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_UNKNOWN		SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_APU_BULK		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_AO_BCRM		SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_AO_DAPC_WRAP	SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_AO_DAPC_CON	SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_RCX_ACX_BULK	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW
+#define SLAVE_ACX0_BCRM		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW
+#define SLAVE_RPCTOP_LITE_ACX0	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_ACX1_BCRM		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW
+#define SLAVE_RPCTOP_LITE_ACX1	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_RCX_TO_ACX0_0	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW
+#define SLAVE_RCX_TO_ACX0_1	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_SAE_TO_ACX0_0	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW
+#define SLAVE_SAE_TO_ACX0_1	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_RCX_TO_ACX1_0	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_RCX_TO_ACX1_1	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_SAE_TO_ACX1_0	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_SAE_TO_ACX1_1	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+
+/* Power Domain: AO */
+#define APU_CTRL_DAPC_AO_SLAVE_NUM_IN_1_DOM	(16)
+#define APU_CTRL_DAPC_AO_DOM_NUM		(16)
+#define APU_CTRL_DAPC_AO_SLAVE_NUM		(30)
+#define DEVAPC_MASK				(0x3U)
+#define DEVAPC_DOM_SHIFT			(2)
+
+#endif /* APUSYS_DEVAPC_DEF_H */
diff --git a/plat/mediatek/drivers/apusys/mt8188/rules.mk b/plat/mediatek/drivers/apusys/mt8188/rules.mk
index f676b6e..1e6d9b4 100644
--- a/plat/mediatek/drivers/apusys/mt8188/rules.mk
+++ b/plat/mediatek/drivers/apusys/mt8188/rules.mk
@@ -8,6 +8,7 @@
 
 MODULE := apusys_${MTK_SOC}
 
-LOCAL_SRCS-y := ${LOCAL_DIR}/apusys_power.c
+LOCAL_SRCS-y := ${LOCAL_DIR}/apusys_devapc.c
+LOCAL_SRCS-y += ${LOCAL_DIR}/apusys_power.c
 
 $(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
diff --git a/plat/mediatek/drivers/apusys/rules.mk b/plat/mediatek/drivers/apusys/rules.mk
index 1aa67bc..c572d3c 100644
--- a/plat/mediatek/drivers/apusys/rules.mk
+++ b/plat/mediatek/drivers/apusys/rules.mk
@@ -15,5 +15,6 @@
 $(eval $(call MAKE_MODULE,$(MODULE),$(LOCAL_SRCS-y),$(MTK_BL)))
 
 SUB_RULES-y := ${LOCAL_DIR}/${MTK_SOC}
+SUB_RULES-y += ${LOCAL_DIR}/devapc
 
 $(eval $(call INCLUDE_MAKEFILE,$(SUB_RULES-y)))
diff --git a/plat/mediatek/mt8188/include/platform_def.h b/plat/mediatek/mt8188/include/platform_def.h
index 73b0ed3..7138c7a 100644
--- a/plat/mediatek/mt8188/include/platform_def.h
+++ b/plat/mediatek/mt8188/include/platform_def.h
@@ -39,6 +39,7 @@
 #define APU_ARETOP_ARE0		(IO_PHYS + 0x090f6000)
 #define APU_ARETOP_ARE1		(IO_PHYS + 0x090f7000)
 #define APU_ARETOP_ARE2		(IO_PHYS + 0x090f8000)
+#define APU_CTRL_DAPC_AO_BASE	(IO_PHYS + 0x090fc000)
 #define APU_ACX0_RPC_LITE	(IO_PHYS + 0x09140000)
 #define BCRM_FMEM_PDN_SIZE	(0x1000)