diff --git a/plat/mediatek/drivers/apusys/mt8188/apusys_devapc_def.h b/plat/mediatek/drivers/apusys/mt8188/apusys_devapc_def.h
new file mode 100644
index 0000000..3fe69d2
--- /dev/null
+++ b/plat/mediatek/drivers/apusys/mt8188/apusys_devapc_def.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2023, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef APUSYS_DEVAPC_DEF_H
+#define APUSYS_DEVAPC_DEF_H
+
+#include <lib/mmio.h>
+#include "../devapc/apusys_dapc_v1.h"
+
+/* Control */
+#define SLAVE_VCORE		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_RPC		SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT
+#define SLAVE_PCU		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_AO_CTRL		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_PLL		SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT
+#define SLAVE_ACC		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_SEC		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_ARE0		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_ARE1		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_ARE2		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_UNKNOWN		SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_APU_BULK		SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_AO_BCRM		SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_AO_DAPC_WRAP	SLAVE_FORBID_EXCEPT_D5_NO_PROTECT
+#define SLAVE_AO_DAPC_CON	SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT
+#define SLAVE_RCX_ACX_BULK	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW
+#define SLAVE_ACX0_BCRM		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW
+#define SLAVE_RPCTOP_LITE_ACX0	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_ACX1_BCRM		SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW
+#define SLAVE_RPCTOP_LITE_ACX1	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_RCX_TO_ACX0_0	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW
+#define SLAVE_RCX_TO_ACX0_1	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_SAE_TO_ACX0_0	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT_D3_SEC_RW
+#define SLAVE_SAE_TO_ACX0_1	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_RCX_TO_ACX1_0	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_RCX_TO_ACX1_1	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_SAE_TO_ACX1_0	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+#define SLAVE_SAE_TO_ACX1_1	SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT
+
+/* Power Domain: AO */
+#define APU_CTRL_DAPC_AO_SLAVE_NUM_IN_1_DOM	(16)
+#define APU_CTRL_DAPC_AO_DOM_NUM		(16)
+#define APU_CTRL_DAPC_AO_SLAVE_NUM		(30)
+#define DEVAPC_MASK				(0x3U)
+#define DEVAPC_DOM_SHIFT			(2)
+
+#endif /* APUSYS_DEVAPC_DEF_H */