refactor(neoverse-rd): move defines out of platform_def.h
Presently, A75/V1/N1 CPU based platforms have platform port specific
macros defined within their platform_def.h file. To enhance organization
and appropriateness, relocate these definitions to
nrd_arm_platform_def1.h.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I1f55192185df1509756bc2ef022e5aed0724dd05
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h
index 06b532d..0827f98 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h
@@ -35,6 +35,20 @@
NRD_MAX_PE_PER_CPU)
/*******************************************************************************
+ * PA/VA config
+ ******************************************************************************/
+
+#ifdef __aarch64__
+#define PLAT_PHY_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
+ NRD_CHIP_COUNT)
+#define PLAT_VIRT_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
+ NRD_CHIP_COUNT)
+#else
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
+#endif
+
+/*******************************************************************************
* XLAT definitions
******************************************************************************/
@@ -173,6 +187,13 @@
#define PLAT_ARM_NSTIMER_FRAME_ID (0)
/*******************************************************************************
+ * Power config
+ ******************************************************************************/
+
+#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
+#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
+
+/*******************************************************************************
* Flash config
******************************************************************************/
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h
index 27fc628..65ad5f5 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h
+++ b/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h
@@ -27,30 +27,12 @@
#define RDN1EDGE_DMC620_BASE0 UL(0x4e000000)
#define RDN1EDGE_DMC620_BASE1 UL(0x4e100000)
-/* System power domain level */
-#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
-
-#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
-
/* Virtual address used by dynamic mem_protect for chunk_base */
#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
/* Maximum number of address bits used per chip */
#define NRD_ADDR_BITS_PER_CHIP U(42)
-/*
- * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
- */
-#ifdef __aarch64__
-#define PLAT_PHY_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
- NRD_CHIP_COUNT)
-#define PLAT_VIRT_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
- NRD_CHIP_COUNT)
-#else
-#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
-#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
-#endif
-
/* GIC related constants */
#define PLAT_ARM_GICD_BASE UL(0x30000000)
#define PLAT_ARM_GICC_BASE UL(0x2C000000)
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h
index d92508a..b0aa5e7 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h
+++ b/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h
@@ -23,9 +23,6 @@
#define PLAT_CSS_MHU_BASE UL(0x45400000)
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
-#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
-#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
-
/* TZC Related Constants */
#define PLAT_ARM_TZC_BASE UL(0x21830000)
#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0)
@@ -54,17 +51,6 @@
/* Maximum number of address bits used per chip */
#define NRD_ADDR_BITS_PER_CHIP U(42)
-/*
- * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
- */
-#ifdef __aarch64__
-#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << NRD_ADDR_BITS_PER_CHIP)
-#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << NRD_ADDR_BITS_PER_CHIP)
-#else
-#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
-#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
-#endif
-
/* GIC related constants */
#define PLAT_ARM_GICD_BASE UL(0x30000000)
#define PLAT_ARM_GICC_BASE UL(0x2C000000)
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h
index 7814379..bcf4257 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h
+++ b/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h
@@ -23,9 +23,6 @@
#define PLAT_CSS_MHU_BASE UL(0x45400000)
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
-#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
-#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
-
/* TZC Related Constants */
#define PLAT_ARM_TZC_BASE UL(0x21830000)
#define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \
@@ -55,12 +52,6 @@
/* Remote chip address offset (4TB per chip) */
#define NRD_ADDR_BITS_PER_CHIP U(42)
-/* Physical and virtual address space limits for MMU in AARCH64 mode */
-#define PLAT_PHY_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
- NRD_CHIP_COUNT)
-#define PLAT_VIRT_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
- NRD_CHIP_COUNT)
-
/* GIC related constants */
#define PLAT_ARM_GICD_BASE UL(0x30000000)
#define PLAT_ARM_GICC_BASE UL(0x2C000000)
diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/sgi575/include/platform_def.h
index bb21476..9c2ef89 100644
--- a/plat/arm/board/neoverse_rd/platform/sgi575/include/platform_def.h
+++ b/plat/arm/board/neoverse_rd/platform/sgi575/include/platform_def.h
@@ -27,25 +27,9 @@
#define SGI575_DMC620_BASE0 UL(0x4e000000)
#define SGI575_DMC620_BASE1 UL(0x4e100000)
-/* System power domain level */
-#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
-
-#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
-
/* Maximum number of address bits used per chip */
#define NRD_ADDR_BITS_PER_CHIP U(36)
-/*
- * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
- */
-#ifdef __aarch64__
-#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << NRD_ADDR_BITS_PER_CHIP)
-#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << NRD_ADDR_BITS_PER_CHIP)
-#else
-#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
-#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
-#endif
-
/* GIC related constants */
#define PLAT_ARM_GICD_BASE UL(0x30000000)
#define PLAT_ARM_GICC_BASE UL(0x2C000000)