Tegra194: memctrl: platform handlers to reprogram MSS
Introduce platform handlers to reprogram the MSS settings.
Change-Id: Ibb9a5457d1bad9ecccea619d69a62bed3bf7d861
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h
index 3d2eee5..bdfa051 100644
--- a/plat/nvidia/tegra/include/t194/tegra_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_def.h
@@ -51,45 +51,6 @@
#define MISCREG_PFCFG 0x200CU
/*******************************************************************************
- * Tegra TSA Controller constants
- ******************************************************************************/
-#define TEGRA_TSA_BASE 0x02000000
-
-#define TSA_CONFIG_STATIC0_CSW_SESWR 0x1010
-#define TSA_CONFIG_STATIC0_CSW_SESWR_RESET 0x1100
-#define TSA_CONFIG_STATIC0_CSW_ETRW 0xD034
-#define TSA_CONFIG_STATIC0_CSW_ETRW_RESET 0x1100
-#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x3020
-#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET 0x1100
-#define TSA_CONFIG_STATIC0_CSW_AXISW 0x8008
-#define TSA_CONFIG_STATIC0_CSW_AXISW_RESET 0x1100
-#define TSA_CONFIG_STATIC0_CSW_HDAW 0xD008
-#define TSA_CONFIG_STATIC0_CSW_HDAW_RESET 0x1100
-#define TSA_CONFIG_STATIC0_CSW_AONDMAW 0xE018
-#define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET 0x1100
-#define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0x9008
-#define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET 0x1100
-#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0x9028
-#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET 0x1100
-#define TSA_CONFIG_STATIC0_CSW_APEDMAW 0xB008
-#define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET 0x1100
-#define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x6008
-#define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET 0x1100
-#define TSA_CONFIG_STATIC0_CSW_AFIW 0xF008
-#define TSA_CONFIG_STATIC0_CSW_AFIW_RESET 0x1100
-#define TSA_CONFIG_STATIC0_CSW_SATAW 0x4008
-#define TSA_CONFIG_STATIC0_CSW_SATAW_RESET 0x1100
-#define TSA_CONFIG_STATIC0_CSW_EQOSW 0x3038
-#define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET 0x1100
-#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x6018
-#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET 0x1100
-#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x6028
-#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET 0x1100
-
-#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (0x3 << 11)
-#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (0 << 11)
-
-/*******************************************************************************
* Tegra Memory Controller constants
******************************************************************************/
#define TEGRA_MC_STREAMID_BASE 0x02C00000
@@ -137,7 +98,6 @@
#define MC_TZRAM_CLIENT_ACCESS_CFG0 0x21A0
/* Memory Controller Reset Control registers */
-#define MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB (1 << 27)
#define MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB (1 << 28)
#define MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB (1 << 29)
#define MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB (1 << 30)
@@ -229,143 +189,6 @@
#define GPU_RESET_BIT (1UL << 0)
/*******************************************************************************
- * Stream ID Override Config registers
- ******************************************************************************/
-#define MC_STREAMID_OVERRIDE_CFG_ISPFALR 0x228U
-#define MC_STREAMID_OVERRIDE_CFG_AXIAPR 0x410U
-#define MC_STREAMID_OVERRIDE_CFG_AXIAPW 0x418U
-#define MC_STREAMID_OVERRIDE_CFG_MIU0R 0x530U
-#define MC_STREAMID_OVERRIDE_CFG_MIU0W 0x538U
-#define MC_STREAMID_OVERRIDE_CFG_MIU1R 0x540U
-#define MC_STREAMID_OVERRIDE_CFG_MIU1W 0x548U
-#define MC_STREAMID_OVERRIDE_CFG_MIU2R 0x570U
-#define MC_STREAMID_OVERRIDE_CFG_MIU2W 0x578U
-#define MC_STREAMID_OVERRIDE_CFG_MIU3R 0x580U
-#define MC_STREAMID_OVERRIDE_CFG_MIU3W 0x588U
-#define MC_STREAMID_OVERRIDE_CFG_VIFALR 0x5E0U
-#define MC_STREAMID_OVERRIDE_CFG_VIFALW 0x5E8U
-#define MC_STREAMID_OVERRIDE_CFG_DLA0RDA 0x5F0U
-#define MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB 0x5F8U
-#define MC_STREAMID_OVERRIDE_CFG_DLA0WRA 0x600U
-#define MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB 0x608U
-#define MC_STREAMID_OVERRIDE_CFG_DLA1RDA 0x610U
-#define MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB 0x618U
-#define MC_STREAMID_OVERRIDE_CFG_DLA1WRA 0x620U
-#define MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB 0x628U
-#define MC_STREAMID_OVERRIDE_CFG_PVA0RDA 0x630U
-#define MC_STREAMID_OVERRIDE_CFG_PVA0RDB 0x638U
-#define MC_STREAMID_OVERRIDE_CFG_PVA0RDC 0x640U
-#define MC_STREAMID_OVERRIDE_CFG_PVA0WRA 0x648U
-#define MC_STREAMID_OVERRIDE_CFG_PVA0WRB 0x650U
-#define MC_STREAMID_OVERRIDE_CFG_PVA0WRC 0x658U
-#define MC_STREAMID_OVERRIDE_CFG_PVA1RDA 0x660U
-#define MC_STREAMID_OVERRIDE_CFG_PVA1RDB 0x668U
-#define MC_STREAMID_OVERRIDE_CFG_PVA1RDC 0x670U
-#define MC_STREAMID_OVERRIDE_CFG_PVA1WRA 0x678U
-#define MC_STREAMID_OVERRIDE_CFG_PVA1WRB 0x680U
-#define MC_STREAMID_OVERRIDE_CFG_PVA1WRC 0x688U
-#define MC_STREAMID_OVERRIDE_CFG_RCER 0x690U
-#define MC_STREAMID_OVERRIDE_CFG_RCEW 0x698U
-#define MC_STREAMID_OVERRIDE_CFG_RCEDMAR 0x6A0U
-#define MC_STREAMID_OVERRIDE_CFG_RCEDMAW 0x6A8U
-#define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD 0x6B0U
-#define MC_STREAMID_OVERRIDE_CFG_NVENC1SWR 0x6B8U
-#define MC_STREAMID_OVERRIDE_CFG_PCIE0R 0x6C0U
-#define MC_STREAMID_OVERRIDE_CFG_PCIE0W 0x6C8U
-#define MC_STREAMID_OVERRIDE_CFG_PCIE1R 0x6D0U
-#define MC_STREAMID_OVERRIDE_CFG_PCIE1W 0x6D8U
-#define MC_STREAMID_OVERRIDE_CFG_PCIE2AR 0x6E0U
-#define MC_STREAMID_OVERRIDE_CFG_PCIE2AW 0x6E8U
-#define MC_STREAMID_OVERRIDE_CFG_PCIE3R 0x6F0U
-#define MC_STREAMID_OVERRIDE_CFG_PCIE3W 0x6F8U
-#define MC_STREAMID_OVERRIDE_CFG_PCIE4R 0x700U
-#define MC_STREAMID_OVERRIDE_CFG_PCIE4W 0x708U
-#define MC_STREAMID_OVERRIDE_CFG_PCIE5R 0x710U
-#define MC_STREAMID_OVERRIDE_CFG_PCIE5W 0x718U
-#define MC_STREAMID_OVERRIDE_CFG_ISPFALW 0x720U
-#define MC_STREAMID_OVERRIDE_CFG_DLA0RDA1 0x748U
-#define MC_STREAMID_OVERRIDE_CFG_DLA1RDA1 0x750U
-#define MC_STREAMID_OVERRIDE_CFG_PVA0RDA1 0x758U
-#define MC_STREAMID_OVERRIDE_CFG_PVA0RDB1 0x760U
-#define MC_STREAMID_OVERRIDE_CFG_PVA1RDA1 0x768U
-#define MC_STREAMID_OVERRIDE_CFG_PVA1RDB1 0x770U
-#define MC_STREAMID_OVERRIDE_CFG_PCIE5R1 0x778U
-#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD1 0x780U
-#define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1 0x788U
-#define MC_STREAMID_OVERRIDE_CFG_ISPRA1 0x790U
-#define MC_STREAMID_OVERRIDE_CFG_PCIE0R1 0x798U
-#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD 0x7C8U
-#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD1 0x7D0U
-#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SWR 0x7D8U
-
-/*******************************************************************************
- * Memory Controller transaction override config registers
- ******************************************************************************/
-#define MC_TXN_OVERRIDE_CONFIG_MIU0R 0x1530
-#define MC_TXN_OVERRIDE_CONFIG_MIU0W 0x1538
-#define MC_TXN_OVERRIDE_CONFIG_MIU1R 0x1540
-#define MC_TXN_OVERRIDE_CONFIG_MIU1W 0x1548
-#define MC_TXN_OVERRIDE_CONFIG_MIU2R 0x1570
-#define MC_TXN_OVERRIDE_CONFIG_MIU2W 0x1578
-#define MC_TXN_OVERRIDE_CONFIG_MIU3R 0x1580
-#define MC_TXN_OVERRIDE_CONFIG_MIU3W 0x158C
-#define MC_TXN_OVERRIDE_CONFIG_VIFALR 0x15E4
-#define MC_TXN_OVERRIDE_CONFIG_VIFALW 0x15EC
-#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA 0x15F4
-#define MC_TXN_OVERRIDE_CONFIG_DLA0FALRDB 0x15FC
-#define MC_TXN_OVERRIDE_CONFIG_DLA0WRA 0x1604
-#define MC_TXN_OVERRIDE_CONFIG_DLA0FALWRB 0x160C
-#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA 0x1614
-#define MC_TXN_OVERRIDE_CONFIG_DLA1FALRDB 0x161C
-#define MC_TXN_OVERRIDE_CONFIG_DLA1WRA 0x1624
-#define MC_TXN_OVERRIDE_CONFIG_DLA1FALWRB 0x162C
-#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA 0x1634
-#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB 0x163C
-#define MC_TXN_OVERRIDE_CONFIG_PVA0RDC 0x1644
-#define MC_TXN_OVERRIDE_CONFIG_PVA0WRA 0x164C
-#define MC_TXN_OVERRIDE_CONFIG_PVA0WRB 0x1654
-#define MC_TXN_OVERRIDE_CONFIG_PVA0WRC 0x165C
-#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA 0x1664
-#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB 0x166C
-#define MC_TXN_OVERRIDE_CONFIG_PVA1RDC 0x1674
-#define MC_TXN_OVERRIDE_CONFIG_PVA1WRA 0x167C
-#define MC_TXN_OVERRIDE_CONFIG_PVA1WRB 0x1684
-#define MC_TXN_OVERRIDE_CONFIG_PVA1WRC 0x168C
-#define MC_TXN_OVERRIDE_CONFIG_RCER 0x1694
-#define MC_TXN_OVERRIDE_CONFIG_RCEW 0x169C
-#define MC_TXN_OVERRIDE_CONFIG_RCEDMAR 0x16A4
-#define MC_TXN_OVERRIDE_CONFIG_RCEDMAW 0x16AC
-#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD 0x16B4
-#define MC_TXN_OVERRIDE_CONFIG_NVENC1SWR 0x16BC
-#define MC_TXN_OVERRIDE_CONFIG_PCIE0R 0x16C4
-#define MC_TXN_OVERRIDE_CONFIG_PCIE0W 0x16CC
-#define MC_TXN_OVERRIDE_CONFIG_PCIE1R 0x16D4
-#define MC_TXN_OVERRIDE_CONFIG_PCIE1W 0x16DC
-#define MC_TXN_OVERRIDE_CONFIG_PCIE2AR 0x16E4
-#define MC_TXN_OVERRIDE_CONFIG_PCIE2AW 0x16EC
-#define MC_TXN_OVERRIDE_CONFIG_PCIE3R 0x16F4
-#define MC_TXN_OVERRIDE_CONFIG_PCIE3W 0x16FC
-#define MC_TXN_OVERRIDE_CONFIG_PCIE4R 0x1704
-#define MC_TXN_OVERRIDE_CONFIG_PCIE4W 0x170C
-#define MC_TXN_OVERRIDE_CONFIG_PCIE5R 0x1714
-#define MC_TXN_OVERRIDE_CONFIG_PCIE5W 0x171C
-#define MC_TXN_OVERRIDE_CONFIG_ISPFALW 0x1724
-#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA1 0x174C
-#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA1 0x1754
-#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA1 0x175C
-#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB1 0x1764
-#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA1 0x176C
-#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB1 0x1774
-#define MC_TXN_OVERRIDE_CONFIG_PCIE5R1 0x177C
-#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD1 0x1784
-#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD1 0x178C
-#define MC_TXN_OVERRIDE_CONFIG_ISPRA1 0x1794
-#define MC_TXN_OVERRIDE_CONFIG_PCIE0R1 0x179C
-#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD 0x17CC
-#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD1 0x17D4
-#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SWR 0x17DC
-
-/*******************************************************************************
* XUSB PADCTL
******************************************************************************/
#define TEGRA_XUSB_PADCTL_BASE (0x3520000U)
diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c
index 0a39ef1..a9341b1 100644
--- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c
+++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c
@@ -4,8 +4,12 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include <bl_common.h>
+#include <assert.h>
+#include <common/bl_common.h>
+#include <mce.h>
#include <memctrl_v2.h>
+#include <tegra_mc_def.h>
+#include <tegra_platform.h>
/*******************************************************************************
* Array to hold stream_id override config register offsets
@@ -297,6 +301,325 @@
mc_make_txn_override_cfg(SCEDMAW, CGID_TAG_ADR),
};
+/* To be called by common memctrl_v2.c */
+static void tegra194_memctrl_reconfig_mss_clients(void)
+{
+ uint32_t reg_val, wdata_0, wdata_1, wdata_2;
+
+ wdata_0 = MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB;
+ if (tegra_platform_is_silicon()) {
+ wdata_0 |= MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB;
+ }
+
+ tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0);
+
+ /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
+ do {
+ reg_val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0);
+ } while ((reg_val & wdata_0) != wdata_0);
+
+ wdata_1 = MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB|
+ MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB;
+ if (tegra_platform_is_silicon()) {
+ wdata_1 |= MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL1_RCE_FLUSH_ENB;
+ }
+ tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1);
+ /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
+ do {
+ reg_val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1);
+ } while ((reg_val & wdata_1) != wdata_1);
+
+ wdata_2 = MC_CLIENT_HOTRESET_CTRL2_PCIE_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL2_AONDMA_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL2_BPMPDMA_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL2_SCEDMA_FLUSH_ENB;
+ if (tegra_platform_is_silicon()) {
+ wdata_2 |= MC_CLIENT_HOTRESET_CTRL2_RCEDMA_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL2_PCIE_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL2_PCIE5A_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL2_PCIE3A_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL2_PCIE3_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL2_PCIE0A_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL2_PCIE0A2_FLUSH_ENB |
+ MC_CLIENT_HOTRESET_CTRL2_PCIE4A_FLUSH_ENB;
+ }
+ tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL2, wdata_2);
+ /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
+ do {
+ reg_val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS2);
+ } while ((reg_val & wdata_2) != wdata_2);
+
+ /*
+ * Change MEMTYPE_OVERRIDE from SO_DEV -> PASSTHRU for boot and
+ * strongly ordered MSS clients.
+ *
+ * MC clients with default SO_DEV override still enabled at TSA:
+ * EQOSW, SATAW, XUSB_DEVW, XUSB_HOSTW, PCIe0w, PCIe1w, PCIe2w,
+ * PCIe3w, PCIe4w and PCIe5w.
+ */
+ mc_set_tsa_w_passthrough(AONDMAW);
+ mc_set_tsa_w_passthrough(AONW);
+ mc_set_tsa_w_passthrough(APEDMAW);
+ mc_set_tsa_w_passthrough(APEW);
+ mc_set_tsa_w_passthrough(AXISW);
+ mc_set_tsa_w_passthrough(BPMPDMAW);
+ mc_set_tsa_w_passthrough(BPMPW);
+ mc_set_tsa_w_passthrough(ETRW);
+ mc_set_tsa_w_passthrough(SCEDMAW);
+ mc_set_tsa_w_passthrough(RCEDMAW);
+ mc_set_tsa_w_passthrough(RCEW);
+ mc_set_tsa_w_passthrough(SDMMCW);
+ mc_set_tsa_w_passthrough(SDMMCWA);
+ mc_set_tsa_w_passthrough(SDMMCWAB);
+ mc_set_tsa_w_passthrough(SESWR);
+ mc_set_tsa_w_passthrough(TSECSWR);
+ mc_set_tsa_w_passthrough(TSECSWRB);
+ mc_set_tsa_w_passthrough(UFSHCW);
+ mc_set_tsa_w_passthrough(VICSWR);
+ mc_set_tsa_w_passthrough(VIFALW);
+
+ /* Ordered MC Clients on Xavier are EQOS, SATA, XUSB, PCIe1 and PCIe3
+ * ISO clients(DISP, VI, EQOS) should never snoop caches and
+ * don't need ROC/PCFIFO ordering.
+ * ISO clients(EQOS) that need ordering should use PCFIFO ordering
+ * and bypass ROC ordering by using FORCE_NON_COHERENT path.
+ * FORCE_NON_COHERENT/FORCE_COHERENT config take precedence
+ * over SMMU attributes.
+ * Force all Normal memory transactions from ISO and non-ISO to be
+ * non-coherent(bypass ROC, avoid cache snoop to avoid perf hit).
+ * Force the SO_DEV transactions from ordered ISO clients(EQOS) to
+ * non-coherent path and enable MC PCFIFO interlock for ordering.
+ * Force the SO_DEV transactions from ordered non-ISO clients (PCIe,
+ * XUSB, SATA) to coherent so that the transactions are
+ * ordered by ROC.
+ * PCFIFO ensure write ordering.
+ * Read after Write ordering is maintained/enforced by MC clients.
+ * Clients that need PCIe type write ordering must
+ * go through ROC ordering.
+ * Ordering enable for Read clients is not necessary.
+ * R5's and A9 would get necessary ordering from AXI and
+ * don't need ROC ordering enable:
+ * - MMIO ordering is through dev mapping and MMIO
+ * accesses bypass SMMU.
+ * - Normal memory is accessed through SMMU and ordering is
+ * ensured by client and AXI.
+ * - Ack point for Normal memory is WCAM in MC.
+ * - MMIO's can be early acked and AXI ensures dev memory ordering,
+ * Client ensures read/write direction change ordering.
+ * - See Bug 200312466 for more details.
+ *
+ * CGID_TAG_ADR is only present from T186 A02. As this code is common
+ * between A01 and A02, tegra_memctrl_set_overrides() programs
+ * CGID_TAG_ADR for the necessary clients on A02.
+ */
+ mc_set_txn_override(AONDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(AONDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(AONR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(AONW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(APEDMAR, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(APEDMAW, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(APER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(APEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(AXISR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(AXISW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(BPMPDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(BPMPDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(BPMPR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(BPMPW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(EQOSR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(EQOSW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
+ mc_set_txn_override(ETRR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(ETRW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(HOST1XDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(MPCORER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(MPCOREW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(NVDISPLAYR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
+ mc_set_txn_override(PTCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
+ mc_set_txn_override(SATAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(SATAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP);
+ mc_set_txn_override(SCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(SCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(SCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(SCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(RCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(RCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(RCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(RCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(SDMMCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(SDMMCRAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(SDMMCRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(SDMMCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(SDMMCWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(SDMMCWAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(SESRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(SESWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(TSECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(TSECSRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(TSECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(TSECSWRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(UFSHCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(UFSHCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(VICSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(VICSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(VICSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(VIFALR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(VIFALW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(XUSB_DEVR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(XUSB_DEVW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT,
+ FORCE_COHERENT_SNOOP);
+ mc_set_txn_override(XUSB_HOSTR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(XUSB_HOSTW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT,
+ FORCE_COHERENT_SNOOP);
+ mc_set_txn_override(PCIE0R, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(PCIE0R1, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(PCIE0W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT,
+ FORCE_COHERENT_SNOOP);
+ mc_set_txn_override(PCIE1R, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(PCIE1W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT,
+ FORCE_COHERENT_SNOOP);
+ if (tegra_platform_is_silicon()) {
+ mc_set_txn_override(PCIE2AR, CGID_TAG_DEFAULT, SO_DEV_ZERO,
+ NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(PCIE2AW, CGID_TAG_DEFAULT, SO_DEV_ZERO,
+ FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP);
+ mc_set_txn_override(PCIE3R, CGID_TAG_DEFAULT, SO_DEV_ZERO,
+ NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(PCIE3W, CGID_TAG_DEFAULT, SO_DEV_ZERO,
+ FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP);
+ mc_set_txn_override(PCIE4R, CGID_TAG_DEFAULT, SO_DEV_ZERO,
+ NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(PCIE4W, CGID_TAG_DEFAULT, SO_DEV_ZERO,
+ FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP);
+ mc_set_txn_override(PCIE5R, CGID_TAG_DEFAULT, SO_DEV_ZERO,
+ NO_OVERRIDE, NO_OVERRIDE);
+ mc_set_txn_override(PCIE5W, CGID_TAG_DEFAULT, SO_DEV_ZERO,
+ FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP);
+ mc_set_txn_override(PCIE5R1, CGID_TAG_DEFAULT, SO_DEV_ZERO,
+ NO_OVERRIDE, NO_OVERRIDE);
+ }
+ /*
+ * At this point, ordering can occur at ROC. So, remove PCFIFO's
+ * control over ordering requests.
+ *
+ * Change PCFIFO_*_ORDERED_CLIENT from ORDERED -> UNORDERED for
+ * boot and strongly ordered MSS clients
+ */
+ /* SATAW is ordered client */
+ reg_val = MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL |
+ mc_set_pcfifo_ordered_boot_so_mss(1, SATAW);
+ tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG1, reg_val);
+
+ reg_val = MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL &
+ mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_HOSTW) &
+ mc_set_pcfifo_unordered_boot_so_mss(2, TSECSWR);
+ /* XUSB_DEVW has PCFIFO enabled. */
+ reg_val |= mc_set_pcfifo_ordered_boot_so_mss(2, XUSB_DEVW);
+ tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG2, reg_val);
+
+ reg_val = MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL &
+ mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCWA) &
+ mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCW) &
+ mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCWAB) &
+ mc_set_pcfifo_unordered_boot_so_mss(3, VICSWR) &
+ mc_set_pcfifo_unordered_boot_so_mss(3, APEW);
+ tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG3, reg_val);
+
+ reg_val = MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL &
+ mc_set_pcfifo_unordered_boot_so_mss(4, SESWR) &
+ mc_set_pcfifo_unordered_boot_so_mss(4, ETRW) &
+ mc_set_pcfifo_unordered_boot_so_mss(4, TSECSWRB) &
+ mc_set_pcfifo_unordered_boot_so_mss(4, AXISW) &
+ mc_set_pcfifo_unordered_boot_so_mss(4, UFSHCW) &
+ mc_set_pcfifo_unordered_boot_so_mss(4, BPMPW) &
+ mc_set_pcfifo_unordered_boot_so_mss(4, BPMPDMAW) &
+ mc_set_pcfifo_unordered_boot_so_mss(4, AONW) &
+ mc_set_pcfifo_unordered_boot_so_mss(4, AONDMAW) &
+ mc_set_pcfifo_unordered_boot_so_mss(4, SCEW) &
+ mc_set_pcfifo_unordered_boot_so_mss(4, SCEDMAW);
+ /* EQOSW has PCFIFO order enabled. */
+ reg_val |= mc_set_pcfifo_ordered_boot_so_mss(4, EQOSW);
+ tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG4, reg_val);
+
+ reg_val = MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL &
+ mc_set_pcfifo_unordered_boot_so_mss(5, APEDMAW) &
+ mc_set_pcfifo_unordered_boot_so_mss(5, VIFALW);
+ tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG5, reg_val);
+
+ reg_val = MC_PCFIFO_CLIENT_CONFIG6_RESET_VAL &
+ mc_set_pcfifo_unordered_boot_so_mss(6, RCEW) &
+ mc_set_pcfifo_unordered_boot_so_mss(6, RCEDMAW) &
+ mc_set_pcfifo_unordered_boot_so_mss(6, PCIE0W);
+ /* PCIE1, PCIE2 and PCI3 has PCFIFO enabled. */
+ reg_val |= mc_set_pcfifo_ordered_boot_so_mss(6, PCIE1W) |
+ mc_set_pcfifo_ordered_boot_so_mss(6, PCIE2W) |
+ mc_set_pcfifo_ordered_boot_so_mss(6, PCIE3W);
+ tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG6, reg_val);
+
+ reg_val = MC_PCFIFO_CLIENT_CONFIG7_RESET_VAL &
+ mc_set_pcfifo_unordered_boot_so_mss(7, PCIE4W) &
+ mc_set_pcfifo_unordered_boot_so_mss(7, PCIE5W);
+ tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG7, reg_val);
+
+ /* Set Order Id only for the clients having non zero order id */
+ reg_val = MC_CLIENT_ORDER_ID_9_RESET_VAL &
+ mc_client_order_id(9, XUSB_HOSTW);
+ tegra_mc_write_32(MC_CLIENT_ORDER_ID_9, reg_val);
+
+ reg_val = MC_CLIENT_ORDER_ID_27_RESET_VAL &
+ mc_client_order_id(27, PCIE0W);
+ tegra_mc_write_32(MC_CLIENT_ORDER_ID_27, reg_val);
+
+ reg_val = MC_CLIENT_ORDER_ID_28_RESET_VAL &
+ mc_client_order_id(28, PCIE4W) &
+ mc_client_order_id(28, PCIE5W);
+ tegra_mc_write_32(MC_CLIENT_ORDER_ID_28, reg_val);
+
+ /* Set VC Id only for the clients having different reset values */
+ reg_val = MC_HUB_PC_VC_ID_0_RESET_VAL &
+ /*
+ * SDMMCRAB, SDMMCWAB, SESRD, SESWR, TSECSRD,TSECSRDB,
+ * TSECSWR and TSECSWRB clients
+ */
+ mc_hub_vc_id(0, APB);
+ tegra_mc_write_32(MC_HUB_PC_VC_ID_0, reg_val);
+
+ reg_val = MC_HUB_PC_VC_ID_2_RESET_VAL &
+ /* SDMMCRAB and SDMMCWAB clients */
+ mc_hub_vc_id(2, SD);
+ tegra_mc_write_32(MC_HUB_PC_VC_ID_2, reg_val);
+
+ reg_val = MC_HUB_PC_VC_ID_4_RESET_VAL &
+ /* AXIR and AXIW clients */
+ mc_hub_vc_id(4, NIC);
+ tegra_mc_write_32(MC_HUB_PC_VC_ID_4, reg_val);
+
+ wdata_0 = MC_CLIENT_HOTRESET_CTRL0_RESET_VAL;
+ tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0);
+
+ wdata_1 = MC_CLIENT_HOTRESET_CTRL1_RESET_VAL;
+ tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1);
+
+ wdata_2 = MC_CLIENT_HOTRESET_CTRL2_RESET_VAL;
+ tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL2, wdata_2);
+}
+
/*******************************************************************************
* Struct to hold the memory controller settings
******************************************************************************/
@@ -306,7 +629,8 @@
.streamid_security_cfg = tegra194_streamid_sec_cfgs,
.num_streamid_security_cfgs = ARRAY_SIZE(tegra194_streamid_sec_cfgs),
.txn_override_cfg = tegra194_txn_override_cfgs,
- .num_txn_override_cfgs = ARRAY_SIZE(tegra194_txn_override_cfgs)
+ .num_txn_override_cfgs = ARRAY_SIZE(tegra194_txn_override_cfgs),
+ .reconfig_mss_clients = tegra194_memctrl_reconfig_mss_clients
};
/*******************************************************************************
diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c
index 4471ba0..b325e4e 100644
--- a/plat/nvidia/tegra/soc/t194/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t194/plat_setup.c
@@ -21,6 +21,7 @@
#include <mce.h>
#include <plat/common/platform.h>
#include <tegra_def.h>
+#include <tegra_mc_def.h>
#include <tegra_platform.h>
#include <tegra_private.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
diff --git a/plat/nvidia/tegra/soc/t194/plat_smmu.c b/plat/nvidia/tegra/soc/t194/plat_smmu.c
index edca16b..ccdf7f8 100644
--- a/plat/nvidia/tegra/soc/t194/plat_smmu.c
+++ b/plat/nvidia/tegra/soc/t194/plat_smmu.c
@@ -8,6 +8,7 @@
#include <common/debug.h>
#include <smmu.h>
#include <tegra_def.h>
+#include <tegra_mc_def.h>
#define BOARD_SYSTEM_FPGA_BASE U(1)
#define BASE_CONFIG_SMMU_DEVICES U(2)