fix(drivers/marvell/comphy-3700): drop MODE_REFDIV constant
The MODE_REFDIV constant is only used as mask of the MODE_REFDIV
register, but we already have MODE_REFDIV_MASK constant for that.
Drop MODE_REFDIV.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: Icabb32189a7ca1a857dcf86cf0846bd0335f75d0
diff --git a/drivers/marvell/comphy/phy-comphy-3700.c b/drivers/marvell/comphy/phy-comphy-3700.c
index 175befb..d542867 100644
--- a/drivers/marvell/comphy/phy-comphy-3700.c
+++ b/drivers/marvell/comphy/phy-comphy-3700.c
@@ -886,7 +886,7 @@
/* 11. Release SW reset */
reg_set16(GLOB_PHY_CTRL0_ADDR(PCIE) + COMPHY_SD_ADDR,
MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32,
- SOFT_RESET | MODE_REFDIV);
+ SOFT_RESET | MODE_REFDIV_MASK);
/* Wait for > 55 us to allow PCLK be enabled */
udelay(PLL_SET_DELAY_US);
diff --git a/drivers/marvell/comphy/phy-comphy-3700.h b/drivers/marvell/comphy/phy-comphy-3700.h
index c46905b..3d3a51b 100644
--- a/drivers/marvell/comphy/phy-comphy-3700.h
+++ b/drivers/marvell/comphy/phy-comphy-3700.h
@@ -180,7 +180,6 @@
#define GLOB_PHY_CTRL0_ADDR(unit) (COMPHY_REG_GLOB_PHY_CTRL0_ADDR * \
PHY_SHFT(unit))
#define SOFT_RESET BIT(0)
-#define MODE_REFDIV 0x30
#define MODE_CORE_CLK_FREQ_SEL BIT(9)
#define MODE_PIPE_WIDTH_32 BIT(3)
#define MODE_REFDIV_OFFSET 4