fix(tc): modify DPU configuration in dts for TC4 FPGA
TC4 FPGA DPU base addr and irq doesn't match with TC3 FPGA
so refactor the code to manage it accordingly.
Change-Id: Ie31933e0bcbd489945935829940a5c5434e6b1d7
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
diff --git a/fdts/tc3-4-base.dtsi b/fdts/tc3-4-base.dtsi
index 84aa8e8..049a4c6 100644
--- a/fdts/tc3-4-base.dtsi
+++ b/fdts/tc3-4-base.dtsi
@@ -22,10 +22,8 @@
#if TARGET_FLAVOUR_FVP
#define DPU_ADDR 4000000000
#define DPU_IRQ 579
-#elif TARGET_FLAVOUR_FPGA
-#define DPU_ADDR 2cc00000
-#define DPU_IRQ 69
#endif
+
#include "tc-base.dtsi"
/ {
diff --git a/fdts/tc3.dts b/fdts/tc3.dts
index b8fe587..22d4d10 100644
--- a/fdts/tc3.dts
+++ b/fdts/tc3.dts
@@ -40,6 +40,11 @@
#define VIRTIO_BLOCK_ADDR 1c130000
#define VIRTIO_BLOCK_INT 204
+#if TARGET_FLAVOUR_FPGA
+#define DPU_ADDR 2cc00000
+#define DPU_IRQ 69
+#endif
+
#include "tc-common.dtsi"
#if TARGET_FLAVOUR_FVP
#include "tc-fvp.dtsi"
diff --git a/fdts/tc4.dts b/fdts/tc4.dts
index 0782093..ae9a0e5 100644
--- a/fdts/tc4.dts
+++ b/fdts/tc4.dts
@@ -46,6 +46,11 @@
#define VIRTIO_BLOCK_ADDR 60020000
#define VIRTIO_BLOCK_INT 769
+#if TARGET_FLAVOUR_FPGA
+#define DPU_ADDR 4000000000
+#define DPU_IRQ 579
+#endif
+
#include "tc-common.dtsi"
#if TARGET_FLAVOUR_FVP
#include "tc-fvp.dtsi"