Prepare platforms to use refactored ARM GIC drivers
This patch adds platform helpers for the new GICv2 and GICv3 drivers in
plat_gicv2.c and plat_gicv3.c. The platforms can include the appropriate
file in their build according to the GIC driver to be used. The existing
plat_gic.c is only meant for the legacy GIC driver.
In the case of ARM platforms, the major changes are as follows:
1. The crash reporting helper macro `arm_print_gic_regs` that prints the GIC CPU
interface register values has been modified to detect the type of CPU
interface being used (System register or memory mappped interface) before
using the right interface to print the registers.
2. The power management helper function that is called after a core is powered
up has been further refactored. This is to highlight that the per-cpu
distributor interface should be initialised only when the core was originally
powered down using the CPU_OFF PSCI API and not when the CPU_SUSPEND PSCI API
was used.
3. In the case of CSS platforms, the system power domain restore helper
`arm_system_pwr_domain_resume()` is now only invoked in the `suspend_finish`
handler as the system power domain is always expected to be initialized when
the `on_finish` handler is invoked.
Change-Id: I7fc27d61fc6c2a60cea2436b676c5737d0257df6
diff --git a/plat/arm/board/fvp/aarch64/fvp_helpers.S b/plat/arm/board/fvp/aarch64/fvp_helpers.S
index 2c24e61..338d158 100644
--- a/plat/arm/board/fvp/aarch64/fvp_helpers.S
+++ b/plat/arm/board/fvp/aarch64/fvp_helpers.S
@@ -30,7 +30,8 @@
#include <arch.h>
#include <asm_macros.S>
-#include <gic_v2.h>
+#include <gicv2.h>
+#include <gicv3.h>
#include <platform_def.h>
#include <v2m_def.h>
#include "../drivers/pwrc/fvp_pwrc.h"
@@ -74,9 +75,26 @@
str w0, [x1, #PPOFFR_OFF]
/* ---------------------------------------------
- * Deactivate the gic cpu interface as well
+ * Disable GIC bypass as well
* ---------------------------------------------
*/
+ /* Check for GICv3 system register access */
+ mrs x0, id_aa64pfr0_el1
+ ubfx x0, x0, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
+ cmp x0, #1
+ b.ne gicv2_bypass_disable
+
+ /* Check for SRE enable */
+ mrs x1, ICC_SRE_EL3
+ tst x1, #ICC_SRE_SRE_BIT
+ b.eq gicv2_bypass_disable
+
+ mrs x2, ICC_SRE_EL3
+ orr x2, x2, #(ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)
+ msr ICC_SRE_EL3, x2
+ b secondary_cold_boot_wait
+
+gicv2_bypass_disable:
ldr x0, =VE_GICC_BASE
ldr x1, =BASE_GICC_BASE
fvp_choose_gicmmap x0, x1, x2, w2, x1
@@ -84,6 +102,7 @@
orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0)
str w0, [x1, #GICC_CTLR]
+secondary_cold_boot_wait:
/* ---------------------------------------------
* There is no sane reason to come out of this
* wfi so panic if we do. This cpu will be pow-
diff --git a/plat/arm/board/fvp/fvp_pm.c b/plat/arm/board/fvp/fvp_pm.c
index 21ad14f..d7b459d 100644
--- a/plat/arm/board/fvp/fvp_pm.c
+++ b/plat/arm/board/fvp/fvp_pm.c
@@ -93,6 +93,42 @@
fvp_pwrc_write_pcoffr(mpidr);
}
+static void fvp_power_domain_on_finish_common(const psci_power_state_t *target_state)
+{
+ unsigned long mpidr;
+
+ assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
+ ARM_LOCAL_STATE_OFF);
+
+ /* Get the mpidr for this cpu */
+ mpidr = read_mpidr_el1();
+
+ /* Perform the common cluster specific operations */
+ if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
+ ARM_LOCAL_STATE_OFF) {
+ /*
+ * This CPU might have woken up whilst the cluster was
+ * attempting to power down. In this case the FVP power
+ * controller will have a pending cluster power off request
+ * which needs to be cleared by writing to the PPONR register.
+ * This prevents the power controller from interpreting a
+ * subsequent entry of this cpu into a simple wfi as a power
+ * down request.
+ */
+ fvp_pwrc_write_pponr(mpidr);
+
+ /* Enable coherency if this cluster was off */
+ fvp_cci_enable();
+ }
+
+ /*
+ * Clear PWKUPR.WEN bit to ensure interrupts do not interfere
+ * with a cpu power down unless the bit is set again
+ */
+ fvp_pwrc_clr_wen(mpidr);
+}
+
+
/*******************************************************************************
* FVP handler called when a CPU is about to enter standby.
******************************************************************************/
@@ -196,42 +232,11 @@
******************************************************************************/
void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state)
{
- unsigned long mpidr;
-
- assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
- ARM_LOCAL_STATE_OFF);
-
- /* Get the mpidr for this cpu */
- mpidr = read_mpidr_el1();
-
- /* Perform the common cluster specific operations */
- if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
- ARM_LOCAL_STATE_OFF) {
- /*
- * This CPU might have woken up whilst the cluster was
- * attempting to power down. In this case the FVP power
- * controller will have a pending cluster power off request
- * which needs to be cleared by writing to the PPONR register.
- * This prevents the power controller from interpreting a
- * subsequent entry of this cpu into a simple wfi as a power
- * down request.
- */
- fvp_pwrc_write_pponr(mpidr);
-
- /* Enable coherency if this cluster was off */
- fvp_cci_enable();
- }
-
- /*
- * Clear PWKUPR.WEN bit to ensure interrupts do not interfere
- * with a cpu power down unless the bit is set again
- */
- fvp_pwrc_clr_wen(mpidr);
+ fvp_power_domain_on_finish_common(target_state);
/* Enable the gic cpu interface */
arm_gic_cpuif_setup();
-
- /* TODO: This setup is needed only after a cold boot */
+ /* Program the gic per-cpu distributor interface */
arm_gic_pcpu_distif_setup();
}
@@ -251,7 +256,10 @@
ARM_LOCAL_STATE_RET)
return;
+ fvp_power_domain_on_finish_common(target_state);
+
- fvp_pwr_domain_on_finish(target_state);
+ /* Enable the gic cpu interface */
+ arm_gic_cpuif_setup();
}
/*******************************************************************************
diff --git a/plat/arm/board/fvp/include/plat_macros.S b/plat/arm/board/fvp/include/plat_macros.S
index 2feffbe..2ed0d85 100644
--- a/plat/arm/board/fvp/include/plat_macros.S
+++ b/plat/arm/board/fvp/include/plat_macros.S
@@ -53,16 +53,14 @@
/* Check if VE mmap */
cmp w16, #BLD_GIC_VE_MMAP
b.eq use_ve_mmap
- /* Check if Cortex-A53/A57 mmap */
- cmp w16, #BLD_GIC_A53A57_MMAP
- b.ne exit_print_gic_regs
+ /* Assume Base Cortex mmap */
mov_imm x17, BASE_GICC_BASE
mov_imm x16, BASE_GICD_BASE
- b print_gicc_regs
+ b print_gic_regs
use_ve_mmap:
mov_imm x17, VE_GICC_BASE
mov_imm x16, VE_GICD_BASE
-print_gicc_regs:
+print_gic_regs:
arm_print_gic_regs
.endm
diff --git a/plat/arm/css/common/css_pm.c b/plat/arm/css/common/css_pm.c
index 3f46857..1d9bd59 100644
--- a/plat/arm/css/common/css_pm.c
+++ b/plat/arm/css/common/css_pm.c
@@ -41,6 +41,12 @@
#include <platform_def.h>
#include "css_scpi.h"
+/* Macros to read the CSS power domain state */
+#define CSS_CORE_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL0]
+#define CSS_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL1]
+#define CSS_SYSTEM_PWR_STATE(state) ((PLAT_MAX_PWR_LVL > ARM_PWR_LVL1) ?\
+ (state)->pwr_domain_state[ARM_PWR_LVL2] : 0)
+
/* Allow CSS platforms to override `plat_arm_psci_pm_ops` */
#pragma weak plat_arm_psci_pm_ops
@@ -93,50 +99,37 @@
return PSCI_E_SUCCESS;
}
-/*******************************************************************************
- * Handler called when a power level has just been powered on after
- * being turned off earlier. The target_state encodes the low power state that
- * each level has woken up from.
- ******************************************************************************/
-void css_pwr_domain_on_finish(const psci_power_state_t *target_state)
+static void css_pwr_domain_on_finisher_common(
+ const psci_power_state_t *target_state)
{
- assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
- ARM_LOCAL_STATE_OFF);
-
- if (PLAT_MAX_PWR_LVL > ARM_PWR_LVL1) {
- /*
- * Perform system initialization if woken up from system
- * suspend.
- */
- if (target_state->pwr_domain_state[ARM_PWR_LVL2] ==
- ARM_LOCAL_STATE_OFF)
- arm_system_pwr_domain_resume();
- }
+ assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF);
/*
* Perform the common cluster specific operations i.e enable coherency
* if this cluster was off.
*/
- if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
- ARM_LOCAL_STATE_OFF)
+ if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF)
cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
+}
+/*******************************************************************************
+ * Handler called when a power level has just been powered on after
+ * being turned off earlier. The target_state encodes the low power state that
+ * each level has woken up from. This handler would never be invoked with
+ * the system power domain uninitialized as either the primary would have taken
+ * care of it as part of cold boot or the first core awakened from system
+ * suspend would have already initialized it.
+ ******************************************************************************/
+void css_pwr_domain_on_finish(const psci_power_state_t *target_state)
+{
+ /* Assert that the system power domain need not be initialized */
+ assert(CSS_SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_RUN);
- if (PLAT_MAX_PWR_LVL > ARM_PWR_LVL1) {
- /*
- * Skip GIC CPU interface and per-CPU Distributor interface
- * setups if woken up from system suspend as it is done as
- * part of css_system_pwr_domain_resume().
- */
- if (target_state->pwr_domain_state[ARM_PWR_LVL2] ==
- ARM_LOCAL_STATE_OFF)
- return;
- }
+ css_pwr_domain_on_finisher_common(target_state);
/* Enable the gic cpu interface */
arm_gic_cpuif_setup();
-
- /* todo: Is this setup only needed after a cold boot? */
+ /* Program the gic per-cpu distributor interface */
arm_gic_pcpu_distif_setup();
}
@@ -154,19 +147,12 @@
/* Prevent interrupts from spuriously waking up this cpu */
arm_gic_cpuif_deactivate();
- if (PLAT_MAX_PWR_LVL > ARM_PWR_LVL1) {
- /*
- * Check if power down at system power domain level is
- * requested.
- */
- if (target_state->pwr_domain_state[ARM_PWR_LVL2] ==
- ARM_LOCAL_STATE_OFF)
+ /* Check if power down at system power domain level is requested */
+ if (CSS_SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF)
system_state = scpi_power_retention;
- }
/* Cluster is to be turned off, so disable coherency */
- if (target_state->pwr_domain_state[ARM_PWR_LVL1] ==
- ARM_LOCAL_STATE_OFF) {
+ if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
cluster_state = scpi_power_off;
}
@@ -187,9 +173,7 @@
******************************************************************************/
void css_pwr_domain_off(const psci_power_state_t *target_state)
{
- assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
- ARM_LOCAL_STATE_OFF);
-
+ assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF);
css_power_down_common(target_state);
}
@@ -200,16 +184,13 @@
void css_pwr_domain_suspend(const psci_power_state_t *target_state)
{
/*
- * Juno has retention only at cpu level. Just return
+ * CSS currently supports retention only at cpu level. Just return
* as nothing is to be done for retention.
*/
- if (target_state->pwr_domain_state[ARM_PWR_LVL0] ==
- ARM_LOCAL_STATE_RET)
+ if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET)
return;
- assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
- ARM_LOCAL_STATE_OFF);
-
+ assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF);
css_power_down_common(target_state);
}
@@ -223,14 +204,18 @@
void css_pwr_domain_suspend_finish(
const psci_power_state_t *target_state)
{
- /*
- * Return as nothing is to be done on waking up from retention.
- */
- if (target_state->pwr_domain_state[ARM_PWR_LVL0] ==
- ARM_LOCAL_STATE_RET)
+ /* Return as nothing is to be done on waking up from retention. */
+ if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET)
return;
- css_pwr_domain_on_finish(target_state);
+ /* Perform system domain restore if woken up from system suspend */
+ if (CSS_SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF)
+ arm_system_pwr_domain_resume();
+ else
+ /* Enable the gic cpu interface */
+ arm_gic_cpuif_setup();
+
+ css_pwr_domain_on_finisher_common(target_state);
}
/*******************************************************************************