Merge changes from topic "st-clk-cleanup" into integration
* changes:
refactor(st-clock): code size optimization
refactor(st-clock): remove unused PLL field
diff --git a/Makefile b/Makefile
index 5916963..d412078 100644
--- a/Makefile
+++ b/Makefile
@@ -9,6 +9,7 @@
#
VERSION_MAJOR := 2
VERSION_MINOR := 7
+VERSION := ${VERSION_MAJOR}.${VERSION_MINOR}
# Default goal is build all images
.DEFAULT_GOAL := all
@@ -322,7 +323,7 @@
ifeq (${BUILD_STRING},)
BUILD_STRING := $(shell git describe --always --dirty --tags 2> /dev/null)
endif
-VERSION_STRING := v${VERSION_MAJOR}.${VERSION_MINOR}(${BUILD_TYPE}):${BUILD_STRING}
+VERSION_STRING := v${VERSION}(${BUILD_TYPE}):${BUILD_STRING}
ifeq (${AARCH32_INSTRUCTION_SET},A32)
TF_CFLAGS_aarch32 += -marm
@@ -600,6 +601,9 @@
PIE_FOUND := $(findstring --enable-default-pie,${GCC_V_OUTPUT})
ifneq ($(PIE_FOUND),)
TF_CFLAGS += -fno-PIE
+ifneq ($(findstring gcc,$(notdir $(LD))),)
+ TF_LDFLAGS += -no-pie
+endif
endif
ifneq ($(findstring gcc,$(notdir $(LD))),)
diff --git a/bl31/aarch64/ea_delegate.S b/bl31/aarch64/ea_delegate.S
index fa6ede8..5e53ab4 100644
--- a/bl31/aarch64/ea_delegate.S
+++ b/bl31/aarch64/ea_delegate.S
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -84,10 +85,6 @@
b 2f
1:
- /* Test for EA bit in the instruction syndrome */
- mrs x30, esr_el3
- tbz x30, #ESR_ISS_EABORT_EA_BIT, 3f
-
/*
* Save general purpose and ARMv8.3-PAuth registers (if enabled).
* If Secure Cycle Counter is not disabled in MDCR_EL3 when
@@ -114,7 +111,6 @@
ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
-3:
/* Synchronous exceptions other than the above are assumed to be EA */
ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
no_ret report_unhandled_exception
diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S
index 8a1573a..3d3dc95 100644
--- a/bl31/bl31.ld.S
+++ b/bl31/bl31.ld.S
@@ -186,10 +186,10 @@
__RW_END__ = .;
__BL31_END__ = .;
+ ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.")
+#endif
+
/DISCARD/ : {
*(.dynsym .dynstr .hash .gnu.hash)
}
-
- ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.")
-#endif
}
diff --git a/common/bl_common.c b/common/bl_common.c
index 9bfaafd..8fce02f 100644
--- a/common/bl_common.c
+++ b/common/bl_common.c
@@ -269,3 +269,12 @@
#endif
#undef PRINT_IMAGE_ARG
}
+
+/*
+ * This function is for returning the TF-A version
+ */
+const char *get_version(void)
+{
+ extern const char version[];
+ return version;
+}
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 2ddccac..ef4c1a3 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -390,6 +390,10 @@
For Neoverse V1, the following errata build flags are defined :
+- ``ERRATA_V1_1618635``: This applies errata 1618635 workaround to Neoverse-V1
+ CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
+ r1p0.
+
- ``ERRATA_V1_1774420``: This applies errata 1774420 workaround to Neoverse-V1
CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
in r1p1.
diff --git a/include/common/bl_common.h b/include/common/bl_common.h
index 3a06cfb..539280e 100644
--- a/include/common/bl_common.h
+++ b/include/common/bl_common.h
@@ -178,6 +178,7 @@
extern const char build_message[];
extern const char version_string[];
+const char *get_version(void);
void print_entry_point_info(const entry_point_info_t *ep_info);
uintptr_t page_align(uintptr_t value, unsigned dir);
diff --git a/include/lib/cpus/aarch64/neoverse_v1.h b/include/lib/cpus/aarch64/neoverse_v1.h
index 181be1d..9c7e967 100644
--- a/include/lib/cpus/aarch64/neoverse_v1.h
+++ b/include/lib/cpus/aarch64/neoverse_v1.h
@@ -16,6 +16,10 @@
* CPU Extended Control register specific definitions.
******************************************************************************/
#define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4
+#define NEOVERSE_V1_CPUPSELR_EL3 S3_6_C15_C8_0
+#define NEOVERSE_V1_CPUPOR_EL3 S3_6_C15_C8_2
+#define NEOVERSE_V1_CPUPMR_EL3 S3_6_C15_C8_3
+#define NEOVERSE_V1_CPUPCR_EL3 S3_6_C15_C8_1
#define NEOVERSE_V1_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
#define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53)
#define NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3)
diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S
index 378cb92..109b725 100644
--- a/lib/cpus/aarch64/neoverse_v1.S
+++ b/lib/cpus/aarch64/neoverse_v1.S
@@ -27,6 +27,82 @@
#endif /* WORKAROUND_CVE_2022_23960 */
/* --------------------------------------------------
+ * Errata Workaround for Neoverse V1 Errata #1618635.
+ * This applies to revision r0p0 and is fixed in
+ * r1p0.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0, x17
+ * --------------------------------------------------
+ */
+func errata_neoverse_v1_1618635_wa
+ /* Check workaround compatibility. */
+ mov x17, x30
+ bl check_errata_1618635
+ cbz x0, 1f
+
+ /* Inserts a DMB SY before and after MRS PAR_EL1 */
+ ldr x0, =0x0
+ msr NEOVERSE_V1_CPUPSELR_EL3, x0
+ ldr x0, = 0xEE070F14
+ msr NEOVERSE_V1_CPUPOR_EL3, x0
+ ldr x0, = 0xFFFF0FFF
+ msr NEOVERSE_V1_CPUPMR_EL3, x0
+ ldr x0, =0x4005027FF
+ msr NEOVERSE_V1_CPUPCR_EL3, x0
+
+ /* Inserts a DMB SY before STREX imm offset */
+ ldr x0, =0x1
+ msr NEOVERSE_V1_CPUPSELR_EL3, x0
+ ldr x0, =0x00e8400000
+ msr NEOVERSE_V1_CPUPOR_EL3, x0
+ ldr x0, =0x00fff00000
+ msr NEOVERSE_V1_CPUPMR_EL3, x0
+ ldr x0, = 0x4001027FF
+ msr NEOVERSE_V1_CPUPCR_EL3, x0
+
+ /* Inserts a DMB SY before STREX[BHD}/STLEX* */
+ ldr x0, =0x2
+ msr NEOVERSE_V1_CPUPSELR_EL3, x0
+ ldr x0, =0x00e8c00040
+ msr NEOVERSE_V1_CPUPOR_EL3, x0
+ ldr x0, =0x00fff00040
+ msr NEOVERSE_V1_CPUPMR_EL3, x0
+ ldr x0, = 0x4001027FF
+ msr NEOVERSE_V1_CPUPCR_EL3, x0
+
+ /* Inserts a DMB SY after STREX imm offset */
+ ldr x0, =0x3
+ msr NEOVERSE_V1_CPUPSELR_EL3, x0
+ ldr x0, =0x00e8400000
+ msr NEOVERSE_V1_CPUPOR_EL3, x0
+ ldr x0, =0x00fff00000
+ msr NEOVERSE_V1_CPUPMR_EL3, x0
+ ldr x0, = 0x4004027FF
+ msr NEOVERSE_V1_CPUPCR_EL3, x0
+
+ /* Inserts a DMB SY after STREX[BHD}/STLEX* */
+ ldr x0, =0x4
+ msr NEOVERSE_V1_CPUPSELR_EL3, x0
+ ldr x0, =0x00e8c00040
+ msr NEOVERSE_V1_CPUPOR_EL3, x0
+ ldr x0, =0x00fff00040
+ msr NEOVERSE_V1_CPUPMR_EL3, x0
+ ldr x0, = 0x4004027FF
+ msr NEOVERSE_V1_CPUPCR_EL3, x0
+
+ /* Synchronize to enable patches */
+ isb
+1:
+ ret x17
+endfunc errata_neoverse_v1_1618635_wa
+
+func check_errata_1618635
+ /* Applies to revision r0p0. */
+ mov x1, #0x00
+ b cpu_rev_var_ls
+endfunc check_errata_1618635
+
+ /* --------------------------------------------------
* Errata Workaround for Neoverse V1 Errata #1774420.
* This applies to revisions r0p0 and r1p0, fixed in r1p1.
* x0: variant[4:7] and revision[0:3] of current cpu.
@@ -425,6 +501,7 @@
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
+ report_errata ERRATA_V1_1618635, neoverse_v1, 1618635
report_errata ERRATA_V1_1774420, neoverse_v1, 1774420
report_errata ERRATA_V1_1791573, neoverse_v1, 1791573
report_errata ERRATA_V1_1852267, neoverse_v1, 1852267
@@ -450,6 +527,11 @@
msr SSBS, xzr
isb
+#if ERRATA_V1_1618635
+ mov x0, x18
+ bl errata_neoverse_v1_1618635_wa
+#endif
+
#if ERRATA_V1_1774420
mov x0, x18
bl errata_neoverse_v1_1774420_wa
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index b114824..2ed1c6d 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -442,6 +442,10 @@
# to revisions r0p0 of the Neoverse-N2 cpu, it is still open.
ERRATA_N2_2002655 ?=0
+# Flag to apply erratum 1618635 workaround during reset. This erratum applies
+# to revision r0p0 of the Neoverse V1 cpu and was fixed in the revision r1p0.
+ERRATA_V1_1618635 ?=0
+
# Flag to apply erratum 1774420 workaround during reset. This erratum applies
# to revisions r0p0 and r1p0 of the Neoverse V1 core, and was fixed in r1p1.
ERRATA_V1_1774420 ?=0
@@ -1011,6 +1015,10 @@
$(eval $(call assert_boolean,ERRATA_N2_2002655))
$(eval $(call add_define,ERRATA_N2_2002655))
+# Process ERRATA_V1_1618635 flag
+$(eval $(call assert_boolean,ERRATA_V1_1618635))
+$(eval $(call add_define,ERRATA_V1_1618635))
+
# Process ERRATA_V1_1774420 flag
$(eval $(call assert_boolean,ERRATA_V1_1774420))
$(eval $(call add_define,ERRATA_V1_1774420))
diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk
index a58caf5..abdd4d0 100644
--- a/make_helpers/build_macros.mk
+++ b/make_helpers/build_macros.mk
@@ -499,7 +499,8 @@
$(call MAKE_BUILD_STRINGS, $(BUILD_DIR)/build_message.o)
else
@echo 'const char build_message[] = "Built : "$(BUILD_MESSAGE_TIMESTAMP); \
- const char version_string[] = "${VERSION_STRING}";' | \
+ const char version_string[] = "${VERSION_STRING}"; \
+ const char version[] = "${VERSION}";' | \
$$(CC) $$(TF_CFLAGS) $$(CFLAGS) -xc -c - -o $(BUILD_DIR)/build_message.o
endif
ifneq ($(findstring armlink,$(notdir $(LD))),)
diff --git a/make_helpers/windows.mk b/make_helpers/windows.mk
index 26ea88e..0f78f61 100644
--- a/make_helpers/windows.mk
+++ b/make_helpers/windows.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2022, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -81,6 +81,7 @@
# by defining the MAKE_BUILD_STRINGS macro.
BUILT_TIME_DATE_STRING = const char build_message[] = "Built : "${BUILD_MESSAGE_TIMESTAMP};
VERSION_STRING_MESSAGE = const char version_string[] = "${VERSION_STRING}";
+const char version[] = "${VERSION}";
define MAKE_BUILD_STRINGS
@echo $$(BUILT_TIME_DATE_STRING) $$(VERSION_STRING_MESSAGE) | \
$$(CC) $$(TF_CFLAGS) $$(CFLAGS) -x c -c - -o $1